67 lines
2.5 KiB
Diff
67 lines
2.5 KiB
Diff
From e4d0e84e490790798691aaa0f2e598637f1867ec Mon Sep 17 00:00:00 2001
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From: Tom Lendacky <thomas.lendacky@amd.com>
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Date: Mon, 8 Jan 2018 16:09:21 -0600
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Subject: [PATCH 1/2] x86/cpu/AMD: Make LFENCE a serializing instruction
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To aid in speculation control, make LFENCE a serializing instruction
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since it has less overhead than MFENCE. This is done by setting bit 1
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of MSR 0xc0011029 (DE_CFG). Some families that support LFENCE do not
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have this MSR. For these families, the LFENCE instruction is already
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serializing.
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Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Reviewed-by: Reviewed-by: Borislav Petkov <bp@suse.de>
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Cc: Peter Zijlstra <peterz@infradead.org>
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Cc: Tim Chen <tim.c.chen@linux.intel.com>
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Cc: Dave Hansen <dave.hansen@intel.com>
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Cc: Borislav Petkov <bp@alien8.de>
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Cc: Dan Williams <dan.j.williams@intel.com>
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Cc: Linus Torvalds <torvalds@linux-foundation.org>
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Cc: Greg Kroah-Hartman <gregkh@linux-foundation.org>
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Cc: David Woodhouse <dwmw@amazon.co.uk>
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Cc: Paul Turner <pjt@google.com>
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Link: https://lkml.kernel.org/r/20180108220921.12580.71694.stgit@tlendack-t1.amdoffice.net
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---
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arch/x86/include/asm/msr-index.h | 2 ++
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arch/x86/kernel/cpu/amd.c | 10 ++++++++++
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2 files changed, 12 insertions(+)
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diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
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index ab022618a50a..1e7d710fef43 100644
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--- a/arch/x86/include/asm/msr-index.h
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+++ b/arch/x86/include/asm/msr-index.h
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@@ -352,6 +352,8 @@
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#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
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#define FAM10H_MMIO_CONF_BASE_SHIFT 20
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#define MSR_FAM10H_NODE_ID 0xc001100c
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+#define MSR_F10H_DECFG 0xc0011029
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+#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1
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/* K8 MSRs */
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#define MSR_K8_TOP_MEM1 0xc001001a
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diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
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index bcb75dc97d44..5b438d81beb2 100644
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--- a/arch/x86/kernel/cpu/amd.c
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+++ b/arch/x86/kernel/cpu/amd.c
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@@ -829,6 +829,16 @@ static void init_amd(struct cpuinfo_x86 *c)
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set_cpu_cap(c, X86_FEATURE_K8);
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if (cpu_has(c, X86_FEATURE_XMM2)) {
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+ /*
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+ * A serializing LFENCE has less overhead than MFENCE, so
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+ * use it for execution serialization. On families which
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+ * don't have that MSR, LFENCE is already serializing.
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+ * msr_set_bit() uses the safe accessors, too, even if the MSR
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+ * is not present.
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+ */
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+ msr_set_bit(MSR_F10H_DECFG,
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+ MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
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+
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/* MFENCE stops RDTSC speculation */
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set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
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}
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--
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2.14.3
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