43 lines
1.7 KiB
Diff
43 lines
1.7 KiB
Diff
From 6e8bed6a3e2fd6f1e82ea9b1f705bbc82060a2b7 Mon Sep 17 00:00:00 2001
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From: Rob Clark <robdclark@gmail.com>
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Date: Tue, 3 Jul 2018 08:14:32 -0400
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Subject: [PATCH] drm/msm/mdp5: fix missing CTL flush
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f9cb8d8d836e fixed various race conditions with CTL flush, in particular
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flushing and sending the START signal before encoder state was updated.
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But it did this a little too well in some cases that don't trigger
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encoder->enable(), and CTL[n].FLUSH would never be set. When page flips
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happen it would paper over the bug, since the first plag flip would
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flush out the state to the hardware.
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The issue could be reproduced with, for example, modetest (without the
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'-v' argument).
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Fixes: f9cb8d8d836e drm/msm/mdp5: rework CTL START signal handling
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Signed-off-by: Rob Clark <robdclark@gmail.com>
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Reviewed-by: Sean Paul <seanpaul@chromium.org>
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diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c
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index 9af94e35f678..fcd44d1d1068 100644
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--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c
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+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c
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@@ -319,7 +319,17 @@ static int mdp5_encoder_atomic_check(struct drm_encoder *encoder,
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mdp5_cstate->ctl = ctl;
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mdp5_cstate->pipeline.intf = intf;
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- mdp5_cstate->defer_start = true;
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+
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+ /*
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+ * This is a bit awkward, but we want to flush the CTL and hit the
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+ * START bit at most once for an atomic update. In the non-full-
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+ * modeset case, this is done from crtc->atomic_flush(), but that
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+ * is too early in the case of full modeset, in which case we
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+ * defer to encoder->enable(). But we need to *know* whether
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+ * encoder->enable() will be called to do this:
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+ */
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+ if (drm_atomic_crtc_needs_modeset(crtc_state))
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+ mdp5_cstate->defer_start = true;
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return 0;
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}
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