96 lines
2.5 KiB
Diff
96 lines
2.5 KiB
Diff
From cf27cca5f287108e0c91643289fb431a77c1ece8 Mon Sep 17 00:00:00 2001
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From: ningyu <ningyu@eswincomputing.com>
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Date: Thu, 1 Aug 2024 17:32:12 +0800
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Subject: [PATCH 134/219] refactor:modify evb1 dts
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Changelogs:
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1. Modify evb1 dts, adjust mmz size to 6GB, in order to consistent with other board.
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Signed-off-by: ningyu <ningyu@eswincomputing.com>
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---
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arch/riscv/boot/dts/eswin/eic7700-evb.dts | 48 +++++------------------
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1 file changed, 10 insertions(+), 38 deletions(-)
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diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb.dts b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
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index fc7dd40a4bc4..854bd4a80e1d 100644
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--- a/arch/riscv/boot/dts/eswin/eic7700-evb.dts
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+++ b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
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@@ -23,9 +23,9 @@
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#define RTCCLK_FREQ 1000000
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#define LSPCLK_FREQ 200000000
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-/* reserve 2GB space for ddr ecc */
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-#define MEMORY_SIZE_H 0x3
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-#define MEMORY_SIZE_L 0x80000000
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+/* If wanna enable ECC capability of DDR, should reserve highest zone of 1/8 all space for it */
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+#define MEMORY_SIZE_H 0x4
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+#define MEMORY_SIZE_L 0x0
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#define CMA_SIZE 0x20000000
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#include "eswin-win2030-die0-soc.dtsi"
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@@ -89,54 +89,26 @@ npu0_reserved: sprammemory@59000000 {
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reg = <0x0 0x59000000 0x0 0x400000>;
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};
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- smpmemtest_rsv0@91200000 {
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- reg = <0 0x91200000 0 0x2000000>;
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- no-map;
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- };
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-
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- lpcpu0_reserved: lpcpu@a0000000 {
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+ g2d_4GB_boundary_reserved_4k {
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no-map;
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- reg = <0x0 0xa0000000 0x0 0x100000>;
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+ reg = <0x0 0xfffff000 0x0 0x1000>;
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};
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- secure_memory_nid_0_part_0 {
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- compatible = "eswin-reserve-memory";
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- reg = <0x0 0xb0000000 0x0 0x8000000>;
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+ g2d_8GB_boundary_reserved_4k {
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no-map;
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+ reg = <0x1 0xfffff000 0x0 0x1000>;
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};
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- secure_memory_nid_0_part_1 {
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- compatible = "eswin-reserve-memory";
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- reg = <0x0 (0xb0000000 + 0x8000000) 0x0 0x8000000>;
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+ g2d_12GB_boundary_reserved_4k {
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no-map;
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- };
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-
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- g2d_4GB_boundary_reserved_4k {
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- no-map;
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- reg = <0x0 0xfffff000 0x0 0x1000>;
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+ reg = <0x2 0xfffff000 0x0 0x1000>;
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};
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mmz_nid_0_part_0 {
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compatible = "eswin-reserve-memory";
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- reg = <0x1 0x40000000 0x2 0x80000000>;
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+ reg = <0x3 0x0 0x1 0x80000000>;
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no-map;
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};
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-
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- mmz_nid_0_part_1 {
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- compatible = "eswin-reserve-memory";
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- reg = <0x3 0xc0000000 0x0 0x40000000>;
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- no-map;
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- };
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- };
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-
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- soc {
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- reset_test@1e00e000 {
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- compatible = "reset_test";
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- resets = <&d0_reset SCPU_RST_CTRL SW_SCPU_BUS_RSTN>,
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- <&d0_reset SCPU_RST_CTRL SW_SCPU_CORE_RSTN>,
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- <&d0_reset SCPU_RST_CTRL SW_SCPU_DBG_RSTN>;
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- reset-names = "bus", "core", "dbg";
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- };
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};
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};
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--
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2.47.0
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