131 lines
4.7 KiB
Diff
131 lines
4.7 KiB
Diff
From c584b7c1e5d788952134eabc3addb89cbc0513e0 Mon Sep 17 00:00:00 2001
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From: Han Gao <gaohan@iscas.ac.cn>
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Date: Wed, 26 Jun 2024 21:42:42 +0800
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Subject: [PATCH 078/219] feat: enable h ext
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Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
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---
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.../boot/dts/eswin/eswin-win2030-arch-d2d.dtsi | 16 ++++++++--------
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.../riscv/boot/dts/eswin/eswin-win2030-arch.dtsi | 8 ++++----
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2 files changed, 12 insertions(+), 12 deletions(-)
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diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-arch-d2d.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-arch-d2d.dtsi
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index 08b35addb5b7..725d93d2165f 100644
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--- a/arch/riscv/boot/dts/eswin/eswin-win2030-arch-d2d.dtsi
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+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-arch-d2d.dtsi
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@@ -99,7 +99,7 @@ cpu_0: cpu@0 {
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mmu-type = "riscv,sv48";
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next-level-cache = <&L15>;
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reg = <0x0>;
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- riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
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+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb";
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riscv,pmpgranularity = <4096>;
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riscv,pmpregions = <8>;
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sifive,buserror = <&L16>;
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@@ -146,7 +146,7 @@ cpu_1: cpu@1 {
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mmu-type = "riscv,sv48";
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next-level-cache = <&L20>;
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reg = <0x1>;
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- riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
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+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb";
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riscv,pmpgranularity = <4096>;
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riscv,pmpregions = <8>;
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sifive,buserror = <&L21>;
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@@ -193,7 +193,7 @@ cpu_2: cpu@2 {
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mmu-type = "riscv,sv48";
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next-level-cache = <&L25>;
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reg = <0x2>;
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- riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
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+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb";
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riscv,pmpgranularity = <4096>;
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riscv,pmpregions = <8>;
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sifive,buserror = <&L26>;
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@@ -240,7 +240,7 @@ cpu_3: cpu@3 {
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mmu-type = "riscv,sv48";
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next-level-cache = <&L30>;
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reg = <0x3>;
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- riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
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+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb";
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riscv,pmpgranularity = <4096>;
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riscv,pmpregions = <8>;
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sifive,buserror = <&L31>;
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@@ -297,7 +297,7 @@ cpu_4: cpu@4 {
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#else
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reg = <0x4>;
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#endif
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- riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
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+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb";
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riscv,pmpgranularity = <4096>;
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riscv,pmpregions = <8>;
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#if (CHIPLET_AND_DIE & 0x2)
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@@ -344,7 +344,7 @@ cpu_5: cpu@5 {
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mmu-type = "riscv,sv48";
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next-level-cache = <&D2L2_1>;
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reg = <0x5>;
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- riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
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+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb";
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riscv,pmpgranularity = <4096>;
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riscv,pmpregions = <8>;
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#if (CHIPLET_AND_DIE & 0x2)
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@@ -390,7 +390,7 @@ cpu_6: cpu@6 {
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mmu-type = "riscv,sv48";
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next-level-cache = <&D2L2_2>;
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reg = <0x6>;
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- riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
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+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb";
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riscv,pmpgranularity = <4096>;
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riscv,pmpregions = <8>;
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#if (CHIPLET_AND_DIE & 0x2)
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@@ -436,7 +436,7 @@ cpu_7: cpu@7 {
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mmu-type = "riscv,sv48";
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next-level-cache = <&D2L2_3>;
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reg = <0x7>;
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- riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
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+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb";
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riscv,pmpgranularity = <4096>;
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riscv,pmpregions = <8>;
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#if (CHIPLET_AND_DIE & 0x2)
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diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-arch.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-arch.dtsi
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index 3571f134aacc..cde282a61863 100644
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--- a/arch/riscv/boot/dts/eswin/eswin-win2030-arch.dtsi
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+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-arch.dtsi
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@@ -66,7 +66,7 @@ L17: cpu@0 {
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mmu-type = "riscv,sv48";
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next-level-cache = <&L15>;
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reg = <0x0>;
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- riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb_sscofpmf";
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+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf";
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riscv,pmpgranularity = <4096>;
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riscv,pmpregions = <8>;
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sifive,buserror = <&L16>;
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@@ -108,7 +108,7 @@ L22: cpu@1 {
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mmu-type = "riscv,sv48";
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next-level-cache = <&L20>;
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reg = <0x1>;
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- riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb_sscofpmf";
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+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf";
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riscv,pmpgranularity = <4096>;
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riscv,pmpregions = <8>;
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sifive,buserror = <&L21>;
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@@ -150,7 +150,7 @@ L27: cpu@2 {
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mmu-type = "riscv,sv48";
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next-level-cache = <&L25>;
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reg = <0x2>;
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- riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb_sscofpmf";
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+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf";
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riscv,pmpgranularity = <4096>;
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riscv,pmpregions = <8>;
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sifive,buserror = <&L26>;
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@@ -192,7 +192,7 @@ L32: cpu@3 {
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mmu-type = "riscv,sv48";
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next-level-cache = <&L30>;
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reg = <0x3>;
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- riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb_sscofpmf";
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+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf";
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riscv,pmpgranularity = <4096>;
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riscv,pmpregions = <8>;
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sifive,buserror = <&L31>;
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--
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2.47.0
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