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6904001a3c
kernel/0009-feat-EVB-A2-dts-pcie-Added-EVB-A2-dts.patch
Jason Montleon 6904001a3c Update to 6.6.67
2024-12-19 16:34:44 -05:00

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From fe7c74cb3d4cbfa7957789002875ed628699842b Mon Sep 17 00:00:00 2001
From: ningyu <ningyu@eswincomputing.com>
Date: Sat, 18 May 2024 11:16:41 +0800
Subject: [PATCH 009/219] feat(EVB-A2 dts+pcie):Added EVB-A2 dts
Changelogs:
1.Added EVB-A2 dts file "eic7700-evb-a2.dts"
2.Added HiFive Premier dts file "hifive-premier-550.dts"
3.Updated files from 5.17 include EVB dts, pinctrl dtsi, di0 soc dtsi, defconfig
4.Added pcie driver
---
arch/riscv/boot/dts/eswin/Makefile | 4 +-
arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts | 905 ++++++++++++++++++
arch/riscv/boot/dts/eswin/eic7700-evb.dts | 112 ++-
.../riscv/boot/dts/eswin/eic7700-pinctrl.dtsi | 136 ++-
.../dts/eswin/eswin-win2030-die0-soc.dtsi | 332 ++-----
.../dts/eswin/eswin-win2030-die1-soc.dtsi | 72 +-
arch/riscv/boot/dts/eswin/eswin-win2030.dts | 69 +-
.../boot/dts/eswin/hifive-premier-550.dts | 861 +++++++++++++++++
arch/riscv/configs/win2030_defconfig | 32 +-
drivers/pci/controller/dwc/Kconfig | 8 +
drivers/pci/controller/dwc/Makefile | 1 +
drivers/pci/controller/dwc/pcie-eswin.c | 531 ++++++++++
12 files changed, 2663 insertions(+), 400 deletions(-)
create mode 100644 arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
create mode 100644 arch/riscv/boot/dts/eswin/hifive-premier-550.dts
create mode 100644 drivers/pci/controller/dwc/pcie-eswin.c
diff --git a/arch/riscv/boot/dts/eswin/Makefile b/arch/riscv/boot/dts/eswin/Makefile
index dd52dd167996..5f6f08e84743 100644
--- a/arch/riscv/boot/dts/eswin/Makefile
+++ b/arch/riscv/boot/dts/eswin/Makefile
@@ -1,4 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_SOC_SIFIVE) += eswin-win2030.dtb \
- eic7700-evb.dtb
+ eic7700-evb.dtb \
+ eic7700-evb-a2.dtb \
+ hifive-premier-550.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
new file mode 100644
index 000000000000..300eed57dca6
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
@@ -0,0 +1,905 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for Eswin EIC7700 SoC.
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+
+#define RTCCLK_FREQ 1000000
+#define LSPCLK_FREQ 200000000
+
+/* If wanna enable ECC capability of DDR, should reserve highest zone of 1/8 all space for it */
+#define MEMORY_SIZE_H 0x4
+#define MEMORY_SIZE_L 0x0
+#define CMA_SIZE 0x20000000
+
+#include "eswin-win2030-die0-soc.dtsi"
+#include "eic7700-pinctrl.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "ESWIN EIC7700";
+ compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000",
+ "sifive,fu740", "eswin,eic7700";
+
+ aliases {
+ serial0 = &d0_uart0;
+ ethernet0 = &d0_gmac0;
+ ethernet1 = &d0_gmac1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpus {
+ timebase-frequency = <RTCCLK_FREQ>;
+ };
+/*
+ memory@59000000 {
+ device_type = "memory";
+ reg = <0x0 0x59000000 0x0 0x400000>;
+ numa-node-id = <0>;
+ };
+*/
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 MEMORY_SIZE_H MEMORY_SIZE_L>;
+ numa-node-id = <0>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 CMA_SIZE>;
+ alignment = <0x0 0x1000>;
+ alloc-ranges = <0x0 0x80000000 MEMORY_SIZE_H MEMORY_SIZE_L>;
+ linux,cma-default;
+ };
+/*
+ npu0_reserved: sprammemory@59000000 {
+ no-map;
+ reg = <0x0 0x59000000 0x0 0x400000>;
+ };
+*/
+ /*
+ dsp_reserved0: dsp@90000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x90000000 0x0 0x1000000>;
+ reusable;
+ status = "okay";
+ };
+ */
+
+ dsp_reserved1: dsp@91000000 {
+ reg = <0 0x91000000 0 0x200000>;
+ no-map;
+ };
+
+ smpmemtest_rsv0@91200000 {
+ reg = <0 0x91200000 0 0x2000000>;
+ no-map;
+ };
+
+ lpcpu0_reserved: lpcpu@a0000000 {
+ no-map;
+ reg = <0x0 0xa0000000 0x0 0x100000>;
+ };
+
+ secure_memory_nid_0_part_0 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x0 0xb0000000 0x0 0x8000000>;
+ no-map;
+ };
+
+ secure_memory_nid_0_part_1 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x0 (0xb0000000 + 0x8000000) 0x0 0x8000000>;
+ no-map;
+ };
+
+ mmz_nid_0_part_0 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x1 0x40000000 0x2 0x80000000>;
+ no-map;
+ };
+
+ mmz_nid_0_part_1 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x3 0xc0000000 0x0 0x40000000>;
+ no-map;
+ };
+ };
+
+ soc {
+ reset_test@1e00e000 {
+ compatible = "reset_test";
+ resets = <&d0_reset SCPU_RST_CTRL SW_SCPU_BUS_RSTN>,
+ <&d0_reset SCPU_RST_CTRL SW_SCPU_CORE_RSTN>,
+ <&d0_reset SCPU_RST_CTRL SW_SCPU_DBG_RSTN>;
+ reset-names = "bus", "core", "dbg";
+ };
+ };
+ npu0_reserved: sprammemory@59000000 {
+ reg = <0x0 0x59000000 0x0 0x400000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio107_default &pinctrl_gpio108_default &pinctrl_gpio109_default>;
+
+ gpio-107 {
+ gpios = <&portd 11 GPIO_ACTIVE_HIGH>;
+ label = "power";
+ linux,default-trigger = "default-on";
+ };
+
+ gpio-108 {
+ gpios = <&portd 12 GPIO_ACTIVE_LOW>;
+ label = "heartbeat";
+ linux,default-trigger = "heartbeat";
+ };
+
+ gpio-109 {
+ gpios = <&portd 13 GPIO_ACTIVE_HIGH>;
+ label = "gpio-109";
+ linux,default-trigger = "default-off";
+ };
+
+ gpio-110 {
+ gpios = <&portd 14 GPIO_ACTIVE_HIGH>;
+ label = "gpio-109";
+ linux,default-trigger = "default-off";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ ok_key {
+ label = "OK";
+ linux,code = <KEY_OK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio6_default>;
+ gpios = <&porta 6 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&d0_clock {
+ status = "okay";
+};
+
+&d0_reset {
+ status = "okay";
+};
+
+&d0_pmu {
+ status = "okay";
+};
+
+&ddr0 {
+ status = "okay";
+};
+
+&ddr1 {
+ status = "okay";
+};
+
+&smmu0 {
+ status = "okay";
+};
+
+&smmu_pmu0 {
+ status = "disabled";
+};
+
+&dev_foo_a {
+ status = "okay";
+};
+
+&d0_cfg_noc {
+ status = "okay";
+};
+
+&d0_llc_noc {
+ status = "okay";
+ stat,0 = "TracePort:ddr0_p0_req";
+ stat,1 = "TracePort:ddr1_p0_req";
+ //latency,0 = "TracePort:llcnoc_trans_probe";
+ //pending,0 = "TracePort:llcnoc_trans_probe";
+};
+
+&d0_sys_noc {
+ status = "okay";
+
+ //eswin,DSPT-qos-owner;
+ //eswin,NPU-qos-owner;
+ //eswin,SPISLV_TBU3-qos-owner;
+
+ stat,0 = "TracePort:ddr0_p1_req",
+ "InitFlow:mcput_snoc_mp/I/0";
+
+ stat,1 = "TracePort:ddr0_p2_req",
+ "InitFlow:dspt_snoc/I/0",
+ "AddrBase:0x81000000", "AddrSize:0x30",
+ "Opcode:RdWrLockUrg", "Status:ReqRsp", "Length:0x8000", "Urgency:0x0";
+
+ stat,2 = "TracePort:ddr1_p1_req",
+ "Status:Req", "AddrSize:0x28";
+
+ stat,3 = "TracePort:ddr1_p2_req";
+
+ latency,0 = "TracePort:sysnoc_trans_probe_0", "AddrSize:0x0";
+ latency,1 = "TracePort:sysnoc_trans_probe_1","Mode:latency","AddrBase:0x82000000","AddrSize:0x28","Opcode:RdWr";
+ //latency,2 = "TracePort:sysnoc_trans_probe_2";
+
+ //pending,0 = "TracePort:sysnoc_trans_probe_0";
+ //pending,1 = "TracePort:sysnoc_trans_probe_1","Mode:latency","AddrBase:0x82000000","AddrSize:0x0","Opcode:RdWr";
+ pending,0 = "TracePort:sysnoc_trans_probe_2", "AddrSize:0x3";
+};
+
+&d0_media_noc {
+ status = "okay";
+
+ //eswin,GPU-qos-owner;
+ //eswin,TBU2-qos-owner;
+ //eswin,VC-qos-owner;
+
+ stat,0 = "TracePort:ddr0_p3_req";
+ stat,1 = "TracePort:ddr1_p3_req";
+ //latency,0 = "TracePort:mnoc_trans_probe";
+ //pending,0 = "TracePort:mnoc_trans_probe";
+};
+
+&d0_realtime_noc {
+ status = "okay";
+
+ //eswin,TBU0-qos-owner;
+ //eswin,VO-qos-owner;
+
+ stat,0 = "TracePort:ddr0_p4_req";
+ stat,1 = "TracePort:ddr1_p4_req";
+ //latency,0 = "TracePort:rnoc_trans_probe";
+ //pending,0 = "TracePort:rnoc_trans_probe";
+};
+
+&d0_noc_wdt {
+ status = "okay";
+};
+
+&d0_ipc_scpu {
+ status = "okay";
+};
+
+&d0_lpcpu {
+ status = "disabled";
+};
+
+&pcie {
+ status = "okay";
+};
+
+&d0_npu{
+ status = "okay";
+};
+
+&d0_dsp_subsys {
+ status = "okay";
+};
+
+&d0_dsp0 {
+ status = "okay";
+};
+
+&d0_dsp1 {
+ status = "okay";
+};
+
+&d0_dsp2 {
+ status = "okay";
+};
+
+&d0_dsp3 {
+ status = "okay";
+};
+
+&gpu0 {
+ status = "okay";
+};
+
+&gc820 {
+ status = "okay";
+};
+
+&vdec0 {
+ status = "okay";
+};
+
+&venc0 {
+ status = "okay";
+};
+
+&video_output {
+ status = "okay";
+};
+
+&dc {
+ status = "okay";
+};
+
+&dc_test {
+ status = "disabled";
+};
+
+&virtual_display {
+ status = "okay";
+};
+
+&dsi_output {
+ status = "okay";
+};
+
+&dsi_controller {
+ status = "okay";
+};
+
+&dsi_panel {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio5_default &pinctrl_gpio111_default>;
+ backlight0-gpios = <&porta 5 GPIO_ACTIVE_HIGH>;
+ rst-gpios = <&portd 15 GPIO_ACTIVE_HIGH>;
+};
+
+&dw_hdmi {
+ status = "okay";
+ eswin-plat = <1>;
+ ports {
+ port@2 {
+ reg = <2>;
+ hdmi_in_i2s: endpoint@1 {
+ system-clock-frequency = <12288000>;
+ remote-endpoint = <&d0_i2s0_endpoint>;
+ };
+ };
+ };
+};
+
+&dw_hdmi_hdcp2 {
+ status = "okay";
+};
+
+&d0_i2s0 {
+ status = "okay";
+ eswin-plat = <1>;
+ d0_i2s0_port: port {
+ d0_i2s0_endpoint: endpoint {
+ remote-endpoint = <&hdmi_in_i2s>;
+ dai-format = "i2s";
+ };
+ };
+};
+
+&d0_i2s1 {
+ status = "okay";
+ eswin-plat = <1>;
+ d0_i2s1_port: port {
+ d0_i2s1_endpoint: endpoint {
+ remote-endpoint = <&d0_codec0_endpoint>;
+ dai-format = "i2s";
+ };
+ };
+};
+
+&d0_i2s2 {
+ status = "okay";
+ eswin-plat = <1>;
+ d0_i2s2_port: port {
+ d0_i2s2_endpoint: endpoint {
+ remote-endpoint = <&d0_codec1_endpoint>;
+ dai-format = "i2s";
+ };
+ };
+};
+
+&d0_graphcard0 {
+ status = "okay";
+ dais = <&d0_i2s1_port>;
+};
+
+&d0_graphcard1 {
+ status = "okay";
+ dais = <&d0_i2s2_port>;
+};
+
+&d0_graphcard2 {
+ status = "okay";
+ dais = <&d0_i2s0_port>;
+};
+
+&isp_0 {
+ status = "disabled";
+};
+
+&isp_1 {
+ status = "disabled";
+};
+
+&dewarp {
+ status = "okay";
+};
+
+&mipi_dphy_rx {
+ status = "disabled";
+};
+
+&csi_dma0 {
+ status = "disabled";
+};
+
+&csi_dma1 {
+ status = "disabled";
+};
+
+&csi2_0 {
+ status = "disabled";
+};
+
+&csi2_1 {
+ status = "disabled";
+};
+
+&sdhci_emmc {
+ /* emmc */
+ status = "okay";
+ delay_code = <0x17>;
+ drive-impedance-ohm = <50>;
+ enable-cmd-pullup;
+ enable-data-pullup;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_emmc_led_control_default>;
+};
+
+&sdio0 {
+ /* sd card */
+ status = "okay";
+ delay_code = <0x16>;
+ drive-impedance-ohm = <33>;
+ enable-cmd-pullup;
+ enable-data-pullup;
+ no-sdio;
+};
+
+&sdio1 {
+ /* wifi module */
+ status = "okay";
+ delay_code = <0x21>;
+ drive-impedance-ohm = <33>;
+ enable-cmd-pullup;
+ enable-data-pullup;
+ enable_sw_tuning;
+ non-removable;
+ no-sd;
+};
+
+&d0_gmac0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio94_default>;
+ rst-gpios = <&portc 30 GPIO_ACTIVE_LOW>;
+ eswin,rgmiisel = <&pinctrl 0x290 0x3>;
+ eswin,led-cfgs = <0x6100 0xa40 0x420>;
+
+ status = "okay";
+};
+
+&d0_gmac1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio16_default>;
+ rst-gpios = <&porta 16 GPIO_ACTIVE_LOW>;
+ eswin,rgmiisel = <&pinctrl 0x294 0x3>;
+ eswin,led-cfgs = <0x6100 0xa40 0x420>;
+
+ status = "okay";
+};
+
+&d0_sata {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sata_act_led_default>;
+};
+
+&d0_usbdrd3_0 {
+ status = "okay";
+};
+
+&d0_usbdrd_dwc3_0 {
+ status = "okay";
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+};
+
+&d0_usbdrd3_1 {
+ status = "okay";
+};
+
+&d0_usbdrd_dwc3_1 {
+ status = "okay";
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+};
+
+&d0_dmac0 {
+ status = "okay";
+};
+
+&d0_aon_dmac {
+ status = "okay";
+};
+
+&d0_uart0 {
+ /* debug */
+ status = "okay";
+};
+
+&d0_uart1 {
+ /* BT M.2 KEY-E */
+ status = "okay";
+};
+
+&d0_uart2 {
+ /* RS232 DB9 */
+ status = "okay";
+};
+
+&d0_uart3 {
+ /* unused */
+ status = "disabled";
+};
+
+&d0_uart4 {
+ /* unused */
+ status = "disabled";
+};
+
+&ssi0 {
+ /* spi flash */
+ status = "okay";
+ num-cs = <2>;
+ spi-flash@0 {
+ compatible = "winbond,w25q128fw",
+ "jedec,spi-nor";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <4800000>;
+ rx-sample-delay-ns = <10>;
+ };
+ spi-flash@1 {
+ compatible = "winbond,w25q128fw",
+ "jedec,spi-nor";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <4800000>;
+ rx-sample-delay-ns = <10>;
+ };
+};
+
+&ssi1 {
+ /* spi flash */
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi2_default>;
+ num-cs = <2>;
+ spi-flash@0 {
+ compatible = "winbond,w25q128fw",
+ "jedec,spi-nor";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <4800000>;
+ rx-sample-delay-ns = <10>;
+ };
+ spi-flash@1 {
+ compatible = "winbond,w25q128fw",
+ "jedec,spi-nor";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <4800000>;
+ rx-sample-delay-ns = <10>;
+ };
+};
+
+&bootspi {
+ /* spi flash */
+ status = "okay";
+ num-cs = <1>;
+ cs-gpios = <&portd 0 GPIO_ACTIVE_LOW>;
+ spi-flash@0 {
+ compatible = "winbond,w25q128jw",
+ "jedec,spi-nor";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <4800000>;
+ rx-sample-delay-ns = <10>;
+ };
+};
+
+&d0_mbox0 {
+ status = "okay";
+};
+
+&d0_mbox1 {
+ status = "okay";
+};
+
+&d0_mbox2 {
+ status = "okay";
+};
+
+&d0_mbox3 {
+ status = "okay";
+};
+
+&d0_mbox4 {
+ status = "okay";
+};
+
+&d0_mbox5 {
+ status = "okay";
+};
+
+&d0_mbox6 {
+ status = "okay";
+};
+
+&d0_mbox7 {
+ status = "okay";
+};
+
+&fan_control {
+ status = "okay";
+};
+
+&d0_i2c0 {
+ /* codec es8388 */
+ status = "okay";
+ d0_es8388_0: es8388-0@10 {
+ compatible = "eswin,es8388";
+ reg = <0x10>;
+ #sound-dai-cells = <0>;
+ port {
+ d0_codec0_endpoint: endpoint {
+ system-clock-frequency = <12288000>;
+ remote-endpoint = <&d0_i2s1_endpoint>;
+ };
+ };
+ };
+ d0_es8388_1: es8388-1@11 {
+ compatible = "eswin,es8388";
+ reg = <0x11>;
+ #sound-dai-cells = <0>;
+ port {
+ d0_codec1_endpoint: endpoint {
+ system-clock-frequency = <12288000>;
+ remote-endpoint = <&d0_i2s2_endpoint>;
+ };
+ };
+ };
+};
+
+&d0_i2c1 {
+ /* mpq8785 */
+ status = "okay";
+ eswin,syscfg = <&d0_sys_con 0x3C0 15>;
+ iic_hold_time = <0x40>;
+ mpq8785@10 {
+ compatible = "mps,mpq8785";
+ reg = <0x10>;
+ regulators{
+ npu_vcc1:npu_svcc{
+ regulator-name="NPU_SVCC";
+ regulator-min-microvolt=<100000>;
+ regulator-max-microvolt=<1600000>;
+ regulator-min-microamp=<50000000>;
+ regulator-max-microamp=<90000000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&d0_i2c2 {
+ /* mipi dsi */
+ status = "disabled";
+};
+
+&d0_i2c3 {
+ /* mipi csi0/csi1 */
+ status = "disabled";
+};
+
+&d0_i2c4 {
+ /* mipi csi2/csi3 */
+ status = "disabled";
+};
+
+&d0_i2c5 {
+ /* mipi csi4/csi5 */
+ status = "disabled";
+};
+
+&d0_i2c6 {
+ /* unused */
+ status = "disabled";
+};
+
+&d0_i2c7 {
+ /* unused */
+ status = "disabled";
+};
+
+&d0_i2c8 {
+ /* io extended for mipi csi */
+ status = "disabled";
+};
+
+&d0_i2c9 {
+ /* unused */
+ status = "disabled";
+};
+
+&d0_aon_i2c0 {
+ /* temp sensor & rtc */
+ status = "okay";
+ eswin,syscfg = <&d0_sys_con 0x3C0 16>;
+ rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+};
+
+&d0_aon_i2c1 {
+ /* ina226x4 */
+ status = "okay";
+ eswin,syscfg = <&d0_sys_con 0x3C0 15>;
+ iic_hold_time = <0x40>;
+
+ u80_cpu: ina226@45 {
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u80_CPU";
+ reg = <0x45>;
+ shunt-resistor = <1000>;
+ };
+ u82_soc: ina226@44 {
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u82_soc";
+ reg = <0x44>;
+ shunt-resistor = <1000>;
+ };
+ u83_lpddr4: ina226@41 {
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u83_lpddr4";
+ reg = <0x41>;
+ shunt-resistor = <1000>;
+ };
+ u99_dc: ina226@4c {
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u99_dc";
+ reg = <0x4c>;
+ shunt-resistor = <1000>;
+ };
+};
+
+&pwm0 {
+ /* fan */
+ status = "okay";
+};
+
+&pvt0 {
+ status = "okay";
+};
+
+&pvt1 {
+ status = "okay";
+};
+
+&wdt0 {
+ status = "disabled";
+};
+
+&wdt1 {
+ status = "disabled";
+};
+
+&wdt2 {
+ status = "disabled";
+};
+
+&wdt3 {
+ status = "disabled";
+};
+
+&die0_rtc {
+ status = "okay";
+};
+
+&timer0 {
+ status = "okay";
+};
+
+&timer1 {
+ status = "okay";
+};
+
+&timer2 {
+ status = "okay";
+};
+
+&timer3 {
+ status = "okay";
+};
+
+&pinctrl {
+ status = "okay";
+};
+
+/* GPIO Function Description
+
+ gpio0 : pcie prstn(I)
+ gpio5 : led back light power on/off(O)
+ gpio6 : system key(I)
+ gpio10 : dsi touch interrupt(I)
+ gpio11 : head phone plug/unplug detection2(I)
+ gpio12 : tf card power on/off(O)
+ gpio14 : bt wake host(I)
+ gpio15 : wlan wake host(I)
+ gpio16 : gphy1 resetn(O)
+ gpio28 : head phone plug/unplug detection1(I)
+ gpio34 : m.2 power on/off(O)
+ gpio94 : gphy0 resetn(O)
+ gpio106 : touch reset(O)
+ gpio107 : system led0(O)
+ gpio108 : system led1(O)
+ gpio109 : system led2(O)
+ gpio110 : system led3(O)
+ gpio111 : mipi dsi resetn(O)
+*/
+
+&gpio0 {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb.dts b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
index 25bdb68ef921..ba2b6a3ea3b5 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
@@ -26,7 +26,7 @@
/* reserve 2GB space for ddr ecc */
#define MEMORY_SIZE_H 0x3
#define MEMORY_SIZE_L 0x80000000
-#define CMA_SIZE 0x10000000
+#define CMA_SIZE 0x20000000
#include "eswin-win2030-die0-soc.dtsi"
#include "eic7700-pinctrl.dtsi"
@@ -125,13 +125,13 @@ secure_memory_nid_0_part_1 {
mmz_nid_0_part_0 {
compatible = "eswin-reserve-memory";
- reg = <0x1 0x80000000 0x1 0x80000000>;
+ reg = <0x1 0x40000000 0x2 0x80000000>;
no-map;
};
mmz_nid_0_part_1 {
compatible = "eswin-reserve-memory";
- reg = <0x3 0x0 0x1 0x0>;
+ reg = <0x3 0xc0000000 0x0 0x40000000>;
no-map;
};
};
@@ -145,9 +145,7 @@ reset_test@1e00e000 {
reset-names = "bus", "core", "dbg";
};
};
-
npu0_reserved: sprammemory@59000000 {
- no-map;
reg = <0x0 0x59000000 0x0 0x400000>;
};
};
@@ -161,15 +159,15 @@ &d0_reset {
};
&d0_pmu {
- status = "disabled";
+ status = "okay";
};
&ddr0 {
- status = "disabled";
+ status = "okay";
};
&ddr1 {
- status = "disabled";
+ status = "okay";
};
&smmu0 {
@@ -251,7 +249,7 @@ &d0_realtime_noc {
};
&d0_noc_wdt {
- status = "disabled";
+ status = "okay";
};
&d0_ipc_scpu {
@@ -270,7 +268,7 @@ &pcie {
status = "okay";
};
-&d0_nvdla {
+&d0_npu{
status = "okay";
};
@@ -294,10 +292,6 @@ &d0_dsp3 {
status = "okay";
};
-&d0_sofdsp {
- status = "disabled";
-};
-
&gpu0 {
status = "okay";
};
@@ -318,11 +312,11 @@ &video_output {
status = "okay";
};
-&dc8k {
+&dc {
status = "okay";
};
-&dc8k_test {
+&dc_test {
status = "disabled";
};
@@ -331,11 +325,19 @@ &virtual_display {
};
&dsi_output {
- status = "disabled";
+ status = "okay";
};
&dsi_controller {
- status = "disabled";
+ status = "okay";
+};
+
+&dsi_panel {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio7_default &pinctrl_gpio111_default>;
+ backlight0-gpios = <&porta 7 GPIO_ACTIVE_HIGH>;
+ rst-gpios = <&portd 15 GPIO_ACTIVE_HIGH>;
};
&dw_hdmi {
@@ -401,10 +403,6 @@ d0_i2s2_endpoint: endpoint {
};
};
-&d0_soundcard {
- status = "disabled";
-};
-
&d0_graphcard0 {
status = "okay";
dais = <&d0_i2s1_port>;
@@ -420,14 +418,6 @@ &d0_graphcard2 {
dais = <&d0_i2s0_port0>, <&d0_i2s0_port1>;
};
-&d0_dummy_codec {
- status = "disabled";
-};
-
-&d0_thruout{
- status = "disabled";
-};
-
&isp_0 {
status = "disabled";
};
@@ -436,7 +426,7 @@ &isp_1 {
status = "disabled";
};
-&dw200 {
+&dewarp {
status = "okay";
};
@@ -463,16 +453,32 @@ &csi2_1 {
&sdhci_emmc {
/* emmc */
status = "okay";
+ delay_code = <0x17>;
+ drive-impedance-ohm = <50>;
+ enable-cmd-pullup;
+ enable-data-pullup;
};
&sdio0 {
/* sd card */
status = "okay";
+ delay_code = <0x16>;
+ drive-impedance-ohm = <33>;
+ enable-cmd-pullup;
+ enable-data-pullup;
+ no-sdio;
};
&sdio1 {
/* wifi module */
- status = "disabled";
+ status = "okay";
+ delay_code = <0x21>;
+ drive-impedance-ohm = <33>;
+ enable-cmd-pullup;
+ enable-data-pullup;
+ enable_sw_tuning;
+ non-removable;
+ no-sd;
};
&d0_gmac0 {
@@ -481,6 +487,7 @@ &d0_gmac0 {
rst-gpios = <&portc 30 GPIO_ACTIVE_LOW>;
eswin,rgmiisel = <&pinctrl 0x290 0x3>;
eswin,led-cfgs = <0x6251 0x6251 0x6251>;
+
status = "okay";
};
@@ -490,6 +497,7 @@ &d0_gmac1 {
rst-gpios = <&porta 16 GPIO_ACTIVE_LOW>;
eswin,rgmiisel = <&pinctrl 0x294 0x3>;
eswin,led-cfgs = <0x6251 0x6251 0x6251>;
+
status = "okay";
};
@@ -574,7 +582,7 @@ spi-flash@1 {
&ssi1 {
/* spi flash */
- status = "okay";
+ status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2_default>;
num-cs = <2>;
@@ -598,6 +606,22 @@ spi-flash@1 {
};
};
+&bootspi {
+ /* spi flash */
+ status = "okay";
+ num-cs = <1>;
+ cs-gpios = <&portd 0 GPIO_ACTIVE_LOW>;
+ spi-flash@0 {
+ compatible = "winbond,w25q128jw",
+ "jedec,spi-nor";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <4800000>;
+ rx-sample-delay-ns = <10>;
+ };
+};
+
&d0_mbox0 {
status = "okay";
};
@@ -631,7 +655,7 @@ &d0_mbox7 {
};
&fan_control {
- status = "disabled";
+ status = "okay";
};
&d0_i2c0 {
@@ -731,24 +755,18 @@ &d0_aon_i2c1 {
/* mpq8785 & ina226x4 */
status = "okay";
eswin,syscfg = <&d0_sys_con 0x3C0 15>;
- iic_hold_time = <0x10>;
+ iic_hold_time = <0x40>;
mpq8785@10 {
compatible = "mps,mpq8785";
reg = <0x10>;
regulators{
npu_vcc1:npu_svcc{
regulator-name="NPU_SVCC";
- regulator-min-microvolt=<1000000>;
- regulator-max-microvolt=<6400000>;
- regulator-min-microamp=<10000000>;
- regulator-max-microamp=<40000000>;
- };
- npu_vcc2:npu_lvcc{
- regulator-name="NPU_LVCC";
- regulator-min-microvolt=<1000000>;
- regulator-max-microvolt=<8000000>;
- regulator-min-microamp=<10000000>;
- regulator-max-microamp=<40000000>;
+ regulator-min-microvolt=<100000>;
+ regulator-max-microvolt=<1600000>;
+ regulator-min-microamp=<50000000>;
+ regulator-max-microamp=<90000000>;
+ regulator-always-on;
};
};
};
@@ -784,7 +802,7 @@ u99_dc: ina226@4c {
&pwm0 {
/* fan */
- status = "disabled";
+ status = "okay";
};
&pvt0 {
diff --git a/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi b/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
index 1b194f9d04ee..0529f98d4dd3 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
@@ -221,7 +221,6 @@ mux {
function = "uart2_func";
};
};
- //pwm0: fan_pwm
pinctrl_pwm0_default: pwm0-default{
mux {
groups = "pwm0_group";
@@ -349,6 +348,11 @@ mux {
groups = "emmc_led_control_group";
function = "emmc_led_control_func";
};
+ conf {
+ groups = "emmc_led_control_group";
+ input-enable = <0>;
+ bias-pull-down = <1>;
+ };
};
pinctrl_sd0_led_control_default: sd0_led_control-default{
mux {
@@ -454,12 +458,22 @@ mux {
groups = "gpio5_group";
function = "gpio5_func";
};
+ conf {
+ groups = "gpio5_group";
+ input-enable = <1>;
+ bias-pull-up = <1>;
+ };
};
pinctrl_gpio6_default: gpio6-default{
mux {
groups = "gpio6_group";
function = "gpio6_func";
};
+ conf {
+ groups = "gpio6_group";
+ input-enable = <1>;
+ bias-pull-down = <1>;
+ };
};
pinctrl_gpio7_default: gpio7-default{
mux {
@@ -468,7 +482,7 @@ mux {
};
conf {
groups = "gpio7_group";
- input-enable = <0>;
+ input-enable = <1>;
bias-pull-down = <1>;
};
};
@@ -556,30 +570,55 @@ mux {
groups = "gpio17_group";
function = "gpio17_func";
};
+ conf {
+ groups = "gpio17_group";
+ input-enable = <1>;
+ bias-pull-down = <1>;
+ };
};
pinctrl_gpio18_default: gpio18-default{
mux {
groups = "gpio18_group";
function = "gpio18_func";
};
+ conf {
+ groups = "gpio18_group";
+ input-enable = <1>;
+ bias-pull-down = <1>;
+ };
};
pinctrl_gpio19_default: gpio19-default{
mux {
groups = "gpio19_group";
function = "gpio19_func";
};
+ conf {
+ groups = "gpio19_group";
+ input-enable = <1>;
+ bias-pull-down = <1>;
+ };
};
pinctrl_gpio20_default: gpio20-default{
mux {
groups = "gpio20_group";
function = "gpio20_func";
};
+ conf {
+ groups = "gpio20_group";
+ input-enable = <1>;
+ bias-pull-down = <1>;
+ };
};
pinctrl_gpio21_default: gpio21-default{
mux {
groups = "gpio21_group";
function = "gpio21_func";
};
+ conf {
+ groups = "gpio21_group";
+ input-enable = <1>;
+ bias-pull-down = <1>;
+ };
};
pinctrl_gpio22_default: gpio22-default{
mux {
@@ -669,36 +708,66 @@ mux {
groups = "gpio35_group";
function = "gpio35_func";
};
+ conf {
+ groups = "gpio35_group";
+ input-enable = <1>;
+ bias-pull-down = <1>;
+ };
};
pinctrl_gpio36_default: gpio36-default{
mux {
groups = "gpio36_group";
function = "gpio36_func";
};
+ conf {
+ groups = "gpio36_group";
+ input-enable = <1>;
+ bias-pull-down = <1>;
+ };
};
pinctrl_gpio37_default: gpio37-default{
mux {
groups = "gpio37_group";
function = "gpio37_func";
};
+ conf {
+ groups = "gpio37_group";
+ input-enable = <1>;
+ bias-pull-down = <1>;
+ };
};
pinctrl_gpio38_default: gpio38-default{
mux {
groups = "gpio38_group";
function = "gpio38_func";
};
+ conf {
+ groups = "gpio38_group";
+ input-enable = <1>;
+ bias-pull-down = <1>;
+ };
};
pinctrl_gpio39_default: gpio39-default{
mux {
groups = "gpio39_group";
function = "gpio39_func";
};
+ conf {
+ groups = "gpio39_group";
+ input-enable = <1>;
+ bias-pull-down = <1>;
+ };
};
pinctrl_gpio40_default: gpio40-default{
mux {
groups = "gpio40_group";
function = "gpio40_func";
};
+ conf {
+ groups = "gpio40_group";
+ input-enable = <1>;
+ bias-pull-down = <1>;
+ };
};
pinctrl_gpio41_default: gpio41-default{
mux {
@@ -711,6 +780,11 @@ mux {
groups = "gpio42_group";
function = "gpio42_func";
};
+ conf {
+ groups = "gpio42_group";
+ input-enable = <1>;
+ bias-pull-down = <1>;
+ };
};
pinctrl_gpio43_default: gpio43-default{
mux {
@@ -735,12 +809,22 @@ mux {
groups = "gpio46_group";
function = "gpio46_func";
};
+ conf {
+ groups = "gpio46_group";
+ input-enable = <1>;
+ bias-pull-down = <1>;
+ };
};
pinctrl_gpio47_default: gpio47-default{
mux {
groups = "gpio47_group";
function = "gpio47_func";
};
+ conf {
+ groups = "gpio47_group";
+ input-enable = <1>;
+ bias-pull-down = <1>;
+ };
};
pinctrl_gpio48_default: gpio48-default{
mux {
@@ -771,12 +855,22 @@ mux {
groups = "gpio52_group";
function = "gpio52_func";
};
+ conf {
+ groups = "gpio52_group";
+ input-enable = <1>;
+ bias-pull-down = <1>;
+ };
};
pinctrl_gpio53_default: gpio53-default{
mux {
groups = "gpio53_group";
function = "gpio53_func";
};
+ conf {
+ groups = "gpio53_group";
+ input-enable = <1>;
+ bias-pull-down = <1>;
+ };
};
pinctrl_gpio54_default: gpio54-default{
mux {
@@ -843,24 +937,44 @@ mux {
groups = "gpio64_group";
function = "gpio64_func";
};
+ conf {
+ groups = "gpio64_group";
+ input-enable = <1>;
+ bias-pull-down = <1>;
+ };
};
pinctrl_gpio65_default: gpio65-default{
mux {
groups = "gpio65_group";
function = "gpio65_func";
};
+ conf {
+ groups = "gpio65_group";
+ input-enable = <1>;
+ bias-pull-down = <1>;
+ };
};
pinctrl_gpio66_default: gpio66-default{
mux {
groups = "gpio66_group";
function = "gpio66_func";
};
+ conf {
+ groups = "gpio66_group";
+ input-enable = <1>;
+ bias-pull-down = <1>;
+ };
};
pinctrl_gpio67_default: gpio67-default{
mux {
groups = "gpio67_group";
function = "gpio67_func";
};
+ conf {
+ groups = "gpio67_group";
+ input-enable = <1>;
+ bias-pull-down = <1>;
+ };
};
pinctrl_gpio68_default: gpio68-default{
mux {
@@ -1011,12 +1125,22 @@ mux {
groups = "gpio92_group";
function = "gpio92_func";
};
+ conf {
+ groups = "gpio92_group";
+ input-enable = <1>;
+ bias-pull-down = <1>;
+ };
};
pinctrl_gpio93_default: gpio93-default{
mux {
groups = "gpio93_group";
function = "gpio93_func";
};
+ conf {
+ groups = "gpio93_group";
+ input-enable = <1>;
+ bias-pull-down = <1>;
+ };
};
pinctrl_gpio94_default: gpio94-default{
mux {
@@ -1113,7 +1237,7 @@ mux {
};
conf {
groups = "gpio107_group";
- input-enable = <0>;
+ input-enable = <1>;
bias-pull-down = <1>;
};
};
@@ -1124,7 +1248,7 @@ mux {
};
conf {
groups = "gpio108_group";
- input-enable = <0>;
+ input-enable = <1>;
bias-pull-down = <1>;
};
};
@@ -1135,7 +1259,7 @@ mux {
};
conf {
groups = "gpio109_group";
- input-enable = <0>;
+ input-enable = <1>;
bias-pull-down = <1>;
};
};
@@ -1146,7 +1270,7 @@ mux {
};
conf {
groups = "gpio110_group";
- input-enable = <0>;
+ input-enable = <1>;
bias-pull-down = <1>;
};
};
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
index e56ff06664f1..453f15acbd15 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
@@ -201,6 +201,7 @@ d0_noc_wdt:noc@51810324 {
<416>, <417>, <418>, <419>, <420>,
<421>, <422>, <423>, <424>, <425>,
<426>;
+ eswin,syscrg_csr = <&d0_sys_crg 0x100 0xffff>; //timeout paramerter
status = "disabled";
};
};
@@ -276,7 +277,7 @@ dev_foo_a: E21@0 {
compatible = "riscv,dev-foo-a";
#size-cells = <2>;
dma-ranges = <0x0 0x20000000 0x0 0xc0000000 0x0 0x40000000>;
- /*iommus = <&smmu0 WIN2030_SID_DEV_FOO_A>;*/
+ iommus = <&smmu0 WIN2030_SID_DEV_FOO_A>;
tbus = <WIN2030_TBUID_0xF00>;
/*
tbus = <WIN2030_TBUID_0x0>,
@@ -295,7 +296,6 @@ d0_pmu: power-controller@51808000 {
compatible = "eswin,win2030-pmu-controller";
reg = <0x0 0x51808000 0x0 0x8000>;
numa-node-id = <0>;
-
d0_pmu_pcie: win2030-pmu-controller-port@0 {
compatible = "eswin,win2030-pmu-controller-port";
reg_base = <0x0>;
@@ -305,15 +305,17 @@ d0_pmu_pcie: win2030-pmu-controller-port@0 {
reset_delay = <2 4 2 2>;
clamp_delay = <3 3 2 2>;
label = "D0_PCIE";
+ tbus = <WIN2030_TBUID_PCIE>;
};
d0_pmu_dsp1: win2030-pmu-controller-port@40 {
compatible = "eswin,win2030-pmu-controller-port";
reg_base = <0x40>;
- power_status = <0>;
+ power_status = <1>;
power_delay = <6 6 3 3>;
clock_delay = <4 2 2 2>;
reset_delay = <2 4 2 2>;
clamp_delay = <3 3 2 2>;
+ tbus = <WIN2030_TBUID_DSP1>;
label = "D0_DSP1";
};
d0_pmu_vi: win2030-pmu-controller-port@80 {
@@ -324,12 +326,13 @@ d0_pmu_vi: win2030-pmu-controller-port@80 {
clock_delay = <4 2 2 2>;
reset_delay = <2 4 2 2>;
clamp_delay = <3 3 2 2>;
+ tbus = <WIN2030_TBUID_ISP>,<WIN2030_TBUID_DW>;
label = "D0_VI";
};
d0_pmu_vo: win2030-pmu-controller-port@c0 {
compatible = "eswin,win2030-pmu-controller-port";
reg_base = <0xc0>;
- power_status = <0>;
+ power_status = <1>;
power_delay = <6 6 3 3>;
clock_delay = <4 2 2 2>;
reset_delay = <2 4 2 2>;
@@ -339,31 +342,34 @@ d0_pmu_vo: win2030-pmu-controller-port@c0 {
d0_pmu_codec: win2030-pmu-controller-port@140 {
compatible = "eswin,win2030-pmu-controller-port";
reg_base = <0x140>;
- power_status = <0>;
+ power_status = <1>;
power_delay = <6 6 3 3>;
clock_delay = <4 2 2 2>;
reset_delay = <2 4 2 2>;
clamp_delay = <3 3 2 2>;
+ tbus = <WIN2030_TBUID_VDEC>, <WIN2030_TBUID_JDEC>,<WIN2030_TBUID_VENC>, <WIN2030_TBUID_JENC>;
label = "D0_CODEC";
};
d0_pmu_dsp2: win2030-pmu-controller-port@200 {
compatible = "eswin,win2030-pmu-controller-port";
reg_base = <0x200>;
- power_status = <0>;
+ power_status = <1>;
power_delay = <6 6 3 3>;
clock_delay = <4 2 2 2>;
reset_delay = <2 4 2 2>;
clamp_delay = <3 3 2 2>;
+ tbus = <WIN2030_TBUID_DSP2>;
label = "D0_DSP2";
};
d0_pmu_dsp3: win2030-pmu-controller-port@240 {
compatible = "eswin,win2030-pmu-controller-port";
reg_base = <0x240>;
- power_status = <0>;
+ power_status = <1>;
power_delay = <6 6 3 3>;
clock_delay = <4 2 2 2>;
reset_delay = <2 4 2 2>;
clamp_delay = <3 3 2 2>;
+ tbus = <WIN2030_TBUID_DSP3>;
label = "D0_DSP3";
};
};
@@ -489,12 +495,12 @@ noc {
#include "eswin-win2030-die0-noc.dtsi"
};
- d0_nvdla: nvdla-controller@51c00000 {
+ d0_npu: eswin-npu@51c00000 {
compatible = "eswin,npu0";
reg = <0x0 0x51c00000 0x0 0x400000>;
interrupt-parent = <&plic0>;
interrupts = <387 16>;
- spram-region = <&npu0_reserved>;
+ /*spram-region = <&npu0_reserved>;*/
#size-cells = <2>;
dma-ranges = <0x1 0x0 0x0 0xc0000000 0x1ff 0x0>;
iommus = <&smmu0 WIN2030_SID_NPU_DMA>;
@@ -502,6 +508,11 @@ d0_nvdla: nvdla-controller@51c00000 {
dsp-avail-num = <1>;
spram-size = <0x400000>;
npu_mbox = <&d0_mbox2>;
+ clocks = <&d0_clock WIN2030_CLK_NPU_ACLK>,
+ <&d0_clock WIN2030_CLK_NPU_CFG_CLK>,
+ <&d0_clock WIN2030_CLK_NPU_CLK>,
+ <&d0_clock WIN2030_CLK_NPU_E31_CLK>;
+ clock-names = "aclk", "cfg_clk", "core_clk", "e31_core_clk";
resets = <&d0_reset NPU_RST_CTRL SW_NPU_E31CORE_RSTN>;
reset-names = "e31_core";
@@ -563,8 +574,10 @@ d0_dsp0:es_dsp@0 {
ESWIN_MAILBOX_DSP_0_TO_U84_REG_BASE
ESWIN_MAILBOX_WR_LOCK_BIT_DSP_0
ESWIN_MAILBOX_U84_TO_DSP_0_REG_BASE
- ESWIN_MAIBOX_U84_IRQ_BIT>;
- device-uart = <0x50910000>;
+ ESWIN_MAIBOX_U84_IRQ_BIT
+ ESWIN_MAILBOX_U84_TO_NPU_0_REG_BASE>;
+
+ device-uart = <0x50900000>;
device-irq-mode = <1>;
host-irq-mode = <1>;
firmware-name = "eic7700_dsp_fw";
@@ -592,8 +605,9 @@ d0_dsp1:es_dsp@1 {
ESWIN_MAILBOX_DSP_1_TO_U84_REG_BASE
ESWIN_MAILBOX_WR_LOCK_BIT_DSP_1
ESWIN_MAILBOX_U84_TO_DSP_1_REG_BASE
- ESWIN_MAIBOX_U84_IRQ_BIT>;
- device-uart = <0x50910000>;
+ ESWIN_MAIBOX_U84_IRQ_BIT
+ ESWIN_MAILBOX_U84_TO_NPU_0_REG_BASE>;
+ device-uart = <0x50900000>;
device-irq-mode = <1>;
host-irq-mode = <1>;
firmware-name = "eic7700_dsp_fw";
@@ -621,8 +635,9 @@ d0_dsp2:es_dsp@2 {
ESWIN_MAILBOX_DSP_2_TO_U84_REG_BASE
ESWIN_MAILBOX_WR_LOCK_BIT_DSP_2
ESWIN_MAILBOX_U84_TO_DSP_2_REG_BASE
- ESWIN_MAIBOX_U84_IRQ_BIT>;
- device-uart = <0x50910000>;
+ ESWIN_MAIBOX_U84_IRQ_BIT
+ ESWIN_MAILBOX_U84_TO_NPU_0_REG_BASE>;
+ device-uart = <0x50900000>;
device-irq-mode = <1>;
host-irq-mode = <1>;
firmware-name = "eic7700_dsp_fw";
@@ -650,8 +665,9 @@ d0_dsp3:es_dsp@3 {
ESWIN_MAILBOX_DSP_3_TO_U84_REG_BASE
ESWIN_MAILBOX_WR_LOCK_BIT_DSP_3
ESWIN_MAILBOX_U84_TO_DSP_3_REG_BASE
- ESWIN_MAIBOX_U84_IRQ_BIT>;
- device-uart = <0x50910000>;
+ ESWIN_MAIBOX_U84_IRQ_BIT
+ ESWIN_MAILBOX_U84_TO_NPU_0_REG_BASE>;
+ device-uart = <0x50900000>;
device-irq-mode = <1>;
host-irq-mode = <1>;
firmware-name = "eic7700_dsp_fw";
@@ -665,29 +681,6 @@ ESWIN_MAILBOX_U84_TO_DSP_3_REG_BASE
dsp@0 {
};
};
- d0_sofdsp: sofdsp@4 {
- #sound-dai-cells = <1>;
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "eswin,vision-dsp";
- reg = <0x0 0x5b000000 0x0 0x10000>,
- <0x0 0x5b100000 0x0 0x40000>;
- /* memory-region = <&dsp_reserved0>; */
- mbox-names = "sof-dsp0";
- mboxes = <&d0_mbox4 0>;
- tplg-name = "sof-win2030-es8316.tplg";
- machine-drv-name = "asoc-simple-card";
- clocks = <&d0_clock WIN2030_CLK_DSP_ACLK_0>;
- clock-names = "aclk";
- process-id = <0>;
- dma-ranges = <0x0 0x40000000 0x0 0xc0000000 0x0 0xc0000000>;
- iommus = <&smmu0 WIN2030_SID_DSP_0>;
- mailbox-dsp-to-u84-addr = <ESWIN_MAILBOX_DSP_0_TO_U84_REG_BASE>;
- mailbox-u84-to-dsp-addr = <ESWIN_MAILBOX_U84_TO_DSP_0_REG_BASE>;
- dsp-uart = <&d0_uart1>;
- ringbuffer-region = <&dsp_reserved1>;
- dma-noncoherent;
- };
};
gc820: g2d@50140000 {
@@ -749,8 +742,9 @@ d0_sata: sata@0x50420000{
resets = <&d0_reset HSPDMA_RST_CTRL SW_SATA_ASIC0_RSTN>,
<&d0_reset HSPDMA_RST_CTRL SW_SATA_OOB_RSTN>,
<&d0_reset HSPDMA_RST_CTRL SW_SATA_PMALIVE_RSTN>,
- <&d0_reset HSPDMA_RST_CTRL SW_SATA_RBC_RSTN>;
- reset-names = "asic0", "oob", "pmalive", "rbc";
+ <&d0_reset HSPDMA_RST_CTRL SW_SATA_RBC_RSTN>,
+ <&d0_reset HSPDMA_RST_CTRL SW_HSP_SATA_ARSTN>;
+ reset-names = "asic0", "oob", "pmalive", "rbc", "apb";
#size-cells = <2>;
iommus = <&smmu0 WIN2030_SID_SATA>;
tbus = <WIN2030_TBUID_SATA>;
@@ -787,7 +781,7 @@ pcie: pcie@0x54000000 {
ranges = <0x81000000 0x0 0x40800000 0x0 0x40800000 0x0 0x800000>, /* I/O */
<0x82000000 0x0 0x41000000 0x0 0x41000000 0x0 0xf000000>, /* mem */
- <0xc3000000 0x80 0x00000000 0x80 0x00000000 0x20 0x00000000>; /* mem prefetchable */
+ <0xc3000000 0x80 0x00000000 0x80 0x00000000 0x2 0x00000000>; /* mem prefetchable */
/* num-lanes = <0x4>; */
/**********************************
@@ -811,10 +805,10 @@ msi_ctrl_int : 220
dma-noncoherent;
};
- ssi0: spi0@50810000 {
+ ssi0: spi@50810000 {
compatible = "snps,win2030-spi";
- #address-cells = <2>;
- #size-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x0 0x50810000 0x0 0x4000>;
spi-max-frequency = <4800000>;
clocks = <&d0_clock WIN2030_CLK_LSP_SSI0_PCLK>;
@@ -831,10 +825,10 @@ ssi0: spi0@50810000 {
dma-noncoherent;
};
- ssi1: spi1@50814000 {
+ ssi1: spi@50814000 {
compatible = "snps,win2030-spi";
- #address-cells = <2>;
- #size-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x0 0x50814000 0x0 0x4000>;
spi-max-frequency = <4800000>;
clocks = <&d0_clock WIN2030_CLK_LSP_SSI1_PCLK>;
@@ -851,6 +845,22 @@ ssi1: spi1@50814000 {
dma-noncoherent;
};
+ bootspi: spi@51800000 {
+ compatible = "eswin,bootspi";
+ reg = <0x0 0x51800000 0x0 0x8000>,
+ <0x0 0x51828000 0x0 0x8000>,
+ <0x0 0x5c000000 0x0 0x8000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&d0_clock WIN2030_CLK_CLK_BOOTSPI_CFG>,
+ <&d0_clock WIN2030_CLK_CLK_BOOTSPI>;
+ clock-names = "cfg_clk", "clk";
+ resets = <&d0_reset BOOTSPI_RST_CTRL SW_BOOTSPI_RSTN>;
+ reset-names = "rst";
+ spi-max-frequency = <4800000>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
sdhci_emmc: mmc@50450000 {
compatible = "eswin,emmc-sdhci-5.1";
reg = <0x0 0x50450000 0x0 0x10000>;
@@ -867,10 +877,7 @@ sdhci_emmc: mmc@50450000 {
<&d0_reset HSPDMA_RST_CTRL SW_MSHC0_PHY_RSTN>,
<&d0_reset HSPDMA_RST_CTRL SW_HSP_EMMC_PRSTN>,
<&d0_reset HSPDMA_RST_CTRL SW_HSP_EMMC_ARSTN>;
- reset-names = "txrx_rst", "phy_rst", "emmc_prstn", "emmc_arstn";
- delay_code = <0x17>;
- drive-impedance-ohm = <50>;
- enable-data-pullup;
+ reset-names = "txrx_rst", "phy_rst", "prstn", "arstn";
disable-cqe-dcmd;
bus-width = <8>;
@@ -901,7 +908,7 @@ sdio0: mmc@0x50460000{
<&d0_clock WIN2030_SPLL2_FOUT3>,
<&d0_clock WIN2030_MUX_U_MSHCORE_ROOT_3MUX1_1>;
clock-names ="clk_xin","clk_ahb","clk_spll2_fout3","clk_mux1_1";
- clock-output-names = "sdio_cardclock";
+ clock-output-names = "sdio0_cardclock";
#clock-cells = <0>;
resets = <&d0_reset HSPDMA_RST_CTRL SW_MSHC1_TXRX_RSTN>,
<&d0_reset HSPDMA_RST_CTRL SW_MSHC1_PHY_RSTN>,
@@ -909,10 +916,6 @@ sdio0: mmc@0x50460000{
<&d0_reset HSPDMA_RST_CTRL SW_HSP_SD0_ARSTN>;
reset-names = "txrx_rst","phy_rst","prstn","arstn";
- delay_code = <0x28>;
- drive-impedance-ohm = <50>;
- enable-data-pullup;
-
core-clk-reg = <0x51828164>;
clock-frequency = <208000000>;
max-frequency = <208000000>;
@@ -938,7 +941,7 @@ sdio1: mmc@0x50470000{
<&d0_clock WIN2030_SPLL2_FOUT3>,
<&d0_clock WIN2030_MUX_U_MSHCORE_ROOT_3MUX1_1>;
clock-names ="clk_xin","clk_ahb","clk_spll2_fout3","clk_mux1_1";
- clock-output-names = "sdio_cardclock";
+ clock-output-names = "sdio1_cardclock";
#clock-cells = <0>;
resets = <&d0_reset HSPDMA_RST_CTRL SW_MSHC2_TXRX_RSTN>,
<&d0_reset HSPDMA_RST_CTRL SW_MSHC2_PHY_RSTN>,
@@ -946,10 +949,6 @@ sdio1: mmc@0x50470000{
<&d0_reset HSPDMA_RST_CTRL SW_HSP_SD1_ARSTN>;
reset-names = "txrx_rst","phy_rst","prstn","arstn";
- delay_code = <0x28>;
- drive-impedance-ohm = <50>;
- enable-data-pullup;
-
core-clk-reg = <0x51828168>;
clock-frequency = <208000000>;
max-frequency = <208000000>;
@@ -1252,7 +1251,7 @@ d0_lpcpu:lpcpu@0 {
};
pvt0: pvt@0x50b00000 {
- compatible = "eswin,eswin-pvt";
+ compatible = "eswin,eswin-pvt-cpu";
clocks = <&d0_clock WIN2030_CLK_PVT_CLK_0>;
clock-names = "pvt_clk";
resets = <&d0_reset PVT_RST_CTRL SW_PVT_RST_N_0>;
@@ -1265,7 +1264,7 @@ pvt0: pvt@0x50b00000 {
status = "disabled";
};
pvt1: pvt@0x52360000 {
- compatible = "eswin,eswin-pvt";
+ compatible = "eswin,eswin-pvt-ddr";
clocks = <&d0_clock WIN2030_CLK_PVT_CLK_1>;
clock-names = "pvt_clk";
resets = <&d0_reset PVT_RST_CTRL SW_PVT_RST_N_1>;
@@ -1289,8 +1288,8 @@ fan_control: fan_control@50b50000 {
interrupt-names = "fanirq";
interrupts = <354>;
pulses-per-revolution = <1>;
- pwm-minimun-period = <3000000>;
- pwms = <&pwm0 0 200>;
+ pwm-minimun-period = <1000>;
+ pwms = <&pwm0 0 100000>;
status = "disabled";
};
@@ -1463,42 +1462,6 @@ pinctrl: pinctrl@0x51600080 {
compatible = "eswin,eic7700-pinctrl";
reg = <0x0 0x51600080 0x0 0x1FFF80>;
status = "disabled";
- pinctrl_pwm0_default: pwm0-default{
- mux{
- groups = "pwm0_group";
- function = "pwm0_func";
- };
- conf {
- groups = "pwm0_group";
- drive-strength = <5>;
- bias-pull-up = <1>;
- input-enable = <0>;
- };
- };
- pinctrl_pwm1_default: pwm1-default{
- mux{
- groups = "pwm1_group";
- function = "pwm1_func";
- };
- conf {
- groups = "pwm1_group";
- drive-strength = <6>;
- bias-pull-up = <0>;
- input-enable = <1>;
- };
- };
- pinctrl_pwm2_default: pwm2-default{
- mux{
- groups = "pwm2_group";
- function = "pwm2_func";
- };
- conf {
- groups = "pwm2_group";
- drive-strength = <7>;
- bias-pull-down = <0>;
- input-enable = <0>;
- };
- };
};
gpio0: gpio@51600000 {
@@ -1542,62 +1505,7 @@ portd: gpio-port@3 {
reg = <3>;
};
};
- // gpio0: gpio@0x51600000 {
- // #address-cells = <1>;
- // #size-cells = <0>;
- // compatible = "eswin,win2030-gpio";
- // reg = <0x0 0x51600000 0x0 0x80>;
- // status = "disabled";
- // eswin,syscfg = <&d0_sys_con 0x3c0>;
-
- // porta: gpio-port@0 {
- // compatible = "eswin,win2030-gpio-port";
- // gpio-controller;
- // #gpio-cells = <2>;
- // ngpios = <32>;
- // reg = <0>;
- // interrupts = <303>;
- // interrupt-parent = <&plic0>;
- // interrupt-state = <0 1 1 1>;
- // direction-input = <5 8 9 16>;
- // direction-output = <1 0 3 1>;
- // gpio-state = <11 1 12 1>;
- // };
-
- // portb: gpio-port@1 {
- // compatible = "eswin,win2030-gpio-port";
- // gpio-controller;
- // #gpio-cells = <2>;
- // ngpios = <32>;
- // reg = <1>;
- // direction-input = <5 13 9 25>;
- // direction-output = <26 0 3 1>;
- // gpio-state = <11 1 17 1>;
- // };
-
- // portc: gpio-port@2 {
- // compatible = "eswin,win2030-gpio-port";
- // gpio-controller;
- // #gpio-cells = <2>;
- // ngpios = <32>;
- // reg = <2>;
- // direction-input = <5 13 9 25>;
- // direction-output = <26 0 3 1>;
- // gpio-state = <11 1 17 1>;
- // };
-
- // portd: gpio-port@3 {
- // compatible = "eswin,win2030-gpio-port";
- // gpio-controller;
- // #gpio-cells = <2>;
- // ngpios = <16>;
- // reg = <3>;
- // direction-input = <9 1 8 1>;
- // direction-output = <3 1 15 1>;
- // gpio-state = <6 1 5 1>;
- // };
- // };
-
+
pwm0: pwm@0x50818000 {
compatible = "eswin,pwm-eswin";
reg = <0x0 0x50818000 0x0 0x4000>;
@@ -1607,8 +1515,6 @@ pwm0: pwm@0x50818000 {
resets = <&d0_reset TIMER_RST_CTRL SW_TIMER_RST_N>;
reset-names = "pwmrst";
#pwm-cells = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default &pinctrl_pwm2_default>;
status = "disabled";
};
@@ -1665,6 +1571,7 @@ timer0: timer@0x51840000 {
#address-cells = <2>;
#size-cells = <2>;
reg = <0x0 0x51840000 0x0 0x8000>;
+ perf_count = <7>;
interrupt-parent = <&plic0>;
interrupts = <345>;
clock-names = "pclk","timer_aclk";
@@ -1757,14 +1664,13 @@ die0_rtc: rtc@51818000 {
interrupts = <292>;
clocks = <&d0_clock WIN2030_CLK_CLK_RTC>;
clock-names = "rtcclk";
- clock-frequency = <15624>;
+ clock-frequency = <15625>;
resets = <&d0_reset RTC_RST_CTRL SW_RTC_RSTN>;
reset-names = "rtcrst";
status = "disabled";
};
d0_i2s0: i2s0@50200000 {
- //compatible = "eswin,i2s-dsp";
compatible = "snps,i2s";
clocks = <&d0_clock WIN2030_CLK_VO_I2S_MCLK>;
clock-names = "mclk";
@@ -1774,7 +1680,6 @@ d0_i2s0: i2s0@50200000 {
reg = <0x0 0x50200000 0x0 0x10000>;
dma-names = "rx", "tx";
dmas = <&d0_aon_dmac 4 0>, <&d0_aon_dmac 5 0>;
- memory-region = <&dsp_reserved1>;
vo_mclk_sel,syscrg = <&d0_sys_crg 0x1bc>;
resets = <&d0_reset VO_I2SRST_CTRL SW_VO_I2S_RSTN>,
<&d0_reset VO_I2SRST_CTRL SW_VO_I2S_PRSTN>,
@@ -1819,45 +1724,6 @@ d0_i2s2: i2s2@50220000 {
dma-noncoherent;
};
- d0_soundcard: soundcard {
- compatible = "simple-audio-card";
- simple-audio-card,name = "Eswin sound card";
- simple-audio-card,widgets = "Headphone", "Headphone Jack";
- simple-audio-card,dai-link@0 {
- format = "i2s";
- cpu {
- sound-dai = <&d0_sofdsp 0>;
- };
- codec {
- sound-dai = <&d0_thruout 0>;
- };
- };
-
- simple-audio-card,dai-link@1 {
- format = "i2s";
- cpu {
- sound-dai = <&d0_sofdsp 1>;
- };
- codec {
- sound-dai = <&d0_thruout 1>;
- };
- };
-
- simple-audio-card,dai-link@2 {
- format = "i2s";
- cpu {
- sound-dai = <&d0_i2s0>;
- };
- codec {
- //sound-dai = <&d0_es8316>;
- //system-clock-frequency = <12288000>;
- };
- plat {
- sound-dai = <&d0_sofdsp 2>;
- };
- };
- };
-
d0_graphcard0: graphcard0 {
compatible = "audio-graph-card";
};
@@ -1871,7 +1737,7 @@ d0_graphcard2: graphcard2 {
};
video_output: display-subsystem {
- compatible = "verisilicon,display-subsystem";
+ compatible = "eswin,display-subsystem";
ports = <&dc_out>;
};
@@ -1880,8 +1746,8 @@ dvb_widgets: dvb-subsystem {
status = "disabled";
};
- dc8k: dc8000@502c0000 {
- compatible = "verisilicon,dc8000";
+ dc: display_control@502c0000 {
+ compatible = "eswin,dc";
reg = <0x0 0x502c0000 0x0 0x100>, <0x0 0x502c0180 0x0 0x700>, <0x0 0x502c1400 0x0 0x1400>;
interrupt-parent = <&plic0>;
interrupts = <238>;
@@ -1913,15 +1779,15 @@ dc_out_dpi1: endpoint@1 {
remote-endpoint = <&vd_input>;
};
- dc_out_hdmi: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&hdmi_in_dc8k>;
- };
+ dc_out_hdmi: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&hdmi_in_dc>;
+ };
};
};
- virtual_display: vs_wb {
- compatible = "verisilicon,virtual_display";
+ virtual_display: es_wb {
+ compatible = "eswin,virtual_display";
bpp = /bits/ 8 <8>;
port {
@@ -1932,7 +1798,7 @@ vd_input: endpoint {
};
dsi_output: dsi-output {
- compatible = "verisilicon,dsi-encoder";
+ compatible = "eswin,dsi-encoder";
ports {
#address-cells = <1>;
@@ -1962,11 +1828,12 @@ dsi_out:endpoint {
dsi_controller: mipi_dsi@50270000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "verisilicon,dw-mipi-dsi";
+ compatible = "eswin,dw-mipi-dsi";
reg = <0x0 0x50270000 0x0 0x10000>;
clocks = <&d0_clock WIN2030_CLK_CLK_MIPI_TXESC>;
clock-names = "pclk";
-
+ resets = <&d0_reset VO_PHYRST_CTRL SW_VO_MIPI_PRSTN>;
+ reset-names ="phyrstn";
/*
phys = <&dphy>;
phy-names = "dphy";
@@ -1997,7 +1864,7 @@ mipi_dsi_out: endpoint {
};
};
- panel@1 {
+ dsi_panel:dsi_panel@0 {
compatible = "eswin,generic-panel";
reg = <0>;
@@ -2009,8 +1876,8 @@ panel_in: endpoint {
};
};
- dc8k_test: dc8ktest@502c0000 {
- compatible = "eswin,dc8000";
+ dc_test: dctest@502c0000 {
+ compatible = "eswin,dc";
reg = <0x0 0x502c0000 0x0 0x10000>;
interrupt-parent = <&plic0>;
interrupts = <238>;
@@ -2041,7 +1908,7 @@ ports {
#size-cells = <0>;
port@0 {
reg = <0>;
- hdmi_in_dc8k: endpoint@0 {
+ hdmi_in_dc: endpoint@0 {
remote-endpoint = <&dc_out_hdmi>;
};
};
@@ -2058,25 +1925,6 @@ dw_hdmi_hdcp2: hdmi-hdcp2@50290000 {
clock-names ="pclk_hdcp2", "hdcp2_clk_hdmi";
};
- d0_dummy_codec:codec@0x50230000 {
- reg = <0x00000000 0x50230000 0x00000000 0x00000100>;
- #sound-dai-cells = <0x00000000>;
- compatible = "eswin_dummy_codec";
- };
- d0_thruout: thru-out {
- compatible = "eswin,thru-out";
- #sound-dai-cells = <1>;
- memory-region = <&dsp_reserved1>;
- };
- d0_dummy_pf: dummy@0x50400000{
- compatible = "eswin,dummy-dai";
- #address-cells = <1>;
- #size-cells = <0>;
- #sound-dai-cells = <0x00000000>;
- reg = <0x0 0x50400000 0x0 0x10000>;
- status = "disabled";
- };
-
d0_usbdrd3_0: usb0@50480000 {
compatible = "eswin,win2030-dwc3";
#address-cells = <2>;
@@ -2229,8 +2077,8 @@ isp_1: isp@0x51010000 {
dma-noncoherent;
};
- dw200: dw200@51020000 {
- compatible = "eswin,dw200";
+ dewarp: dewarp@51020000 {
+ compatible = "eswin,dewarp";
clocks = <&d0_clock WIN2030_CLK_VI_ACLK>,
<&d0_clock WIN2030_CLK_VI_CFG_CLK>,
<&d0_clock WIN2030_CLK_VI_DIG_DW_CLK>,
@@ -2394,8 +2242,8 @@ csi2_dma_1_3: endpoint {
};
};
- dc8k_test: dc8ktest@502c0000 {
- compatible = "eswin,dc8000";
+ dc_test: dctest@502c0000 {
+ compatible = "eswin,dc";
reg = <0x0 0x502c0000 0x0 0x10000>;
interrupt-parent = <&plic0>;
interrupts = <238>;
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
index 9c24a81da4f8..b1b077ceea0e 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
@@ -163,6 +163,7 @@ d1_noc_wdt:noc@71810324 {
<416>, <417>, <418>, <419>, <420>,
<421>, <422>, <423>, <424>, <425>,
<426>;
+ eswin,syscrg_csr = <&d1_sys_crg 0x100 0xffff>; //timeout paramerter
};
};
@@ -660,7 +661,7 @@ d1_lpcpu:lpcpu@1 {
};
d1_pvt0: pvt@0x70b00000 {
- compatible = "eswin,eswin-pvt";
+ compatible = "eswin,eswin-pvt-cpu";
clocks = <&d1_clock WIN2030_CLK_PVT_CLK_0>;
clock-names = "pvt_clk";
resets = <&d1_reset PVT_RST_CTRL SW_PVT_RST_N_0>;
@@ -673,7 +674,7 @@ d1_pvt0: pvt@0x70b00000 {
status = "disabled";
};
d1_pvt1: pvt@0x72360000 {
- compatible = "eswin,eswin-pvt";
+ compatible = "eswin,eswin-pvt-ddr";
clocks = <&d1_clock WIN2030_CLK_PVT_CLK_1>;
clock-names = "pvt_clk";
resets = <&d1_reset PVT_RST_CTRL SW_PVT_RST_N_1>;
@@ -697,8 +698,8 @@ d1_fan_control: fan_control@70b50000 {
interrupt-names = "fanirq";
interrupts = <354>;
pulses-per-revolution = <1>;
- pwm-minimun-period = <3000000>;
- pwms = <&d1_pwm0 0 200>;
+ pwm-minimun-period = <1000>;
+ pwms = <&d1_pwm0 0 100000>;
status = "disabled";
};
@@ -901,7 +902,7 @@ d1_aon_i2c1: i2c@71838000 {
interrupt-parent = <&plic1>;
};
- d1_nvdla: nvdla-controller@71c00000 {
+ d1_npu: eswin-npu@71c00000 {
compatible = "eswin,npu1";
reg = <0x0 0x71c00000 0x0 0x400000>;
interrupt-parent = <&plic1>;
@@ -914,6 +915,11 @@ d1_nvdla: nvdla-controller@71c00000 {
dsp-avail-num = <1>;
spram-size = <0x400000>;
npu_mbox = <&d1_mbox2>;
+ clocks = <&d1_clock WIN2030_CLK_NPU_ACLK>,
+ <&d1_clock WIN2030_CLK_NPU_CFG_CLK>,
+ <&d1_clock WIN2030_CLK_NPU_CLK>,
+ <&d1_clock WIN2030_CLK_NPU_E31_CLK>;
+ clock-names = "aclk", "cfg_clk", "core_clk", "e31_core_clk";
resets = <&d1_reset NPU_RST_CTRL SW_NPU_E31CORE_RSTN>;
reset-names = "e31_core";
@@ -1294,7 +1300,8 @@ d1_dsp0:es_dsp@0 {
(ESWIN_MAILBOX_DSP_0_TO_U84_REG_BASE + 0x20000000)
ESWIN_MAILBOX_WR_LOCK_BIT_DSP_0
(ESWIN_MAILBOX_U84_TO_DSP_0_REG_BASE + 0x20000000)
- ESWIN_MAIBOX_U84_IRQ_BIT>;
+ ESWIN_MAIBOX_U84_IRQ_BIT
+ (ESWIN_MAILBOX_U84_TO_NPU_0_REG_BASE + 0x20000000)>;
device-uart = <0x70910000>;
device-irq-mode = <1>;
host-irq-mode = <1>;
@@ -1323,7 +1330,8 @@ d1_dsp1:es_dsp@1 {
(ESWIN_MAILBOX_DSP_1_TO_U84_REG_BASE + 0x20000000)
ESWIN_MAILBOX_WR_LOCK_BIT_DSP_1
(ESWIN_MAILBOX_U84_TO_DSP_1_REG_BASE + 0x20000000)
- ESWIN_MAIBOX_U84_IRQ_BIT>;
+ ESWIN_MAIBOX_U84_IRQ_BIT
+ (ESWIN_MAILBOX_U84_TO_NPU_0_REG_BASE + 0x20000000)>;
device-uart = <0x70910000>;
device-irq-mode = <1>;
host-irq-mode = <1>;
@@ -1352,7 +1360,8 @@ d1_dsp2:es_dsp@2 {
(ESWIN_MAILBOX_DSP_2_TO_U84_REG_BASE + 0x20000000)
ESWIN_MAILBOX_WR_LOCK_BIT_DSP_2
(ESWIN_MAILBOX_U84_TO_DSP_2_REG_BASE + 0x20000000)
- ESWIN_MAIBOX_U84_IRQ_BIT>;
+ ESWIN_MAIBOX_U84_IRQ_BIT
+ (ESWIN_MAILBOX_U84_TO_NPU_0_REG_BASE + 0x20000000)>;
device-uart = <0x70910000>;
device-irq-mode = <1>;
host-irq-mode = <1>;
@@ -1381,7 +1390,8 @@ d1_dsp3:es_dsp@3 {
(ESWIN_MAILBOX_DSP_3_TO_U84_REG_BASE + 0x20000000)
ESWIN_MAILBOX_WR_LOCK_BIT_DSP_3
(ESWIN_MAILBOX_U84_TO_DSP_3_REG_BASE + 0x20000000)
- ESWIN_MAIBOX_U84_IRQ_BIT>;
+ ESWIN_MAIBOX_U84_IRQ_BIT
+ (ESWIN_MAILBOX_U84_TO_NPU_0_REG_BASE + 0x20000000)>;
device-uart = <0x70910000>;
device-irq-mode = <1>;
host-irq-mode = <1>;
@@ -1429,7 +1439,7 @@ die1_rtc: rtc@71818000 {
interrupts = <292>;
clocks = <&d1_clock WIN2030_CLK_CLK_RTC>;
clock-names = "rtcclk";
- clock-frequency = <15624>;
+ clock-frequency = <15625>;
resets = <&d1_reset RTC_RST_CTRL SW_RTC_RSTN>;
reset-names = "rtcrst";
status = "disabled";
@@ -1563,10 +1573,6 @@ d1_sdio0: mmc@0x70460000{
<&d1_reset HSPDMA_RST_CTRL SW_HSP_SD0_ARSTN>;
reset-names = "txrx_rst","phy_rst","prstn","arstn";
- delay_code = <0x28>;
- drive-impedance-ohm = <50>;
- enable-data-pullup;
-
clock-frequency = <208000000>;
max-frequency = <208000000>;
#size-cells = <2>;
@@ -1599,10 +1605,6 @@ d1_sdio1: mmc@0x70470000{
<&d1_reset HSPDMA_RST_CTRL SW_HSP_SD1_ARSTN>;
reset-names = "txrx_rst","phy_rst","prstn","arstn";
- delay_code = <0x28>;
- drive-impedance-ohm = <50>;
- enable-data-pullup;
-
clock-frequency = <208000000>;
max-frequency = <208000000>;
#size-cells = <2>;
@@ -1643,12 +1645,12 @@ d1_spi_demo: spi-demo@0 {
};
d1_video_output: display-subsystem {
- compatible = "verisilicon,display-subsystem";
+ compatible = "eswin,display-subsystem";
ports = <&d1_dc_out>;
};
- d1_dc8k: dc8000@702c0000 {
- compatible = "verisilicon,dc8000";
+ d1_dc: display_control@702c0000 {
+ compatible = "eswin,dc";
reg = <0x0 0x702c0000 0x0 0x100>, <0x0 0x702c0180 0x0 0x700>, <0x0 0x702c1400 0x0 0x1400>;
interrupt-parent = <&plic1>;
interrupts = <238>;
@@ -1683,13 +1685,13 @@ d1_dc_out_dpi1: endpoint@1 {
d1_dc_out_hdmi: endpoint@2 {
reg = <2>;
- remote-endpoint = <&d1_hdmi_in_dc8k>;
+ remote-endpoint = <&d1_hdmi_in_dc>;
};
};
};
- d1_virtual_display: vs_wb {
- compatible = "verisilicon,virtual_display";
+ d1_virtual_display: es_wb {
+ compatible = "eswin,virtual_display";
bpp = /bits/ 8 <8>;
port {
@@ -1700,7 +1702,7 @@ d1_vd_input: endpoint {
};
d1_dsi_output: dsi-output {
- compatible = "verisilicon,dsi-encoder";
+ compatible = "eswin,dsi-encoder";
ports {
#address-cells = <1>;
@@ -1730,7 +1732,7 @@ d1_dsi_out:endpoint {
d1_dsi_controller: mipi_dsi@70270000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "verisilicon,dw-mipi-dsi";
+ compatible = "eswin,dw-mipi-dsi";
reg = <0x0 0x70270000 0x0 0x10000>;
clocks = <&d1_clock WIN2030_CLK_CLK_MIPI_TXESC>;
clock-names = "pclk";
@@ -1777,8 +1779,8 @@ d1_panel_in: endpoint {
};
};
- d1_dc8k_test: dc8ktest@702c0000 {
- compatible = "eswin,dc8000";
+ d1_dc_test: dctest@702c0000 {
+ compatible = "eswin,dc";
reg = <0x0 0x702c0000 0x0 0x10000>;
interrupt-parent = <&plic1>;
interrupts = <238>;
@@ -1808,7 +1810,7 @@ ports {
port@0 {
#address-cells = <1>;
#size-cells = <0>;
- d1_hdmi_in_dc8k: endpoint@0 {
+ d1_hdmi_in_dc: endpoint@0 {
reg = <0>;
remote-endpoint = <&d1_dc_out_hdmi>;
};
@@ -1929,10 +1931,6 @@ d1_sdhci_emmc: mmc@70450000 {
<&d1_reset HSPDMA_RST_CTRL SW_HSP_EMMC_ARSTN>;
reset-names = "txrx_rst", "phy_rst", "emmc_prstn", "emmc_arstn";
- delay_code = <0x17>;
- drive-impedance-ohm = <50>;
- enable-data-pullup;
-
disable-cqe-dcmd;
bus-width = <8>;
non-removable;
@@ -2180,8 +2178,8 @@ d1_isp_1: isp@0x71010000 {
dma-noncoherent;
};
- d1_dw200: dw200@71020000 {
- compatible = "eswin,dw200";
+ d1_dewarp: dewarp@71020000 {
+ compatible = "eswin,dewarp";
clocks = <&d1_clock WIN2030_CLK_VI_ACLK>,
<&d1_clock WIN2030_CLK_VI_CFG_CLK>,
<&d1_clock WIN2030_CLK_VI_DIG_DW_CLK>,
@@ -2344,8 +2342,8 @@ d1_csi2_dma_1_3: endpoint {
};
};
- d1_dc8k_test: dc8ktest@702c0000 {
- compatible = "eswin,dc8000";
+ d1_dc_test: dctest@702c0000 {
+ compatible = "eswin,dc";
reg = <0x0 0x702c0000 0x0 0x10000>;
interrupt-parent = <&plic1>;
interrupts = <238>;
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030.dts b/arch/riscv/boot/dts/eswin/eswin-win2030.dts
index 3b4815537560..8e7769e5b509 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030.dts
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030.dts
@@ -509,7 +509,7 @@ &d0_gmac1 {
};
-&d0_nvdla {
+&d0_npu {
status = "okay";
};
@@ -533,10 +533,6 @@ &d0_dsp3 {
status = "disabled";
};
-&d0_sofdsp {
- status = "disabled";
-};
-
&d0_i2s0 {
status = "disabled";
eswin-plat = <0>;
@@ -559,26 +555,10 @@ d0_i2s1_endpoint: endpoint {
};
};
-&d0_i2s2 {
- status = "disabled";
- eswin-plat = <0>;
- d0_i2s2_port: port {
- d0_i2s2_endpoint: endpoint {
- remote-endpoint = <&d0_dummy_endpoint2>;
- dai-format = "i2s";
- };
- };
-};
-
-&d0_soundcard {
- status = "disabled";
-};
-
&d0_graphcard0 {
status = "disabled";
dais = <&d0_i2s0_port
- &d0_i2s1_port
- &d0_i2s2_port>;
+ &d0_i2s1_port>;
};
&d0_graphcard1 {
@@ -589,37 +569,6 @@ &d0_graphcard2 {
status = "disabled";
};
-&d0_dummy_codec {
- status = "disabled";
- ports {
- /*port@0 {
- d0_dummy_endpoint0: endpoint {
- system-clock-frequency = <12288000>;
- remote-endpoint = <&d0_i2s0_endpoint>;
- };
- };
- */
- /*
- port@1 {
- d0_dummy_endpoint1: endpoint {
- system-clock-frequency = <12288000>;
- remote-endpoint = <&d0_i2s1_endpoint>;
- };
- };
- */
- port@2 {
- d0_dummy_endpoint2: endpoint {
- system-clock-frequency = <12288000>;
- remote-endpoint = <&d0_i2s2_endpoint>;
- };
- };
- };
-};
-
-&d0_thruout{
- status = "disabled";
-};
-
&gc820 {
status = "disabled";
};
@@ -935,7 +884,7 @@ &video_output {
status = "disabled";
};
-&dc8k {
+&dc {
status = "disabled";
};
@@ -951,7 +900,7 @@ &dsi_controller {
status = "disabled";
};
-&dc8k_test {
+&dc_test {
status = "disabled";
};
@@ -1024,7 +973,7 @@ &isp_1 {
status = "disabled";
};
-&dw200 {
+&dewarp {
status = "disabled";
};
@@ -1229,7 +1178,7 @@ &d1_aon_i2c1 {
status = "disabled";
};
-&d1_nvdla {
+&d1_npu {
status = "disabled";
};
@@ -1400,7 +1349,7 @@ &d1_video_output {
status = "disabled";
};
-&d1_dc8k {
+&d1_dc {
status = "disabled";
};
@@ -1416,7 +1365,7 @@ &d1_dsi_controller {
status = "disabled";
};
-&d1_dc8k_test {
+&d1_dc_test {
status = "disabled";
};
@@ -1468,7 +1417,7 @@ &d1_isp_1 {
status = "disabled";
};
-&d1_dw200 {
+&d1_dewarp {
status = "disabled";
};
diff --git a/arch/riscv/boot/dts/eswin/hifive-premier-550.dts b/arch/riscv/boot/dts/eswin/hifive-premier-550.dts
new file mode 100644
index 000000000000..d3baea543371
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/hifive-premier-550.dts
@@ -0,0 +1,861 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for Eswin EIC7700 SoC.
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+
+#define RTCCLK_FREQ 1000000
+#define LSPCLK_FREQ 200000000
+
+/* If wanna enable ECC capability of DDR, should reserve highest zone of 1/8 all space for it */
+#define MEMORY_SIZE_H 0x4
+#define MEMORY_SIZE_L 0x0
+#define CMA_SIZE 0x10000000
+
+#include "eswin-win2030-die0-soc.dtsi"
+#include "eic7700-pinctrl.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "ESWIN EIC7700";
+ compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000",
+ "sifive,fu740", "eswin,eic7700";
+
+ aliases {
+ serial0 = &d0_uart0;
+ ethernet0 = &d0_gmac0;
+ ethernet1 = &d0_gmac1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpus {
+ timebase-frequency = <RTCCLK_FREQ>;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 MEMORY_SIZE_H MEMORY_SIZE_L>;
+ numa-node-id = <0>;
+ };
+ extcon_usb1: extcon_usb1 {
+ compatible = "linux,extcon-usb-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio6_default>;
+ id-gpio = <&porta 6 GPIO_ACTIVE_HIGH>;
+ };
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 CMA_SIZE>;
+ alignment = <0x0 0x1000>;
+ alloc-ranges = <0x0 0x80000000 MEMORY_SIZE_H MEMORY_SIZE_L>;
+ linux,cma-default;
+ };
+
+ dsp_reserved1: dsp@91000000 {
+ reg = <0 0x91000000 0 0x200000>;
+ no-map;
+ };
+
+ lpcpu0_reserved: lpcpu@a0000000 {
+ no-map;
+ reg = <0x0 0xa0000000 0x0 0x100000>;
+ };
+ };
+
+ soc {
+ reset_test@1e00e000 {
+ compatible = "reset_test";
+ resets = <&d0_reset SCPU_RST_CTRL SW_SCPU_BUS_RSTN>,
+ <&d0_reset SCPU_RST_CTRL SW_SCPU_CORE_RSTN>,
+ <&d0_reset SCPU_RST_CTRL SW_SCPU_DBG_RSTN>;
+ reset-names = "bus", "core", "dbg";
+ };
+ };
+ npu0_reserved: sprammemory@59000000 {
+ reg = <0x0 0x59000000 0x0 0x400000>;
+ };
+};
+
+&d0_clock {
+ status = "okay";
+};
+
+&d0_reset {
+ status = "okay";
+};
+
+&d0_pmu {
+ status = "okay";
+};
+
+&ddr0 {
+ status = "okay";
+};
+
+&ddr1 {
+ status = "okay";
+};
+
+&smmu0 {
+ status = "okay";
+};
+
+&smmu_pmu0 {
+ status = "disabled";
+};
+
+&dev_foo_a {
+ status = "okay";
+};
+
+&d0_cfg_noc {
+ status = "okay";
+};
+
+&d0_llc_noc {
+ status = "okay";
+ stat,0 = "TracePort:ddr0_p0_req";
+ stat,1 = "TracePort:ddr1_p0_req";
+ //latency,0 = "TracePort:llcnoc_trans_probe";
+ //pending,0 = "TracePort:llcnoc_trans_probe";
+};
+
+&d0_sys_noc {
+ status = "okay";
+
+ //eswin,DSPT-qos-owner;
+ //eswin,NPU-qos-owner;
+ //eswin,SPISLV_TBU3-qos-owner;
+
+ stat,0 = "TracePort:ddr0_p1_req",
+ "InitFlow:mcput_snoc_mp/I/0";
+
+ stat,1 = "TracePort:ddr0_p2_req",
+ "InitFlow:dspt_snoc/I/0",
+ "AddrBase:0x81000000", "AddrSize:0x30",
+ "Opcode:RdWrLockUrg", "Status:ReqRsp", "Length:0x8000", "Urgency:0x0";
+
+ stat,2 = "TracePort:ddr1_p1_req",
+ "Status:Req", "AddrSize:0x28";
+
+ stat,3 = "TracePort:ddr1_p2_req";
+
+ latency,0 = "TracePort:sysnoc_trans_probe_0", "AddrSize:0x0";
+ latency,1 = "TracePort:sysnoc_trans_probe_1","Mode:latency","AddrBase:0x82000000","AddrSize:0x28","Opcode:RdWr";
+ //latency,2 = "TracePort:sysnoc_trans_probe_2";
+
+ //pending,0 = "TracePort:sysnoc_trans_probe_0";
+ //pending,1 = "TracePort:sysnoc_trans_probe_1","Mode:latency","AddrBase:0x82000000","AddrSize:0x0","Opcode:RdWr";
+ pending,0 = "TracePort:sysnoc_trans_probe_2", "AddrSize:0x3";
+};
+
+&d0_media_noc {
+ status = "okay";
+
+ //eswin,GPU-qos-owner;
+ //eswin,TBU2-qos-owner;
+ //eswin,VC-qos-owner;
+
+ stat,0 = "TracePort:ddr0_p3_req";
+ stat,1 = "TracePort:ddr1_p3_req";
+ //latency,0 = "TracePort:mnoc_trans_probe";
+ //pending,0 = "TracePort:mnoc_trans_probe";
+};
+
+&d0_realtime_noc {
+ status = "okay";
+
+ //eswin,TBU0-qos-owner;
+ //eswin,VO-qos-owner;
+
+ stat,0 = "TracePort:ddr0_p4_req";
+ stat,1 = "TracePort:ddr1_p4_req";
+ //latency,0 = "TracePort:rnoc_trans_probe";
+ //pending,0 = "TracePort:rnoc_trans_probe";
+};
+
+&d0_noc_wdt {
+ status = "okay";
+};
+
+&d0_ipc_scpu {
+ status = "okay";
+};
+
+&d0_lpcpu {
+ status = "disabled";
+};
+
+&pcie {
+ /* GPIO12 PCIE PRSNT input */
+ status = "okay";
+};
+
+&d0_npu{
+ status = "okay";
+};
+
+&d0_dsp_subsys {
+ status = "okay";
+};
+
+&d0_dsp0 {
+ status = "okay";
+};
+
+&d0_dsp1 {
+ status = "okay";
+};
+
+&d0_dsp2 {
+ status = "okay";
+};
+
+&d0_dsp3 {
+ status = "okay";
+};
+
+&gpu0 {
+ status = "okay";
+};
+
+&gc820 {
+ status = "okay";
+};
+
+&vdec0 {
+ status = "okay";
+};
+
+&venc0 {
+ status = "okay";
+};
+
+&video_output {
+ status = "okay";
+};
+
+&dc {
+ status = "okay";
+};
+
+&dc_test {
+ status = "disabled";
+};
+
+&virtual_display {
+ status = "okay";
+};
+
+&dsi_output {
+ status = "okay";
+};
+
+&dsi_controller {
+ status = "okay";
+};
+
+&dsi_panel {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio82_default &pinctrl_gpio85_default>;
+ backlight0-gpios = <&portc 18 GPIO_ACTIVE_HIGH>;
+ rst-gpios = <&portc 21 GPIO_ACTIVE_HIGH>;
+};
+
+&dw_hdmi {
+ status = "okay";
+ eswin-plat = <1>;
+ ports {
+ port@2 {
+ reg = <2>;
+ hdmi_in_i2s: endpoint@1 {
+ system-clock-frequency = <12288000>;
+ remote-endpoint = <&d0_i2s0_endpoint>;
+ };
+ };
+ };
+};
+
+&dw_hdmi_hdcp2 {
+ status = "okay";
+};
+
+&d0_i2s0 {
+ /* connect M.2 KEY E */
+ status = "okay";
+ eswin-plat = <1>;
+ d0_i2s0_port: port {
+ d0_i2s0_endpoint: endpoint {
+ remote-endpoint = <&hdmi_in_i2s>;
+ dai-format = "i2s";
+ };
+ };
+};
+
+&d0_i2s1 {
+ status = "okay";
+ eswin-plat = <1>;
+ d0_i2s1_port: port {
+ d0_i2s1_endpoint: endpoint {
+ remote-endpoint = <&d0_codec0_endpoint>;
+ dai-format = "i2s";
+ };
+ };
+};
+
+&d0_i2s2 {
+ /* connect WIFI module */
+ status = "disabled";
+};
+
+&d0_graphcard0 {
+ status = "okay";
+ dais = <&d0_i2s1_port>;
+};
+
+&d0_graphcard1 {
+ status = "okay";
+ dais = <&d0_i2s0_port>;
+};
+
+&d0_graphcard2 {
+ status = "disabled";
+};
+
+&isp_0 {
+ status = "disabled";
+};
+
+&isp_1 {
+ status = "disabled";
+};
+
+&dewarp {
+ status = "okay";
+};
+
+&mipi_dphy_rx {
+ status = "disabled";
+};
+
+&csi_dma0 {
+ status = "disabled";
+};
+
+&csi_dma1 {
+ status = "disabled";
+};
+
+&csi2_0 {
+ status = "disabled";
+};
+
+&csi2_1 {
+ status = "disabled";
+};
+
+&sdhci_emmc {
+ /* emmc */
+ status = "okay";
+ delay_code = <0x17>;
+ drive-impedance-ohm = <50>;
+ enable-cmd-pullup;
+ enable-data-pullup;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_emmc_led_control_default>;
+};
+
+&sdio0 {
+ /* sd card */
+ status = "okay";
+ delay_code = <0x16>;
+ drive-impedance-ohm = <33>;
+ enable-cmd-pullup;
+ enable-data-pullup;
+ enable_sw_tuning;
+ no-sdio;
+};
+
+&sdio1 {
+ /* wifi module */
+ status = "disabled";
+ delay_code = <0x21>;
+ drive-impedance-ohm = <33>;
+ enable-cmd-pullup;
+ enable-data-pullup;
+ enable_sw_tuning;
+ non-removable;
+ no-sd;
+};
+
+&d0_gmac0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio106_default>;
+ rst-gpios = <&portd 10 GPIO_ACTIVE_LOW>;
+ eswin,rgmiisel = <&pinctrl 0x290 0x3>;
+ eswin,led-cfgs = <0x6100 0xa40 0x420>;
+};
+
+&d0_gmac1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio111_default>;
+ rst-gpios = <&portd 11 GPIO_ACTIVE_LOW>;
+ eswin,rgmiisel = <&pinctrl 0x294 0x3>;
+ eswin,led-cfgs = <0x6100 0xa40 0x420>;
+};
+
+&d0_sata {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sata_act_led_default>;
+};
+
+&d0_usbdrd3_0 {
+ status = "okay";
+ extcon = <&extcon_usb1>;
+};
+
+&d0_usbdrd_dwc3_0 {
+ status = "okay";
+ dr_mode = "otg";
+ usb-role-switch;
+ role-switch-default-mode = "host";
+ maximum-speed = "super-speed";
+};
+
+&d0_usbdrd3_1 {
+ status = "okay";
+};
+
+&d0_usbdrd_dwc3_1 {
+ status = "okay";
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+};
+
+&d0_dmac0 {
+ status = "okay";
+};
+
+&d0_aon_dmac {
+ status = "okay";
+};
+
+&d0_uart0 {
+ /* debug */
+ status = "okay";
+};
+
+&d0_uart1 {
+ /* M.2 KEY E */
+ status = "okay";
+};
+
+&d0_uart2 {
+ /* connect MCU */
+ status = "okay";
+};
+
+&d0_uart3 {
+ /* pin header mux with GPIO 92,93 */
+ status = "disabled";
+};
+
+&d0_uart4 {
+ /* unused */
+ status = "disabled";
+};
+
+&ssi0 {
+ /* pin header mux with GPIO 35,36,37,38,39,40 */
+ status = "disabled";
+};
+
+&ssi1 {
+ /* unused */
+ status = "disabled";
+};
+
+&bootspi {
+ /* spi flash */
+ status = "okay";
+ num-cs = <1>;
+ cs-gpios = <&portd 0 GPIO_ACTIVE_LOW>;
+ spi-flash@0 {
+ compatible = "winbond,w25q128jw",
+ "jedec,spi-nor";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <4800000>;
+ rx-sample-delay-ns = <10>;
+ };
+};
+
+&d0_mbox0 {
+ status = "okay";
+};
+
+&d0_mbox1 {
+ status = "okay";
+};
+
+&d0_mbox2 {
+ status = "okay";
+};
+
+&d0_mbox3 {
+ status = "okay";
+};
+
+&d0_mbox4 {
+ status = "okay";
+};
+
+&d0_mbox5 {
+ status = "okay";
+};
+
+&d0_mbox6 {
+ status = "okay";
+};
+
+&d0_mbox7 {
+ status = "okay";
+};
+
+&fan_control {
+ status = "okay";
+};
+
+&d0_i2c0 {
+ /* codec es8388 */
+ status = "okay";
+ d0_es8388_0: es8388-0@11 {
+ compatible = "eswin,es8388";
+ reg = <0x11>;
+ #sound-dai-cells = <0>;
+ eswin-plat = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio0_default &pinctrl_gpio28_default>;
+ front-jack-gpios = <&porta 0 GPIO_ACTIVE_HIGH>;
+ back-jack-gpios = <&porta 28 GPIO_ACTIVE_HIGH>;
+ port {
+ d0_codec0_endpoint: endpoint {
+ system-clock-frequency = <12288000>;
+ remote-endpoint = <&d0_i2s1_endpoint>;
+ };
+ };
+ };
+};
+
+&d0_i2c1 {
+ /* pin header mux with GPIO 46,47 */
+ status = "disabled";
+};
+
+&d0_i2c2 {
+ /* mipi dsi touch ctrl con */
+ status = "disabled";
+};
+
+&d0_i2c3 {
+ /* FUSB303B cc logic */
+ status = "okay";
+ fusb303b@21 {
+ compatible = "fcs,fusb303b";
+ status = "okay";
+ reg = <0x21>;
+ eswin,syscfg = <&d0_sys_con 0x3C0 12>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio5_default>;
+ int-gpios = <&porta 5 GPIO_ACTIVE_HIGH>;
+ connector {
+ label = "USB-C";
+ pd-disable = "true";
+ power-role = "dual";
+ data-role = "dual";
+ compatible = "usb-c-connector";
+ typec-power-opmode = "default";
+ try-power-role = "sink";
+ };
+ };
+
+};
+
+&d0_i2c4 {
+ /* unused */
+ status = "disabled";
+};
+
+&d0_i2c5 {
+ /* PCA9548 */
+ status = "okay";
+};
+
+&d0_i2c6 {
+ /* unused */
+ status = "disabled";
+};
+
+&d0_i2c7 {
+ /* unused */
+ status = "disabled";
+};
+
+&d0_i2c8 {
+ /* unused */
+ status = "disabled";
+};
+
+&d0_i2c9 {
+ /* unused */
+ status = "disabled";
+};
+
+&d0_aon_i2c0 {
+ /* AT24C02C EEPROM */
+ status = "okay";
+ eswin,syscfg = <&d0_sys_con 0x3C0 16>;
+ aon_eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ };
+};
+
+&d0_aon_i2c1 {
+ /* PCA9450 & SiC451 & INA226 & PAC1934 */
+ status = "okay";
+ eswin,syscfg = <&d0_sys_con 0x3C0 15>;
+ iic_hold_time = <0x40>;
+ sic451@10 {
+ compatible = "microchip,pac1934";
+ /*update all register data*/
+ update_time_ms = <1000>;
+ /*The update number of times the energy accumulates*/
+ energy_acc_count = <0>;
+ sense_resistances=<4 4 4 4>;
+ reg = <0x10>;
+ };
+ sic451@11 {
+ compatible = "Vishay,sic451";
+ reg = <0x11>;
+ regulators{
+ vdd_npu1:vdd_npu{
+ regulator-name="VDD_NPU";
+ regulator-min-microvolt=<100000>;
+ regulator-max-microvolt=<1600000>;
+ /* regulator-max-step-microvolt = <100000>; */
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+ pca9450: pmic@25 {
+ compatible = "nxp,pca9450c";
+ interrupts = <134 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x25>;
+ regulators {
+ BUCK1 {
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ BUCK2 {
+ regulator-name = "BUCK2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ BUCK4 {
+ regulator-name = "BUCK4";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ BUCK5 {
+ regulator-name = "BUCK5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ BUCK6 {
+ regulator-name = "BUCK6";
+ regulator-min-microvolt = <1075000>;
+ regulator-max-microvolt = <1075000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO3 {
+ regulator-name = "LDO3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO5 {
+ regulator-name = "LDO5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ u71_sys: ina226@44 {
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u71_sys";
+ reg = <0x44>;
+ shunt-resistor = <1000>;
+ };
+};
+
+&pwm0 {
+ /* fan */
+ status = "okay";
+};
+
+&pvt0 {
+ status = "okay";
+};
+
+&pvt1 {
+ status = "okay";
+};
+
+&wdt0 {
+ status = "disabled";
+};
+
+&wdt1 {
+ status = "disabled";
+};
+
+&wdt2 {
+ status = "disabled";
+};
+
+&wdt3 {
+ status = "disabled";
+};
+
+&die0_rtc {
+ status = "okay";
+};
+
+&timer0 {
+ status = "okay";
+};
+
+&timer1 {
+ status = "okay";
+};
+
+&timer2 {
+ status = "okay";
+};
+
+&timer3 {
+ status = "okay";
+};
+
+&pinctrl {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio21_default &pinctrl_gpio52_default &pinctrl_gpio53_default &pinctrl_gpio42_default
+ &pinctrl_gpio17_default &pinctrl_gpio64_default &pinctrl_gpio65_default &pinctrl_gpio66_default
+ &pinctrl_gpio67_default &pinctrl_gpio18_default &pinctrl_gpio19_default &pinctrl_gpio20_default
+ &pinctrl_gpio7_default &pinctrl_gpio8_default &pinctrl_gpio9_default &pinctrl_gpio10_default
+ &pinctrl_gpio35_default &pinctrl_gpio36_default &pinctrl_gpio37_default &pinctrl_gpio38_default &pinctrl_gpio39_default &pinctrl_gpio40_default
+ &pinctrl_gpio46_default &pinctrl_gpio47_default
+ &pinctrl_gpio92_default &pinctrl_gpio93_default>;
+
+ /* pin header default function for GPIO
+ SPI1 (CS0,SCLK,MOSI,MISO,D2,D3): GPIO 35,36,37,38,39,40
+ I2C1 (SCL,SDA): GPIO 46,47
+ UART3(TX,RX): GPIO 92,93
+ */
+};
+
+/* GPIO USED
+ gpio0 : FP Audio Jack Sense(I)
+ gpio5 : TYPE C cc logic interrupt(I)
+ gpio6 : TYPE C cc logic ID(I)
+ gpio11 : RP Audio Jack Sense(I)
+ gpio12 : PCIE present(I)
+ gpio13 : TF card insert detect(I)
+ gpio14 : Display touch ctrl interrupt(I)
+ gpio15 : Wlan wake host(I)
+ gpio16 : VDD NPU Alert(I)
+ gpio27 : SATA active led ctrl(O)
+ gpio28 : RP audio jack sense(I)
+ gpio29 : EMMC active led ctrl(O)
+ gpio41 : PWM ctrl led(O)
+ gpio43 : USB3.2 Gen1 hub Resetn(O)
+ gpio70 : Map on pin header(J46)
+ gpio71 : CSI fpc con ctrl(O)
+ gpio73 : Map on pin header(J46)
+ gpio74 : CSI fpc con ctrl(O)
+ gpio76 : Map on pin header(J46)
+ gpio77 : CSI fpc con ctrl(O)
+ gpio79 : Map on pin header(J46)
+ gpio80 : CSI fpc con ctrl(O)
+ gpio82 : LED back light power ctrl(O)
+ gpio83 : CSI fpc con ctrl(O)
+ gpio85 : DSI Resetn(O)
+ gpio86 : CSI fpc con ctrl(O)
+ gpio94 : Host wake wlan(I)
+ gpio106 : gphy0 resern(O)
+ gpio111 : gphy1 resern(O)
+*/
+
+&gpio0 {
+ status = "okay";
+};
diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig
index c0695f06820c..332acc518c31 100644
--- a/arch/riscv/configs/win2030_defconfig
+++ b/arch/riscv/configs/win2030_defconfig
@@ -12,8 +12,6 @@ CONFIG_CGROUP_BPF=y
CONFIG_NAMESPACES=y
CONFIG_USER_NS=y
CONFIG_CHECKPOINT_RESTORE=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE="${BR_BINARIES_DIR}/rootfs.cpio"
CONFIG_EXPERT=y
# CONFIG_SYSFS_SYSCALL is not set
CONFIG_PERF_EVENTS=y
@@ -22,7 +20,7 @@ CONFIG_SOC_VIRT=y
CONFIG_SMP=y
CONFIG_RISCV_SBI_V01=y
# CONFIG_RISCV_BOOT_SPINWAIT is not set
-CONFIG_CMDLINE="earlycon=sbi console=ttyS0,115200n8 clk_ignore_unused cma_pernuma=0x2000000 disable_bypass=false"
+CONFIG_CMDLINE="earlycon=sbi console=tty1 console=ttyS0,115200n8 clk_ignore_unused cma_pernuma=0x2000000 disable_bypass=false"
CONFIG_CMDLINE_EXTEND=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_STAT=y
@@ -42,6 +40,9 @@ CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
# CONFIG_IPV6 is not set
CONFIG_NET_SCHED=y
CONFIG_NET_CLS_ACT=y
@@ -51,9 +52,7 @@ CONFIG_PCIEPORTBUS=y
CONFIG_PCIEAER=y
CONFIG_PCIEASPM_PERFORMANCE=y
CONFIG_PCIE_PTM=y
-# CONFIG_PCI_QUIRKS is not set
-CONFIG_PCI_PRI=y
-CONFIG_PCI_PASID=y
+CONFIG_PCIE_ESWIN=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
@@ -153,13 +152,21 @@ CONFIG_REGULATOR=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_DRM=y
+# CONFIG_DRM_I2C_CH7006 is not set
+# CONFIG_DRM_I2C_SIL164 is not set
CONFIG_DRM_I2C_NXP_TDA9950=y
+CONFIG_DRM_RADEON=m
+CONFIG_DRM_AMDGPU=m
+CONFIG_DRM_AMDGPU_SI=y
+CONFIG_DRM_AMDGPU_CIK=y
+CONFIG_DRM_AMDGPU_USERPTR=y
+CONFIG_DRM_AMD_ACP=y
+CONFIG_DRM_NOUVEAU=y
CONFIG_DRM_DISPLAY_CONNECTOR=y
CONFIG_DRM_SIMPLE_BRIDGE=y
CONFIG_DRM_TOSHIBA_TC358768=m
CONFIG_DRM_LEGACY=y
CONFIG_FB=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_SOC=y
@@ -212,6 +219,15 @@ CONFIG_MMC_TEST=y
CONFIG_MMC_DEBUG=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_PCF8563=y
CONFIG_DMADEVICES=y
@@ -245,12 +261,14 @@ CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_NFS_V4_1=y
CONFIG_NFS_V4_2=y
+CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=m
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_DEV_VIRTIO=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC7=y
+CONFIG_XZ_DEC=y
CONFIG_PRINTK_TIME=y
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
CONFIG_CONSOLE_LOGLEVEL_QUIET=15
diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index ab96da43e0c2..09f44434f854 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -415,4 +415,12 @@ config PCIE_VISCONTI_HOST
Say Y here if you want PCIe controller support on Toshiba Visconti SoC.
This driver supports TMPV7708 SoC.
+config PCIE_ESWIN
+ tristate "ESWIN PCIe host controller"
+ depends on PCI_MSI
+ depends on SOC_SIFIVE || COMPILE_TEST
+ select PCIE_DW_HOST
+ help
+ Say Y here if you want PCIe controller support for the ESWIN.
+
endmenu
diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
index bf5c311875a1..927459a28dc7 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o
obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o
obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o
+obj-$(CONFIG_PCIE_ESWIN) += pcie-eswin.o
# The following drivers are for devices that use the generic ACPI
# pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/controller/dwc/pcie-eswin.c b/drivers/pci/controller/dwc/pcie-eswin.c
new file mode 100644
index 000000000000..66941cce9dde
--- /dev/null
+++ b/drivers/pci/controller/dwc/pcie-eswin.c
@@ -0,0 +1,531 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ESWIN PCIe root complex driver
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Authors: Yu Ning <ningyu@eswincomputing.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/resource.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/iopoll.h>
+#include <linux/reset.h>
+#include <linux/eswin-win2030-sid-cfg.h>
+#include <linux/gpio/consumer.h>
+#include <linux/property.h>
+#include "pcie-designware.h"
+
+#undef _IO_DEBUG_
+
+#ifdef _IO_DEBUG_
+#define _writel_relaxed(v, p) ({ u32 __dbg_v; writel_relaxed(v, p); __dbg_v = readl_relaxed(p); printk("CFG 0x%lx : 0x%08x\n",p, __dbg_v); })
+
+// #define _io_read32(p) ({ u32 __dbg_v; __dbg_v = readl(p); printf("RD 0x%lx : 0x%08x\n",p, __dbg_v); __dbg_v; })
+
+#else
+#define _writel_relaxed(v, p) writel_relaxed(v, p)
+// #define _io_read32(p) io_read32(p)
+#endif
+
+#define to_eswin_pcie(x) dev_get_drvdata((x)->dev)
+
+struct eswin_pcie {
+ struct dw_pcie pci;
+ void __iomem *mgmt_base;
+ // void __iomem *sysmgt_base;
+ struct gpio_desc *reset;
+ // struct gpio_desc *pwren;
+ struct clk *pcie_aux;
+ struct clk *pcie_cfg;
+ struct clk *pcie_cr;
+ struct clk *pcie_aclk;
+ struct reset_control *powerup_rst;
+ struct reset_control *cfg_rst;
+ struct reset_control *perst;
+ int gen_x;
+ int lane_x;
+};
+
+#define PCIEMGMT_ACLK_CTRL 0x170
+#define PCIEMGMT_ACLK_CLKEN BIT(31)
+#define PCIEMGMT_XTAL_SEL BIT(20)
+#define PCIEMGMT_DIVSOR 0xf0
+
+#define PCIEMGMT_CFG_CTRL 0x174
+#define PCIEMGMT_CFG_CLKEN BIT(31)
+#define PCIEMGMT_AUX_CLKEN BIT(1)
+#define PCIEMGMT_CR_CLKEN BIT(0)
+
+#define PCIEMGMT_RST_CTRL 0x420
+#define PCIEMGMT_PERST_N BIT(2)
+#define PCIEMGMT_POWERUP_RST_N BIT(1)
+#define PCIEMGMT_CFG_RST_N BIT(0)
+
+#define PCIE_PM_SEL_AUX_CLK BIT(16)
+
+#define PCIEMGMT_APP_HOLD_PHY_RST BIT(6)
+#define PCIEMGMT_APP_LTSSM_ENABLE BIT(5)
+#define PCIEMGMT_DEVICE_TYPE_MASK 0xf
+
+#define PCIEMGMT_LINKUP_STATE_VALIDATE ((0x11<<2)|0x3)
+#define PCIEMGMT_LINKUP_STATE_MASK 0xff
+
+static void eswin_pcie_shutdown(struct platform_device *pdev)
+{
+ struct eswin_pcie *pcie = platform_get_drvdata(pdev);
+
+ /* Bring down link, so bootloader gets clean state in case of reboot */
+ reset_control_assert(pcie->perst);
+}
+
+static int eswin_pcie_start_link(struct dw_pcie *pci)
+{
+ struct device *dev = pci->dev;
+ struct eswin_pcie *pcie = dev_get_drvdata(dev);
+ u32 val;
+
+ /* Enable LTSSM */
+ val = readl_relaxed(pcie->mgmt_base);
+ val |= PCIEMGMT_APP_LTSSM_ENABLE;
+ _writel_relaxed(val, pcie->mgmt_base);
+ return 0;
+}
+
+static int eswin_pcie_link_up(struct dw_pcie *pci)
+{
+ struct device *dev = pci->dev;
+ struct eswin_pcie *pcie = dev_get_drvdata(dev);
+ u32 val;
+
+ val = readl_relaxed(pcie->mgmt_base + 0x100);
+ if ((val & PCIEMGMT_LINKUP_STATE_MASK) == PCIEMGMT_LINKUP_STATE_VALIDATE)
+ return 1;
+ else
+ return 0;
+}
+
+static int eswin_pcie_clk_enable(struct eswin_pcie *pcie)
+{
+ int ret;
+
+ ret = clk_prepare_enable(pcie->pcie_cr);
+ if (ret) {
+ pr_err("PCIe: failed to enable cr clk: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(pcie->pcie_aclk);
+ if (ret) {
+ pr_err("PCIe: failed to enable aclk: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(pcie->pcie_cfg);
+ if (ret) {
+ pr_err("PCIe: failed to enable cfg_clk: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(pcie->pcie_aux);
+ if (ret) {
+ pr_err("PCIe: failed to enable aux_clk: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int eswin_pcie_clk_disable(struct eswin_pcie *eswin_pcie)
+{
+ clk_disable_unprepare(eswin_pcie->pcie_aux);
+ clk_disable_unprepare(eswin_pcie->pcie_cfg);
+ clk_disable_unprepare(eswin_pcie->pcie_cr);
+ clk_disable_unprepare(eswin_pcie->pcie_aclk);
+
+ return 0;
+}
+
+static int eswin_pcie_power_on(struct eswin_pcie *pcie)
+{
+ // struct device *dev = &pdev->dev;
+ int ret = 0;
+
+ /* pciet_cfg_rstn */
+ ret = reset_control_reset(pcie->cfg_rst);
+ WARN_ON(0 != ret);
+
+ /* pciet_powerup_rstn */
+ ret = reset_control_reset(pcie->powerup_rst);
+ WARN_ON(0 != ret);
+
+ /* pcie_perst_n */
+ // ret = reset_control_reset(pcie->perst);
+ // WARN_ON(0 != ret);
+
+ return ret;
+}
+
+static int eswin_pcie_power_off(struct eswin_pcie *eswin_pcie)
+{
+ reset_control_assert(eswin_pcie->perst);
+
+ reset_control_assert(eswin_pcie->powerup_rst);
+
+ reset_control_assert(eswin_pcie->cfg_rst);
+
+ return 0;
+}
+
+/*
+ pinctrl-0 = <&pinctrl_gpio106_default &pinctrl_gpio9_default>;
+ pci-socket-gpios = <&portd 10 GPIO_ACTIVE_LOW>;
+ pci-prsnt-gpios = <&porta 9 GPIO_ACTIVE_LOW>;
+*/
+
+int eswin_evb_socket_power_on(struct device *dev)
+{
+ int err_desc=0;
+ struct gpio_desc *gpio;
+ gpio = devm_gpiod_get(dev, "pci-socket", GPIOD_OUT_LOW);
+ err_desc = IS_ERR(gpio);
+
+ if (err_desc) {
+ pr_debug("No power control gpio found, maybe not needed\n");
+ return 0;
+ }
+
+ gpiod_set_value(gpio,1);
+
+ return err_desc;
+}
+
+/* Not use gpio9 which mux with JTAG1_TDI in EVB */
+
+int eswin_evb_device_scan(struct device *dev)
+{
+ int err_desc=0;
+ struct gpio_desc *gpio;
+ gpio = devm_gpiod_get(dev, "pci-prsnt", GPIOD_IN);
+ err_desc = IS_ERR(gpio);
+
+ if (err_desc) {
+ pr_debug("failed to get prsnt gpio, debug: %d, gpio addr:%px\n",err_desc,gpio);
+ return err_desc;
+ }
+
+ err_desc = gpiod_get_value(gpio);
+
+ /* If gpio is low means device exist */
+ if (!gpiod_get_value(gpio)) {
+ pr_info("No device exist\n");
+ return -ENODEV;
+ } else {
+ return 0;
+ }
+}
+
+static int eswin_pcie_host_init(struct dw_pcie_rp *pp)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct eswin_pcie *pcie = to_eswin_pcie(pci);
+ int ret;
+ u32 val;
+
+ /* evb has device exist detect gpio, NO use */
+ // ret = eswin_evb_device_scan(pcie->pci.dev);
+ // if (ret)
+ // return ret;
+
+ /* pciet_aux_clken, pcie_cfg_clken */
+ ret = eswin_pcie_clk_enable(pcie);
+ if (ret)
+ return ret;
+
+ ret = eswin_pcie_power_on(pcie);
+ if (ret)
+ return ret;
+
+ ret = win2030_tbu_power(pcie->pci.dev, true);
+ if (ret)
+ return ret;
+
+ /* set device type : rc */
+ val = readl_relaxed(pcie->mgmt_base);
+ val &= 0xfffffff0;
+ _writel_relaxed(val|0x4, pcie->mgmt_base);
+
+ ret = reset_control_assert(pcie->perst);
+ WARN_ON(0 != ret);
+
+ eswin_evb_socket_power_on(pcie->pci.dev);
+ msleep(100);
+ ret = reset_control_deassert(pcie->perst);
+ WARN_ON(0 != ret);
+
+ /* app_hold_phy_rst */
+ val = readl_relaxed(pcie->mgmt_base);
+ val &= ~(0x40);
+ _writel_relaxed(val, pcie->mgmt_base);
+
+ /* wait pm_sel_aux_clk to 0 */
+ while (1) {
+ val = readl_relaxed(pcie->mgmt_base + 0x100);
+ if (!(val & PCIE_PM_SEL_AUX_CLK)) {
+ break;
+ }
+ msleep(1);
+ }
+
+ /* config eswin vendor id and win2030 device id */
+ dw_pcie_writel_dbi(pci, 0, 0x20301fe1);
+
+ if (pcie->gen_x == 3) {
+ /* GEN3 */
+ dw_pcie_writel_dbi(pci, 0xa0, 0x00010003);
+
+ /* GEN3 config , this config only for zebu*/
+ // val = dw_pcie_readl_dbi(pci, 0x890);
+ // val = 0x00012001;
+ // dw_pcie_writel_dbi(pci, 0x890, val);
+
+ /* LINK_CAPABILITIES_REG : PCIE_CAP_BASE + 0xc */
+ val = dw_pcie_readl_dbi(pci, 0x7c);
+ val &= 0xfffffff0;
+ /* GEN3 */
+ val |= 0x3;
+ dw_pcie_writel_dbi(pci, 0x7c, val);
+ } else if (pcie->gen_x == 2) {
+ /* GEN2 */
+ dw_pcie_writel_dbi(pci, 0xa0, 0x00010002);
+
+ /* LINK_CAPABILITIES_REG : PCIE_CAP_BASE + 0xc */
+ val = dw_pcie_readl_dbi(pci, 0x7c);
+ val &= 0xfffffff0;
+ val |= 0x2;
+ dw_pcie_writel_dbi(pci, 0x7c, val);
+ }else {
+ /* GEN1 */
+ dw_pcie_writel_dbi(pci, 0xa0, 0x00010001);
+
+ /* LINK_CAPABILITIES_REG : PCIE_CAP_BASE + 0xc */
+ val = dw_pcie_readl_dbi(pci, 0x7c);
+ val &= 0xfffffff0;
+ val |= 0x1;
+ dw_pcie_writel_dbi(pci, 0x7c, val);
+ }
+
+ /* LINK_CAPABILITIES_REG : PCIE_CAP_BASE + 0xc : laneX */
+ val = dw_pcie_readl_dbi(pci, 0x7c);
+ val &= 0xfffffc0f;
+ if (pcie->lane_x == 4) {
+ val |= 0x40;
+ } else if (pcie->lane_x == 2) {
+ val |= 0x20;
+ } else {
+ val |= 0x10;
+ }
+
+ dw_pcie_writel_dbi(pci, 0x7c, val);
+
+ /* lane fix config, real driver NOT need, default x4 */
+ val = dw_pcie_readl_dbi(pci, 0x8c0);
+ val &= 0xffffff80;
+ if (pcie->lane_x == 4) {
+ val |= 0x44;
+ } else if (pcie->lane_x == 2) {
+ val |= 0x42;
+ } else {
+ val |= 0x41;
+ }
+ dw_pcie_writel_dbi(pci, 0x8c0, val);
+
+ /* config msix table size to 0 in RC mode because our RC not support msix */
+ val = dw_pcie_readl_dbi(pci, 0xb0);
+ val &= ~(0x7ff<<16);
+ dw_pcie_writel_dbi(pci, 0xb0, val);
+
+ /* config max payload size to 4K */
+ val = dw_pcie_readl_dbi(pci, 0x74);
+ val &= ~(0x7);
+ val |= 0x5;
+ dw_pcie_writel_dbi(pci, 0x74, val);
+
+ val = dw_pcie_readl_dbi(pci, 0x78);
+ val &= ~(0x7<<5);
+ val |= (0x5<<5);
+ dw_pcie_writel_dbi(pci, 0x78, val);
+
+#if 0
+ /* config GEN3_EQ_PSET_REQ_VEC */
+ val = dw_pcie_readl_dbi(pci, 0x8a8);
+ val &= ~(0xffff<<8);
+ val |= (0x480<<8);
+ dw_pcie_writel_dbi(pci, 0x8a8, val);
+
+ /* config preset from lane0 to lane3 */
+ val = dw_pcie_readl_dbi(pci, 0x154);
+ val &= 0xfff0fff0;
+ val |= 0x70007;
+ dw_pcie_writel_dbi(pci, 0x154, val);
+
+ val = dw_pcie_readl_dbi(pci, 0x158);
+ val &= 0xfff0fff0;
+ val |= 0x70007;
+ dw_pcie_writel_dbi(pci, 0x158, val);
+#endif
+
+ /* config support 32 msi vectors */
+ dw_pcie_writel_dbi(pci, 0x50, 0x018a7005);
+
+ /* disable msix cap */
+ val = dw_pcie_readl_dbi(pci, 0x70);
+ val &= 0xffff00ff;
+ dw_pcie_writel_dbi(pci, 0x70, val);
+
+ return 0;
+}
+
+static const struct dw_pcie_host_ops eswin_pcie_host_ops = {
+ .host_init = eswin_pcie_host_init,
+};
+
+static const struct dw_pcie_ops dw_pcie_ops = {
+ .start_link = eswin_pcie_start_link,
+ .link_up = eswin_pcie_link_up,
+};
+
+static int __exit eswin_pcie_remove(struct platform_device *pdev)
+{
+ struct eswin_pcie *pcie = platform_get_drvdata(pdev);
+
+ dw_pcie_host_deinit(&pcie->pci.pp);
+
+ win2030_tbu_power(&pdev->dev, false);
+ eswin_pcie_power_off(pcie);
+ eswin_pcie_clk_disable(pcie);
+
+ return 0;
+}
+
+static int eswin_pcie_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct dw_pcie *pci;
+ struct eswin_pcie *pcie;
+
+ pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
+ if (!pcie)
+ return -ENOMEM;
+ pci = &pcie->pci;
+ pci->dev = dev;
+ pci->ops = &dw_pcie_ops;
+ pci->pp.ops = &eswin_pcie_host_ops;
+
+ /* SiFive specific region: mgmt */
+ pcie->mgmt_base = devm_platform_ioremap_resource_byname(pdev, "mgmt");
+ if (IS_ERR(pcie->mgmt_base))
+ return PTR_ERR(pcie->mgmt_base);
+
+ // /* Fetch GPIOs */
+ // pcie->reset = devm_gpiod_get_optional(dev, "reset-gpios", GPIOD_OUT_LOW);
+ // if (IS_ERR(pcie->reset))
+ // return dev_err_probe(dev, PTR_ERR(pcie->reset), "unable to get reset-gpios\n");
+
+ // /* Fetch clocks */
+ pcie->pcie_aux = devm_clk_get(dev, "pcie_aux_clk");
+ if (IS_ERR(pcie->pcie_aux)) {
+ dev_err(dev, "pcie_aux clock source missing or invalid\n");
+ return PTR_ERR(pcie->pcie_aux);
+ }
+
+ pcie->pcie_cfg = devm_clk_get(dev, "pcie_cfg_clk");
+ if (IS_ERR(pcie->pcie_cfg)) {
+ dev_err(dev, "pcie_cfg_clk clock source missing or invalid\n");
+ return PTR_ERR(pcie->pcie_cfg);
+ }
+
+ pcie->pcie_cr = devm_clk_get(dev, "pcie_cr_clk");
+ if (IS_ERR(pcie->pcie_cr)) {
+ dev_err(dev, "pcie_cr_clk clock source missing or invalid\n");
+ return PTR_ERR(pcie->pcie_cr);
+ }
+
+ pcie->pcie_aclk = devm_clk_get(dev, "pcie_aclk");
+
+ if (IS_ERR(pcie->pcie_aclk)) {
+ dev_err(dev, "pcie_aclk clock source missing or invalid\n");
+ return PTR_ERR(pcie->pcie_aclk);
+ }
+
+ /* Fetch reset */
+ pcie->powerup_rst = devm_reset_control_get_optional(&pdev->dev, "pcie_powerup");
+ if (IS_ERR_OR_NULL(pcie->powerup_rst)) {
+ dev_err_probe(dev, PTR_ERR(pcie->powerup_rst), "unable to get powerup reset\n");
+ }
+
+ pcie->cfg_rst = devm_reset_control_get_optional(&pdev->dev, "pcie_cfg");
+ if (IS_ERR_OR_NULL(pcie->cfg_rst)) {
+ dev_err_probe(dev, PTR_ERR(pcie->cfg_rst), "unable to get cfg reset\n");
+ }
+
+ pcie->perst = devm_reset_control_get_optional(&pdev->dev, "pcie_pwren");
+ if (IS_ERR_OR_NULL(pcie->perst)) {
+ dev_err_probe(dev, PTR_ERR(pcie->perst), "unable to get perst\n");
+ }
+
+ device_property_read_u32(&pdev->dev, "gen-x", &pcie->gen_x);
+ device_property_read_u32(&pdev->dev, "lane-x", &pcie->lane_x);
+
+ platform_set_drvdata(pdev, pcie);
+
+ return dw_pcie_host_init(&pci->pp);
+}
+
+static const struct of_device_id eswin_pcie_of_match[] = {
+ { .compatible = "eswin,win2030-pcie", },
+ {},
+};
+
+static struct platform_driver eswin_pcie_driver = {
+ .driver = {
+ .name = "eswin-pcie",
+ .of_match_table = eswin_pcie_of_match,
+ .suppress_bind_attrs = true,
+ },
+ .probe = eswin_pcie_probe,
+ .remove = __exit_p(eswin_pcie_remove),
+ .shutdown = eswin_pcie_shutdown,
+};
+
+// builtin_platform_driver(eswin_pcie_driver);
+module_platform_driver(eswin_pcie_driver);
+
+MODULE_DEVICE_TABLE(of, eswin_pcie_of_match);
+MODULE_DESCRIPTION("PCIe host controller driver for ESWIN WIN2030 SoCs");
+MODULE_AUTHOR("Ning Yu <ningyu@eswincomputing.com>");
+MODULE_LICENSE("GPL v2");
\ No newline at end of file
--
2.47.0
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