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6904001a3c
kernel/0001-Added-dts-and-defconfig-files-modified-8250_dwlib.c-.patch
Jason Montleon 6904001a3c Update to 6.6.67
2024-12-19 16:34:44 -05:00

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From 3958164a85a3c25a70480364004c9bc64cddd52d Mon Sep 17 00:00:00 2001
From: linmin <linmin@eswincomputing.com>
Date: Mon, 11 Mar 2024 14:43:40 +0800
Subject: [PATCH 001/219] Added dts and defconfig files,modified 8250_dwlib.c
for print
Changelogs:
1.Added dts and defconfig for ESWIN evb board
2.Modified 8250_dwlib.c to adapt ESWIN uart IP
---
arch/riscv/boot/dts/eswin/Makefile | 4 +
arch/riscv/boot/dts/eswin/eic7700-evb.dts | 860 +++++
.../riscv/boot/dts/eswin/eic7700-pinctrl.dtsi | 1234 ++++++++
.../dts/eswin/eswin-win2030-arch-d2d.dtsi | 869 +++++
.../boot/dts/eswin/eswin-win2030-arch.dtsi | 484 +++
.../dts/eswin/eswin-win2030-die0-noc.dtsi | 2804 +++++++++++++++++
.../dts/eswin/eswin-win2030-die0-soc.dtsi | 2403 ++++++++++++++
.../dts/eswin/eswin-win2030-die1-noc.dtsi | 2804 +++++++++++++++++
.../dts/eswin/eswin-win2030-die1-soc.dtsi | 2322 ++++++++++++++
.../dts/eswin/eswin-win2030-platform.dtsi | 83 +
arch/riscv/boot/dts/eswin/eswin-win2030.dts | 1503 +++++++++
arch/riscv/configs/win2030_defconfig | 327 ++
drivers/tty/serial/8250/8250_dwlib.c | 6 +-
include/dt-bindings/clock/win2030-clock.h | 624 ++++
.../dt-bindings/interconnect/eswin,win2030.h | 160 +
include/dt-bindings/mailbox/eswin-mailbox.h | 88 +
.../dt-bindings/memory/eswin-win2030-sid.h | 164 +
.../dt-bindings/reset/eswin,win2030-syscrg.h | 693 ++++
18 files changed, 17429 insertions(+), 3 deletions(-)
create mode 100644 arch/riscv/boot/dts/eswin/Makefile
create mode 100644 arch/riscv/boot/dts/eswin/eic7700-evb.dts
create mode 100644 arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
create mode 100644 arch/riscv/boot/dts/eswin/eswin-win2030-arch-d2d.dtsi
create mode 100644 arch/riscv/boot/dts/eswin/eswin-win2030-arch.dtsi
create mode 100644 arch/riscv/boot/dts/eswin/eswin-win2030-die0-noc.dtsi
create mode 100644 arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
create mode 100644 arch/riscv/boot/dts/eswin/eswin-win2030-die1-noc.dtsi
create mode 100644 arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
create mode 100644 arch/riscv/boot/dts/eswin/eswin-win2030-platform.dtsi
create mode 100644 arch/riscv/boot/dts/eswin/eswin-win2030.dts
create mode 100644 arch/riscv/configs/win2030_defconfig
create mode 100755 include/dt-bindings/clock/win2030-clock.h
create mode 100644 include/dt-bindings/interconnect/eswin,win2030.h
create mode 100755 include/dt-bindings/mailbox/eswin-mailbox.h
create mode 100644 include/dt-bindings/memory/eswin-win2030-sid.h
create mode 100755 include/dt-bindings/reset/eswin,win2030-syscrg.h
diff --git a/arch/riscv/boot/dts/eswin/Makefile b/arch/riscv/boot/dts/eswin/Makefile
new file mode 100644
index 000000000000..dd52dd167996
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_SOC_SIFIVE) += eswin-win2030.dtb \
+ eic7700-evb.dtb
+obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb.dts b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
new file mode 100644
index 000000000000..07976356e5b5
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
@@ -0,0 +1,860 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for Eswin EIC7700 SoC.
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+
+#define RTCCLK_FREQ 1000000
+#define LSPCLK_FREQ 200000000
+
+/* reserve 2GB space for ddr ecc */
+#define MEMORY_SIZE_H 0x3
+#define MEMORY_SIZE_L 0x80000000
+#define CMA_SIZE 0x10000000
+
+#include "eswin-win2030-die0-soc.dtsi"
+#include "eic7700-pinctrl.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "ESWIN EIC7700";
+ compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000",
+ "sifive,fu740", "eswin,eic7700";
+
+ aliases {
+ serial0 = &d0_uart0;
+ ethernet0 = &d0_gmac0;
+ ethernet1 = &d0_gmac1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpus {
+ timebase-frequency = <RTCCLK_FREQ>;
+ };
+/*
+ memory@59000000 {
+ device_type = "memory";
+ reg = <0x0 0x59000000 0x0 0x400000>;
+ numa-node-id = <0>;
+ };
+*/
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 MEMORY_SIZE_H MEMORY_SIZE_L>;
+ numa-node-id = <0>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 CMA_SIZE>;
+ alignment = <0x0 0x1000>;
+ alloc-ranges = <0x0 0x80000000 MEMORY_SIZE_H MEMORY_SIZE_L>;
+ linux,cma-default;
+ };
+/*
+ npu0_reserved: sprammemory@59000000 {
+ no-map;
+ reg = <0x0 0x59000000 0x0 0x400000>;
+ };
+*/
+ /*
+ dsp_reserved0: dsp@90000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x90000000 0x0 0x1000000>;
+ reusable;
+ status = "okay";
+ };
+ */
+
+ dsp_reserved1: dsp@91000000 {
+ reg = <0 0x91000000 0 0x200000>;
+ no-map;
+ };
+
+ smpmemtest_rsv0@91200000 {
+ reg = <0 0x91200000 0 0x2000000>;
+ no-map;
+ };
+
+ lpcpu0_reserved: lpcpu@a0000000 {
+ no-map;
+ reg = <0x0 0xa0000000 0x0 0x100000>;
+ };
+
+ secure_memory_nid_0_part_0 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x0 0xb0000000 0x0 0x8000000>;
+ no-map;
+ };
+
+ secure_memory_nid_0_part_1 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x0 (0xb0000000 + 0x8000000) 0x0 0x8000000>;
+ no-map;
+ };
+
+ mmz_nid_0_part_0 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x1 0x80000000 0x1 0x80000000>;
+ no-map;
+ };
+
+ mmz_nid_0_part_1 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x3 0x0 0x1 0x0>;
+ no-map;
+ };
+ };
+
+ soc {
+ reset_test@1e00e000 {
+ compatible = "reset_test";
+ resets = <&d0_reset SCPU_RST_CTRL SW_SCPU_BUS_RSTN>,
+ <&d0_reset SCPU_RST_CTRL SW_SCPU_CORE_RSTN>,
+ <&d0_reset SCPU_RST_CTRL SW_SCPU_DBG_RSTN>;
+ reset-names = "bus", "core", "dbg";
+ };
+ };
+
+ npu0_reserved: sprammemory@59000000 {
+ no-map;
+ reg = <0x0 0x59000000 0x0 0x400000>;
+ };
+};
+
+&d0_clock {
+ status = "okay";
+};
+
+&d0_reset {
+ status = "okay";
+};
+
+&d0_pmu {
+ status = "disabled";
+};
+
+&ddr0 {
+ status = "disabled";
+};
+
+&ddr1 {
+ status = "disabled";
+};
+
+&smmu0 {
+ status = "okay";
+};
+
+&smmu_pmu0 {
+ status = "disabled";
+};
+
+&dev_foo_b {
+ status = "disabled";
+};
+
+&dev_foo_a {
+ status = "okay";
+};
+
+&d0_cfg_noc {
+ status = "okay";
+};
+
+&d0_llc_noc {
+ status = "okay";
+ stat,0 = "TracePort:ddr0_p0_req";
+ stat,1 = "TracePort:ddr1_p0_req";
+ //latency,0 = "TracePort:llcnoc_trans_probe";
+ //pending,0 = "TracePort:llcnoc_trans_probe";
+};
+
+&d0_sys_noc {
+ status = "okay";
+
+ //eswin,DSPT-qos-owner;
+ //eswin,NPU-qos-owner;
+ //eswin,SPISLV_TBU3-qos-owner;
+
+ stat,0 = "TracePort:ddr0_p1_req",
+ "InitFlow:mcput_snoc_mp/I/0";
+
+ stat,1 = "TracePort:ddr0_p2_req",
+ "InitFlow:dspt_snoc/I/0",
+ "AddrBase:0x81000000", "AddrSize:0x30",
+ "Opcode:RdWrLockUrg", "Status:ReqRsp", "Length:0x8000", "Urgency:0x0";
+
+ stat,2 = "TracePort:ddr1_p1_req",
+ "Status:Req", "AddrSize:0x28";
+
+ stat,3 = "TracePort:ddr1_p2_req";
+
+ latency,0 = "TracePort:sysnoc_trans_probe_0", "AddrSize:0x0";
+ latency,1 = "TracePort:sysnoc_trans_probe_1","Mode:latency","AddrBase:0x82000000","AddrSize:0x28","Opcode:RdWr";
+ //latency,2 = "TracePort:sysnoc_trans_probe_2";
+
+ //pending,0 = "TracePort:sysnoc_trans_probe_0";
+ //pending,1 = "TracePort:sysnoc_trans_probe_1","Mode:latency","AddrBase:0x82000000","AddrSize:0x0","Opcode:RdWr";
+ pending,0 = "TracePort:sysnoc_trans_probe_2", "AddrSize:0x3";
+};
+
+&d0_media_noc {
+ status = "okay";
+
+ //eswin,GPU-qos-owner;
+ //eswin,TBU2-qos-owner;
+ //eswin,VC-qos-owner;
+
+ stat,0 = "TracePort:ddr0_p3_req";
+ stat,1 = "TracePort:ddr1_p3_req";
+ //latency,0 = "TracePort:mnoc_trans_probe";
+ //pending,0 = "TracePort:mnoc_trans_probe";
+};
+
+&d0_realtime_noc {
+ status = "okay";
+
+ //eswin,TBU0-qos-owner;
+ //eswin,VO-qos-owner;
+
+ stat,0 = "TracePort:ddr0_p4_req";
+ stat,1 = "TracePort:ddr1_p4_req";
+ //latency,0 = "TracePort:rnoc_trans_probe";
+ //pending,0 = "TracePort:rnoc_trans_probe";
+};
+
+&d0_noc_wdt {
+ status = "disabled";
+};
+
+&d0_ipc_scpu {
+ status = "okay";
+};
+
+&d0_lpcpu {
+ status = "disabled";
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio106_default>;
+ pci-socket-gpios = <&portd 10 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+};
+
+&d0_nvdla {
+ status = "okay";
+};
+
+&d0_dsp_subsys {
+ status = "okay";
+};
+
+&d0_dsp0 {
+ status = "okay";
+};
+
+&d0_dsp1 {
+ status = "okay";
+};
+
+&d0_dsp2 {
+ status = "okay";
+};
+
+&d0_dsp3 {
+ status = "okay";
+};
+
+&d0_sofdsp {
+ status = "disabled";
+};
+
+&gpu0 {
+ status = "okay";
+};
+
+&gc820 {
+ status = "okay";
+};
+
+&vdec0 {
+ status = "okay";
+};
+
+&venc0 {
+ status = "okay";
+};
+
+&video_output {
+ status = "okay";
+};
+
+&dc8k {
+ status = "okay";
+};
+
+&dc8k_test {
+ status = "disabled";
+};
+
+&virtual_display {
+ status = "okay";
+};
+
+&dsi_output {
+ status = "disabled";
+};
+
+&dsi_controller {
+ status = "disabled";
+};
+
+&dw_hdmi {
+ status = "okay";
+ eswin-plat = <1>;
+ ports {
+ port@2 {
+ reg = <2>;
+ hdmi_in_i2s: endpoint@1 {
+ system-clock-frequency = <12288000>;
+ remote-endpoint = <&d0_i2s0_endpoint0>;
+ };
+ };
+ };
+};
+
+&dw_hdmi_hdcp2 {
+ status = "okay";
+};
+
+&d0_i2s0 {
+ status = "okay";
+ eswin-plat = <1>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ d0_i2s0_port0: port@0 {
+ reg = <0>;
+ d0_i2s0_endpoint0: endpoint {
+ remote-endpoint = <&hdmi_in_i2s>;
+ dai-format = "i2s";
+ };
+ };
+ d0_i2s0_port1: port@1 {
+ reg = <1>;
+ d0_i2s0_endpoint1: endpoint {
+ remote-endpoint = <&d0_codec0_endpoint>;
+ dai-format = "i2s";
+ };
+ };
+ };
+};
+
+&d0_i2s1 {
+ status = "okay";
+ eswin-plat = <1>;
+ d0_i2s1_port: port {
+ d0_i2s1_endpoint: endpoint {
+ remote-endpoint = <&d0_codec1_endpoint>;
+ dai-format = "i2s";
+ };
+ };
+};
+
+&d0_i2s2 {
+ status = "okay";
+ eswin-plat = <1>;
+ d0_i2s2_port: port {
+ d0_i2s2_endpoint: endpoint {
+ remote-endpoint = <&d0_codec2_endpoint>;
+ dai-format = "i2s";
+ };
+ };
+};
+
+&d0_soundcard {
+ status = "disabled";
+};
+
+&d0_graphcard0 {
+ status = "okay";
+ dais = <&d0_i2s1_port>;
+};
+
+&d0_graphcard1 {
+ status = "okay";
+ dais = <&d0_i2s2_port>;
+};
+
+&d0_graphcard2 {
+ status = "okay";
+ dais = <&d0_i2s0_port0>, <&d0_i2s0_port1>;
+};
+
+&d0_dummy_codec {
+ status = "disabled";
+};
+
+&d0_thruout{
+ status = "disabled";
+};
+
+&isp_0 {
+ status = "disabled";
+};
+
+&isp_1 {
+ status = "disabled";
+};
+
+&dw200 {
+ status = "okay";
+};
+
+&mipi_dphy_rx {
+ status = "disabled";
+};
+
+&csi_dma0 {
+ status = "disabled";
+};
+
+&csi_dma1 {
+ status = "disabled";
+};
+
+&csi2_0 {
+ status = "disabled";
+};
+
+&csi2_1 {
+ status = "disabled";
+};
+
+&sdhci_emmc {
+ /* emmc */
+ status = "okay";
+};
+
+&sdio0 {
+ /* sd card */
+ status = "okay";
+};
+
+&sdio1 {
+ /* wifi module */
+ status = "disabled";
+};
+
+&d0_gmac0 {
+ mac-address=[00 00 00 00 00 00];
+ status = "okay";
+};
+
+&d0_gmac1 {
+ mac-address=[00 00 00 00 00 00];
+ status = "okay";
+};
+
+&d0_sata {
+ status = "okay";
+};
+
+&d0_usbdrd3_0 {
+ status = "okay";
+};
+
+&d0_usbdrd_dwc3_0 {
+ status = "okay";
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+};
+
+&d0_usbdrd3_1 {
+ status = "okay";
+};
+
+&d0_usbdrd_dwc3_1 {
+ status = "okay";
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+};
+
+&d0_dmac0 {
+ status = "okay";
+};
+
+&d0_aon_dmac {
+ status = "okay";
+};
+
+&d0_uart0 {
+ /* debug */
+ status = "okay";
+};
+
+&d0_uart1 {
+ /* have cts & rts */
+ status = "okay";
+};
+
+&d0_uart2 {
+ /* rs485 */
+ status = "okay";
+};
+
+&d0_uart3 {
+ status = "disabled";
+};
+
+&d0_uart4 {
+ status = "disabled";
+};
+
+&ssi0 {
+ /* spi flash */
+ status = "okay";
+ num-cs = <2>;
+ spi-flash@0 {
+ compatible = "winbond,w25q128fw",
+ "jedec,spi-nor";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <4800000>;
+ rx-sample-delay-ns = <10>;
+ };
+ spi-flash@1 {
+ compatible = "winbond,w25q128fw",
+ "jedec,spi-nor";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <4800000>;
+ rx-sample-delay-ns = <10>;
+ };
+};
+
+&ssi1 {
+ /* spi flash */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi2_default>;
+ num-cs = <2>;
+ spi-flash@0 {
+ compatible = "winbond,w25q128fw",
+ "jedec,spi-nor";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <4800000>;
+ rx-sample-delay-ns = <10>;
+ };
+ spi-flash@1 {
+ compatible = "winbond,w25q128fw",
+ "jedec,spi-nor";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <4800000>;
+ rx-sample-delay-ns = <10>;
+ };
+};
+
+&d0_mbox0 {
+ status = "okay";
+};
+
+&d0_mbox1 {
+ status = "okay";
+};
+
+&d0_mbox2 {
+ status = "okay";
+};
+
+&d0_mbox3 {
+ status = "okay";
+};
+
+&d0_mbox4 {
+ status = "okay";
+};
+
+&d0_mbox5 {
+ status = "okay";
+};
+
+&d0_mbox6 {
+ status = "okay";
+};
+
+&d0_mbox7 {
+ status = "okay";
+};
+
+&fan_control {
+ status = "disabled";
+};
+
+&d0_i2c0 {
+ /* codec es8388 */
+ status = "okay";
+ d0_es8388_0: es8388-0@11 {
+ compatible = "eswin,es8388";
+ reg = <0x11>;
+ #sound-dai-cells = <0>;
+ port {
+ d0_codec0_endpoint: endpoint {
+ system-clock-frequency = <12288000>;
+ remote-endpoint = <&d0_i2s0_endpoint1>;
+ };
+ };
+ };
+ d0_es8388_1: es8388-1@10 {
+ compatible = "eswin,es8388";
+ reg = <0x10>;
+ #sound-dai-cells = <0>;
+ port {
+ d0_codec1_endpoint: endpoint {
+ system-clock-frequency = <12288000>;
+ remote-endpoint = <&d0_i2s1_endpoint>;
+ };
+ };
+ };
+};
+
+&d0_i2c1 {
+ /* codec es8388 */
+ status = "okay";
+ d0_es8388_2: es8388-2@10 {
+ compatible = "eswin,es8388";
+ reg = <0x10>;
+ #sound-dai-cells = <0>;
+ port {
+ d0_codec2_endpoint: endpoint {
+ system-clock-frequency = <12288000>;
+ remote-endpoint = <&d0_i2s2_endpoint>;
+ };
+ };
+ };
+};
+
+&d0_i2c2 {
+ /* mipi dsi */
+ status = "disabled";
+};
+
+&d0_i2c3 {
+ /* mipi csi0/csi1 */
+ status = "disabled";
+};
+
+&d0_i2c4 {
+ /* mipi csi2/csi3 */
+ status = "disabled";
+};
+
+&d0_i2c5 {
+ /* mipi csi4/csi5 */
+ status = "disabled";
+};
+
+&d0_i2c6 {
+ /* unused */
+ status = "disabled";
+};
+
+&d0_i2c7 {
+ /* unused */
+ status = "disabled";
+};
+
+&d0_i2c8 {
+ /* io extended for mipi csi */
+ status = "disabled";
+};
+
+&d0_i2c9 {
+ /* unused */
+ status = "disabled";
+};
+
+&d0_aon_i2c0 {
+ /* temp sensor & rtc */
+ status = "okay";
+ eswin,syscfg = <&d0_sys_con 0x3C0 16>;
+ rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+};
+
+&d0_aon_i2c1 {
+ /* mpq8785 & ina226x4 */
+ status = "okay";
+ eswin,syscfg = <&d0_sys_con 0x3C0 15>;
+ iic_hold_time = <0x10>;
+ mpq8785@10 {
+ compatible = "mps,mpq8785";
+ reg = <0x10>;
+ regulators{
+ npu_vcc1:npu_svcc{
+ regulator-name="NPU_SVCC";
+ regulator-min-microvolt=<1000000>;
+ regulator-max-microvolt=<6400000>;
+ regulator-min-microamp=<10000000>;
+ regulator-max-microamp=<40000000>;
+ };
+ npu_vcc2:npu_lvcc{
+ regulator-name="NPU_LVCC";
+ regulator-min-microvolt=<1000000>;
+ regulator-max-microvolt=<8000000>;
+ regulator-min-microamp=<10000000>;
+ regulator-max-microamp=<40000000>;
+ };
+ };
+ };
+ u80_cpu: ina226@45 {
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u80_CPU";
+ reg = <0x45>;
+ shunt-resistor = <1000>;
+ };
+ u82_soc: ina226@44 {
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u82_soc";
+ reg = <0x44>;
+ shunt-resistor = <1000>;
+ };
+ u83_lpddr4: ina226@41 {
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u83_lpddr4";
+ reg = <0x41>;
+ shunt-resistor = <1000>;
+ };
+ u99_dc: ina226@4c {
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u99_dc";
+ reg = <0x4c>;
+ shunt-resistor = <1000>;
+ };
+};
+
+&pwm0 {
+ /* fan */
+ status = "disabled";
+};
+
+&pvt0 {
+ status = "okay";
+};
+
+&pvt1 {
+ status = "okay";
+};
+
+&wdt0 {
+ status = "disabled";
+};
+
+&wdt1 {
+ status = "disabled";
+};
+
+&wdt2 {
+ status = "disabled";
+};
+
+&wdt3 {
+ status = "disabled";
+};
+
+&die0_rtc {
+ status = "okay";
+};
+
+&timer0 {
+ status = "okay";
+};
+
+&timer1 {
+ status = "okay";
+};
+
+&timer2 {
+ status = "okay";
+};
+
+&timer3 {
+ status = "okay";
+};
+
+&pinctrl {
+ status = "okay";
+};
+
+/*
+ gpio function unused
+ group A: gpio1~6,12~15, 17~27, 29~31
+ group B: gpio32~63
+ group C: gpio64~93, 95
+ group D: gpio96~105
+
+ gpio0 : head phone plug/unplug detection0(I)
+ gpio7 : led back light power on/off(O)
+ gpio8 : dsi touch interrupt(I)
+ gpio9 : pcie present(I)
+ gpio10 : software define key input(I)
+ gpio11 : head phone plug/unplug detection2(I)
+ gpio16 : gphy1 resern(O)
+ gpio28 : head phone plug/unplug detection1(I)
+ gpio94 : gphy0 resern(O)
+ gpio106 : pcie socket power on/off(O)
+ gpio107 : tf card power on/off(O)
+ gpio108 : system led0(O)
+ gpio109 : system led1(O)
+ gpio110 : system led2(O)
+ gpio111 : mipi dsi resetn(O)
+*/
+
+&gpio0 {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi b/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
new file mode 100644
index 000000000000..a6dd5aaeee00
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
@@ -0,0 +1,1234 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Include file for pin control of Eswin EIC770x family SoC.
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ */
+#include "eswin-win2030-die0-soc.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ soc {
+ pinctrl: pinctrl@0x51600080 {
+ compatible = "eswin,eic7700-pinctrl";
+ reg = <0x0 0x51600080 0x0 0x1FFF80>;
+ status = "disabled";
+ //func0
+ pinctrl_sdio0_default: sdio0-default{
+ mux {
+ groups = "sdio0_group";
+ function = "sdio0_func";
+ };
+ };
+ pinctrl_sdio1_default: sdio1-default{
+ mux {
+ groups = "sdio1_group";
+ function = "sdio1_func";
+ };
+ };
+ pinctrl_por_sel_default: por_sel-default{
+ mux {
+ groups = "por_sel_group";
+ function = "por_sel_func";
+ };
+ };
+ pinctrl_jtag0_default: jtag0-default{
+ mux {
+ groups = "jtag0_group";
+ function = "jtag0_func";
+ };
+ };
+ pinctrl_jtag1_default: jtag1-default{
+ mux {
+ groups = "jtag1_group";
+ function = "jtag1_func";
+ };
+ };
+ pinctrl_jtag2_default: jtag2-default{
+ mux {
+ groups = "jtag2_group";
+ function = "jtag2_func";
+ };
+ };
+ pinctrl_pcie_default: pcie-default{
+ mux{
+ groups = "pcie_group";
+ function = "pcie_func";
+ };
+ };
+ pinctrl_hdmi_default: hdmi-default{
+ mux{
+ groups = "hdmi_group";
+ function = "hdmi_func";
+ };
+ };
+ pinctrl_rgmii0_default: rgmii0-default{
+ mux {
+ groups = "rgmii0_group";
+ function = "rgmii0_func";
+ };
+ };
+ pinctrl_rgmii1_default: rgmii1-default{
+ mux{
+ groups = "rgmii1_group";
+ function = "rgmii1_func";
+ };
+ };
+ pinctrl_spi0_default: spi0-default{
+ mux {
+ groups = "spi0_group";
+ function = "spi0_func";
+ };
+ };
+ pinctrl_spi1_default: spi1-default{
+ mux{
+ groups = "spi1_group";
+ function = "spi1_func";
+ };
+ };
+ pinctrl_spi3_default: spi3-default{
+ mux {
+ groups = "spi3_group";
+ function = "spi3_func";
+ };
+ };
+ pinctrl_por_time_sel0_default: por_time_sel0-default{
+ mux {
+ groups = "por_time_sel0_group";
+ function = "por_time_sel0_func";
+ };
+ };
+ pinctrl_por_time_sel1_default: por_time_sel1-default{
+ mux {
+ groups = "por_time_sel1_group";
+ function = "por_time_sel1_func";
+ };
+ };
+ pinctrl_i2s0_default: i2s0-default{
+ mux {
+ groups = "i2s0_group";
+ function = "i2s0_func";
+ };
+ };
+ pinctrl_i2s1_default: i2s1-default{
+ mux {
+ groups = "i2s1_group";
+ function = "i2s1_func";
+ };
+ };
+ pinctrl_i2s2_default: i2s2-default{
+ mux {
+ groups = "i2s2_group";
+ function = "i2s2_func";
+ };
+ };
+ pinctrl_usb0_pwren_default: usb0_pwren-default{
+ mux {
+ groups = "usb0_pwren_group";
+ function = "usb0_pwren_func";
+ };
+ };
+ pinctrl_usb1_pwren_default: usb1_pwren-default{
+ mux {
+ groups = "usb1_pwren_group";
+ function = "usb1_pwren_func";
+ };
+ };
+ pinctrl_i2c0_default: i2c0-default{
+ mux {
+ groups = "i2c0_group";
+ function = "i2c0_func";
+ };
+ };
+ pinctrl_i2c1_default: i2c1-default{
+ mux {
+ groups = "i2c1_group";
+ function = "i2c1_func";
+ };
+ };
+ pinctrl_i2c2_default: i2c2-default{
+ mux {
+ groups = "i2c2_group";
+ function = "i2c2_func";
+ };
+ };
+ pinctrl_i2c3_default: i2c3-default{
+ mux {
+ groups = "i2c3_group";
+ function = "i2c3_func";
+ };
+ };
+ pinctrl_i2c4_default: i2c4-default{
+ mux {
+ groups = "i2c4_group";
+ function = "i2c4_func";
+ };
+ };
+ pinctrl_i2c5_default: i2c5-default{
+ mux {
+ groups = "i2c5_group";
+ function = "i2c5_func";
+ };
+ };
+ pinctrl_i2c8_default: i2c8-default{
+ mux {
+ groups = "i2c8_group";
+ function = "i2c8_func";
+ };
+ };
+ pinctrl_i2c10_default: i2c10-default{
+ mux {
+ groups = "i2c10_group";
+ function = "i2c10_func";
+ };
+ };
+ pinctrl_i2c11_default: i2c11-default{
+ mux {
+ groups = "i2c11_group";
+ function = "i2c11_func";
+ };
+ };
+ pinctrl_uart0_default: uart0-default{
+ mux {
+ groups = "uart0_group";
+ function = "uart0_func";
+ };
+ };
+ pinctrl_uart1_default: uart1-default{
+ mux {
+ groups = "uart1_group";
+ function = "uart1_func";
+ };
+ };
+ pinctrl_uart2_default: uart2-default{
+ mux {
+ groups = "uart2_group";
+ function = "uart2_func";
+ };
+ };
+ //pwm0: fan_pwm
+ pinctrl_pwm0_default: pwm0-default{
+ mux {
+ groups = "pwm0_group";
+ function = "pwm0_func";
+ };
+ };
+ pinctrl_fan_tach_default: fan_tach-default{
+ mux {
+ groups = "fan_tach_group";
+ function = "fan_tach_func";
+ };
+ };
+ pinctrl_mipi_csi0_default: mipi_csi0-default{
+ mux {
+ groups = "mipi_csi0_group";
+ function = "mipi_csi0_func";
+ };
+ };
+ pinctrl_mipi_csi1_default: mipi_csi1-default{
+ mux {
+ groups = "mipi_csi1_group";
+ function = "mipi_csi1_func";
+ };
+ };
+ pinctrl_mipi_csi2_default: mipi_csi2-default{
+ mux {
+ groups = "mipi_csi2_group";
+ function = "mipi_csi2_func";
+ };
+ };
+ pinctrl_mipi_csi3_default: mipi_csi3-default{
+ mux {
+ groups = "mipi_csi3_group";
+ function = "mipi_csi3_func";
+ };
+ };
+ pinctrl_mipi_csi4_default: mipi_csi4-default{
+ mux {
+ groups = "mipi_csi4_group";
+ function = "mipi_csi4_func";
+ };
+ };
+ pinctrl_mipi_csi5_default: mipi_csi5-default{
+ mux {
+ groups = "mipi_csi5_group";
+ function = "mipi_csi5_func";
+ };
+ };
+ pinctrl_s_mode_default: s_mode-default{
+ mux {
+ groups = "s_mode_group";
+ function = "s_mode_func";
+ };
+ };
+ pinctrl_pinmux_ddr_refclk_sel_default: pinmux_ddr_refclk_sel-default{
+ mux {
+ groups = "pinmux_ddr_refclk_sel_group";
+ function = "pinmux_ddr_refclk_sel_func";
+ };
+ };
+ pinctrl_boot_sel_default: boot_sel-default{
+ mux {
+ groups = "boot_sel_group";
+ function = "boot_sel_func";
+ };
+ };
+ pinctrl_lpddr_ref_clk_default: lpddr_ref_clk-default{
+ mux {
+ groups = "lpddr_ref_clk_group";
+ function = "lpddr_ref_clk_func";
+ };
+ };
+
+ //func1
+ pinctrl_spi2_default: spi2-default{
+ mux1 {
+ groups = "spi2_clk_group";
+ function = "spi2_clk_func";
+ };
+ conf1 {
+ groups = "spi2_clk_group";
+ input-enable = <1>;
+ bias-pull-up = <1>;
+ bias-pull-down = <0>;
+ };
+ mux2 {
+ groups = "spi2_d0_group";
+ function = "spi2_d0_func";
+ };
+ conf2 {
+ groups = "spi2_d0_group";
+ input-enable = <1>;
+ bias-pull-up = <1>;
+ bias-pull-down = <0>;
+ };
+ mux3 {
+ groups = "spi2_d1_d2_d3_group";
+ function = "spi2_d1_d2_d3_func";
+ };
+ conf3 {
+ groups = "spi2_d1_d2_d3_group";
+ input-enable = <1>;
+ bias-pull-up = <1>;
+ bias-pull-down = <0>;
+ };
+ mux4 {
+ groups = "spi2_cs_group";
+ function = "spi2_cs_func";
+ };
+ };
+
+ pinctrl_sata_act_led_default: sata_act_led-default{
+ mux {
+ groups = "sata_act_led_group";
+ function = "sata_act_led_func";
+ };
+ conf {
+ groups = "sata_act_led_group";
+ input-enable = <0>;
+ bias-pull-down = <1>;
+ };
+ };
+ pinctrl_emmc_led_control_default: emmc_led_control-default{
+ mux {
+ groups = "emmc_led_control_group";
+ function = "emmc_led_control_func";
+ };
+ };
+ pinctrl_sd0_led_control_default: sd0_led_control-default{
+ mux {
+ groups = "sd0_led_control_group";
+ function = "sd0_led_control_func";
+ };
+ };
+ pinctrl_sd1_led_control_default: sd1_led_control-default{
+ mux {
+ groups = "sd1_led_control_group";
+ function = "sd1_led_control_func";
+ };
+ };
+ pinctrl_i2c6_default: i2c6-default{
+ mux {
+ groups = "i2c6_group";
+ function = "i2c6_func";
+ };
+ };
+ pinctrl_i2c7_default: i2c7-default{
+ mux {
+ groups = "i2c7_group";
+ function = "i2c7_func";
+ };
+ };
+ pinctrl_i2c9_default: i2c9-default{
+ mux {
+ groups = "i2c9_group";
+ function = "i2c9_func";
+ };
+ };
+ pinctrl_pwm1_default: pwm1-default{
+ mux {
+ groups = "pwm1_group";
+ function = "pwm1_func";
+ };
+ };
+ pinctrl_pwm2_default: pwm2-default{
+ mux {
+ groups = "pwm2_group";
+ function = "pwm2_func";
+ };
+ };
+ pinctrl_mipi_csi_xtrig_default: mipi_csi_xtrig-default{
+ mux {
+ groups = "mipi_csi_xtrig_group";
+ function = "mipi_csi_xtrig_func";
+ };
+ };
+
+ //func3
+ pinctrl_uart3_default: uart3-default{
+ mux {
+ groups = "uart3_group";
+ function = "uart3_func";
+ };
+ };
+ pinctrl_uart4_default: uart4-default{
+ mux {
+ groups = "uart4_group";
+ function = "uart4_func";
+ };
+ };
+
+ //gpio
+ pinctrl_gpio0_default: gpio0-default{
+ mux {
+ groups = "gpio0_group";
+ function = "gpio0_func";
+ };
+ conf {
+ groups = "gpio0_group";
+ input-enable = <1>;
+ bias-pull-up = <1>;
+ };
+ };
+ pinctrl_gpio1_default: gpio1-default{
+ mux {
+ groups = "gpio1_group";
+ function = "gpio1_func";
+ };
+ };
+ pinctrl_gpio2_default: gpio2-default{
+ mux {
+ groups = "gpio2_group";
+ function = "gpio2_func";
+ };
+ };
+ pinctrl_gpio3_default: gpio3-default{
+ mux {
+ groups = "gpio3_group";
+ function = "gpio3_func";
+ };
+ };
+ pinctrl_gpio4_default: gpio4-default{
+ mux {
+ groups = "gpio4_group";
+ function = "gpio4_func";
+ };
+ };
+ pinctrl_gpio5_default: gpio5-default{
+ mux {
+ groups = "gpio5_group";
+ function = "gpio5_func";
+ };
+ };
+ pinctrl_gpio6_default: gpio6-default{
+ mux {
+ groups = "gpio6_group";
+ function = "gpio6_func";
+ };
+ };
+ pinctrl_gpio7_default: gpio7-default{
+ mux {
+ groups = "gpio7_group";
+ function = "gpio7_func";
+ };
+ conf {
+ groups = "gpio7_group";
+ input-enable = <0>;
+ bias-pull-down = <1>;
+ };
+ };
+ pinctrl_gpio8_default: gpio8-default{
+ mux {
+ groups = "gpio8_group";
+ function = "gpio8_func";
+ };
+ conf {
+ groups = "gpio8_group";
+ input-enable = <1>;
+ bias-pull-up = <1>;
+ };
+ };
+ pinctrl_gpio9_default: gpio9-default{
+ mux {
+ groups = "gpio9_group";
+ function = "gpio9_func";
+ };
+ conf {
+ groups = "gpio9_group";
+ input-enable = <1>;
+ bias-pull-up = <1>;
+ };
+ };
+ pinctrl_gpio10_default: gpio10-default{
+ mux {
+ groups = "gpio10_group";
+ function = "gpio10_func";
+ };
+ conf {
+ groups = "gpio10_group";
+ input-enable = <1>;
+ bias-pull-up = <1>;
+ };
+ };
+ pinctrl_gpio11_default: gpio11-default{
+ mux {
+ groups = "gpio11_group";
+ function = "gpio11_func";
+ };
+ conf {
+ groups = "gpio11_group";
+ input-enable = <1>;
+ bias-pull-up = <1>;
+ };
+ };
+ pinctrl_gpio12_default: gpio12-default{
+ mux {
+ groups = "gpio12_group";
+ function = "gpio12_func";
+ };
+ };
+ pinctrl_gpio13_default: gpio13-default{
+ mux {
+ groups = "gpio13_group";
+ function = "gpio13_func";
+ };
+ };
+ pinctrl_gpio14_default: gpio14-default{
+ mux {
+ groups = "gpio14_group";
+ function = "gpio14_func";
+ };
+ };
+ pinctrl_gpio15_default: gpio15-default{
+ mux {
+ groups = "gpio15_group";
+ function = "gpio15_func";
+ };
+ };
+ pinctrl_gpio16_default: gpio16-default{
+ mux {
+ groups = "gpio16_group";
+ function = "gpio16_func";
+ };
+ conf {
+ groups = "gpio16_group";
+ input-enable = <0>;
+ bias-pull-down = <1>;
+ };
+ };
+ pinctrl_gpio17_default: gpio17-default{
+ mux {
+ groups = "gpio17_group";
+ function = "gpio17_func";
+ };
+ };
+ pinctrl_gpio18_default: gpio18-default{
+ mux {
+ groups = "gpio18_group";
+ function = "gpio18_func";
+ };
+ };
+ pinctrl_gpio19_default: gpio19-default{
+ mux {
+ groups = "gpio19_group";
+ function = "gpio19_func";
+ };
+ };
+ pinctrl_gpio20_default: gpio20-default{
+ mux {
+ groups = "gpio20_group";
+ function = "gpio20_func";
+ };
+ };
+ pinctrl_gpio21_default: gpio21-default{
+ mux {
+ groups = "gpio21_group";
+ function = "gpio21_func";
+ };
+ };
+ pinctrl_gpio22_default: gpio22-default{
+ mux {
+ groups = "gpio22_group";
+ function = "gpio22_func";
+ };
+ };
+ pinctrl_gpio23_default: gpio23-default{
+ mux {
+ groups = "gpio23_group";
+ function = "gpio23_func";
+ };
+ };
+ pinctrl_gpio24_default: gpio24-default{
+ mux {
+ groups = "gpio24_group";
+ function = "gpio24_func";
+ };
+ };
+ pinctrl_gpio25_default: gpio25-default{
+ mux {
+ groups = "gpio25_group";
+ function = "gpio25_func";
+ };
+ };
+ pinctrl_gpio26_default: gpio26-default{
+ mux {
+ groups = "gpio26_group";
+ function = "gpio26_func";
+ };
+ };
+ pinctrl_gpio27_default: gpio27-default{
+ mux {
+ groups = "gpio27_group";
+ function = "gpio27_func";
+ };
+ };
+ pinctrl_gpio28_default: gpio28-default{
+ mux {
+ groups = "gpio28_group";
+ function = "gpio28_func";
+ };
+ conf {
+ groups = "gpio28_group";
+ input-enable = <1>;
+ bias-pull-up = <1>;
+ };
+ };
+ pinctrl_gpio29_default: gpio29-default{
+ mux {
+ groups = "gpio29_group";
+ function = "gpio29_func";
+ };
+ };
+ pinctrl_gpio30_default: gpio30-default{
+ mux {
+ groups = "gpio30_group";
+ function = "gpio30_func";
+ };
+ };
+ pinctrl_gpio31_default: gpio31-default{
+ mux {
+ groups = "gpio31_group";
+ function = "gpio31_func";
+ };
+ };
+ pinctrl_gpio32_default: gpio32-default{
+ mux {
+ groups = "gpio32_group";
+ function = "gpio32_func";
+ };
+ };
+ pinctrl_gpio33_default: gpio33-default{
+ mux {
+ groups = "gpio33_group";
+ function = "gpio33_func";
+ };
+ };
+ pinctrl_gpio34_default: gpio34-default{
+ mux {
+ groups = "gpio34_group";
+ function = "gpio34_func";
+ };
+ };
+ pinctrl_gpio35_default: gpio35-default{
+ mux {
+ groups = "gpio35_group";
+ function = "gpio35_func";
+ };
+ };
+ pinctrl_gpio36_default: gpio36-default{
+ mux {
+ groups = "gpio36_group";
+ function = "gpio36_func";
+ };
+ };
+ pinctrl_gpio37_default: gpio37-default{
+ mux {
+ groups = "gpio37_group";
+ function = "gpio37_func";
+ };
+ };
+ pinctrl_gpio38_default: gpio38-default{
+ mux {
+ groups = "gpio38_group";
+ function = "gpio38_func";
+ };
+ };
+ pinctrl_gpio39_default: gpio39-default{
+ mux {
+ groups = "gpio39_group";
+ function = "gpio39_func";
+ };
+ };
+ pinctrl_gpio40_default: gpio40-default{
+ mux {
+ groups = "gpio40_group";
+ function = "gpio40_func";
+ };
+ };
+ pinctrl_gpio41_default: gpio41-default{
+ mux {
+ groups = "gpio41_group";
+ function = "gpio41_func";
+ };
+ };
+ pinctrl_gpio42_default: gpio42-default{
+ mux {
+ groups = "gpio42_group";
+ function = "gpio42_func";
+ };
+ };
+ pinctrl_gpio43_default: gpio43-default{
+ mux {
+ groups = "gpio43_group";
+ function = "gpio43_func";
+ };
+ };
+ pinctrl_gpio44_default: gpio44-default{
+ mux {
+ groups = "gpio44_group";
+ function = "gpio44_func";
+ };
+ };
+ pinctrl_gpio45_default: gpio45-default{
+ mux {
+ groups = "gpio45_group";
+ function = "gpio45_func";
+ };
+ };
+ pinctrl_gpio46_default: gpio46-default{
+ mux {
+ groups = "gpio46_group";
+ function = "gpio46_func";
+ };
+ };
+ pinctrl_gpio47_default: gpio47-default{
+ mux {
+ groups = "gpio47_group";
+ function = "gpio47_func";
+ };
+ };
+ pinctrl_gpio48_default: gpio48-default{
+ mux {
+ groups = "gpio48_group";
+ function = "gpio48_func";
+ };
+ };
+ pinctrl_gpio49_default: gpio49-default{
+ mux {
+ groups = "gpio49_group";
+ function = "gpio49_func";
+ };
+ };
+ pinctrl_gpio50_default: gpio50-default{
+ mux {
+ groups = "gpio50_group";
+ function = "gpio50_func";
+ };
+ };
+ pinctrl_gpio51_default: gpio51-default{
+ mux {
+ groups = "gpio51_group";
+ function = "gpio51_func";
+ };
+ };
+ pinctrl_gpio52_default: gpio52-default{
+ mux {
+ groups = "gpio52_group";
+ function = "gpio52_func";
+ };
+ };
+ pinctrl_gpio53_default: gpio53-default{
+ mux {
+ groups = "gpio53_group";
+ function = "gpio53_func";
+ };
+ };
+ pinctrl_gpio54_default: gpio54-default{
+ mux {
+ groups = "gpio54_group";
+ function = "gpio54_func";
+ };
+ };
+ pinctrl_gpio55_default: gpio55-default{
+ mux {
+ groups = "gpio55_group";
+ function = "gpio55_func";
+ };
+ };
+ pinctrl_gpio56_default: gpio56-default{
+ mux {
+ groups = "gpio56_group";
+ function = "gpio56_func";
+ };
+ };
+ pinctrl_gpio57_default: gpio57-default{
+ mux {
+ groups = "gpio57_group";
+ function = "gpio57_func";
+ };
+ };
+ pinctrl_gpio58_default: gpio58-default{
+ mux {
+ groups = "gpio58_group";
+ function = "gpio58_func";
+ };
+ };
+ pinctrl_gpio59_default: gpio59-default{
+ mux {
+ groups = "gpio59_group";
+ function = "gpio59_func";
+ };
+ };
+ pinctrl_gpio60_default: gpio60-default{
+ mux {
+ groups = "gpio60_group";
+ function = "gpio60_func";
+ };
+ };
+ pinctrl_gpio61_default: gpio61-default{
+ mux {
+ groups = "gpio61_group";
+ function = "gpio61_func";
+ };
+ };
+ pinctrl_gpio62_default: gpio62-default{
+ mux {
+ groups = "gpio62_group";
+ function = "gpio62_func";
+ };
+ };
+ pinctrl_gpio63_default: gpio63-default{
+ mux {
+ groups = "gpio63_group";
+ function = "gpio63_func";
+ };
+ };
+ pinctrl_gpio64_default: gpio64-default{
+ mux {
+ groups = "gpio64_group";
+ function = "gpio64_func";
+ };
+ };
+ pinctrl_gpio65_default: gpio65-default{
+ mux {
+ groups = "gpio65_group";
+ function = "gpio65_func";
+ };
+ };
+ pinctrl_gpio66_default: gpio66-default{
+ mux {
+ groups = "gpio66_group";
+ function = "gpio66_func";
+ };
+ };
+ pinctrl_gpio67_default: gpio67-default{
+ mux {
+ groups = "gpio67_group";
+ function = "gpio67_func";
+ };
+ };
+ pinctrl_gpio68_default: gpio68-default{
+ mux {
+ groups = "gpio68_group";
+ function = "gpio68_func";
+ };
+ };
+ pinctrl_gpio69_default: gpio69-default{
+ mux {
+ groups = "gpio69_group";
+ function = "gpio69_func";
+ };
+ };
+ pinctrl_gpio70_default: gpio70-default{
+ mux {
+ groups = "gpio70_group";
+ function = "gpio70_func";
+ };
+ };
+ pinctrl_gpio71_default: gpio71-default{
+ mux {
+ groups = "gpio71_group";
+ function = "gpio71_func";
+ };
+ };
+ pinctrl_gpio72_default: gpio72-default{
+ mux {
+ groups = "gpio72_group";
+ function = "gpio72_func";
+ };
+ };
+ pinctrl_gpio73_default: gpio73-default{
+ mux {
+ groups = "gpio73_group";
+ function = "gpio73_func";
+ };
+ };
+ pinctrl_gpio74_default: gpio74-default{
+ mux {
+ groups = "gpio74_group";
+ function = "gpio74_func";
+ };
+ };
+ pinctrl_gpio75_default: gpio75-default{
+ mux {
+ groups = "gpio75_group";
+ function = "gpio75_func";
+ };
+ };
+ pinctrl_gpio76_default: gpio76-default{
+ mux {
+ groups = "gpio76_group";
+ function = "gpio76_func";
+ };
+ };
+ pinctrl_gpio77_default: gpio77-default{
+ mux {
+ groups = "gpio77_group";
+ function = "gpio77_func";
+ };
+ };
+ pinctrl_gpio78_default: gpio78-default{
+ mux {
+ groups = "gpio78_group";
+ function = "gpio78_func";
+ };
+ };
+ pinctrl_gpio79_default: gpio79-default{
+ mux {
+ groups = "gpio79_group";
+ function = "gpio79_func";
+ };
+ };
+ pinctrl_gpio80_default: gpio80-default{
+ mux {
+ groups = "gpio80_group";
+ function = "gpio80_func";
+ };
+ };
+ pinctrl_gpio81_default: gpio81-default{
+ mux {
+ groups = "gpio81_group";
+ function = "gpio81_func";
+ };
+ };
+ pinctrl_gpio82_default: gpio82-default{
+ mux {
+ groups = "gpio82_group";
+ function = "gpio82_func";
+ };
+ };
+ pinctrl_gpio83_default: gpio83-default{
+ mux {
+ groups = "gpio83_group";
+ function = "gpio83_func";
+ };
+ };
+ pinctrl_gpio84_default: gpio84-default{
+ mux {
+ groups = "gpio84_group";
+ function = "gpio84_func";
+ };
+ };
+ pinctrl_gpio85_default: gpio85-default{
+ mux {
+ groups = "gpio85_group";
+ function = "gpio85_func";
+ };
+ };
+ pinctrl_gpio86_default: gpio86-default{
+ mux {
+ groups = "gpio86_group";
+ function = "gpio86_func";
+ };
+ };
+ pinctrl_gpio87_default: gpio87-default{
+ mux {
+ groups = "gpio87_group";
+ function = "gpio87_func";
+ };
+ };
+ pinctrl_gpio88_default: gpio88-default{
+ mux {
+ groups = "gpio88_group";
+ function = "gpio88_func";
+ };
+ };
+ pinctrl_gpio89_default: gpio89-default{
+ mux {
+ groups = "gpio89_group";
+ function = "gpio89_func";
+ };
+ };
+ pinctrl_gpio90_default: gpio90-default{
+ mux {
+ groups = "gpio90_group";
+ function = "gpio90_func";
+ };
+ };
+ pinctrl_gpio91_default: gpio91-default{
+ mux {
+ groups = "gpio91_group";
+ function = "gpio91_func";
+ };
+ };
+ pinctrl_gpio92_default: gpio92-default{
+ mux {
+ groups = "gpio92_group";
+ function = "gpio92_func";
+ };
+ };
+ pinctrl_gpio93_default: gpio93-default{
+ mux {
+ groups = "gpio93_group";
+ function = "gpio93_func";
+ };
+ };
+ pinctrl_gpio94_default: gpio94-default{
+ mux {
+ groups = "gpio94_group";
+ function = "gpio94_func";
+ };
+ conf {
+ groups = "gpio94_group";
+ input-enable = <0>;
+ bias-pull-down = <1>;
+ };
+ };
+ pinctrl_gpio95_default: gpio95-default{
+ mux {
+ groups = "gpio95_group";
+ function = "gpio95_func";
+ };
+ };
+ pinctrl_gpio96_default: gpio96-default{
+ mux {
+ groups = "gpio96_group";
+ function = "gpio96_func";
+ };
+ };
+ pinctrl_gpio97_default: gpio97-default{
+ mux {
+ groups = "gpio97_group";
+ function = "gpio97_func";
+ };
+ };
+ pinctrl_gpio98_default: gpio98-default{
+ mux {
+ groups = "gpio98_group";
+ function = "gpio98_func";
+ };
+ };
+ pinctrl_gpio99_default: gpio99-default{
+ mux {
+ groups = "gpio99_group";
+ function = "gpio99_func";
+ };
+ };
+ pinctrl_gpio100_default: gpio100-default{
+ mux {
+ groups = "gpio100_group";
+ function = "gpio100_func";
+ };
+ };
+ pinctrl_gpio101_default: gpio101-default{
+ mux {
+ groups = "gpio101_group";
+ function = "gpio101_func";
+ };
+ };
+ pinctrl_gpio102_default: gpio102-default{
+ mux {
+ groups = "gpio102_group";
+ function = "gpio102_func";
+ };
+ };
+ pinctrl_gpio103_default: gpio103-default{
+ mux {
+ groups = "gpio103_group";
+ function = "gpio103_func";
+ };
+ };
+ pinctrl_gpio104_default: gpio104-default{
+ mux {
+ groups = "gpio104_group";
+ function = "gpio104_func";
+ };
+ };
+ pinctrl_gpio105_default: gpio105-default{
+ mux {
+ groups = "gpio105_group";
+ function = "gpio105_func";
+ };
+ };
+ pinctrl_gpio106_default: gpio106-default{
+ mux {
+ groups = "gpio106_group";
+ function = "gpio106_func";
+ };
+ conf {
+ groups = "gpio106_group";
+ input-enable = <0>;
+ bias-pull-down = <1>;
+ };
+ };
+ pinctrl_gpio107_default: gpio107-default{
+ mux {
+ groups = "gpio107_group";
+ function = "gpio107_func";
+ };
+ conf {
+ groups = "gpio107_group";
+ input-enable = <0>;
+ bias-pull-down = <1>;
+ };
+ };
+ pinctrl_gpio108_default: gpio108-default{
+ mux {
+ groups = "gpio108_group";
+ function = "gpio108_func";
+ };
+ conf {
+ groups = "gpio108_group";
+ input-enable = <0>;
+ bias-pull-down = <1>;
+ };
+ };
+ pinctrl_gpio109_default: gpio109-default{
+ mux {
+ groups = "gpio109_group";
+ function = "gpio109_func";
+ };
+ conf {
+ groups = "gpio109_group";
+ input-enable = <0>;
+ bias-pull-down = <1>;
+ };
+ };
+ pinctrl_gpio110_default: gpio110-default{
+ mux {
+ groups = "gpio110_group";
+ function = "gpio110_func";
+ };
+ conf {
+ groups = "gpio110_group";
+ input-enable = <0>;
+ bias-pull-down = <1>;
+ };
+ };
+ pinctrl_gpio111_default: gpio111-default{
+ mux {
+ groups = "gpio111_group";
+ function = "gpio111_func";
+ };
+ conf {
+ groups = "gpio111_group";
+ input-enable = <0>;
+ bias-pull-up = <1>;
+ };
+ };
+
+ //func6
+ pinctrl_csi_mon_out_default: csi_mon_out-default{
+ mux {
+ groups = "csi_mon_out_group";
+ function = "csi_mon_out_func";
+ };
+ };
+ pinctrl_csi_ocla_clk_default: csi_ocla_clk-default{
+ mux {
+ groups = "csi_ocla_clk_group";
+ function = "csi_ocla_clk_func";
+ };
+ };
+ pinctrl_csi_mon_out_valid_default: csi_mon_out_valid-default{
+ mux {
+ groups = "csi_mon_out_valid_group";
+ function = "csi_mon_out_valid_func";
+ };
+ };
+ pinctrl_csi_parity_error_default: csi_parity_error-default{
+ mux {
+ groups = "csi_parity_error_group";
+ function = "csi_parity_error_func";
+ };
+ };
+ pinctrl_csi_dtb_out_default: csi_dtb_out-default{
+ mux {
+ groups = "csi_dtb_out_group";
+ function = "csi_dtb_out_func";
+ };
+ };
+ pinctrl_csi_phy_sel_default: csi_phy_sel-default{
+ mux {
+ groups = "csi_phy_sel_group";
+ function = "csi_phy_sel_func";
+ };
+ };
+ pinctrl_vc_g2d0_debug_out_default: vc_g2d0_debug_out-default{
+ mux {
+ groups = "vc_g2d0_debug_out_group";
+ function = "vc_g2d0_debug_out_func";
+ };
+ };
+ pinctrl_vc_g2d1_debug_out_default: vc_g2d1_debug_out-default{
+ mux {
+ groups = "vc_g2d1_debug_out_group";
+ function = "vc_g2d1_debug_out_func";
+ };
+ };
+ pinctrl_sata_mpll_clk_default: sata_mpll_clk-default{
+ mux {
+ groups = "sata_mpll_clk_group";
+ function = "sata_mpll_clk_func";
+ };
+ };
+ pinctrl_sata_ref_repeat_clk_m_default: sata_ref_repeat_clk_m-default{
+ mux {
+ groups = "sata_ref_repeat_clk_m_group";
+ function = "sata_ref_repeat_clk_m_func";
+ };
+ };
+ pinctrl_sata_ref_repeat_clk_p_default: sata_ref_repeat_clk_p-default{
+ mux {
+ groups = "sata_ref_repeat_clk_p_group";
+ function = "sata_ref_repeat_clk_p_func";
+ };
+ };
+ };
+ };
+};
\ No newline at end of file
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-arch-d2d.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-arch-d2d.dtsi
new file mode 100644
index 000000000000..08b35addb5b7
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-arch-d2d.dtsi
@@ -0,0 +1,869 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Include file for Eswin EIC7702 SoC's cpu.
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#include <dt-bindings/clock/win2030-clock.h>
+#include "eswin-win2030-platform.dtsi"
+
+#define UART0_INT 100
+#define UART1_INT 101
+#define UART2_INT 102
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "SiFive,FU800-dev", "fu800-dev", "sifive-dev", "eic770x-dev";
+
+ L64: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <RTCCLK_FREQ>;
+
+ cpu-map {
+ #if (CHIPLET_AND_DIE & 0x2)
+ cluster0 {
+ core0 {
+ cpu = <&cpu_0>;
+ };
+ core1 {
+ cpu = <&cpu_1>;
+ };
+ core2 {
+ cpu = <&cpu_2>;
+ };
+ core3 {
+ cpu = <&cpu_3>;
+ };
+ };
+ #endif
+ cluster1 {
+ core0 {
+ cpu = <&cpu_4>;
+ };
+ #ifndef PLATFORM_HAPS
+ core1 {
+ cpu = <&cpu_5>;
+ };
+ core2 {
+ cpu = <&cpu_6>;
+ };
+ core3 {
+ cpu = <&cpu_7>;
+ };
+ #endif
+ };
+
+ };
+
+ #if (CHIPLET_AND_DIE & 0x2)
+ cpu_0: cpu@0 {
+ clock-frequency = <0>;
+ compatible = "eswin,eic770x", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <4>;
+ hwpf-distanceBits = <6>;
+ hwpf-hitCacheThrdBits = <5>;
+ hwpf-hitMSHRThrdBits = <4>;
+ hwpf-l2pfPoolSize = <10>;
+ hwpf-nIssQEnt = <6>;
+ hwpf-nPrefetchQueueEntries = <8>;
+ hwpf-nStreams = <16>;
+ hwpf-qFullnessThrdBits = <4>;
+ hwpf-windowBits = <6>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <&L15>;
+ reg = <0x0>;
+ riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
+ riscv,pmpgranularity = <4096>;
+ riscv,pmpregions = <8>;
+ sifive,buserror = <&L16>;
+ status = "okay";
+ timebase-frequency = <RTCCLK_FREQ>;
+ tlb-split;
+ numa-node-id = <0>;
+ clocks = <&d0_clock WIN2030_CLK_CPU_EXT_SRC_CORE_CLK_0>;
+ operating-points-v2 = <&d0_cpu_opp_table>;
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ L13: pmu {
+ compatible = "riscv,pmu0", "riscv,pmu";
+ interrupts-extended = <&cpu0_intc 13>;
+ };
+ };
+ cpu_1: cpu@1 {
+ clock-frequency = <0>;
+ compatible = "eswin,eic770x", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <4>;
+ hwpf-distanceBits = <6>;
+ hwpf-hitCacheThrdBits = <5>;
+ hwpf-hitMSHRThrdBits = <4>;
+ hwpf-l2pfPoolSize = <10>;
+ hwpf-nIssQEnt = <6>;
+ hwpf-nPrefetchQueueEntries = <8>;
+ hwpf-nStreams = <16>;
+ hwpf-qFullnessThrdBits = <4>;
+ hwpf-windowBits = <6>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <&L20>;
+ reg = <0x1>;
+ riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
+ riscv,pmpgranularity = <4096>;
+ riscv,pmpregions = <8>;
+ sifive,buserror = <&L21>;
+ status = "okay";
+ timebase-frequency = <RTCCLK_FREQ>;
+ tlb-split;
+ numa-node-id = <0>;
+ clocks = <&d0_clock WIN2030_CLK_CPU_EXT_SRC_CORE_CLK_1>;
+ operating-points-v2 = <&d0_cpu_opp_table>;
+ cpu1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ L18: pmu {
+ compatible = "riscv,pmu0", "riscv,pmu";
+ interrupts-extended = <&cpu1_intc 13>;
+ };
+ };
+ cpu_2: cpu@2 {
+ clock-frequency = <0>;
+ compatible = "eswin,eic770x", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <4>;
+ hwpf-distanceBits = <6>;
+ hwpf-hitCacheThrdBits = <5>;
+ hwpf-hitMSHRThrdBits = <4>;
+ hwpf-l2pfPoolSize = <10>;
+ hwpf-nIssQEnt = <6>;
+ hwpf-nPrefetchQueueEntries = <8>;
+ hwpf-nStreams = <16>;
+ hwpf-qFullnessThrdBits = <4>;
+ hwpf-windowBits = <6>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <&L25>;
+ reg = <0x2>;
+ riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
+ riscv,pmpgranularity = <4096>;
+ riscv,pmpregions = <8>;
+ sifive,buserror = <&L26>;
+ status = "okay";
+ timebase-frequency = <RTCCLK_FREQ>;
+ tlb-split;
+ numa-node-id = <0>;
+ clocks = <&d0_clock WIN2030_CLK_CPU_EXT_SRC_CORE_CLK_2>;
+ operating-points-v2 = <&d0_cpu_opp_table>;
+ cpu2_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ L23: pmu {
+ compatible = "riscv,pmu0", "riscv,pmu";
+ interrupts-extended = <&cpu2_intc 13>;
+ };
+ };
+ cpu_3: cpu@3 {
+ clock-frequency = <0>;
+ compatible = "eswin,eic770x", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <4>;
+ hwpf-distanceBits = <6>;
+ hwpf-hitCacheThrdBits = <5>;
+ hwpf-hitMSHRThrdBits = <4>;
+ hwpf-l2pfPoolSize = <10>;
+ hwpf-nIssQEnt = <6>;
+ hwpf-nPrefetchQueueEntries = <8>;
+ hwpf-nStreams = <16>;
+ hwpf-qFullnessThrdBits = <4>;
+ hwpf-windowBits = <6>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <&L30>;
+ reg = <0x3>;
+ riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
+ riscv,pmpgranularity = <4096>;
+ riscv,pmpregions = <8>;
+ sifive,buserror = <&L31>;
+ status = "okay";
+ timebase-frequency = <RTCCLK_FREQ>;
+ tlb-split;
+ numa-node-id = <0>;
+ clocks = <&d0_clock WIN2030_CLK_CPU_EXT_SRC_CORE_CLK_3>;
+ operating-points-v2 = <&d0_cpu_opp_table>;
+ cpu3_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ L28: pmu {
+ compatible = "riscv,pmu0", "riscv,pmu";
+ interrupts-extended = <&cpu3_intc 13>;
+ };
+ };
+ #endif
+
+ cpu_4: cpu@4 {
+ clock-frequency = <0>;
+ compatible = "eswin,eic770x", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <4>;
+ hwpf-distanceBits = <6>;
+ hwpf-hitCacheThrdBits = <5>;
+ hwpf-hitMSHRThrdBits = <4>;
+ hwpf-l2pfPoolSize = <10>;
+ hwpf-nIssQEnt = <6>;
+ hwpf-nPrefetchQueueEntries = <8>;
+ hwpf-nStreams = <16>;
+ hwpf-qFullnessThrdBits = <4>;
+ hwpf-windowBits = <6>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <&D2L2_0>;
+ #if (CHIPLET_AND_DIE == 1)
+ #ifdef PLATFORM_HAPS
+ reg = <0x1>;
+ #else
+ reg = <0x4>;
+ #endif
+ #else
+ reg = <0x4>;
+ #endif
+ riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
+ riscv,pmpgranularity = <4096>;
+ riscv,pmpregions = <8>;
+ #if (CHIPLET_AND_DIE & 0x2)
+ sifive,buserror = <&L16>;
+ #endif
+ status = "okay";
+ timebase-frequency = <RTCCLK_FREQ>;
+ tlb-split;
+ numa-node-id = <1>;
+ clocks = <&d1_clock WIN2030_CLK_CPU_EXT_SRC_CORE_CLK_0>;
+ operating-points-v2 = <&d1_cpu_opp_table>;
+ cpu4_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+
+ };
+ #ifndef PLATFORM_HAPS
+ cpu_5: cpu@5 {
+ clock-frequency = <0>;
+ compatible = "eswin,eic770x", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <4>;
+ hwpf-distanceBits = <6>;
+ hwpf-hitCacheThrdBits = <5>;
+ hwpf-hitMSHRThrdBits = <4>;
+ hwpf-l2pfPoolSize = <10>;
+ hwpf-nIssQEnt = <6>;
+ hwpf-nPrefetchQueueEntries = <8>;
+ hwpf-nStreams = <16>;
+ hwpf-qFullnessThrdBits = <4>;
+ hwpf-windowBits = <6>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <&D2L2_1>;
+ reg = <0x5>;
+ riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
+ riscv,pmpgranularity = <4096>;
+ riscv,pmpregions = <8>;
+ #if (CHIPLET_AND_DIE & 0x2)
+ sifive,buserror = <&L21>;
+ #endif
+ status = "okay";
+ timebase-frequency = <RTCCLK_FREQ>;
+ tlb-split;
+ numa-node-id = <1>;
+ clocks = <&d1_clock WIN2030_CLK_CPU_EXT_SRC_CORE_CLK_1>;
+ operating-points-v2 = <&d1_cpu_opp_table>;
+ cpu5_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+
+ };
+ cpu_6: cpu@6 {
+ clock-frequency = <0>;
+ compatible = "eswin,eic770x", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <4>;
+ hwpf-distanceBits = <6>;
+ hwpf-hitCacheThrdBits = <5>;
+ hwpf-hitMSHRThrdBits = <4>;
+ hwpf-l2pfPoolSize = <10>;
+ hwpf-nIssQEnt = <6>;
+ hwpf-nPrefetchQueueEntries = <8>;
+ hwpf-nStreams = <16>;
+ hwpf-qFullnessThrdBits = <4>;
+ hwpf-windowBits = <6>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <&D2L2_2>;
+ reg = <0x6>;
+ riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
+ riscv,pmpgranularity = <4096>;
+ riscv,pmpregions = <8>;
+ #if (CHIPLET_AND_DIE & 0x2)
+ sifive,buserror = <&L26>;
+ #endif
+ status = "okay";
+ timebase-frequency = <RTCCLK_FREQ>;
+ tlb-split;
+ numa-node-id = <1>;
+ clocks = <&d1_clock WIN2030_CLK_CPU_EXT_SRC_CORE_CLK_2>;
+ operating-points-v2 = <&d1_cpu_opp_table>;
+ cpu6_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+
+ };
+ cpu_7: cpu@7 {
+ clock-frequency = <0>;
+ compatible = "eswin,eic770x", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <4>;
+ hwpf-distanceBits = <6>;
+ hwpf-hitCacheThrdBits = <5>;
+ hwpf-hitMSHRThrdBits = <4>;
+ hwpf-l2pfPoolSize = <10>;
+ hwpf-nIssQEnt = <6>;
+ hwpf-nPrefetchQueueEntries = <8>;
+ hwpf-nStreams = <16>;
+ hwpf-qFullnessThrdBits = <4>;
+ hwpf-windowBits = <6>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <&D2L2_3>;
+ reg = <0x7>;
+ riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
+ riscv,pmpgranularity = <4096>;
+ riscv,pmpregions = <8>;
+ #if (CHIPLET_AND_DIE & 0x2)
+ sifive,buserror = <&L31>;
+ #endif
+ status = "okay";
+ timebase-frequency = <RTCCLK_FREQ>;
+ tlb-split;
+ numa-node-id = <1>;
+ clocks = <&d1_clock WIN2030_CLK_CPU_EXT_SRC_CORE_CLK_3>;
+ operating-points-v2 = <&d1_cpu_opp_table>;
+ cpu7_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+
+ };
+ #endif
+ };
+ //D1MEM: memory@80000000 {
+ // compatible = "sifive,axi4-mem-port", "sifive,axi4-port", "sifive,mem-port";
+ // device_type = "memory";
+ // reg = <0x0 0x80000000 0xf 0x80000000>;
+ // sifive,port-width-bytes = <32>;
+ //};
+
+ //D2MEM: memory@2000000000 {
+ // compatible = "sifive,axi4-mem-port", "sifive,axi4-port", "sifive,mem-port";
+ // device_type = "memory";
+ // reg = <0x20 0x00000000 0x10 0x00000000>;
+ // sifive,port-width-bytes = <32>;
+ //};
+
+ SOC: soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "SiFive,FU800-soc", "fu800-soc", "sifive-soc", "simple-bus";
+ ranges;
+ L40: authentication-controller {
+ compatible = "sifive,authentication0";
+ sifive,auth-types = "fuse";
+ };
+ L51: axi4-sys-port@40000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "sifive,axi4-sys-port", "sifive,axi4-port", "sifive,sys-port", "simple-external-bus", "simple-bus";
+ ranges = <0x40000000 0x0 0x40000000 0x40000000>;
+ sifive,port-width-bytes = <16>;
+ };
+ L52: axi4-sys-port@8000000000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "sifive,axi4-sys-port", "sifive,axi4-port", "sifive,sys-port", "simple-external-bus", "simple-bus";
+ ranges = <0x80 0x0 0x80 0x0 0x180 0x0>;
+ sifive,port-width-bytes = <16>;
+ };
+ L46: basic-bus-blocker@200000 {
+ compatible = "sifive,basic-bus-blocker1";
+ reg = <0x0 0x200000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L43: basic-bus-blocker@202000 {
+ compatible = "sifive,basic-bus-blocker1";
+ reg = <0x0 0x202000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L48: basic-bus-blocker@204000 {
+ compatible = "sifive,basic-bus-blocker1";
+ reg = <0x0 0x204000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L54: burst-bundler@10010000 {
+ compatible = "sifive,burst-bundler0";
+ reg = <0x0 0x10010000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ #if (CHIPLET_AND_DIE & 0x2)
+ L16: bus-error-unit@1700000 {
+ compatible = "sifive,buserror";
+ interrupt-parent = <&plic0>;
+ interrupts = <517>;
+ reg = <0x0 0x1700000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L21: bus-error-unit@1701000 {
+ compatible = "sifive,buserror";
+ interrupt-parent = <&plic0>;
+ interrupts = <518>;
+ reg = <0x0 0x1701000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L26: bus-error-unit@1702000 {
+ compatible = "sifive,buserror";
+ interrupt-parent = <&plic0>;
+ interrupts = <519>;
+ reg = <0x0 0x1702000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L31: bus-error-unit@1703000 {
+ compatible = "sifive,buserror";
+ interrupt-parent = <&plic0>;
+ interrupts = <520>;
+ reg = <0x0 0x1703000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ #endif
+
+ d1_bus_err0: bus-error-unit@21700000 {
+ compatible = "sifive,buserror";
+ interrupt-parent = <&plic1>;
+ interrupts = <517>;
+ reg = <0x0 0x21700000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ d1_bus_err1: bus-error-unit@21701000 {
+ compatible = "sifive,buserror";
+ interrupt-parent = <&plic1>;
+ interrupts = <518>;
+ reg = <0x0 0x21701000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ d1_bus_err2: bus-error-unit@21702000 {
+ compatible = "sifive,buserror";
+ interrupt-parent = <&plic1>;
+ interrupts = <519>;
+ reg = <0x0 0x21702000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ d1_bus_err3: bus-error-unit@21703000 {
+ compatible = "sifive,buserror";
+ interrupt-parent = <&plic1>;
+ interrupts = <520>;
+ reg = <0x0 0x21703000 0x0 0x1000>;
+ reg-names = "control";
+ };
+
+ #if (CHIPLET_AND_DIE & 0x2)
+ D1CACHE: cache-controller@2010000 {
+ cache-block-size = <64>;
+ cache-level = <3>;
+ cache-sets = <4096>;
+ cache-size = <4194304>;
+ cache-unified;
+ compatible = "sifive,ccache1", "cache", "sifive,fu740-c000-ccache";
+ interrupt-parent = <&plic0>;
+ interrupts = <1>, <3>, <4>, <2>;
+ //next-level-cache = <&L9 &L10 &L11 &D1MEM>;
+ next-level-cache = <&L9 &L10 &L11>;
+ reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x400000>;
+ reg-names = "control", "sideband";
+ sifive,a-mshr-count = <60>;
+ sifive,bank-count = <4>;
+ sifive,ecc-granularity = <8>;
+ sifive,max-master-id = <13>;
+ sifive,perfmon-counters = <6>;
+ numa-node-id = <0>;
+ };
+ #endif
+
+ D2CACHE: cache-controller@22010000 {
+ cache-block-size = <64>;
+ cache-level = <3>;
+ cache-sets = <4096>;
+ cache-size = <4194304>;
+ cache-unified;
+ compatible = "sifive,ccache1", "cache", "sifive,fu740-c000-ccache";
+ interrupt-parent = <&plic1>;
+ interrupts = <1>, <3>, <4>, <2>;
+ //next-level-cache = <&L9 &L10 &L11 &D2MEM>;
+ next-level-cache = <&L9 &L10 &L11>;
+ reg = <0x0 0x22010000 0x0 0x4000 0x0 0x8000000 0x0 0x400000>;
+ reg-names = "control", "sideband";
+ sifive,a-mshr-count = <60>;
+ sifive,bank-count = <4>;
+ sifive,ecc-granularity = <8>;
+ sifive,max-master-id = <13>;
+ sifive,perfmon-counters = <6>;
+ numa-node-id = <1>;
+ };
+
+ /*
+ clint0: clint@2000000 {
+ compatible = "riscv,clint0";
+ interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 &cpu1_intc 3 &cpu1_intc 7 &cpu2_intc 3 &cpu2_intc 7 &cpu3_intc 3 &cpu3_intc 7>;
+ reg = <0x0 0x2000000 0x0 0x10000>;
+ reg-names = "control";
+ };
+
+ clint1: clint@22000000 {
+ compatible = "riscv,clint0";
+ interrupts-extended = <&cpu4_intc 3 &cpu4_intc 7 &cpu5_intc 3 &cpu5_intc 7 &cpu6_intc 3 &cpu6_intc 7 &cpu7_intc 3 &cpu7_intc 7>;
+ reg = <0x0 0x2000000 0x0 0x10000>;
+ reg-names = "control";
+ };
+ */
+
+ L34: debug-controller@0 {
+ compatible = "sifive,debug-100", "riscv,debug-100";
+ debug-attach = "jtag";
+ reg = <0x0 0x0 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L8: error-device@1000 {
+ compatible = "sifive,error0";
+ reg = <0x0 0x1000 0x0 0x3000 0x0 0x5000 0x0 0x13000 0x0 0x19000 0x0 0xe7000 0x0 0x114000 0x0 0xec000 0x0 0x201000 0x0 0x1000 0x0 0x203000 0x0 0x1000 0x0 0x205000 0x0 0x14fb000 0x0 0x1704000 0x0 0x8fc000 0x0 0x2014000 0x0 0x5fec000 0x0 0x8400000 0x0 0x3c00000 0x0 0x10000000 0x0 0x3000 0x0 0x10004000 0x0 0xc000 0x0 0x10011000 0x0 0x1f000 0x0 0x10034000 0x0 0x9fcc000 0x0 0x1a400000 0x0 0x5c00000>;
+ };
+ L9: error-device@10003000 {
+ compatible = "sifive,error0";
+ reg = <0x0 0x10003000 0x0 0x1000>;
+ };
+ /*
+ L49: global-external-interrupts {
+ compatible = "sifive,global-external-interrupts0";
+ interrupt-parent = <&plic0>;
+ interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515>;
+ };
+ */
+ #if (CHIPLET_AND_DIE & 0x2)
+ plic0: interrupt-controller@c000000 {
+ #interrupt-cells = <1>;
+ compatible = "sifive,plic-1.0.0";
+ interrupt-controller;
+ interrupts-extended = <
+ &cpu0_intc 0xffffffff &cpu0_intc 9
+ &cpu1_intc 0xffffffff &cpu1_intc 9
+ &cpu2_intc 0xffffffff &cpu2_intc 9
+ &cpu3_intc 0xffffffff &cpu3_intc 9>;
+ reg = <0x0 0xc000000 0x0 0x4000000>;
+ reg-names = "control";
+ riscv,max-priority = <7>;
+ riscv,ndev = <520>;
+ numa-node-id = <0>;
+ };
+ #endif
+
+ plic1: interrupt-controller@2c000000 {
+ #interrupt-cells = <1>;
+ compatible = "sifive,plic-1.0.0";
+ interrupt-controller;
+ interrupts-extended = <
+ &cpu4_intc 0xffffffff &cpu4_intc 9
+ #ifndef PLATFORM_HAPS
+ &cpu5_intc 0xffffffff &cpu5_intc 9
+ &cpu6_intc 0xffffffff &cpu6_intc 9
+ &cpu7_intc 0xffffffff &cpu7_intc 9
+ #endif
+ >;
+ reg = <0x0 0x2c000000 0x0 0x4000000>;
+ reg-names = "control";
+ riscv,max-priority = <7>;
+ riscv,ndev = <520>;
+ numa-node-id = <1>;
+ };
+
+ #if (CHIPLET_AND_DIE & 0x2)
+ L53: order-obliterator@10030000 {
+ compatible = "sifive,order-obliterator0";
+ interrupt-parent = <&plic0>;
+ interrupts = <516>;
+ reg = <0x0 0x10030000 0x0 0x4000>;
+ reg-names = "control";
+ };
+ L15: pl2@104000 {
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <512>;
+ cache-size = <262144>;
+ cache-unified;
+ compatible = "sifive,pL2Cache0", "cache";
+ next-level-cache = <&D1CACHE>;
+ reg = <0x0 0x104000 0x0 0x4000>;
+ reg-names = "control";
+ sifive,ecc-granularity = <16>;
+ sifive,perfmon-counters = <6>;
+ };
+ L20: pl2@108000 {
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <512>;
+ cache-size = <262144>;
+ cache-unified;
+ compatible = "sifive,pL2Cache0", "cache";
+ next-level-cache = <&D1CACHE>;
+ reg = <0x0 0x108000 0x0 0x4000>;
+ reg-names = "control";
+ sifive,ecc-granularity = <16>;
+ sifive,perfmon-counters = <6>;
+ };
+ L25: pl2@10c000 {
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <512>;
+ cache-size = <262144>;
+ cache-unified;
+ compatible = "sifive,pL2Cache0", "cache";
+ next-level-cache = <&D1CACHE>;
+ reg = <0x0 0x10c000 0x0 0x4000>;
+ reg-names = "control";
+ sifive,ecc-granularity = <16>;
+ sifive,perfmon-counters = <6>;
+ };
+ L30: pl2@110000 {
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <512>;
+ cache-size = <262144>;
+ cache-unified;
+ compatible = "sifive,pL2Cache0", "cache";
+ next-level-cache = <&D1CACHE>;
+ reg = <0x0 0x110000 0x0 0x4000>;
+ reg-names = "control";
+ sifive,ecc-granularity = <16>;
+ sifive,perfmon-counters = <6>;
+ };
+ #endif
+
+ D2L2_0: pl2@20104000 {
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <512>;
+ cache-size = <262144>;
+ cache-unified;
+ compatible = "sifive,pL2Cache0", "cache";
+ next-level-cache = <&D2CACHE>;
+ reg = <0x0 0x20104000 0x0 0x4000>;
+ reg-names = "control";
+ sifive,ecc-granularity = <16>;
+ sifive,perfmon-counters = <6>;
+ };
+ D2L2_1: pl2@20108000 {
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <512>;
+ cache-size = <262144>;
+ cache-unified;
+ compatible = "sifive,pL2Cache0", "cache";
+ next-level-cache = <&D2CACHE>;
+ reg = <0x0 0x20108000 0x0 0x4000>;
+ reg-names = "control";
+ sifive,ecc-granularity = <16>;
+ sifive,perfmon-counters = <6>;
+ };
+ D2L2_2: pl2@2010c000 {
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <512>;
+ cache-size = <262144>;
+ cache-unified;
+ compatible = "sifive,pL2Cache0", "cache";
+ next-level-cache = <&D2CACHE>;
+ reg = <0x0 0x2010c000 0x0 0x4000>;
+ reg-names = "control";
+ sifive,ecc-granularity = <16>;
+ sifive,perfmon-counters = <6>;
+ };
+ D2L2_3: pl2@20110000 {
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <512>;
+ cache-size = <262144>;
+ cache-unified;
+ compatible = "sifive,pL2Cache0", "cache";
+ next-level-cache = <&D2CACHE>;
+ reg = <0x0 0x20110000 0x0 0x4000>;
+ reg-names = "control";
+ sifive,ecc-granularity = <16>;
+ sifive,perfmon-counters = <6>;
+ };
+
+ L10: rom@1a000000 {
+ compatible = "ucbbar,cacheable-zero0";
+ reg = <0x0 0x1a000000 0x0 0x400000>;
+ };
+ L11: rom@3a000000 {
+ compatible = "ucbbar,cacheable-zero0";
+ reg = <0x0 0x3a000000 0x0 0x400000>;
+ };
+ L6: subsystem_pbus_clock {
+ #clock-cells = <0>;
+ clock-frequency = <10000000>;
+ clock-output-names = "subsystem_pbus_clock";
+ compatible = "fixed-clock";
+ };
+ L61: teststatus@4000 {
+ compatible = "sifive,test0";
+ reg = <0x0 0x4000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L45: tl-address-adjuster@20000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "sifive,tl-inter-sys-port", "sifive,tl-port", "simple-external-bus", "simple-bus";
+ ranges = <0x20000000 0x0 0x20000000 0x1a000000 0x3a400000 0x0 0x3a400000 0x5c00000>;
+ sifive,port-width-bytes = <8>;
+ };
+ L42: tl-inter-mem-master-port@80000000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "sifive,tl-inter-mem-master-port", "sifive,tl-port", "sifive,inter-mem-master-port", "simple-external-bus", "simple-bus";
+ ranges = <0x0 0x80000000 0x0 0x80000000 0x7f 0x80000000>;
+ sifive,port-width-bytes = <32>;
+ };
+ L55: trace-encoder-0@100000 {
+ compatible = "sifive,trace0";
+ reg = <0x0 0x100000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L56: trace-encoder-1@101000 {
+ compatible = "sifive,trace0";
+ reg = <0x0 0x101000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L57: trace-encoder-2@102000 {
+ compatible = "sifive,trace0";
+ reg = <0x0 0x102000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L58: trace-encoder-3@103000 {
+ compatible = "sifive,trace0";
+ reg = <0x0 0x103000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L59: trace-funnel-0@18000 {
+ compatible = "sifive,trace0";
+ reg = <0x0 0x18000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ };
+};
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-arch.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-arch.dtsi
new file mode 100644
index 000000000000..997afe1fa6a2
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-arch.dtsi
@@ -0,0 +1,484 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Include file for Eswin EIC7700 SoC's cpu.
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#include <dt-bindings/clock/win2030-clock.h>
+
+#define UART0_INT 100
+#define UART1_INT 101
+#define UART2_INT 102
+#define UART3_INT 103
+#define UART4_INT 104
+#define I2C_BITRATE_STANDARD 100000 /* 100 Kbit/s */
+#define I2C_BITRATE_FAST 400000 /* 400 Kbit/s */
+#define I2C_BITRATE_FAST_PLUS 1000000 /* 1 Mbit/s */
+#define I2C_BITRATE_HIGH 3400000 /* 3.4 Mbit/s */
+#define I2C_BITRATE_ULTRA 5000000 /* 5 Mbit/s */
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "SiFive,FU800-dev", "fu800-dev", "sifive-dev", "eic7700-dev";
+
+ L64: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <RTCCLK_FREQ>;
+ L17: cpu@0 {
+ clock-frequency = <0>;
+ compatible = "eswin,eic770x", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <4>;
+ hwpf-distanceBits = <6>;
+ hwpf-hitCacheThrdBits = <5>;
+ hwpf-hitMSHRThrdBits = <4>;
+ hwpf-l2pfPoolSize = <10>;
+ hwpf-nIssQEnt = <6>;
+ hwpf-nPrefetchQueueEntries = <8>;
+ hwpf-nStreams = <16>;
+ hwpf-qFullnessThrdBits = <4>;
+ hwpf-windowBits = <6>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <&L15>;
+ reg = <0x0>;
+ riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
+ riscv,pmpgranularity = <4096>;
+ riscv,pmpregions = <8>;
+ sifive,buserror = <&L16>;
+ status = "okay";
+ timebase-frequency = <RTCCLK_FREQ>;
+ tlb-split;
+ clocks = <&d0_clock WIN2030_CLK_CPU_EXT_SRC_CORE_CLK_0>;
+ operating-points-v2 = <&d0_cpu_opp_table>;
+ L14: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ L13: pmu {
+ compatible = "riscv,pmu0", "riscv,pmu";
+ interrupts-extended = <&L14 13>;
+ };
+ };
+ L22: cpu@1 {
+ clock-frequency = <0>;
+ compatible = "eswin,eic770x", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <4>;
+ hwpf-distanceBits = <6>;
+ hwpf-hitCacheThrdBits = <5>;
+ hwpf-hitMSHRThrdBits = <4>;
+ hwpf-l2pfPoolSize = <10>;
+ hwpf-nIssQEnt = <6>;
+ hwpf-nPrefetchQueueEntries = <8>;
+ hwpf-nStreams = <16>;
+ hwpf-qFullnessThrdBits = <4>;
+ hwpf-windowBits = <6>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <&L20>;
+ reg = <0x1>;
+ riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
+ riscv,pmpgranularity = <4096>;
+ riscv,pmpregions = <8>;
+ sifive,buserror = <&L21>;
+ status = "okay";
+ timebase-frequency = <RTCCLK_FREQ>;
+ tlb-split;
+ clocks = <&d0_clock WIN2030_CLK_CPU_EXT_SRC_CORE_CLK_1>;
+ operating-points-v2 = <&d0_cpu_opp_table>;
+ L19: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ L18: pmu {
+ compatible = "riscv,pmu0", "riscv,pmu";
+ interrupts-extended = <&L19 13>;
+ };
+ };
+ L27: cpu@2 {
+ clock-frequency = <0>;
+ compatible = "eswin,eic770x", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <4>;
+ hwpf-distanceBits = <6>;
+ hwpf-hitCacheThrdBits = <5>;
+ hwpf-hitMSHRThrdBits = <4>;
+ hwpf-l2pfPoolSize = <10>;
+ hwpf-nIssQEnt = <6>;
+ hwpf-nPrefetchQueueEntries = <8>;
+ hwpf-nStreams = <16>;
+ hwpf-qFullnessThrdBits = <4>;
+ hwpf-windowBits = <6>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <&L25>;
+ reg = <0x2>;
+ riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
+ riscv,pmpgranularity = <4096>;
+ riscv,pmpregions = <8>;
+ sifive,buserror = <&L26>;
+ status = "okay";
+ timebase-frequency = <RTCCLK_FREQ>;
+ tlb-split;
+ clocks = <&d0_clock WIN2030_CLK_CPU_EXT_SRC_CORE_CLK_2>;
+ operating-points-v2 = <&d0_cpu_opp_table>;
+ L24: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ L23: pmu {
+ compatible = "riscv,pmu0", "riscv,pmu";
+ interrupts-extended = <&L24 13>;
+ };
+ };
+ L32: cpu@3 {
+ clock-frequency = <0>;
+ compatible = "eswin,eic770x", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <4>;
+ hwpf-distanceBits = <6>;
+ hwpf-hitCacheThrdBits = <5>;
+ hwpf-hitMSHRThrdBits = <4>;
+ hwpf-l2pfPoolSize = <10>;
+ hwpf-nIssQEnt = <6>;
+ hwpf-nPrefetchQueueEntries = <8>;
+ hwpf-nStreams = <16>;
+ hwpf-qFullnessThrdBits = <4>;
+ hwpf-windowBits = <6>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <&L30>;
+ reg = <0x3>;
+ riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
+ riscv,pmpgranularity = <4096>;
+ riscv,pmpregions = <8>;
+ sifive,buserror = <&L31>;
+ status = "okay";
+ timebase-frequency = <RTCCLK_FREQ>;
+ tlb-split;
+ clocks = <&d0_clock WIN2030_CLK_CPU_EXT_SRC_CORE_CLK_3>;
+ operating-points-v2 = <&d0_cpu_opp_table>;
+ L29: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ L28: pmu {
+ compatible = "riscv,pmu0", "riscv,pmu";
+ interrupts-extended = <&L29 13>;
+ };
+ };
+ };
+ L50: memory@80000000 {
+ compatible = "sifive,axi4-mem-port", "sifive,axi4-port", "sifive,mem-port";
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x7f 0x80000000>;
+ sifive,port-width-bytes = <32>;
+ };
+ SOC: soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "SiFive,FU800-soc", "fu800-soc", "sifive-soc", "simple-bus";
+ ranges;
+ L40: authentication-controller {
+ compatible = "sifive,authentication0";
+ sifive,auth-types = "fuse";
+ };
+ L51: axi4-sys-port@40000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "sifive,axi4-sys-port", "sifive,axi4-port", "sifive,sys-port", "simple-external-bus", "simple-bus";
+ ranges = <0x40000000 0x0 0x40000000 0x40000000>;
+ sifive,port-width-bytes = <16>;
+ };
+ L52: axi4-sys-port@8000000000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "sifive,axi4-sys-port", "sifive,axi4-port", "sifive,sys-port", "simple-external-bus", "simple-bus";
+ ranges = <0x80 0x0 0x80 0x0 0x180 0x0>;
+ sifive,port-width-bytes = <16>;
+ };
+ L46: basic-bus-blocker@200000 {
+ compatible = "sifive,basic-bus-blocker1";
+ reg = <0x0 0x200000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L43: basic-bus-blocker@202000 {
+ compatible = "sifive,basic-bus-blocker1";
+ reg = <0x0 0x202000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L48: basic-bus-blocker@204000 {
+ compatible = "sifive,basic-bus-blocker1";
+ reg = <0x0 0x204000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L54: burst-bundler@10010000 {
+ compatible = "sifive,burst-bundler0";
+ reg = <0x0 0x10010000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L16: bus-error-unit@hart0 {
+ compatible = "sifive,buserror";
+ interrupt-parent = <&plic0>;
+ interrupts = <517>;
+ reg = <0x0 0x1700000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L21: bus-error-unit@hart1 {
+ compatible = "sifive,buserror";
+ interrupt-parent = <&plic0>;
+ interrupts = <518>;
+ reg = <0x0 0x1701000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L26: bus-error-unit@hart2 {
+ compatible = "sifive,buserror";
+ interrupt-parent = <&plic0>;
+ interrupts = <519>;
+ reg = <0x0 0x1702000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L31: bus-error-unit@hart3 {
+ compatible = "sifive,buserror";
+ interrupt-parent = <&plic0>;
+ interrupts = <520>;
+ reg = <0x0 0x1703000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L7: cache-controller@2010000 {
+ cache-block-size = <64>;
+ cache-level = <3>;
+ cache-sets = <4096>;
+ cache-size = <4194304>;
+ cache-unified;
+ compatible = "sifive,ccache1", "cache", "sifive,fu740-c000-ccache";
+ interrupt-parent = <&plic0>;
+ interrupts = <1>, <3>, <4>, <2>;
+ next-level-cache = <&L9 &L10 &L11 &L50>;
+ reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x400000>;
+ reg-names = "control", "sideband";
+ sifive,a-mshr-count = <60>;
+ sifive,bank-count = <4>;
+ sifive,ecc-granularity = <8>;
+ sifive,max-master-id = <13>;
+ sifive,perfmon-counters = <6>;
+ numa-node-id = <0>;
+ };
+ /*
+ L33: clint@2000000 {
+ compatible = "riscv,clint0";
+ interrupts-extended = <&L14 3 &L14 7 &L19 3 &L19 7 &L24 3 &L24 7 &L29 3 &L29 7>;
+ reg = <0x0 0x2000000 0x0 0x10000>;
+ reg-names = "control";
+ };
+ */
+ L34: debug-controller@0 {
+ compatible = "sifive,debug-100", "riscv,debug-100";
+ debug-attach = "jtag";
+ reg = <0x0 0x0 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L8: error-device@1000 {
+ compatible = "sifive,error0";
+ reg = <0x0 0x1000 0x0 0x3000 0x0 0x5000 0x0 0x13000 0x0 0x19000 0x0 0xe7000 0x0 0x114000 0x0 0xec000 0x0 0x201000 0x0 0x1000 0x0 0x203000 0x0 0x1000 0x0 0x205000 0x0 0x14fb000 0x0 0x1704000 0x0 0x8fc000 0x0 0x2014000 0x0 0x5fec000 0x0 0x8400000 0x0 0x3c00000 0x0 0x10000000 0x0 0x3000 0x0 0x10004000 0x0 0xc000 0x0 0x10011000 0x0 0x1f000 0x0 0x10034000 0x0 0x9fcc000 0x0 0x1a400000 0x0 0x5c00000>;
+ };
+ L9: error-device@10003000 {
+ compatible = "sifive,error0";
+ reg = <0x0 0x10003000 0x0 0x1000>;
+ };
+ /*
+ L49: global-external-interrupts {
+ compatible = "sifive,global-external-interrupts0";
+ interrupt-parent = <&plic0>;
+ interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515>;
+ };
+ */
+ plic0: interrupt-controller@c000000 {
+ #interrupt-cells = <1>;
+ compatible = "sifive,plic-1.0.0";
+ interrupt-controller;
+ interrupts-extended = <
+ &L14 0xffffffff &L14 9
+ &L19 0xffffffff &L19 9
+ &L24 0xffffffff &L24 9
+ &L29 0xffffffff &L29 9>;
+ reg = <0x0 0xc000000 0x0 0x4000000>;
+ reg-names = "control";
+ riscv,max-priority = <7>;
+ riscv,ndev = <520>;
+ };
+ L53: order-obliterator@10030000 {
+ compatible = "sifive,order-obliterator0";
+ interrupt-parent = <&plic0>;
+ interrupts = <516>;
+ reg = <0x0 0x10030000 0x0 0x4000>;
+ reg-names = "control";
+ };
+ L15: pl2@104000 {
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <512>;
+ cache-size = <262144>;
+ cache-unified;
+ compatible = "sifive,pL2Cache0", "cache";
+ next-level-cache = <&L7>;
+ reg = <0x0 0x104000 0x0 0x4000>;
+ reg-names = "control";
+ sifive,ecc-granularity = <16>;
+ sifive,perfmon-counters = <6>;
+ };
+ L20: pl2@108000 {
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <512>;
+ cache-size = <262144>;
+ cache-unified;
+ compatible = "sifive,pL2Cache0", "cache";
+ next-level-cache = <&L7>;
+ reg = <0x0 0x108000 0x0 0x4000>;
+ reg-names = "control";
+ sifive,ecc-granularity = <16>;
+ sifive,perfmon-counters = <6>;
+ };
+ L25: pl2@10c000 {
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <512>;
+ cache-size = <262144>;
+ cache-unified;
+ compatible = "sifive,pL2Cache0", "cache";
+ next-level-cache = <&L7>;
+ reg = <0x0 0x10c000 0x0 0x4000>;
+ reg-names = "control";
+ sifive,ecc-granularity = <16>;
+ sifive,perfmon-counters = <6>;
+ };
+ L30: pl2@110000 {
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <512>;
+ cache-size = <262144>;
+ cache-unified;
+ compatible = "sifive,pL2Cache0", "cache";
+ next-level-cache = <&L7>;
+ reg = <0x0 0x110000 0x0 0x4000>;
+ reg-names = "control";
+ sifive,ecc-granularity = <16>;
+ sifive,perfmon-counters = <6>;
+ };
+ L10: rom@1a000000 {
+ compatible = "ucbbar,cacheable-zero0";
+ reg = <0x0 0x1a000000 0x0 0x400000>;
+ };
+ L11: rom@3a000000 {
+ compatible = "ucbbar,cacheable-zero0";
+ reg = <0x0 0x3a000000 0x0 0x400000>;
+ };
+ L6: subsystem_pbus_clock {
+ #clock-cells = <0>;
+ clock-frequency = <10000000>;
+ clock-output-names = "subsystem_pbus_clock";
+ compatible = "fixed-clock";
+ };
+ L61: teststatus@4000 {
+ compatible = "sifive,test0";
+ reg = <0x0 0x4000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L45: tl-address-adjuster@20000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "sifive,tl-inter-sys-port", "sifive,tl-port", "simple-external-bus", "simple-bus";
+ ranges = <0x20000000 0x0 0x20000000 0x1a000000 0x3a400000 0x0 0x3a400000 0x5c00000>;
+ sifive,port-width-bytes = <8>;
+ };
+ L42: tl-inter-mem-master-port@80000000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "sifive,tl-inter-mem-master-port", "sifive,tl-port", "sifive,inter-mem-master-port", "simple-external-bus", "simple-bus";
+ ranges = <0x0 0x80000000 0x0 0x80000000 0x7f 0x80000000>;
+ sifive,port-width-bytes = <32>;
+ };
+ L55: trace-encoder-0@100000 {
+ compatible = "sifive,trace0";
+ reg = <0x0 0x100000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L56: trace-encoder-1@101000 {
+ compatible = "sifive,trace0";
+ reg = <0x0 0x101000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L57: trace-encoder-2@102000 {
+ compatible = "sifive,trace0";
+ reg = <0x0 0x102000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L58: trace-encoder-3@103000 {
+ compatible = "sifive,trace0";
+ reg = <0x0 0x103000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L59: trace-funnel-0@18000 {
+ compatible = "sifive,trace0";
+ reg = <0x0 0x18000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ };
+};
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-noc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-noc.dtsi
new file mode 100644
index 000000000000..fe81f8e622e6
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-noc.dtsi
@@ -0,0 +1,2804 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Include file for Die0 NOC monitor of Eswin EIC770x family SoC.
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ */
+
+d0_cfg_noc:d0_cfg_noc{
+ compatible = "eswin,win2030-noc";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ reg = <0 0x52060000 0 0x4000>;
+
+ interrupts = <446>;
+ interrupt-names = "error";
+ interrupt-parent = <&plic0>;
+ errlogger,idx = <0 1 3 5>;
+
+ sideband_manager@52061000{
+ compatible = "eswin,win2xxx-noc-sideband-manager";
+ reg = <0 0x52061000 0 0x10>;
+ SenseIn0 =
+ <SBM_CLMM OFFSET0>,
+ <SBM_CNOC_AON OFFSET1>,
+ <SBM_CNOC_DDRT0_CTRL OFFSET2>,
+ <SBM_CNOC_DDRT0_PHY OFFSET3>,
+ <SBM_CNOC_DDRT1_CTRL OFFSET4>,
+ <SBM_CNOC_DDRT1_PHY OFFSET5>,
+ <SBM_CNOC_DSPT OFFSET6>,
+ <SBM_CNOC_GPU OFFSET7>,
+ <SBM_CNOC_HSP OFFSET8>,
+ <SBM_CNOC_LSP_APB2 OFFSET9>,
+ <SBM_CNOC_LSP_APB3 OFFSET10>,
+ <SBM_CNOC_LSP_APB4 OFFSET11>,
+ <SBM_CNOC_LSP_APB6 OFFSET12>,
+ <SBM_CNOC_MCPUT_D2D OFFSET13>,
+ <SBM_CNOC_NPU OFFSET14>,
+ <SBM_CNOC_PCIET_P OFFSET15>,
+ <SBM_CNOC_PCIET_X OFFSET16>,
+ <SBM_CNOC_TCU OFFSET17>,
+ <SBM_CNOC_VC OFFSET18>,
+ <SBM_CNOC_VI OFFSET19>,
+ <SBM_CNOC_VO OFFSET20>;
+ bf-name =
+ "SBM_CLMM",
+ "SBM_CNOC_AON",
+ "SBM_CNOC_DDRT0_CTRL",
+ "SBM_CNOC_DDRT0_PHY ",
+ "SBM_CNOC_DDRT1_CTRL",
+ "SBM_CNOC_DDRT1_PHY",
+ "SBM_CNOC_DSPT",
+ "SBM_CNOC_GPU",
+ "SBM_CNOC_HSP",
+ "SBM_CNOC_LSP_APB2",
+ "SBM_CNOC_LSP_APB3",
+ "SBM_CNOC_LSP_APB4",
+ "SBM_CNOC_LSP_APB6",
+ "SBM_CNOC_MCPUT_D2D",
+ "SBM_CNOC_NPU",
+ "SBM_CNOC_PCIET_P",
+ "SBM_CNOC_PCIET_X",
+ "SBM_CNOC_TCU",
+ "SBM_CNOC_VC",
+ "SBM_CNOC_VI",
+ "SBM_CNOC_VO";
+ };
+ ErrorLogger0 {
+ compatible = "eswin,win2030,register";
+ offset,length = < 0x14 32 >;
+ description = "Register 0 to log errors";
+ lock {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0 1>;
+ lut = "Not Locked", "Locked";
+ };
+ OpCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 1 4>;
+ lut = "RD: data read with incrementing address",
+ "RDW: data read with wrapping address",
+ "RDL: allocates monitor in the Target with incrementing address",
+ "RDX: exclusive read with incrementing address",
+ "WR: data write with incrementing address",
+ "WRW: data write with wrapping address",
+ "WRC: conditional write if matching monitor in Target is found",
+ "RSV: reserved",
+ "PRE: preamble packet of linked sequence (locked sequence)",
+ "URG: urgency packet used for QoS (status must be REQ)";
+ };
+ ErrCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 8 3 >;
+ lut = "SLV (error source: Target): error detected by the Slave without any information or no Error",
+ "DEC (error source: Initiator NIU): decode error",
+ "UNS (error source: Target NIU): unsupported access type",
+ "DISC (error source: Power Disconnect): disconnected Target or NoC domain",
+ "SEC (error source: Initiator NIU or Firewall): security error",
+ "HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator",
+ "TMO (error source: Target NIU): time-out",
+ "RSV: reserved";
+
+ };
+ Len1 {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 16 12 >;
+ };
+ Format {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 31 1 >;
+ lut = "NTTP v3.0 (Invalid)", "NTTP v3.5 (Ok)";
+ };
+ };
+
+ ErrorLogger1 {
+ compatible = "eswin,win2030,register", "eswin,win2030,noc,filter,routeid";
+ offset,length = < 0x18 32>;
+ description = "Register 1 to log errors";
+ InitFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 15 1 >; /*bit 15 will aloways be 0, then we will always get "snoc_cnoc/I/0"*/
+ lut =
+ "snoc_cnoc/I/0";
+ };
+
+ TargetFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 10 5 >;
+ lut =
+ "clmm/T/0",
+ "cnoc_aon/T/0",
+ "cnoc_ddrt0_ctrl/T/0",
+ "cnoc_ddrt0_phy/T/0",
+ "cnoc_ddrt1_ctrl/T/0",
+ "cnoc_ddrt1_phy/T/0",
+ "cnoc_dspt/T/0",
+ "cnoc_gpu/T/0",
+ "cnoc_hsp/T/0",
+ "cnoc_lsp_apb2/T/0",
+ "cnoc_lsp_apb3/T/0",
+ "cnoc_lsp_apb4/T/0",
+ "cnoc_lsp_apb6/T/0",
+ "cnoc_mcput_d2d/T/0",
+ "cnoc_npu/T/0",
+ "cnoc_pciet_p/T/0",
+ "cnoc_pciet_x/T/0",
+ "cnoc_service/T/0",
+ "cnoc_tcu/T/0",
+ "cnoc_vc/T/0",
+ "cnoc_vi/T/0",
+ "cnoc_vo/T/0",
+ "RESERVED",
+ "RESERVED",
+ "RESERVED",
+ "RESERVED",
+ "RESERVED",
+ "RESERVED",
+ "RESERVED",
+ "RESERVED",
+ "RESERVED",
+ "RESERVED";
+ };
+
+ TargetSubRange {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 8 2 >;
+ };
+
+ SeqId {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0 8 >;
+ };
+ };
+
+ ErrorLogger3 {
+ /* This register does not really include a bitfield or its bitfield is 32 bits and it provides an offset address */
+ /* To calculate the absolute address, you must use the initflow:targetflow:subrange from ErrorLogger1 register */
+ /* And use it as an index in the aperture table. Then you must add the value of this register to the value given */
+ /* by the table to get the absolute address. */
+ compatible = "eswin,win2030,register";
+ offset,length = <0x20 32>;
+ description = "Register 3 to log errors";
+ aperture-link = <1>; /* link to ErrorLogger1 whose information are required to calculate real absolute address */
+ AbsoluteAddress {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 8 8 >; /* bitfield initflow:targeflow:subrange from aperture-link register */
+ aperture-size= < 46 >; /* Number of line in the aperture table below */
+ aperture-idx,aperture-base = /* Aperture_idx is concatenation of initflow:targetflow:subrange bitfield from ErrorLogger1 */
+ /bits/ 64 <0x0 0x0 0x0 0x51600000>,
+ /bits/ 64 <0x0 0x0 0x1 0x71600000>,
+ /bits/ 64 <0x0 0x1 0x0 0x51800000>,
+ /bits/ 64 <0x0 0x1 0x1 0x71800000>,
+ /bits/ 64 <0x0 0x1 0x2 0x0 >,
+ /bits/ 64 <0x0 0x1 0x3 0x0 >,
+ /bits/ 64 <0x0 0x2 0x0 0x52300000>,
+ /bits/ 64 <0x0 0x2 0x1 0x72300000>,
+ /bits/ 64 <0x0 0x3 0x0 0x53000000>,
+ /bits/ 64 <0x0 0x3 0x1 0x73000000>,
+ /bits/ 64 <0x0 0x4 0x0 0x52380000>,
+ /bits/ 64 <0x0 0x4 0x1 0x72380000>,
+ /bits/ 64 <0x0 0x5 0x0 0x53800000>,
+ /bits/ 64 <0x0 0x5 0x1 0x73800000>,
+ /bits/ 64 <0x0 0x6 0x0 0x52200000>,
+ /bits/ 64 <0x0 0x6 0x1 0x72200000>,
+ /bits/ 64 <0x0 0x7 0x0 0x51400000>,
+ /bits/ 64 <0x0 0x7 0x1 0x71400000>,
+ /bits/ 64 <0x0 0x8 0x0 0x50400000>,
+ /bits/ 64 <0x0 0x8 0x1 0x70400000>,
+ /bits/ 64 <0x0 0x9 0x0 0x50800000>,
+ /bits/ 64 <0x0 0x9 0x1 0x70800000>,
+ /bits/ 64 <0x0 0xa 0x0 0x50900000>,
+ /bits/ 64 <0x0 0xa 0x1 0x70900000>,
+ /bits/ 64 <0x0 0xb 0x0 0x50a00000>,
+ /bits/ 64 <0x0 0xb 0x1 0x70a00000>,
+ /bits/ 64 <0x0 0xc 0x0 0x50b00000>,
+ /bits/ 64 <0x0 0xc 0x1 0x70b00000>,
+ /bits/ 64 <0x0 0xd 0x0 0x52100000>,
+ /bits/ 64 <0x0 0xd 0x1 0x72100000>,
+ /bits/ 64 <0x0 0xe 0x0 0x51c00000>,
+ /bits/ 64 <0x0 0xe 0x1 0x71c00000>,
+ /bits/ 64 <0x0 0xf 0x0 0x50000000>,
+ /bits/ 64 <0x0 0xf 0x1 0x70000000>,
+ /bits/ 64 <0x0 0x10 0x0 0x54000000>,
+ /bits/ 64 <0x0 0x10 0x1 0x74000000>,
+ /bits/ 64 <0x0 0x11 0x0 0x52060000>,
+ /bits/ 64 <0x0 0x11 0x1 0x72060000>,
+ /bits/ 64 <0x0 0x12 0x0 0x50c00000>,
+ /bits/ 64 <0x0 0x12 0x1 0x70c00000>,
+ /bits/ 64 <0x0 0x13 0x0 0x50100000>,
+ /bits/ 64 <0x0 0x13 0x1 0x70100000>,
+ /bits/ 64 <0x0 0x14 0x0 0x51000000>,
+ /bits/ 64 <0x0 0x14 0x1 0x71000000>,
+ /bits/ 64 <0x0 0x15 0x0 0x50200000>,
+ /bits/ 64 <0x0 0x15 0x1 0x70200000>;
+ };
+ };
+
+ ErrorLogger5 {
+ compatible = "eswin,win2030,register";
+ offset,length = < 0x28 32>;
+ description = "Register 5 to log errors";
+
+ User_flag {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0x0 7 >;
+ lut =
+ "Cache_0",
+ "Cache_1",
+ "Cache_2",
+ "Cache_3",
+ "Prot_0",
+ "Prot_1",
+ "Prot_2";
+ };
+ };
+};
+
+d0_llc_noc:d0_llc_noc@52081400 {
+ compatible = "eswin,win2030-noc";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ reg = <0 0x52081400 0 0x4000>;
+ interrupts = <441>;
+ interrupt-names = "error";
+ interrupt-parent = <&plic0>;
+ errlogger,idx = <0 1 3 4 5>;
+#ifdef PLATFORM_HAPS
+ clock,rate = <5000000>; /*haps ddr controller clk*/
+#endif
+ sideband_manager@52082000 {
+ compatible = "eswin,win2xxx-noc-sideband-manager";
+ reg = <0 0x52082000 0 0x10>;
+ SenseIn0 =
+ <SBM_LNOC_NPU_LLC0 OFFSET0>,
+ <SBM_LNOC_NPU_LLC1 OFFSET1>,
+ <SBM_LNOC_DDRT0_P0 OFFSET2>,
+ <SBM_LNOC_DDRT1_P0 OFFSET3>;
+ bf-name =
+ "SBM_LNOC_NPU_LLC0",
+ "SBM_LNOC_NPU_LLC1",
+ "SBM_LNOC_DDRT0_P0",
+ "SBM_LNOC_DDRT1_P0";
+ };
+
+ llcnoc_packet_ddr0_p0_req_probe@52080000 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0 0x52080000 0 0x4000>;
+ clocks = <&d0_clock WIN2030_CLK_DDRT0_P0_ACLK>;
+ clock-names = "clk";
+ interrupts = <445>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic0>;
+ filter,nr = <1>;
+ counter,nr = <2>;
+ portsel = "ddr0_p0_req";
+ };
+ llcnoc_packet_ddr1_p0_req_probe@52080800 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0 0x52080800 0 0x4000>;
+ clocks =<&d0_clock WIN2030_CLK_DDRT1_P0_ACLK>;
+ clock-names = "clk";
+ interrupts = <443>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic0>;
+ filter,nr = <1>;
+ counter,nr = <2>;
+ portsel = "ddr1_p0_req";
+ };
+ llcnoc_trans_probe@52081000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ compatible = "eswin,win2xxx-noc-trans-probe";
+ reg = <0 0x52081000 0 0x4000>;
+ clocks =<&d0_clock WIN2030_CLK_NOC_NSP_CLK>;
+ clock-names = "clk";
+ interrupts = <441>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic0>;
+ filter,nr = <2>;
+ counter,nr = <8>;
+ profiler,nr = <1>;
+ portsel = "npu_llc0", "npu_llc1";
+ llcnoc_trans_npu_llc0_filter@52081480 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x52081480 0 0x80>;
+ };
+ llcnoc_trans_npu_llc1_filter@52081500 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x52081500 0 0x80>;
+ };
+ llcnoc_trans_profiler@52081580 {
+ compatible = "eswin,win2xxx-noc-trans-profiler";
+ reg = <0 0x52081580 0 0x80>;
+ };
+ };
+ ErrorLogger0 {
+ compatible = "eswin,win2030,register";
+ offset,length = < 0x14 32 >;
+ description = "Register 0 to log errors";
+ lock {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0 1 >;
+ lut = "Not Locked", "Locked";
+ };
+ OpCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 1 4 >;
+ lut = "RD: data read with incrementing address",
+ "RDW: data read with wrapping address",
+ "RDL: allocates monitor in the Target with incrementing address",
+ "RDX: exclusive read with incrementing address",
+ "WR: data write with incrementing address",
+ "WRW: data write with wrapping address",
+ "WRC: conditional write if matching monitor in Target is found",
+ "RSV: reserved",
+ "PRE: preamble packet of linked sequence (locked sequence)",
+ "URG: urgency packet used for QoS (status must be REQ)";
+ };
+ ErrCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 8 3 >;
+ lut = "SLV (error source: Target): error detected by the Slave without any information or no Error",
+ "DEC (error source: Initiator NIU): decode error",
+ "UNS (error source: Target NIU): unsupported access type",
+ "DISC (error source: Power Disconnect): disconnected Target or NoC domain",
+ "SEC (error source: Initiator NIU or Firewall): security error",
+ "HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator",
+ "TMO (error source: Target NIU): time-out",
+ "RSV: reserved";
+
+ };
+ Len1 {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 16 12 >;
+ };
+ Format {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 31 1 >;
+ lut = "NTTP v3.0 (Invalid)", "NTTP v3.5 (Ok)";
+ };
+ };
+
+ ErrorLogger1 {
+ compatible = "eswin,win2030,register", "eswin,win2030,noc,filter,routeid";
+ offset,length = < 0x18 32>;
+ description = "Register 1 to log errors";
+ InitFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 14 2 >;
+ lut =
+ "npu_lnoc_llc0/I/0",
+ "npu_lnoc_llc1/I/0",
+ "snoc_lnoc/I/0",
+ "RESERVED";
+ };
+
+ TargetFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 12 2 >;
+ lut =
+ "lnoc_ddrt0_p0/T/0",
+ "lnoc_ddrt1_p0/T/0",
+ "lnoc_service/T/0",
+ "RESERVED";
+ };
+
+ TargetSubRange {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 8 4 >;
+ };
+
+ SeqId {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0 8 >;
+ };
+ };
+
+ ErrorLogger3 {
+ /* This register does not really include a bitfield or its bitfield is 32 bits and it provides an offset address */
+ /* To calculate the absolute address, you must use the initflow:targetflow:subrange from ErrorLogger1 register */
+ /* And use it as an index in the aperture table. Then you must add the value of this register to the value given */
+ /* by the table to get the absolute address. */
+ compatible = "eswin,win2030,register";
+ offset,length = <0x20 32>;
+ description = "Register 3 to log errors";
+ aperture-link = <1>; /* link to ErrorLogger whose information are required to calculate real absolute address */
+ msb-link = <4>; /*indicate which ErrorLogger contains the msb addrs, -1 means no*/
+ AbsoluteAddress {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 8 8 >; /* bitfield initflow:targeflow:subrange from aperture-link register */
+ aperture-size= < 53 >; /* Number of line in the aperture table below */
+ aperture-idx,aperture-base = /* Aperture_idx is concatenation of initflow:targetflow:subrange bitfield from ErrorLogger1 */
+ /bits/ 64 <0x0 0x0 0x0 0x80000000 >,
+ /bits/ 64 <0x0 0x0 0x1 0x100000000 >,
+ /bits/ 64 <0x0 0x0 0x2 0x200000000 >,
+ /bits/ 64 <0x0 0x0 0x3 0x400000000 >,
+ /bits/ 64 <0x0 0x0 0x4 0x800000000 >,
+ /bits/ 64 <0x0 0x0 0x5 0x2000000000 >,
+ /bits/ 64 <0x0 0x0 0x6 0xc000000000 >,
+ /bits/ 64 <0x0 0x0 0x7 0xe000000000 >,
+ /bits/ 64 <0x0 0x0 0x8 0x4000000000 >,
+ /bits/ 64 <0x0 0x0 0x9 0x4000000100 >,
+ /bits/ 64 <0x0 0x0 0xa 0x10000000000 >,
+ /bits/ 64 <0x0 0x0 0xb 0x10000000100 >,
+ /bits/ 64 <0x0 0x0 0xc 0x0 >,
+ /bits/ 64 <0x0 0x1 0x0 0x80000080 >,
+ /bits/ 64 <0x0 0x1 0x1 0x100000080 >,
+ /bits/ 64 <0x0 0x1 0x2 0x200000080 >,
+ /bits/ 64 <0x0 0x1 0x3 0x400000080 >,
+ /bits/ 64 <0x0 0x1 0x4 0x800000080 >,
+ /bits/ 64 <0x0 0x1 0x5 0x2000000080 >,
+ /bits/ 64 <0x0 0x1 0x6 0xc000000080 >,
+ /bits/ 64 <0x0 0x1 0x7 0xe000000080 >,
+ /bits/ 64 <0x0 0x1 0x8 0x4000000080 >,
+ /bits/ 64 <0x0 0x1 0x9 0x4000000180 >,
+ /bits/ 64 <0x0 0x1 0xa 0x10000000080 >,
+ /bits/ 64 <0x0 0x1 0xb 0x10000000180 >,
+ /bits/ 64 <0x1 0x0 0x0 0x80000000 >,
+ /bits/ 64 <0x1 0x0 0x1 0x100000000 >,
+ /bits/ 64 <0x1 0x0 0x2 0x200000000 >,
+ /bits/ 64 <0x1 0x0 0x3 0x400000000 >,
+ /bits/ 64 <0x1 0x0 0x4 0x800000000 >,
+ /bits/ 64 <0x1 0x0 0x5 0x2000000000 >,
+ /bits/ 64 <0x1 0x0 0x6 0xc000000000 >,
+ /bits/ 64 <0x1 0x0 0x7 0xe000000000 >,
+ /bits/ 64 <0x1 0x0 0x8 0x4000000000 >,
+ /bits/ 64 <0x1 0x0 0x9 0x4000000100 >,
+ /bits/ 64 <0x1 0x0 0xa 0x10000000000 >,
+ /bits/ 64 <0x1 0x0 0xb 0x10000000100 >,
+ /bits/ 64 <0x1 0x0 0xc 0x0 >,
+ /bits/ 64 <0x1 0x1 0x0 0x80000080 >,
+ /bits/ 64 <0x1 0x1 0x1 0x100000080 >,
+ /bits/ 64 <0x1 0x1 0x2 0x200000080 >,
+ /bits/ 64 <0x1 0x1 0x3 0x400000080 >,
+ /bits/ 64 <0x1 0x1 0x4 0x800000080 >,
+ /bits/ 64 <0x1 0x1 0x5 0x2000000080 >,
+ /bits/ 64 <0x1 0x1 0x6 0xc000000080 >,
+ /bits/ 64 <0x1 0x1 0x7 0xe000000080 >,
+ /bits/ 64 <0x1 0x1 0x8 0x4000000080 >,
+ /bits/ 64 <0x1 0x1 0x9 0x4000000180 >,
+ /bits/ 64 <0x1 0x1 0xa 0x10000000080 >,
+ /bits/ 64 <0x1 0x1 0xb 0x10000000180 >,
+ /bits/ 64 <0x2 0x2 0x0 0x52080000 >,
+ /bits/ 64 <0x2 0x2 0x1 0x72080000 >,
+ /bits/ 64 <0x2 0x2 0x2 0x0 >;
+ };
+ };
+
+ ErrorLogger4 {
+ compatible = "eswin,win2030,register";
+ offset,length = < 0x24 32>;
+ description = "Register 4 to log errors";
+ addr_msb {
+ compatible = "eswin,win2030,bitfield";
+ description = "Stores NTTP packet header field Addr (MSBs) of the logged error";
+ offset,length = < 0 9 >;
+ };
+ };
+
+ ErrorLogger5 {
+ compatible = "eswin,win2030,register";
+ offset,length = < 0x28 32 >;
+ description = "Register 5 to log errors";
+
+ User_flag {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0x0 16 >;
+ lut =
+ "Cache_0",
+ "Cache_1",
+ "Cache_2",
+ "Cache_3",
+ "Prot_0",
+ "Prot_1",
+ "Prot_2",
+ "Qos_0",
+ "Qos_1",
+ "Qos_2",
+ "Qos_3",
+ "User_0",
+ "User_1",
+ "User_2",
+ "User_3",
+ "User_4";
+ };
+ };
+};
+
+d0_sys_noc:d0_sys_noc@52002C00 {
+ compatible = "eswin,win2030-noc";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ reg = <0 0x52002C00 0 0x4000>;
+ interrupts = <431>;
+ interrupt-names = "error";
+ interrupt-parent = <&plic0>;
+ errlogger,idx = <0 1 3 4 5>;
+
+ eswin,qos-configs = "DSPT", "NPU", "SPISLV_TBU3";
+#ifdef PLATFORM_HAPS
+ eswin,DSPT-qos-base = <0x52002C80>;
+ eswin,DSPT-qos-settings = <
+ 0x8 0x4 /* prio */
+ 0xC 0x1 /* mode 0:fixed 1:limiter 2:bypass 3:regulator*/
+ /* a number of (1/256)th of Bytes/cycle.
+ Ex:DSP AXI clk=5MHz, BW=1MB/s, register value = (1/5)*256 = 0x33
+ */
+ 0x10 0x33 /* bandwidth. 1MB/s */
+ /*
+ Saturation(B) = ((Requried Bandwidth)*(Windows Time of Bandwidth Calculation))/16
+ Ex:16 byte saturation for BW=1MB/s means 16us window time.
+ The desired value is number of saturation bytes divided by 16(ex,1 for 16byte B)
+ */
+ 0x14 0x1 /* saturation, 16us*/
+ 0x18 0x0>; /* QoSEn */
+
+ eswin,NPU-qos-base = <0x52002D00>;
+ eswin,NPU-qos-settings = <
+ 0x8 0x4 /* prio */
+ 0xC 0x1 /* mode */
+ 0x10 0x18 /* bandwidth */
+ 0x14 0x10 /* saturation */
+ 0x18 0x0>; /* QoSEn */
+
+ eswin,SPISLV_TBU3-qos-base = <0x52002D80>;
+ eswin,SPISLV_TBU3-qos-settings = <
+ 0x8 0x4 /* prio */
+ 0xC 0x1 /* mode */
+ 0x10 0x18 /* bandwidth */
+ 0x14 0x10 /* saturation */
+ 0x18 0x0>; /* QoSEn */
+ clock,rate = <5000000>; /*haps ddr controller axi clk*/
+#else
+ eswin,DSPT-qos-base = <0x52002C80>;
+ eswin,DSPT-qos-settings = <
+ 0x8 0x4 /* prio */
+ 0xC 0x2 /* mode 0:fixed 1:limiter 2:bypass 3:regulator*/
+ /* a number of (1/256)th of Bytes/cycle.
+ Ex:zebu zdfi design feature, dsp AXI Clk=1040MHz, BW=12.1875MB/s, register value = (9.375/1040)*256 = 0x03
+ */
+ 0x10 0x03 /* bandwidth. 12.1875MB/s */
+ /*
+ Saturation(B) = ((Requried Bandwidth)*(Windows Time of Bandwidth Calculation))/16
+ Ex:16 byte saturation for BW=12.1875MB/s means 1.313us window time.
+ The desired value is number of saturation bytes divided by 16(ex,1 for 16byte B)
+ */
+ 0x14 0x1 /* saturation, 1.313us*/
+ 0x18 0x1>; /* QoSEn */
+
+ eswin,NPU-qos-base = <0x52002D00>;
+ eswin,NPU-qos-settings = <
+ 0x8 0x4 /* prio */
+ 0xC 0x2 /* mode */
+ 0x10 0x18 /* bandwidth */
+ 0x14 0x10 /* saturation */
+ 0x18 0x1>; /* QoSEn */
+
+ eswin,SPISLV_TBU3-qos-base = <0x52002D80>;
+ eswin,SPISLV_TBU3-qos-settings = <
+ 0x8 0x4 /* prio */
+ 0xC 0x2 /* mode */
+ 0x10 0x18 /* bandwidth */
+ 0x14 0x10 /* saturation */
+ 0x18 0x1>; /* QoSEn */
+#endif
+ sideband_manager@52004000 {
+ compatible = "eswin,win2xxx-noc-sideband-manager";
+ reg = <0 0x52004000 0 0x10>;
+ SenseIn0 =
+ <SBM_AON_SNOC_SP0 OFFSET0>,
+ <SBM_DSPT_SNOC OFFSET1>,
+ <SBM_JTAG_SNOC OFFSET2>,
+ <SBM_MCPUT_SNOC_D2D OFFSET3>,
+ <SBM_MCPUT_SNOC_MP OFFSET4>,
+ <SBM_MCPUT_SNOC_SP0 OFFSET5>,
+ <SBM_MCPUT_SNOC_SP1 OFFSET6>,
+ <SBM_NPU_SNOC_SP0 OFFSET7>,
+ <SBM_NPU_SNOC_SP1 OFFSET8>,
+ <SBM_PCIET_SNOC_P OFFSET9>,
+ <SBM_SPISLV_PCIET_SNOC OFFSET10>,
+ <SBM_TBU4_SNOC OFFSET11>,
+ <SBM_TCU_SNOC OFFSET12>,
+ <SBM_SNOC_AON OFFSET13>,
+ <SBM_SNOC_DDR0_P1 OFFSET14>,
+ <SBM_SNOC_DDR0_P2 OFFSET15>,
+ <SBM_SNOC_DDR1_P1 OFFSET16>,
+ <SBM_SNOC_DDR1_P2 OFFSET17>,
+ <SBM_SNOC_DSPT OFFSET18>,
+ <SBM_SNOC_MCPUT_D2D OFFSET19>,
+ <SBM_SNOC_NPU OFFSET20>,
+ <SBM_SNOC_PCIET OFFSET21>;
+ bf-name =
+ "SBM_AON_SNOC_SP0",
+ "SBM_DSPT_SNOC",
+ "SBM_JTAG_SNOC",
+ "SBM_MCPUT_SNOC_D2D ",
+ "SBM_MCPUT_SNOC_MP",
+ "SBM_MCPUT_SNOC_SP0",
+ "SBM_MCPUT_SNOC_SP1",
+ "SBM_NPU_SNOC_SP0",
+ "SBM_NPU_SNOC_SP1",
+ "SBM_PCIET_SNOC_P",
+ "SBM_SPISLV_PCIET_SNOC",
+ "SBM_TBU4_SNOC",
+ "SBM_TCU_SNOC",
+ "SBM_SNOC_AON",
+ "SBM_SNOC_DDR0_P1",
+ "SBM_SNOC_DDR0_P2",
+ "SBM_SNOC_DDR1_P1",
+ "SBM_SNOC_DDR1_P2",
+ "SBM_SNOC_DSPT",
+ "SBM_SNOC_MCPUT_D2D",
+ "SBM_SNOC_NPU",
+ "SBM_SNOC_PCIET";
+ };
+ sysnoc_packet_ddr0_p1_req_probe@52000000 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0 0x52000000 0 0x4000>;
+ clocks =<&d0_clock WIN2030_CLK_DDRT0_P1_ACLK>;
+ clock-names = "clk";
+ interrupts = <439>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic0>;
+ filter,nr = <1>;
+ counter,nr = <2>;
+ portsel = "ddr0_p1_req";
+ };
+ sysnoc_packet_ddr0_p2_req_probe@52000800 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0 0x52000800 0 0x4000>;
+ clocks =<&d0_clock WIN2030_CLK_DDRT0_P2_ACLK>;
+ clock-names = "clk";
+ interrupts = <437>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic0>;
+ filter,nr = <1>;
+ counter,nr = <2>;
+ portsel = "ddr0_p2_req";
+ };
+ sysnoc_packet_ddr1_p1_req_probe@52001000 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0 0x52001000 0 0x4000>;
+ clocks =<&d0_clock WIN2030_CLK_DDRT1_P1_ACLK>;
+ clock-names = "clk";
+ interrupts = <435>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic0>;
+ filter,nr = <1>;
+ counter,nr = <2>;
+ portsel = "ddr1_p1_req";
+ };
+ sysnoc_packet_ddr1_p2_req_probe@52001800 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0 0x52001800 0 0x4000>;
+ clocks =<&d0_clock WIN2030_CLK_DDRT1_P2_ACLK>;
+ clock-names = "clk";
+ interrupts = <433>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic0>;
+ filter,nr = <1>;
+ counter,nr = <2>;
+ portsel = "ddr1_p2_req";
+ };
+ sysnoc_trans_probe_0@52002000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ compatible = "eswin,win2xxx-noc-trans-probe";
+ reg = <0 0x52002000 0 0x4000>;
+ clocks =<&d0_clock WIN2030_CLK_NOC_NSP_CLK>;
+ clock-names = "clk";
+ interrupts = <430>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic0>;
+ filter,nr = <2>;
+ counter,nr = <8>;
+ profiler,nr = <1>;
+ portsel = "dspt_snoc", "npu_sp1";
+ sysnoc_trans_dspt_filter@52002E00 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x52002E00 0 0x80>;
+ };
+ sysnoc_trans_npu_sp1_filter@52002F80 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x52002F80 0 0x80>;
+ };
+ sysnoc_trans_profiler@52003180 {
+ compatible = "eswin,win2xxx-noc-trans-profiler";
+ reg = <0 0x52003180 0 0x80>;
+ };
+ };
+ sysnoc_trans_probe_1@52002400 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ compatible = "eswin,win2xxx-noc-trans-probe";
+ reg = <0 0x52002400 0 0x4000>;
+ clocks =<&d0_clock WIN2030_CLK_NOC_NSP_CLK>;
+ clock-names = "clk";
+ interrupts = <429>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic0>;
+ filter,nr = <3>;
+ counter,nr = <12>;
+ profiler,nr = <1>;
+ portsel = "mcput_mp", "mcput_sp1", "tcu";
+ sysnoc_trans_mcput_mp_filter@52002E80 {
+ status = "okay";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x52002E80 0 0x80>;
+ };
+ sysnoc_trans_mcput_sp1_filter@52002F00 {
+ status = "okay";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x52002F00 0 0x80>;
+ };
+ sysnoc_trans_tcu_filter@52003100 {
+ status = "okay";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x52003100 0 0x80>;
+ };
+ sysnoc_trans_profiler@52003200 {
+ compatible = "eswin,win2xxx-noc-trans-profiler";
+ reg = <0 0x52003200 0 0x80>;
+ };
+ };
+ sysnoc_trans_probe_2@52002800 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ compatible = "eswin,win2xxx-noc-trans-probe";
+ reg = <0 0x52002800 0 0x4000>;
+ clocks =<&d0_clock WIN2030_CLK_NOC_NSP_CLK>;
+ clock-names = "clk";
+ interrupts = <428>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic0>;
+ filter,nr = <2>;
+ counter,nr = <8>;
+ profiler,nr = <1>;
+ portsel = "spislv_tbu3", "tbu4_snoc";
+ sysnoc_trans_spislv_tbu3_filter@52003000 { /*pcie subsys*/
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x52003000 0 0x80>;
+ };
+ sysnoc_trans_tbu4_filter@52003080 { /*aon subsys*/
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x52003080 0 0x80>;
+ };
+ sysnoc_trans_profiler@52003280 {
+ compatible = "eswin,win2xxx-noc-trans-profiler";
+ reg = <0 0x52003280 0 0x80>;
+ };
+ };
+ ErrorLogger0 {
+ compatible = "eswin,win2030,register";
+ offset,length = < 0x14 32 >;
+ description = "Register 0 to log errors";
+ lock {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0 1>;
+ lut = "Not Locked", "Locked";
+ };
+ OpCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 1 4>;
+ lut = "RD: data read with incrementing address",
+ "RDW: data read with wrapping address",
+ "RDL: allocates monitor in the Target with incrementing address",
+ "RDX: exclusive read with incrementing address",
+ "WR: data write with incrementing address",
+ "WRW: data write with wrapping address",
+ "WRC: conditional write if matching monitor in Target is found",
+ "RSV: reserved",
+ "PRE: preamble packet of linked sequence (locked sequence)",
+ "URG: urgency packet used for QoS (status must be REQ)";
+ };
+ ErrCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 8 3 >;
+ lut = "SLV (error source: Target): error detected by the Slave without any information or no Error",
+ "DEC (error source: Initiator NIU): decode error",
+ "UNS (error source: Target NIU): unsupported access type",
+ "DISC (error source: Power Disconnect): disconnected Target or NoC domain",
+ "SEC (error source: Initiator NIU or Firewall): security error",
+ "HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator",
+ "TMO (error source: Target NIU): time-out",
+ "RSV: reserved";
+
+ };
+ Len1 {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 16 12 >;
+ };
+ Format {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 31 1 >;
+ lut = "NTTP v3.0 (Invalid)", "NTTP v3.5 (Ok)";
+ };
+ };
+
+ ErrorLogger1 {
+ compatible = "eswin,win2030,register", "eswin,win2030,noc,filter,routeid";
+ offset,length = < 0x18 32>;
+ description = "Register 1 to log errors";
+ InitFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 19 4 >;
+ lut =
+ "aon_snoc_sp0/I/0",
+ "dspt_snoc/I/0",
+#ifdef PLATFORM_HAPS
+ "fpga_snoc/I/0",
+#endif
+ "jtag_snoc/I/0",
+ "mcput_snoc_d2d/I/0",
+ "mcput_snoc_mp/I/0",
+ "mcput_snoc_sp0/I/0",
+ "mcput_snoc_sp1/I/0",
+ "mnoc_snoc/I/0",
+ "npu_snoc_sp0/I/0",
+ "npu_snoc_sp1/I/0",
+ "pciet_snoc_p/I/0",
+ "rnoc_snoc/I/0",
+ "spislv_tbu3_snoc/I/0",
+ "tbu4_snoc/I/0",
+ "tcu_snoc/I/0",
+ "RESERVED0";
+ };
+
+ TargetFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 15 4 >;
+ lut =
+ "snoc_aon/T/0",
+ "snoc_cnoc/T/0",
+ "snoc_ddrt0_p1/T/0",
+ "snoc_ddrt0_p2/T/0",
+ "snoc_ddrt1_p1/T/0",
+ "snoc_ddrt1_p2/T/0",
+ "snoc_dspt/T/0",
+ "snoc_lnoc/T/0",
+ "snoc_mcput_d2d/T/0",
+ "snoc_mnoc/T/0",
+ "snoc_npu/T/0",
+ "snoc_pciet/T/0",
+ "snoc_rnoc/T/0",
+ "snoc_service/T/0",
+ "RESERVED1",
+ "RESERVED2";
+ };
+
+ TargetSubRange {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 9 6 >;
+ };
+
+ SeqId {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0 9 >;
+ };
+ };
+
+ ErrorLogger3 {
+ /* This register does not really include a bitfield or its bitfield is 32 bits and it provides an offset address */
+ /* To calculate the absolute address, you must use the initflow:targetflow:subrange from ErrorLogger1 register */
+ /* And use it as an index in the aperture table. Then you must add the value of this register to the value given */
+ /* by the table to get the absolute address. */
+ compatible = "eswin,win2030,register";
+ offset,length = <0x20 32>;
+ description = "Register 3 to log errors";
+ aperture-link = <1>; /* link to ErrorLogger whose information are required to calculate real absolute address */
+ msb-link = <4>; /*indicate which ErrorLogger contains the msb addrs, -1 means no*/
+ AbsoluteAddress {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 9 14 >; /* bitfield initflow:targeflow:subrange from aperture-link register */
+ aperture-size= < 1181 >; /* Number of line in the aperture table below */
+ aperture-idx,aperture-base = /* Aperture_idx is concatenation of initflow:targetflow:subrange bitfield from ErrorLogger1 */
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0x0 0x52060000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0x1 0x72060000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0x2 0x52100000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0x3 0x52200000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0x4 0x52300000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0x5 0x72100000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0x6 0x72200000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0x7 0x72300000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0x8 0x53000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0x9 0x73000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0xa 0x50000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0xb 0x70000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0xc 0x54000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0xd 0x74000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0xe 0x0 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0xf 0x0 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0x10 0x0 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_dspt_T_O 0x0 0x520e0000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_dspt_T_O 0x1 0x720e0000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_dspt_T_O 0x2 0x5b000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_dspt_T_O 0x3 0x7b000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_lnoc_T_O 0x0 0x52080000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_lnoc_T_O 0x1 0x72080000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x0 0x58400000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x1 0x78400000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x2 0x58800000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x3 0x78800000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x4 0x59000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x5 0x5a000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x6 0x5b000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x7 0x79000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x8 0x7a000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x9 0x7b000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mcput_d2d_T_O 0xa 0x50000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mcput_d2d_T_O 0xb 0x70000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mcput_d2d_T_O 0xc 0x40000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mcput_d2d_T_O 0xd 0x60000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mnoc_T_O 0x0 0x52020000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mnoc_T_O 0x1 0x72020000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_npu_T_O 0x0 0x52080000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_npu_T_O 0x1 0x72080000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_npu_T_O 0x2 0x59000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_npu_T_O 0x3 0x5a000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_npu_T_O 0x4 0x79000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_npu_T_O 0x5 0x7a000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_pciet_T_O 0x0 0x40000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_pciet_T_O 0x1 0x60000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_rnoc_T_O 0x0 0x52040000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_rnoc_T_O 0x1 0x72040000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_service_T_O 0x0 0x52000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_service_T_O 0x1 0x72000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_aon_T_O 0x0 0x520c0000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_aon_T_O 0x1 0x720c0000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_aon_T_O 0x2 0x58400000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_aon_T_O 0x3 0x78400000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_aon_T_O 0x4 0x14000400000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_aon_T_O 0x5 0x14008400000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_aon_T_O 0x6 0x58800000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_aon_T_O 0x7 0x78800000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_aon_T_O 0x8 0x14000800000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_aon_T_O 0x9 0x14008800000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_aon_T_O 0xa 0x5c000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_aon_T_O 0xb 0x7c000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_aon_T_O 0xc 0x14004000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_aon_T_O 0xd 0x1400c000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0x0 0x52060000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0x1 0x72060000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0x2 0x52100000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0x3 0x52200000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0x4 0x52300000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0x5 0x72100000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0x6 0x72200000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0x7 0x72300000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0x8 0x53000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0x9 0x73000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0xa 0x50000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0xb 0x70000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0xc 0x54000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0xd 0x74000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0xe 0x0 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt0_p2_T_O 0x0 0x80000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt0_p2_T_O 0x1 0x100000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt0_p2_T_O 0x2 0x200000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt0_p2_T_O 0x3 0x400000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt0_p2_T_O 0x4 0x800000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt0_p2_T_O 0x5 0x2000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt0_p2_T_O 0x6 0xc000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt0_p2_T_O 0x7 0xe000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt0_p2_T_O 0x8 0x4000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt0_p2_T_O 0x9 0x4000000100 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt0_p2_T_O 0xa 0x10000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt0_p2_T_O 0xb 0x10000000100 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt1_p2_T_O 0x0 0x80000080 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt1_p2_T_O 0x1 0x100000080 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt1_p2_T_O 0x2 0x200000080 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt1_p2_T_O 0x3 0x400000080 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt1_p2_T_O 0x4 0x800000080 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt1_p2_T_O 0x5 0x2000000080 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt1_p2_T_O 0x6 0xc000000080 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt1_p2_T_O 0x7 0xe000000080 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt1_p2_T_O 0x8 0x4000000080 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt1_p2_T_O 0x9 0x4000000180 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt1_p2_T_O 0xa 0x10000000080 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt1_p2_T_O 0xb 0x10000000180 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x0 0x58400000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x1 0x78400000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x2 0x14000400000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x3 0x14008400000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x4 0x58800000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x5 0x78800000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x6 0x14000800000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x7 0x14008800000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x8 0x59000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x9 0x5a000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0xa 0x5b000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0xb 0x79000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0xc 0x7a000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0xd 0x7b000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0xe 0x14001000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0xf 0x14002000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x10 0x14003000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x11 0x14009000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x12 0x1400a000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x13 0x1400b000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x14 0x50000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x15 0x70000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x16 0x40000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x17 0x60000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x18 0x80000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x19 0x100000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x1a 0x200000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x1b 0x400000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x1c 0x800000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x1d 0x1800000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x1e 0x3800000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x1f 0xd800000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x20 0xf800000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x21 0x2000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x22 0x7000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x23 0x7000000100 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x24 0xc000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x25 0xe000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x26 0x13000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x27 0x13000000100 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x28 0x4000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x29 0x4000000100 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x2a 0x8000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x2b 0xa000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x2c 0x10000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x2d 0x10000000100 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0x0 0x52080000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0x1 0x72080000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0x2 0x59000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0x3 0x5a000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0x4 0x79000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0x5 0x7a000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0x6 0x14001000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0x7 0x14002000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0x8 0x14009000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0x9 0x1400a000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0xa 0x1800000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0xb 0x3800000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0xc 0xd800000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0xd 0xf800000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0xe 0x7000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0xf 0x7000000100 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0x10 0x13000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0x11 0x13000000100 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_pciet_T_O 0x0 0x40000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_pciet_T_O 0x1 0x60000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_pciet_T_O 0x2 0x8000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_pciet_T_O 0x3 0xa000000000 >,
+#ifdef PLATFORM_HAPS
+ /bits/ 64 <fpga_snoc_I_O snoc_aon_T_O 0x0 0x520c0000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_aon_T_O 0x1 0x720c0000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_aon_T_O 0x2 0x58400000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_aon_T_O 0x3 0x78400000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_aon_T_O 0x4 0x14000400000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_aon_T_O 0x5 0x14008400000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_aon_T_O 0x6 0x58800000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_aon_T_O 0x7 0x78800000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_aon_T_O 0x8 0x14000800000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_aon_T_O 0x9 0x14008800000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_aon_T_O 0xa 0x5c000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_aon_T_O 0xb 0x7c000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_aon_T_O 0xc 0x14004000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_aon_T_O 0xd 0x1400c000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0x0 0x52060000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0x1 0x72060000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0x2 0x52100000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0x3 0x52200000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0x4 0x52300000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0x5 0x72100000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0x6 0x72200000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0x7 0x72300000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0x8 0x53000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0x9 0x73000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0xa 0x50000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0xb 0x70000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0xc 0x54000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0xd 0x74000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0xe 0x0 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt0_p2_T_O 0x0 0x80000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt0_p2_T_O 0x1 0x100000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt0_p2_T_O 0x2 0x200000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt0_p2_T_O 0x3 0x400000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt0_p2_T_O 0x4 0x800000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt0_p2_T_O 0x5 0x2000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt0_p2_T_O 0x6 0xc000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt0_p2_T_O 0x7 0xe000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt0_p2_T_O 0x8 0x4000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt0_p2_T_O 0x9 0x4000000100 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt0_p2_T_O 0xa 0x10000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt0_p2_T_O 0xb 0x10000000100 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt1_p2_T_O 0x0 0x80000080 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt1_p2_T_O 0x1 0x100000080 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt1_p2_T_O 0x2 0x200000080 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt1_p2_T_O 0x3 0x400000080 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt1_p2_T_O 0x4 0x800000080 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt1_p2_T_O 0x5 0x2000000080 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt1_p2_T_O 0x6 0xc000000080 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt1_p2_T_O 0x7 0xe000000080 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt1_p2_T_O 0x8 0x4000000080 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt1_p2_T_O 0x9 0x4000000180 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt1_p2_T_O 0xa 0x10000000080 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt1_p2_T_O 0xb 0x10000000180 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_dspt_T_O 0x0 0x520e0000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_dspt_T_O 0x1 0x720e0000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_dspt_T_O 0x2 0x5b000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_dspt_T_O 0x3 0x7b000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_dspt_T_O 0x4 0x14003000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_dspt_T_O 0x5 0x1400b000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_lnoc_T_O 0x0 0x52080000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_lnoc_T_O 0x1 0x72080000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x0 0x58400000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x1 0x78400000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x2 0x14000400000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x3 0x14008400000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x4 0x58800000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x5 0x78800000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x6 0x14000800000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x7 0x14008800000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x8 0x59000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x9 0x5a000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0xa 0x5b000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0xb 0x79000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0xc 0x7a000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0xd 0x7b000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0xe 0x14001000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0xf 0x14002000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x10 0x14003000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x11 0x14009000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x12 0x1400a000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x13 0x1400b000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x14 0x50000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x15 0x70000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x16 0x40000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x17 0x60000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x18 0x80000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x19 0x100000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x1a 0x200000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x1b 0x400000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x1c 0x800000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x1d 0x1800000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x1e 0x3800000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x1f 0xd800000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x20 0xf800000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x21 0x2000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x22 0x7000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x23 0x7000000100 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x24 0xc000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x25 0xe000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x26 0x13000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x27 0x13000000100 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x28 0x4000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x29 0x4000000100 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x2a 0x8000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x2b 0xa000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x2c 0x10000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x2d 0x10000000100 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mnoc_T_O 0x0 0x52020000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mnoc_T_O 0x1 0x72020000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0x0 0x52080000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0x1 0x72080000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0x2 0x59000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0x3 0x5a000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0x4 0x79000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0x5 0x7a000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0x6 0x14001000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0x7 0x14002000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0x8 0x14009000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0x9 0x1400a000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0xa 0x1800000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0xb 0x3800000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0xc 0xd800000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0xd 0xf800000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0xe 0x7000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0xf 0x7000000100 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0x10 0x13000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0x11 0x13000000100 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_pciet_T_O 0x0 0x40000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_pciet_T_O 0x1 0x60000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_pciet_T_O 0x2 0x8000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_pciet_T_O 0x3 0xa000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_rnoc_T_O 0x0 0x52040000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_rnoc_T_O 0x1 0x72040000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_service_T_O 0x0 0x52000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_service_T_O 0x1 0x72000000 >,
+#endif
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0x0 0x52060000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0x1 0x72060000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0x2 0x52100000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0x3 0x52200000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0x4 0x52300000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0x5 0x72100000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0x6 0x72200000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0x7 0x72300000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0x8 0x53000000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0x9 0x73000000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0xa 0x50000000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0xb 0x70000000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0xc 0x54000000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0xd 0x74000000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0xe 0x0 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0xf 0x0 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0x10 0x0 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_lnoc_T_O 0x0 0x52080000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_lnoc_T_O 0x1 0x72080000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_mnoc_T_O 0x0 0x52020000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_mnoc_T_O 0x1 0x72020000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_rnoc_T_O 0x0 0x52040000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_rnoc_T_O 0x1 0x72040000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_service_T_O 0x0 0x52000000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_service_T_O 0x1 0x72000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_aon_T_O 0x0 0x520c0000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_aon_T_O 0x1 0x720c0000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_aon_T_O 0x2 0x58400000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_aon_T_O 0x3 0x78400000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_aon_T_O 0x4 0x14000400000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_aon_T_O 0x5 0x14008400000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_aon_T_O 0x6 0x58800000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_aon_T_O 0x7 0x78800000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_aon_T_O 0x8 0x14000800000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_aon_T_O 0x9 0x14008800000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_aon_T_O 0xa 0x5c000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_aon_T_O 0xb 0x7c000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_aon_T_O 0xc 0x14004000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_aon_T_O 0xd 0x1400c000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0x0 0x52060000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0x1 0x72060000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0x2 0x52100000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0x3 0x52200000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0x4 0x52300000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0x5 0x72100000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0x6 0x72200000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0x7 0x72300000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0x8 0x53000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0x9 0x73000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0xa 0x50000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0xb 0x70000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0xc 0x54000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0xd 0x74000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0xe 0x0 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt0_p2_T_O 0x0 0x80000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt0_p2_T_O 0x1 0x100000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt0_p2_T_O 0x2 0x200000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt0_p2_T_O 0x3 0x400000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt0_p2_T_O 0x4 0x800000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt0_p2_T_O 0x5 0x2000000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt0_p2_T_O 0x6 0xc000000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt0_p2_T_O 0x7 0xe000000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt0_p2_T_O 0x8 0x4000000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt0_p2_T_O 0x9 0x4000000100 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt0_p2_T_O 0xa 0x10000000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt0_p2_T_O 0xb 0x10000000100 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt1_p2_T_O 0x0 0x80000080 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt1_p2_T_O 0x1 0x100000080 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt1_p2_T_O 0x2 0x200000080 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt1_p2_T_O 0x3 0x400000080 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt1_p2_T_O 0x4 0x800000080 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt1_p2_T_O 0x5 0x2000000080 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt1_p2_T_O 0x6 0xc000000080 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt1_p2_T_O 0x7 0xe000000080 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt1_p2_T_O 0x8 0x4000000080 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt1_p2_T_O 0x9 0x4000000180 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt1_p2_T_O 0xa 0x10000000080 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt1_p2_T_O 0xb 0x10000000180 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_dspt_T_O 0x0 0x520e0000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_dspt_T_O 0x1 0x720e0000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_dspt_T_O 0x2 0x5b000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_dspt_T_O 0x3 0x7b000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_dspt_T_O 0x4 0x14003000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_dspt_T_O 0x5 0x1400b000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_lnoc_T_O 0x0 0x52080000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_lnoc_T_O 0x1 0x72080000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_mnoc_T_O 0x0 0x52020000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_mnoc_T_O 0x1 0x72020000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0x0 0x52080000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0x1 0x72080000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0x2 0x59000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0x3 0x5a000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0x4 0x79000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0x5 0x7a000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0x6 0x14001000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0x7 0x14002000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0x8 0x14009000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0x9 0x1400a000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0xa 0x1800000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0xb 0x3800000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0xc 0xd800000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0xd 0xf800000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0xe 0x7000000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0xf 0x7000000100 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0x10 0x13000000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0x11 0x13000000100 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_pciet_T_O 0x0 0x40000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_pciet_T_O 0x1 0x60000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_pciet_T_O 0x2 0x8000000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_pciet_T_O 0x3 0xa000000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_rnoc_T_O 0x0 0x52040000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_rnoc_T_O 0x1 0x72040000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_service_T_O 0x0 0x52000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_service_T_O 0x1 0x72000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt0_p1_T_O 0x0 0x80000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt0_p1_T_O 0x1 0x100000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt0_p1_T_O 0x2 0x200000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt0_p1_T_O 0x3 0x400000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt0_p1_T_O 0x4 0x800000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt0_p1_T_O 0x5 0x2000000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt0_p1_T_O 0x6 0x4000000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt0_p1_T_O 0x7 0x4000000100 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt1_p1_T_O 0x0 0x80000080 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt1_p1_T_O 0x1 0x100000080 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt1_p1_T_O 0x2 0x200000080 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt1_p1_T_O 0x3 0x400000080 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt1_p1_T_O 0x4 0x800000080 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt1_p1_T_O 0x5 0x2000000080 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt1_p1_T_O 0x6 0x4000000080 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt1_p1_T_O 0x7 0x4000000180 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_npu_T_O 0x0 0x52080000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_npu_T_O 0x1 0x72080000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_npu_T_O 0x2 0x59000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_npu_T_O 0x3 0x5a000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_npu_T_O 0x4 0x79000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_npu_T_O 0x5 0x7a000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_npu_T_O 0x6 0x1800000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_npu_T_O 0x7 0x3800000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_npu_T_O 0x8 0x7000000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_npu_T_O 0x9 0x7000000100 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_npu_T_O 0xa 0x0 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_npu_T_O 0xb 0x0 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_aon_T_O 0x0 0x520c0000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_aon_T_O 0x1 0x720c0000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_aon_T_O 0x2 0x58400000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_aon_T_O 0x3 0x78400000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_aon_T_O 0x4 0x58800000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_aon_T_O 0x5 0x78800000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_aon_T_O 0x6 0x5c000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_aon_T_O 0x7 0x7c000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0x0 0x52060000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0x1 0x72060000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0x2 0x52100000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0x3 0x52200000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0x4 0x52300000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0x5 0x72100000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0x6 0x72200000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0x7 0x72300000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0x8 0x53000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0x9 0x73000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0xa 0x50000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0xb 0x70000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0xc 0x54000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0xd 0x74000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0xe 0x0 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_dspt_T_O 0x0 0x520e0000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_dspt_T_O 0x1 0x720e0000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_dspt_T_O 0x2 0x5b000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_dspt_T_O 0x3 0x7b000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_lnoc_T_O 0x0 0x52080000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_lnoc_T_O 0x1 0x72080000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x0 0x58400000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x1 0x78400000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x2 0x58800000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x3 0x78800000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x4 0x59000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x5 0x5a000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x6 0x5b000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x7 0x79000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x8 0x7a000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x9 0x7b000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mcput_d2d_T_O 0xa 0x50000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mcput_d2d_T_O 0xb 0x70000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mcput_d2d_T_O 0xc 0x40000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mcput_d2d_T_O 0xd 0x60000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mnoc_T_O 0x0 0x52020000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mnoc_T_O 0x1 0x72020000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_npu_T_O 0x0 0x52080000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_npu_T_O 0x1 0x72080000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_npu_T_O 0x2 0x59000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_npu_T_O 0x3 0x5a000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_npu_T_O 0x4 0x79000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_npu_T_O 0x5 0x7a000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_pciet_T_O 0x0 0x40000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_pciet_T_O 0x1 0x60000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_rnoc_T_O 0x0 0x52040000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_rnoc_T_O 0x1 0x72040000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_service_T_O 0x0 0x52000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_service_T_O 0x1 0x72000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0x0 0x520c0000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0x1 0x720c0000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0x2 0x58400000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0x3 0x78400000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0x4 0x14000400000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0x5 0x14008400000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0x6 0x58800000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0x7 0x78800000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0x8 0x14000800000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0x9 0x14008800000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0xa 0x5c000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0xb 0x7c000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0xc 0x14004000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0xd 0x1400c000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0xe 0x0 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0xf 0x0 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x0 0x80000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x1 0x100000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x2 0x200000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x3 0x400000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x4 0x800000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x5 0x2000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x6 0xc000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x7 0xe000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x8 0x4000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x9 0x4000000100 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0xa 0x10000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0xb 0x10000000100 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x0 0x80000080 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x1 0x100000080 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x2 0x200000080 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x3 0x400000080 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x4 0x800000080 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x5 0x2000000080 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x6 0xc000000080 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x7 0xe000000080 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x8 0x4000000080 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x9 0x4000000180 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0xa 0x10000000080 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0xb 0x10000000180 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_dspt_T_O 0x0 0x520e0000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_dspt_T_O 0x1 0x720e0000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_dspt_T_O 0x2 0x5b000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_dspt_T_O 0x3 0x7b000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_dspt_T_O 0x4 0x14003000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_dspt_T_O 0x5 0x1400b000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x0 0x58400000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x1 0x78400000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x2 0x14000400000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x3 0x14008400000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x4 0x58800000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x5 0x78800000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x6 0x14000800000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x7 0x14008800000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x8 0x59000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x9 0x5a000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0xa 0x5b000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0xb 0x79000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0xc 0x7a000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0xd 0x7b000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0xe 0x14001000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0xf 0x14002000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x10 0x14003000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x11 0x14009000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x12 0x1400a000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x13 0x1400b000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x14 0x50000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x15 0x70000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x16 0x40000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x17 0x60000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x18 0x80000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x19 0x100000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x1a 0x200000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x1b 0x400000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x1c 0x800000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x1d 0x1800000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x1e 0x3800000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x1f 0xd800000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x20 0xf800000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x21 0x2000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x22 0x7000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x23 0x7000000100 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x24 0xc000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x25 0xe000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x26 0x13000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x27 0x13000000100 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x28 0x4000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x29 0x4000000100 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x2a 0x8000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x2b 0xa000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x2c 0x10000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x2d 0x10000000100 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0x0 0x52080000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0x1 0x72080000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0x2 0x59000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0x3 0x5a000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0x4 0x79000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0x5 0x7a000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0x6 0x14001000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0x7 0x14002000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0x8 0x14009000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0x9 0x1400a000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0xa 0x1800000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0xb 0x3800000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0xc 0xd800000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0xd 0xf800000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0xe 0x7000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0xf 0x7000000100 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0x10 0x13000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0x11 0x13000000100 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_pciet_T_O 0x0 0x40000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_pciet_T_O 0x1 0x60000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_pciet_T_O 0x2 0x8000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_pciet_T_O 0x3 0xa000000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0x0 0x52060000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0x1 0x72060000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0x2 0x52100000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0x3 0x52200000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0x4 0x52300000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0x5 0x72100000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0x6 0x72200000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0x7 0x72300000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0x8 0x53000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0x9 0x73000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0xa 0x50000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0xb 0x70000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0xc 0x54000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0xd 0x74000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0xe 0x0 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_dspt_T_O 0x0 0x520e0000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_dspt_T_O 0x1 0x720e0000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_dspt_T_O 0x2 0x5b000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_dspt_T_O 0x3 0x7b000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_dspt_T_O 0x4 0x14003000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_dspt_T_O 0x5 0x1400b000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x0 0x58400000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x1 0x78400000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x2 0x14000400000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x3 0x14008400000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x4 0x58800000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x5 0x78800000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x6 0x14000800000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x7 0x14008800000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x8 0x59000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x9 0x5a000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0xa 0x5b000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0xb 0x79000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0xc 0x7a000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0xd 0x7b000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0xe 0x14001000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0xf 0x14002000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x10 0x14003000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x11 0x14009000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x12 0x1400a000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x13 0x1400b000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x14 0x50000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x15 0x70000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x16 0x40000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x17 0x60000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x18 0x80000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x19 0x100000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x1a 0x200000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x1b 0x400000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x1c 0x800000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x1d 0x1800000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x1e 0x3800000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x1f 0xd800000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x20 0xf800000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x21 0x2000000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x22 0x7000000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x23 0x7000000100 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x24 0xc000000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x25 0xe000000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x26 0x13000000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x27 0x13000000100 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x28 0x4000000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x29 0x4000000100 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x2a 0x8000000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x2b 0xa000000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x2c 0x10000000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x2d 0x10000000100 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0x0 0x52080000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0x1 0x72080000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0x2 0x59000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0x3 0x5a000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0x4 0x79000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0x5 0x7a000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0x6 0x14001000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0x7 0x14002000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0x8 0x14009000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0x9 0x1400a000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0xa 0x1800000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0xb 0x3800000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0xc 0xd800000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0xd 0xf800000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0xe 0x7000000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0xf 0x7000000100 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0x10 0x13000000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0x11 0x13000000100 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_pciet_T_O 0x0 0x40000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_pciet_T_O 0x1 0x60000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_pciet_T_O 0x2 0x8000000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_pciet_T_O 0x3 0xa000000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_aon_T_O 0x0 0x520c0000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_aon_T_O 0x1 0x720c0000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_aon_T_O 0x2 0x58400000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_aon_T_O 0x3 0x78400000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_aon_T_O 0x4 0x58800000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_aon_T_O 0x5 0x78800000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_aon_T_O 0x6 0x5c000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_aon_T_O 0x7 0x7c000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0x0 0x52060000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0x1 0x72060000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0x2 0x52100000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0x3 0x52200000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0x4 0x52300000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0x5 0x72100000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0x6 0x72200000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0x7 0x72300000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0x8 0x53000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0x9 0x73000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0xa 0x50000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0xb 0x70000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0xc 0x54000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0xd 0x74000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0xe 0x0 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0xf 0x0 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0x10 0x0 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_dspt_T_O 0x0 0x520e0000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_dspt_T_O 0x1 0x720e0000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_dspt_T_O 0x2 0x5b000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_dspt_T_O 0x3 0x7b000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_lnoc_T_O 0x0 0x52080000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_lnoc_T_O 0x1 0x72080000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x0 0x58400000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x1 0x78400000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x2 0x58800000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x3 0x78800000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x4 0x59000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x5 0x5a000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x6 0x5b000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x7 0x79000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x8 0x7a000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x9 0x7b000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mcput_d2d_T_O 0xa 0x50000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mcput_d2d_T_O 0xb 0x70000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mcput_d2d_T_O 0xc 0x40000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mcput_d2d_T_O 0xd 0x60000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mnoc_T_O 0x0 0x52020000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mnoc_T_O 0x1 0x72020000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_pciet_T_O 0x0 0x40000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_pciet_T_O 0x1 0x60000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_rnoc_T_O 0x0 0x52040000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_rnoc_T_O 0x1 0x72040000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_service_T_O 0x0 0x52000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_service_T_O 0x1 0x72000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0x0 0x520c0000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0x1 0x720c0000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0x2 0x58400000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0x3 0x78400000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0x4 0x14000400000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0x5 0x14008400000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0x6 0x58800000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0x7 0x78800000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0x8 0x14000800000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0x9 0x14008800000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0xa 0x5c000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0xb 0x7c000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0xc 0x14004000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0xd 0x1400c000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0xe 0x0 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0xf 0x0 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x0 0x80000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x1 0x100000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x2 0x200000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x3 0x400000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x4 0x800000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x5 0x2000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x6 0xc000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x7 0xe000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x8 0x4000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x9 0x4000000100 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0xa 0x10000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0xb 0x10000000100 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x0 0x80000080 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x1 0x100000080 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x2 0x200000080 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x3 0x400000080 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x4 0x800000080 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x5 0x2000000080 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x6 0xc000000080 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x7 0xe000000080 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x8 0x4000000080 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x9 0x4000000180 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0xa 0x10000000080 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0xb 0x10000000180 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_dspt_T_O 0x0 0x520e0000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_dspt_T_O 0x1 0x720e0000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_dspt_T_O 0x2 0x5b000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_dspt_T_O 0x3 0x7b000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_dspt_T_O 0x4 0x14003000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_dspt_T_O 0x5 0x1400b000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x0 0x58400000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x1 0x78400000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x2 0x14000400000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x3 0x14008400000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x4 0x58800000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x5 0x78800000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x6 0x14000800000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x7 0x14008800000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x8 0x59000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x9 0x5a000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0xa 0x5b000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0xb 0x79000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0xc 0x7a000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0xd 0x7b000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0xe 0x14001000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0xf 0x14002000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x10 0x14003000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x11 0x14009000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x12 0x1400a000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x13 0x1400b000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x14 0x50000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x15 0x70000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x16 0x40000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x17 0x60000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x18 0x80000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x19 0x100000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x1a 0x200000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x1b 0x400000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x1c 0x800000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x1d 0x1800000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x1e 0x3800000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x1f 0xd800000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x20 0xf800000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x21 0x2000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x22 0x7000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x23 0x7000000100 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x24 0xc000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x25 0xe000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x26 0x13000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x27 0x13000000100 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x28 0x4000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x29 0x4000000100 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x2a 0x8000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x2b 0xa000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x2c 0x10000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x2d 0x10000000100 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_pciet_T_O 0x0 0x40000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_pciet_T_O 0x1 0x60000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_pciet_T_O 0x2 0x8000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_pciet_T_O 0x3 0xa000000000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0x0 0x52060000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0x1 0x72060000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0x2 0x52100000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0x3 0x52200000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0x4 0x52300000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0x5 0x72100000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0x6 0x72200000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0x7 0x72300000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0x8 0x53000000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0x9 0x73000000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0xa 0x50000000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0xb 0x70000000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0xc 0x54000000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0xd 0x74000000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0xe 0x0 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0xf 0x0 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0x10 0x0 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_lnoc_T_O 0x0 0x52080000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_lnoc_T_O 0x1 0x72080000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_mnoc_T_O 0x0 0x52020000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_mnoc_T_O 0x1 0x72020000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_rnoc_T_O 0x0 0x52040000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_rnoc_T_O 0x1 0x72040000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_service_T_O 0x0 0x52000000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_service_T_O 0x1 0x72000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0x0 0x52080000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0x1 0x72080000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0x2 0x59000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0x3 0x5a000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0x4 0x79000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0x5 0x7a000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0x6 0x14001000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0x7 0x14002000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0x8 0x14009000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0x9 0x1400a000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0xa 0x1800000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0xb 0x3800000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0xc 0xd800000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0xd 0xf800000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0xe 0x7000000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0xf 0x7000000100 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0x10 0x13000000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0x11 0x13000000100 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0x12 0x0 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0x13 0x0 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_aon_T_O 0x0 0x520c0000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_aon_T_O 0x1 0x720c0000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_aon_T_O 0x2 0x58400000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_aon_T_O 0x3 0x78400000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_aon_T_O 0x4 0x14000400000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_aon_T_O 0x5 0x14008400000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_aon_T_O 0x6 0x58800000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_aon_T_O 0x7 0x78800000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_aon_T_O 0x8 0x14000800000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_aon_T_O 0x9 0x14008800000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_aon_T_O 0xa 0x5c000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_aon_T_O 0xb 0x7c000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_aon_T_O 0xc 0x14004000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_aon_T_O 0xd 0x1400c000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0x0 0x52060000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0x1 0x72060000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0x2 0x52100000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0x3 0x52200000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0x4 0x52300000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0x5 0x72100000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0x6 0x72200000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0x7 0x72300000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0x8 0x53000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0x9 0x73000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0xa 0x50000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0xb 0x70000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0xc 0x54000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0xd 0x74000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0xe 0x0 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O 0x0 0x80000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O 0x1 0x100000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O 0x2 0x200000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O 0x3 0x400000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O 0x4 0x800000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O 0x5 0x2000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O 0x6 0xc000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O 0x7 0xe000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O 0x8 0x4000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O 0x9 0x4000000100 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O 0xa 0x10000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O 0xb 0x10000000100 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O 0x0 0x80000080 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O 0x1 0x100000080 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O 0x2 0x200000080 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O 0x3 0x400000080 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O 0x4 0x800000080 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O 0x5 0x2000000080 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O 0x6 0xc000000080 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O 0x7 0xe000000080 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O 0x8 0x4000000080 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O 0x9 0x4000000180 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O 0xa 0x10000000080 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O 0xb 0x10000000180 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_dspt_T_O 0x0 0x520e0000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_dspt_T_O 0x1 0x720e0000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_dspt_T_O 0x2 0x5b000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_dspt_T_O 0x3 0x7b000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_dspt_T_O 0x4 0x14003000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_dspt_T_O 0x5 0x1400b000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_lnoc_T_O 0x0 0x52080000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_lnoc_T_O 0x1 0x72080000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x0 0x58400000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x1 0x78400000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x2 0x14000400000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x3 0x14008400000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x4 0x58800000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x5 0x78800000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x6 0x14000800000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x7 0x14008800000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x8 0x59000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x9 0x5a000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0xa 0x5b000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0xb 0x79000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0xc 0x7a000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0xd 0x7b000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0xe 0x14001000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0xf 0x14002000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x10 0x14003000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x11 0x14009000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x12 0x1400a000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x13 0x1400b000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x14 0x50000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x15 0x70000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x16 0x40000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x17 0x60000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x18 0x80000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x19 0x100000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x1a 0x200000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x1b 0x400000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x1c 0x800000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x1d 0x1800000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x1e 0x3800000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x1f 0xd800000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x20 0xf800000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x21 0x2000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x22 0x7000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x23 0x7000000100 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x24 0xc000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x25 0xe000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x26 0x13000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x27 0x13000000100 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x28 0x4000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x29 0x4000000100 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x2a 0x8000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x2b 0xa000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x2c 0x10000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x2d 0x10000000100 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mnoc_T_O 0x0 0x52020000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mnoc_T_O 0x1 0x72020000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0x0 0x52080000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0x1 0x72080000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0x2 0x59000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0x3 0x5a000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0x4 0x79000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0x5 0x7a000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0x6 0x14001000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0x7 0x14002000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0x8 0x14009000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0x9 0x1400a000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0xa 0x1800000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0xb 0x3800000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0xc 0xd800000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0xd 0xf800000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0xe 0x7000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0xf 0x7000000100 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0x10 0x13000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0x11 0x13000000100 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_rnoc_T_O 0x0 0x52040000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_rnoc_T_O 0x1 0x72040000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_service_T_O 0x0 0x52000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_service_T_O 0x1 0x72000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt0_p2_T_O 0x0 0x80000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt0_p2_T_O 0x1 0x100000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt0_p2_T_O 0x2 0x200000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt0_p2_T_O 0x3 0x400000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt0_p2_T_O 0x4 0x800000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt0_p2_T_O 0x5 0x2000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt0_p2_T_O 0x6 0xc000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt0_p2_T_O 0x7 0xe000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt0_p2_T_O 0x8 0x4000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt0_p2_T_O 0x9 0x4000000100 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt0_p2_T_O 0xa 0x10000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt0_p2_T_O 0xb 0x10000000100 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt1_p2_T_O 0x0 0x80000080 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt1_p2_T_O 0x1 0x100000080 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt1_p2_T_O 0x2 0x200000080 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt1_p2_T_O 0x3 0x400000080 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt1_p2_T_O 0x4 0x800000080 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt1_p2_T_O 0x5 0x2000000080 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt1_p2_T_O 0x6 0xc000000080 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt1_p2_T_O 0x7 0xe000000080 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt1_p2_T_O 0x8 0x4000000080 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt1_p2_T_O 0x9 0x4000000180 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt1_p2_T_O 0xa 0x10000000080 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt1_p2_T_O 0xb 0x10000000180 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_dspt_T_O 0x0 0x520e0000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_dspt_T_O 0x1 0x720e0000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_dspt_T_O 0x2 0x5b000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_dspt_T_O 0x3 0x7b000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_dspt_T_O 0x4 0x14003000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_dspt_T_O 0x5 0x1400b000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x0 0x58400000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x1 0x78400000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x2 0x14000400000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x3 0x14008400000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x4 0x58800000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x5 0x78800000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x6 0x14000800000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x7 0x14008800000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x8 0x59000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x9 0x5a000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0xa 0x5b000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0xb 0x79000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0xc 0x7a000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0xd 0x7b000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0xe 0x14001000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0xf 0x14002000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x10 0x14003000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x11 0x14009000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x12 0x1400a000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x13 0x1400b000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x14 0x50000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x15 0x70000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x16 0x40000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x17 0x60000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x18 0x80000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x19 0x100000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x1a 0x200000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x1b 0x400000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x1c 0x800000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x1d 0x1800000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x1e 0x3800000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x1f 0xd800000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x20 0xf800000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x21 0x2000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x22 0x7000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x23 0x7000000100 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x24 0xc000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x25 0xe000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x26 0x13000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x27 0x13000000100 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x28 0x4000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x29 0x4000000100 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x2a 0x8000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x2b 0xa000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x2c 0x10000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x2d 0x10000000100 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0x0 0x52080000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0x1 0x72080000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0x2 0x59000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0x3 0x5a000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0x4 0x79000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0x5 0x7a000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0x6 0x14001000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0x7 0x14002000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0x8 0x14009000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0x9 0x1400a000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0xa 0x1800000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0xb 0x3800000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0xc 0xd800000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0xd 0xf800000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0xe 0x7000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0xf 0x7000000100 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0x10 0x13000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0x11 0x13000000100 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0x12 0x0 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0x13 0x0 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_pciet_T_O 0x0 0x40000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_pciet_T_O 0x1 0x60000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_pciet_T_O 0x2 0x8000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_pciet_T_O 0x3 0xa000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt0_p2_T_O 0x0 0x80000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt0_p2_T_O 0x1 0x100000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt0_p2_T_O 0x2 0x200000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt0_p2_T_O 0x3 0x400000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt0_p2_T_O 0x4 0x800000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt0_p2_T_O 0x5 0x2000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt0_p2_T_O 0x6 0xc000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt0_p2_T_O 0x7 0xe000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt0_p2_T_O 0x8 0x4000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt0_p2_T_O 0x9 0x4000000100 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt0_p2_T_O 0xa 0x10000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt0_p2_T_O 0xb 0x10000000100 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt1_p2_T_O 0x0 0x80000080 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt1_p2_T_O 0x1 0x100000080 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt1_p2_T_O 0x2 0x200000080 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt1_p2_T_O 0x3 0x400000080 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt1_p2_T_O 0x4 0x800000080 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt1_p2_T_O 0x5 0x2000000080 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt1_p2_T_O 0x6 0xc000000080 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt1_p2_T_O 0x7 0xe000000080 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt1_p2_T_O 0x8 0x4000000080 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt1_p2_T_O 0x9 0x4000000180 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt1_p2_T_O 0xa 0x10000000080 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt1_p2_T_O 0xb 0x10000000180 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_dspt_T_O 0x0 0x520e0000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_dspt_T_O 0x1 0x720e0000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_dspt_T_O 0x2 0x5b000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_dspt_T_O 0x3 0x7b000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_dspt_T_O 0x4 0x14003000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_dspt_T_O 0x5 0x1400b000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x0 0x58400000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x1 0x78400000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x2 0x14000400000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x3 0x14008400000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x4 0x58800000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x5 0x78800000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x6 0x14000800000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x7 0x14008800000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x8 0x59000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x9 0x5a000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0xa 0x5b000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0xb 0x79000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0xc 0x7a000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0xd 0x7b000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0xe 0x14001000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0xf 0x14002000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x10 0x14003000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x11 0x14009000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x12 0x1400a000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x13 0x1400b000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x14 0x50000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x15 0x70000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x16 0x40000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x17 0x60000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x18 0x80000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x19 0x100000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x1a 0x200000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x1b 0x400000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x1c 0x800000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x1d 0x1800000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x1e 0x3800000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x1f 0xd800000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x20 0xf800000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x21 0x2000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x22 0x7000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x23 0x7000000100 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x24 0xc000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x25 0xe000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x26 0x13000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x27 0x13000000100 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x28 0x4000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x29 0x4000000100 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x2a 0x8000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x2b 0xa000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x2c 0x10000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x2d 0x10000000100 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0x0 0x52080000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0x1 0x72080000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0x2 0x59000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0x3 0x5a000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0x4 0x79000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0x5 0x7a000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0x6 0x14001000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0x7 0x14002000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0x8 0x14009000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0x9 0x1400a000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0xa 0x1800000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0xb 0x3800000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0xc 0xd800000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0xd 0xf800000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0xe 0x7000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0xf 0x7000000100 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0x10 0x13000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0x11 0x13000000100 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0x12 0x0 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0x13 0x0 >;
+ };
+ };
+
+ ErrorLogger4 {
+ compatible = "eswin,win2030,register";
+ offset,length = < 0x24 32>;
+ description = "Register 4 to log errors";
+ addr_msb {
+ compatible = "eswin,win2030,bitfield";
+ description = "Stores NTTP packet header field Addr (MSBs) of the logged error";
+ offset,length = < 0 9 >;
+ };
+ };
+
+ ErrorLogger5 {
+ compatible = "eswin,win2030,register";
+ offset,length = < 0x28 32>;
+ description = "Register 5 to log errors";
+
+ User_flag {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0x0 18 >;
+ lut =
+ "Cache_0",
+ "Cache_1",
+ "Cache_2",
+ "Cache_3",
+ "Prot_0 ",
+ "Prot_1 ",
+ "Prot_2 ",
+ "User_0 ",
+ "User_1 ",
+ "User_2 ",
+ "User_3 ",
+ "User_4 ",
+ "User_5 ",
+ "User_6 ",
+ "qos0",
+ "qos1",
+ "qos2",
+ "qos3";
+ };
+ };
+};
+
+d0_media_noc:d0_media_noc@52021400 {
+ compatible = "eswin,win2030-noc";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ reg = <0 0x52021400 0 0x4000>;
+ interrupts = <454>;
+ interrupt-names = "error";
+ interrupt-parent = <&plic0>;
+ errlogger,idx = <0 1 3 4 5>;
+ eswin,qos-configs = "GPU", "TBU2", "VC";
+ eswin,GPU-qos-base = <0x52021480>;
+ eswin,GPU-qos-settings = <
+ 0x8 0x4 /* prio */
+ 0xC 0x2 /* mode */
+ 0x10 0x1E0 /* bandwidth*/
+ 0x14 0x1 /* saturation*/
+ 0x18 0x1>; /* QoSEn */
+
+ eswin,TBU2-qos-base = <0x52021500>;
+ eswin,TBU2-qos-settings = <
+ 0x8 0x4 /* prio */
+ 0xC 0x2 /* mode */
+ 0x10 0x18 /* bandwidth */
+ 0x14 0x10 /* saturation */
+ 0x18 0x1>; /* QoSEn */
+
+ eswin,VC-qos-base = <0x52021580>;
+ eswin,VC-qos-settings = <
+ 0x8 0x4 /* prio */
+ 0xC 0x2 /* mode */
+ 0x10 0x18 /* bandwidth */
+ 0x14 0x10 /* saturation */
+ 0x18 0x1>; /* QoSEn */
+#ifdef PLATFORM_HAPS
+ clock,rate = <5000000>; /*haps ddr controller clk*/
+#endif
+ sideband_manager@52022000 {
+ compatible = "eswin,win2xxx-noc-sideband-manager";
+ reg = <0 0x52022000 0 0x10>;
+ SenseIn0 =
+ <SBM_MNOC_GPU OFFSET0>,
+ <SBM_MNOC_TBU2 OFFSET1>,
+ <SBM_MNOC_VC OFFSET2>,
+ <SBM_MNOC_DDRT0_P3 OFFSET3>,
+ <SBM_MNOC_DDRT1_P3 OFFSET4>;
+ bf-name =
+ "SBM_MNOC_GPU",
+ "SBM_MNOC_TBU2",
+ "SBM_MNOC_VC",
+ "SBM_MNOC_DDRT0_P3",
+ "SBM_MNOC_DDRT1_P3";
+ };
+
+ mnoc_packet_ddr0_p3_req_probe@52020000 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0 0x52020000 0 0x4000>;
+ clocks = <&d0_clock WIN2030_CLK_DDRT0_P3_ACLK>;
+ clock-names = "clk";
+ interrupts = <458>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic0>;
+ filter,nr = <1>;
+ counter,nr = <2>;
+ portsel = "ddr0_p3_req";
+ };
+ mnoc_packet_ddr1_p3_req_probe@52020800 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0 0x52020800 0 0x4000>;
+ clocks =<&d0_clock WIN2030_CLK_DDRT1_P3_ACLK>;
+ clock-names = "clk";
+ interrupts = <456>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic0>;
+ filter,nr = <1>;
+ counter,nr = <2>;
+ portsel = "ddr1_p3_req";
+ };
+ mnoc_trans_probe@52021000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ compatible = "eswin,win2xxx-noc-trans-probe";
+ reg = <0 0x52021000 0 0x4000>;
+ clocks =<&d0_clock WIN2030_CLK_NOC_NSP_CLK>;
+ clock-names = "clk";
+ interrupts = <453>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic0>;
+ filter,nr = <3>;
+ counter,nr = <12>;
+ profiler,nr = <1>;
+ portsel = "gpu", "tbu2", "vc";
+ mnoc_trans_gpu_filter@52021600 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x52021600 0 0x80>;
+ };
+ mnoc_trans_tbu2_filter@52021680 { /*hsp subsys*/
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x52021680 0 0x80>;
+ };
+ mnoc_trans_vc_filter@52021700 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x52021700 0 0x80>;
+ };
+ mnoc_trans_profiler@52021780 {
+ compatible = "eswin,win2xxx-noc-trans-profiler";
+ reg = <0 0x52021780 0 0x80>;
+ };
+ };
+ ErrorLogger0 {
+ compatible = "eswin,win2030,register";
+ offset,length = < 0x14 32 >;
+ description = "Register 0 to log errors";
+ lock {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0 1 >;
+ lut = "Not Locked", "Locked";
+ };
+ OpCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 1 4 >;
+ lut = "RD: data read with incrementing address",
+ "RDW: data read with wrapping address",
+ "RDL: allocates monitor in the Target with incrementing address",
+ "RDX: exclusive read with incrementing address",
+ "WR: data write with incrementing address",
+ "WRW: data write with wrapping address",
+ "WRC: conditional write if matching monitor in Target is found",
+ "RSV: reserved",
+ "PRE: preamble packet of linked sequence (locked sequence)",
+ "URG: urgency packet used for QoS (status must be REQ)";
+ };
+ ErrCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 8 3 >;
+ lut = "SLV (error source: Target): error detected by the Slave without any information or no Error",
+ "DEC (error source: Initiator NIU): decode error",
+ "UNS (error source: Target NIU): unsupported access type",
+ "DISC (error source: Power Disconnect): disconnected Target or NoC domain",
+ "SEC (error source: Initiator NIU or Firewall): security error",
+ "HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator",
+ "TMO (error source: Target NIU): time-out",
+ "RSV: reserved";
+
+ };
+ Len1 {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 16 12 >;
+ };
+ Format {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 31 1 >;
+ lut = "NTTP v3.0 (Invalid)", "NTTP v3.5 (Ok)";
+ };
+ };
+
+ ErrorLogger1 {
+ compatible = "eswin,win2030,register", "eswin,win2030,noc,filter,routeid";
+ offset,length = < 0x18 32>;
+ description = "Register 1 to log errors";
+ InitFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 14 2 >;
+ lut =
+ "gpu_mnoc/I/0",
+ "snoc_mnoc/I/0",
+ "tbu2_mnoc/I/0",
+ "vc_mnoc/I/0";
+ };
+
+ TargetFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 12 2 >;
+ lut =
+ "mnoc_ddrt0_p3/T/0",
+ "mnoc_ddrt1_p3/T/0",
+ "mnoc_service/T/0",
+ "mnoc_snoc/T/0";
+ };
+
+ TargetSubRange {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 9 3 >;
+ };
+
+ SeqId {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0 9 >;
+ };
+ };
+
+ ErrorLogger3 {
+ /* This register does not really include a bitfield or its bitfield is 32 bits and it provides an offset address */
+ /* To calculate the absolute address, you must use the initflow:targetflow:subrange from ErrorLogger1 register */
+ /* And use it as an index in the aperture table. Then you must add the value of this register to the value given */
+ /* by the table to get the absolute address. */
+ compatible = "eswin,win2030,register";
+ offset,length = <0x20 32>;
+ description = "Register 3 to log errors";
+ aperture-link = <1>; /* link to ErrorLogger whose information are required to calculate real absolute address */
+ msb-link = <4>; /*indicate which ErrorLogger contains the msb addrs, -1 means no*/
+ AbsoluteAddress {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 9 7 >; /* bitfield initflow:targeflow:subrange from aperture-link register */
+ aperture-size= < 55 >; /* Number of line in the aperture table below */
+ aperture-idx,aperture-base = /* Aperture_idx is concatenation of initflow:targetflow:subrange bitfield from ErrorLogger1 */
+ /bits/ 64 <0x0 0x0 0x0 0x80000000 >,
+ /bits/ 64 <0x0 0x0 0x1 0x100000000 >,
+ /bits/ 64 <0x0 0x0 0x2 0x200000000 >,
+ /bits/ 64 <0x0 0x0 0x3 0x400000000 >,
+ /bits/ 64 <0x0 0x0 0x4 0x800000000 >,
+ /bits/ 64 <0x0 0x0 0x5 0x2000000000 >,
+ /bits/ 64 <0x0 0x0 0x6 0x4000000000 >,
+ /bits/ 64 <0x0 0x0 0x7 0x4000000100 >,
+ /bits/ 64 <0x0 0x1 0x0 0x80000080 >,
+ /bits/ 64 <0x0 0x1 0x1 0x100000080 >,
+ /bits/ 64 <0x0 0x1 0x2 0x200000080 >,
+ /bits/ 64 <0x0 0x1 0x3 0x400000080 >,
+ /bits/ 64 <0x0 0x1 0x4 0x800000080 >,
+ /bits/ 64 <0x0 0x1 0x5 0x2000000080 >,
+ /bits/ 64 <0x0 0x1 0x6 0x4000000080 >,
+ /bits/ 64 <0x0 0x1 0x7 0x4000000180 >,
+ /bits/ 64 <0x0 0x3 0x0 0x0 >,
+ /bits/ 64 <0x1 0x2 0x0 0x52020000 >,
+ /bits/ 64 <0x1 0x2 0x1 0x72020000 >,
+ /bits/ 64 <0x1 0x2 0x2 0x0 >,
+ /bits/ 64 <0x1 0x2 0x3 0x0 >,
+ /bits/ 64 <0x2 0x0 0x0 0x80000000 >,
+ /bits/ 64 <0x2 0x0 0x1 0x100000000 >,
+ /bits/ 64 <0x2 0x0 0x2 0x200000000 >,
+ /bits/ 64 <0x2 0x0 0x3 0x400000000 >,
+ /bits/ 64 <0x2 0x0 0x4 0x800000000 >,
+ /bits/ 64 <0x2 0x0 0x5 0x2000000000 >,
+ /bits/ 64 <0x2 0x0 0x6 0x4000000000 >,
+ /bits/ 64 <0x2 0x0 0x7 0x4000000100 >,
+ /bits/ 64 <0x2 0x1 0x0 0x80000080 >,
+ /bits/ 64 <0x2 0x1 0x1 0x100000080 >,
+ /bits/ 64 <0x2 0x1 0x2 0x200000080 >,
+ /bits/ 64 <0x2 0x1 0x3 0x400000080 >,
+ /bits/ 64 <0x2 0x1 0x4 0x800000080 >,
+ /bits/ 64 <0x2 0x1 0x5 0x2000000080 >,
+ /bits/ 64 <0x2 0x1 0x6 0x4000000080 >,
+ /bits/ 64 <0x2 0x1 0x7 0x4000000180 >,
+ /bits/ 64 <0x2 0x3 0x0 0x0 >,
+ /bits/ 64 <0x3 0x0 0x0 0x80000000 >,
+ /bits/ 64 <0x3 0x0 0x1 0x100000000 >,
+ /bits/ 64 <0x3 0x0 0x2 0x200000000 >,
+ /bits/ 64 <0x3 0x0 0x3 0x400000000 >,
+ /bits/ 64 <0x3 0x0 0x4 0x800000000 >,
+ /bits/ 64 <0x3 0x0 0x5 0x2000000000 >,
+ /bits/ 64 <0x3 0x0 0x6 0x4000000000 >,
+ /bits/ 64 <0x3 0x0 0x7 0x4000000100 >,
+ /bits/ 64 <0x3 0x1 0x0 0x80000080 >,
+ /bits/ 64 <0x3 0x1 0x1 0x100000080 >,
+ /bits/ 64 <0x3 0x1 0x2 0x200000080 >,
+ /bits/ 64 <0x3 0x1 0x3 0x400000080 >,
+ /bits/ 64 <0x3 0x1 0x4 0x800000080 >,
+ /bits/ 64 <0x3 0x1 0x5 0x2000000080 >,
+ /bits/ 64 <0x3 0x1 0x6 0x4000000080 >,
+ /bits/ 64 <0x3 0x1 0x7 0x4000000180 >,
+ /bits/ 64 <0x3 0x3 0x0 0x0 >;
+ };
+ };
+
+ ErrorLogger4 {
+ compatible = "eswin,win2030,register";
+ offset,length = < 0x24 32>;
+ description = "Register 4 to log errors";
+ addr_msb {
+ compatible = "eswin,win2030,bitfield";
+ description = "Stores NTTP packet header field Addr (MSBs) of the logged error";
+ offset,length = < 0 9 >;
+ };
+ };
+
+ ErrorLogger5 {
+ compatible = "eswin,win2030,register";
+ offset,length = < 0x28 32 >;
+ description = "Register 5 to log errors";
+
+ User_flag {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0x0 18 >;
+ lut =
+ "Cache_0",
+ "Cache_1",
+ "Cache_2",
+ "Cache_3",
+ "Prot_0 ",
+ "Prot_1 ",
+ "Prot_2 ",
+ "User_0 ",
+ "User_1 ",
+ "User_2 ",
+ "User_3 ",
+ "User_4 ",
+ "User_5 ",
+ "User_6 ",
+ "qos0",
+ "qos1",
+ "qos2",
+ "qos3";
+ };
+ };
+};
+
+d0_realtime_noc:d0_realtime_noc@52041400 {
+ compatible = "eswin,win2030-noc";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ reg = <0 0x52041400 0 0x4000>;
+ interrupts = <448>;
+ interrupt-names = "error";
+ interrupt-parent = <&plic0>;
+ errlogger,idx = <0 1 3 4 5>;
+ eswin,qos-configs = "TBU0", "VO";
+ eswin,TBU0-qos-base = <0x52041480>;
+ eswin,TBU0-qos-settings = <
+ 0x8 0x4 /* prio */
+ 0xC 0x2 /* mode */
+ 0x10 0x1E0 /* bandwidth */
+ 0x14 0x1 /* saturation */
+ 0x18 0x1>; /* QoSEn */
+
+ eswin,VO-qos-base = <0x52041500>;
+ eswin,VO-qos-settings = <
+ 0x8 0x4 /* prio */
+ 0xC 0x2 /* mode */
+ 0x10 0x18 /* bandwidth */
+ 0x14 0x10 /* saturation */
+ 0x18 0x1>; /* QoSEn */
+#ifdef PLATFORM_HAPS
+ clock,rate = <5000000>; /*haps ddr controller clk*/
+#endif
+ sideband_manager@52042000 {
+ compatible = "eswin,win2xxx-noc-sideband-manager";
+ reg = <0 0x52042000 0 0x10>;
+ SenseIn0 =
+ <SBM_RNOC_TBU0 OFFSET0>,
+ <SBM_RNOC_VO OFFSET1>,
+ <SBM_RNOC_DDRT0_P4 OFFSET2>,
+ <SBM_RNOC_DDRT1_P4 OFFSET3>;
+ bf-name =
+ "SBM_RNOC_TBU0",
+ "SBM_RNOC_VO",
+ "SBM_RNOC_DDRT0_P4",
+ "SBM_RNOC_DDRT1_P4";
+ };
+
+ rnoc_packet_ddr0_p4_req_probe@52040000 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0 0x52040000 0 0x4000>;
+ clocks = <&d0_clock WIN2030_CLK_DDRT0_P4_ACLK>;
+ clock-names = "clk";
+ interrupts = <452>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic0>;
+ filter,nr = <1>;
+ counter,nr = <2>;
+ portsel = "ddr0_p4_req";
+ };
+ rnoc_packet_ddr1_p4_req_probe@52040800 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0 0x52040800 0 0x4000>;
+ clocks =<&d0_clock WIN2030_CLK_DDRT1_P4_ACLK>;
+ clock-names = "clk";
+ interrupts = <450>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic0>;
+ filter,nr = <1>;
+ counter,nr = <2>;
+ portsel = "ddr1_p4_req";
+ };
+ rnoc_trans_probe@52041000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ compatible = "eswin,win2xxx-noc-trans-probe";
+ reg = <0 0x52041000 0 0x4000>;
+ clocks =<&d0_clock WIN2030_CLK_NOC_NSP_CLK>;
+ clock-names = "clk";
+ interrupts = <447>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic0>;
+ filter,nr = <2>;
+ counter,nr = <8>;
+ profiler,nr = <1>;
+ portsel = "tbu0", "vo";
+ rnoc_trans_tbu0_filter@52041580 { /*vi subsys*/
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x52041580 0 0x80>;
+ };
+ rnoc_trans_vo_filter@52041600 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x52041600 0 0x80>;
+ };
+ rnoc_trans_profiler@52041680 {
+ compatible = "eswin,win2xxx-noc-trans-profiler";
+ reg = <0 0x52041680 0 0x80>;
+ };
+ };
+ ErrorLogger0 {
+ compatible = "eswin,win2030,register";
+ offset,length = < 0x14 32 >;
+ description = "Register 0 to log errors";
+ lock {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0 1 >;
+ lut = "Not Locked", "Locked";
+ };
+ OpCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 1 4 >;
+ lut = "RD: data read with incrementing address",
+ "RDW: data read with wrapping address",
+ "RDL: allocates monitor in the Target with incrementing address",
+ "RDX: exclusive read with incrementing address",
+ "WR: data write with incrementing address",
+ "WRW: data write with wrapping address",
+ "WRC: conditional write if matching monitor in Target is found",
+ "RSV: reserved",
+ "PRE: preamble packet of linked sequence (locked sequence)",
+ "URG: urgency packet used for QoS (status must be REQ)";
+ };
+ ErrCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 8 3 >;
+ lut = "SLV (error source: Target): error detected by the Slave without any information or no Error",
+ "DEC (error source: Initiator NIU): decode error",
+ "UNS (error source: Target NIU): unsupported access type",
+ "DISC (error source: Power Disconnect): disconnected Target or NoC domain",
+ "SEC (error source: Initiator NIU or Firewall): security error",
+ "HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator",
+ "TMO (error source: Target NIU): time-out",
+ "RSV: reserved";
+
+ };
+ Len1 {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 16 12 >;
+ };
+ Format {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 31 1 >;
+ lut = "NTTP v3.0 (Invalid)", "NTTP v3.5 (Ok)";
+ };
+ };
+
+ ErrorLogger1 {
+ compatible = "eswin,win2030,register", "eswin,win2030,noc,filter,routeid";
+ offset,length = < 0x18 32>;
+ description = "Register 1 to log errors";
+ InitFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 14 2 >;
+ lut =
+ "snoc_rnoc/I/0",
+ "tbu0_rnoc/I/0",
+ "vo_rnoc/I/0",
+ "RESERVED0";
+ };
+
+ TargetFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 12 2 >;
+ lut =
+ "rnoc_ddrt0_p4/T/0",
+ "rnoc_ddrt1_p4/T/0",
+ "rnoc_service/T/0",
+ "rnoc_snoc/T/0";
+ };
+
+ TargetSubRange {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 9 3 >;
+ };
+
+ SeqId {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0 9 >;
+ };
+ };
+
+ ErrorLogger3 {
+ /* This register does not really include a bitfield or its bitfield is 32 bits and it provides an offset address */
+ /* To calculate the absolute address, you must use the initflow:targetflow:subrange from ErrorLogger1 register */
+ /* And use it as an index in the aperture table. Then you must add the value of this register to the value given */
+ /* by the table to get the absolute address. */
+ compatible = "eswin,win2030,register";
+ offset,length = <0x20 32>;
+ description = "Register 3 to log errors";
+ aperture-link = <1>; /* link to ErrorLogger whose information are required to calculate real absolute address */
+ msb-link = <4>; /*indicate which ErrorLogger contains the msb addrs, -1 means no*/
+ AbsoluteAddress {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 9 7 >; /* bitfield initflow:targeflow:subrange from aperture-link register */
+ aperture-size= < 40 >; /* Number of line in the aperture table below */
+ aperture-idx,aperture-base = /* Aperture_idx is concatenation of initflow:targetflow:subrange bitfield from ErrorLogger1 */
+ /bits/ 64 <0x0 0x2 0x0 0x52040000 >,
+ /bits/ 64 <0x0 0x2 0x1 0x72040000 >,
+ /bits/ 64 <0x0 0x2 0x2 0x0 >,
+ /bits/ 64 <0x0 0x2 0x3 0x0 >,
+ /bits/ 64 <0x1 0x0 0x0 0x80000000 >,
+ /bits/ 64 <0x1 0x0 0x1 0x100000000 >,
+ /bits/ 64 <0x1 0x0 0x2 0x200000000 >,
+ /bits/ 64 <0x1 0x0 0x3 0x400000000 >,
+ /bits/ 64 <0x1 0x0 0x4 0x800000000 >,
+ /bits/ 64 <0x1 0x0 0x5 0x2000000000 >,
+ /bits/ 64 <0x1 0x1 0x0 0x80000080 >,
+ /bits/ 64 <0x1 0x1 0x1 0x100000080 >,
+ /bits/ 64 <0x1 0x1 0x2 0x200000080 >,
+ /bits/ 64 <0x1 0x1 0x3 0x400000080 >,
+ /bits/ 64 <0x1 0x1 0x4 0x800000080 >,
+ /bits/ 64 <0x1 0x1 0x5 0x2000000080 >,
+ /bits/ 64 <0x1 0x3 0x0 0x59000000 >,
+ /bits/ 64 <0x1 0x3 0x1 0x79000000 >,
+ /bits/ 64 <0x1 0x3 0x2 0x14001000000 >,
+ /bits/ 64 <0x1 0x3 0x3 0x14009000000 >,
+ /bits/ 64 <0x1 0x3 0x4 0x0 >,
+ /bits/ 64 <0x1 0x3 0x5 0x0 >,
+ /bits/ 64 <0x2 0x0 0x0 0x80000000 >,
+ /bits/ 64 <0x2 0x0 0x1 0x100000000 >,
+ /bits/ 64 <0x2 0x0 0x2 0x200000000 >,
+ /bits/ 64 <0x2 0x0 0x3 0x400000000 >,
+ /bits/ 64 <0x2 0x0 0x4 0x800000000 >,
+ /bits/ 64 <0x2 0x0 0x5 0x2000000000 >,
+ /bits/ 64 <0x2 0x1 0x0 0x80000080 >,
+ /bits/ 64 <0x2 0x1 0x1 0x100000080 >,
+ /bits/ 64 <0x2 0x1 0x2 0x200000080 >,
+ /bits/ 64 <0x2 0x1 0x3 0x400000080 >,
+ /bits/ 64 <0x2 0x1 0x4 0x800000080 >,
+ /bits/ 64 <0x2 0x1 0x5 0x2000000080 >,
+ /bits/ 64 <0x2 0x3 0x0 0x59000000 >,
+ /bits/ 64 <0x2 0x3 0x1 0x79000000 >,
+ /bits/ 64 <0x2 0x3 0x2 0x14001000000 >,
+ /bits/ 64 <0x2 0x3 0x3 0x14009000000 >,
+ /bits/ 64 <0x2 0x3 0x4 0x0 >,
+ /bits/ 64 <0x2 0x3 0x5 0x0 >;
+ };
+ };
+
+ ErrorLogger4 {
+ compatible = "eswin,win2030,register";
+ offset,length = < 0x24 32>;
+ description = "Register 4 to log errors";
+ addr_msb {
+ compatible = "eswin,win2030,bitfield";
+ description = "Stores NTTP packet header field Addr (MSBs) of the logged error";
+ offset,length = < 0 9 >;
+ };
+ };
+
+ ErrorLogger5 {
+ compatible = "eswin,win2030,register";
+ offset,length = < 0x28 32 >;
+ description = "Register 5 to log errors";
+
+ User_flag {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0x0 16 >;
+ lut =
+ "Cache_0",
+ "Cache_1",
+ "Cache_2",
+ "Cache_3",
+ "Prot_0 ",
+ "Prot_1 ",
+ "Prot_2 ",
+ "User_0 ",
+ "User_1 ",
+ "User_2 ",
+ "User_3 ",
+ "User_4 ",
+ "qos0",
+ "qos1",
+ "qos2",
+ "qos3";
+ };
+ };
+};
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
new file mode 100644
index 000000000000..0a81e221150c
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
@@ -0,0 +1,2403 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Include file for Die0 System peripherals of Eswin EIC770x family SoC.
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#if (!(CHIPLET_AND_DIE & 0x2))
+#include "eswin-win2030-arch.dtsi"
+#else
+#include "eswin-win2030-arch-d2d.dtsi"
+#endif
+
+#include <dt-bindings/memory/eswin-win2030-sid.h>
+#include <dt-bindings/mailbox/eswin-mailbox.h>
+#include <dt-bindings/reset/eswin,win2030-syscrg.h>
+#include <dt-bindings/clock/win2030-clock.h>
+#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/interconnect/eswin,win2030.h>
+
+/ {
+ compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000","sifive,fu740";
+ d0_cpu_opp_table: opp-table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-24000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_24M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-100000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_100M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-200000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_200M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_400M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_500M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_600M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-700000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_700M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-800000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_800M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-900000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_900M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1000M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1200M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-1300000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1300M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1400M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1500M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-1600000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1600M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1700M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1800M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ };
+};
+
+&SOC {
+ d0_uart0: serial@0x50900000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x50900000 0x0 0x10000>;
+ clock-frequency = <LSPCLK_FREQ>;
+ interrupt-parent = <&plic0>;
+ interrupts = <UART0_INT>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ numa-node-id = <0>;
+ };
+
+ d0_uart1: serial@0x50910000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x50910000 0x0 0x10000>;
+ clock-frequency = <LSPCLK_FREQ>;
+ interrupt-parent = <&plic0>;
+ interrupts = <UART1_INT>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ numa-node-id = <0>;
+ };
+
+ d0_uart2: serial@0x50920000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x50920000 0x0 0x10000>;
+ clock-frequency = <LSPCLK_FREQ>;
+ interrupt-parent = <&plic0>;
+ interrupts = <UART2_INT>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ numa-node-id = <0>;
+ status = "disabled";
+ };
+
+ d0_uart3: serial@0x50930000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x50930000 0x0 0x10000>;
+ clock-frequency = <LSPCLK_FREQ>;
+ interrupt-parent = <&plic0>;
+ interrupts = <UART3_INT>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ numa-node-id = <0>;
+ status = "disabled";
+ };
+
+ d0_uart4: serial@0x50940000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x50940000 0x0 0x10000>;
+ clock-frequency = <LSPCLK_FREQ>;
+ interrupt-parent = <&plic0>;
+ interrupts = <UART4_INT>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ numa-node-id = <0>;
+ status = "disabled";
+ };
+
+ d0_sys_con: scu_sys_con@0x51810000 {
+ compatible = "eswin,win2030-scu-sys-con", "syscon", "simple-mfd";
+ #syscon-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x51810000 0x0 0x8000>;
+ numa-node-id = <0>;
+ d0_noc_wdt:noc@51810324 {
+ compatible = "eswin,win2030-noc-wdt";
+ interrupt-parent = <&plic0>;
+ interrupts = <392>, <393>, <394>, <395>,
+ <396>, <397>, <398>, <399>, <400>,
+ <401>, <402>, <403>, <404>, <405>,
+ <406>, <407>, <408>, <409>, <410>,
+ <411>, <412>, <413>, <414>, <415>,
+ <416>, <417>, <418>, <419>, <420>,
+ <421>, <422>, <423>, <424>, <425>,
+ <426>;
+ status = "disabled";
+ };
+ };
+
+ d0_sys_crg: sys-crg@51828000 {
+ compatible = "eswin,win2030-sys-crg", "syscon", "simple-mfd";
+ reg = <0x000000 0x51828000 0x000000 0x80000>;
+ numa-node-id = <0>;
+ d0_reset: reset-controller {
+ compatible = "eswin,win2030-reset";
+ #reset-cells = <2>;
+ };
+ d0_clock: clock-controller {
+ compatible = "eswin,win2030-clock";
+ #clock-cells = <1>;
+ };
+ };
+
+ hfclk: hfclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <LSPCLK_FREQ>;
+ clock-output-names = "hfclk";
+ };
+
+ d0_hsp_sp_csr: hsp_sp_top_csr@0x50440000 {
+ compatible = "eswin,win2030-hsp-sp-csr", "syscon";
+ #size-cells = <2>;
+ reg = <0x0 0x50440000 0x0 0x2000>;
+ };
+
+ smmu0: iommu@50c00000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x0 0x50c00000 0x0 0x100000>;
+ eswin,syscfg = <&d0_sys_con 0x3fc>;
+ interrupt-parent = <&plic0>;
+ interrupts = <356>,
+ <360>,
+ <357>,
+ <358>;
+ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
+ #iommu-cells = <1>;
+ resets = <&d0_reset TCU_RST_CTRL SW_TCU_AXI_RSTN>,
+ <&d0_reset TCU_RST_CTRL SW_TCU_CFG_RSTN>,
+ <&d0_reset TCU_RST_CTRL TBU_RSTN_0>,
+ <&d0_reset TCU_RST_CTRL TBU_RSTN_1>,
+ <&d0_reset TCU_RST_CTRL TBU_RSTN_2>,
+ <&d0_reset TCU_RST_CTRL TBU_RSTN_3>,
+ <&d0_reset TCU_RST_CTRL TBU_RSTN_4>,
+ <&d0_reset TCU_RST_CTRL TBU_RSTN_5>,
+ <&d0_reset TCU_RST_CTRL TBU_RSTN_6>,
+ <&d0_reset TCU_RST_CTRL TBU_RSTN_7>;
+ reset-names = "axi_rst", "cfg_rst", "tbu0_rst", "tbu1_rst", "tbu2_rst", "tbu3_rst",
+ "tbu4_rst", "tbu5_rst", "tbu6_rst", "tbu7_rst";
+ status = "disabled";
+ numa-node-id = <0>;
+ };
+
+ smmu_pmu0: pmu@50c02000 {
+ compatible = "arm,smmu-v3-pmcg";
+ reg = <0x0 0x50c02000 0x0 0x1000>,
+ <0x0 0x50c22000 0x0 0x1000>;
+ eswin,syscfg = <&d0_sys_con 0x3fc>;
+ interrupt-parent = <&plic0>;
+ interrupts = <363>;
+ status = "disabled";
+ numa-node-id = <0>;
+ };
+
+ dev_foo_b: E21@1 {
+ compatible = "riscv,dev-foo-b";
+ #size-cells = <2>;
+
+ dma-ranges = <0x0 0x20000000 0x0 0xc0000000 0x0 0x40000000>;
+ iommus = <&smmu0 WIN2030_SID_DEV_FOO_B>;
+ tbus = <WIN2030_TBUID_0xF00>;
+ numa-node-id = <0>;
+ status = "disabled";
+ };
+
+ dev_foo_a: E21@0 {
+ compatible = "riscv,dev-foo-a";
+ #size-cells = <2>;
+ dma-ranges = <0x0 0x20000000 0x0 0xc0000000 0x0 0x40000000>;
+ iommus = <&smmu0 WIN2030_SID_DEV_FOO_A>;
+ tbus = <WIN2030_TBUID_0xF00>;
+ /*
+ tbus = <WIN2030_TBUID_0x0>,
+ <WIN2030_TBUID_0x10>, <WIN2030_TBUID_0x11>, <WIN2030_TBUID_0x12>, <WIN2030_TBUID_0x13>,
+ <WIN2030_TBUID_0x2>, <WIN2030_TBUID_0x3>, <WIN2030_TBUID_0x4>, <WIN2030_TBUID_0x5>,
+ <WIN2030_TBUID_0x70>, <WIN2030_TBUID_0x71>, <WIN2030_TBUID_0x72>, <WIN2030_TBUID_0x73>;
+ */
+ status = "disabled";
+ numa-node-id = <0>;
+ };
+
+ d0_pmu: power-controller@51808000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "eswin,win2030-pmu-controller";
+ reg = <0x0 0x51808000 0x0 0x8000>;
+ numa-node-id = <0>;
+
+ d0_pmu_pcie: win2030-pmu-controller-port@0 {
+ compatible = "eswin,win2030-pmu-controller-port";
+ reg_base = <0x0>;
+ power_status = <1>;
+ power_delay = <6 6 3 3>;
+ clock_delay = <4 2 2 2>;
+ reset_delay = <2 4 2 2>;
+ clamp_delay = <3 3 2 2>;
+ label = "D0_PCIE";
+ };
+ d0_pmu_dsp1: win2030-pmu-controller-port@40 {
+ compatible = "eswin,win2030-pmu-controller-port";
+ reg_base = <0x40>;
+ power_status = <0>;
+ power_delay = <6 6 3 3>;
+ clock_delay = <4 2 2 2>;
+ reset_delay = <2 4 2 2>;
+ clamp_delay = <3 3 2 2>;
+ label = "D0_DSP1";
+ };
+ d0_pmu_vi: win2030-pmu-controller-port@80 {
+ compatible = "eswin,win2030-pmu-controller-port";
+ reg_base = <0x80>;
+ power_status = <1>;
+ power_delay = <6 6 3 3>;
+ clock_delay = <4 2 2 2>;
+ reset_delay = <2 4 2 2>;
+ clamp_delay = <3 3 2 2>;
+ label = "D0_VI";
+ };
+ d0_pmu_vo: win2030-pmu-controller-port@c0 {
+ compatible = "eswin,win2030-pmu-controller-port";
+ reg_base = <0xc0>;
+ power_status = <0>;
+ power_delay = <6 6 3 3>;
+ clock_delay = <4 2 2 2>;
+ reset_delay = <2 4 2 2>;
+ clamp_delay = <3 3 2 2>;
+ label = "D0_VO";
+ };
+ d0_pmu_codec: win2030-pmu-controller-port@140 {
+ compatible = "eswin,win2030-pmu-controller-port";
+ reg_base = <0x140>;
+ power_status = <0>;
+ power_delay = <6 6 3 3>;
+ clock_delay = <4 2 2 2>;
+ reset_delay = <2 4 2 2>;
+ clamp_delay = <3 3 2 2>;
+ label = "D0_CODEC";
+ };
+ d0_pmu_dsp2: win2030-pmu-controller-port@200 {
+ compatible = "eswin,win2030-pmu-controller-port";
+ reg_base = <0x200>;
+ power_status = <0>;
+ power_delay = <6 6 3 3>;
+ clock_delay = <4 2 2 2>;
+ reset_delay = <2 4 2 2>;
+ clamp_delay = <3 3 2 2>;
+ label = "D0_DSP2";
+ };
+ d0_pmu_dsp3: win2030-pmu-controller-port@240 {
+ compatible = "eswin,win2030-pmu-controller-port";
+ reg_base = <0x240>;
+ power_status = <0>;
+ power_delay = <6 6 3 3>;
+ clock_delay = <4 2 2 2>;
+ reset_delay = <2 4 2 2>;
+ clamp_delay = <3 3 2 2>;
+ label = "D0_DSP3";
+ };
+ };
+
+ d0_dmac0: dma-controller-hsp@0x50430000 {
+ compatible = "snps,axi-dma-1.01a";
+ reg = <0x0 0x50430000 0x0 0x10000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <57>;
+ #dma-cells = <2>; // change dma-cells value <1> to <2>, to support peripheral selection dma-controller,See the parameter dmas for details;
+ clocks = <&d0_clock WIN2030_CLK_HSP_DMA0_CLK>;
+ clock-names = "core-clk";
+ resets = <&d0_reset HSPDMA_RST_CTRL SW_HSP_DMA0_RSTN>,
+ <&d0_reset HSPDMA_RST_CTRL SW_HSP_DMA_PRSTN>;
+ reset-names = "arst", "prst";
+ dma-channels = <12>;
+ snps,dma-masters = <1>;
+ snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11>;
+ snps,data-width = <2>;
+ snps,block-size = <0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000>;
+ snps,axi-max-burst-len = <16>;
+ snps,max-msize = <64>;
+ iommus = <&smmu0 WIN2030_SID_DMA0>;
+ tbus = <WIN2030_TBUID_DMA0>;
+ eswin,hsp_sp_csr = <&d0_hsp_sp_csr 0x104c>;
+ eswin,syscfg = <&d0_sys_con DMA1_SID_REG_OFFSET 0x370>;
+ numa-node-id = <0>;
+ };
+
+ d0_aon_dmac: dma-controller-aon@0x518c0000 {
+ compatible = "snps,axi-dma-1.01a";
+ reg = <0x0 0x518c0000 0x0 0x10000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <289>;
+ #dma-cells = <2>; // change dma-cells value <1> to <2>, to support peripheral selection dma-controller,See the parameter dmas for details;
+ clocks = <&d0_clock WIN2030_CLK_AONDMA_ACLK>;
+ clock-names = "core-clk";
+ resets = <&d0_reset DMA1_RST_CTRL SW_DMA1_ARSTN>,
+ <&d0_reset DMA1_RST_CTRL SW_DMA1_HRSTN>;
+ reset-names = "arst", "prst";
+ dma-channels = <16>;
+ snps,dma-masters = <2>;
+ snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
+ snps,data-width = <3>;
+ snps,block-size = <0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000>;
+ snps,axi-max-burst-len = <32>;
+ snps,max-msize = <64>;
+ #size-cells = <2>;
+ #address-cells = <2>;
+ dma-ranges = <0x0 0x80000000 0x0 0x80000000 0x100 0x0>;
+ iommus = <&smmu0 WIN2030_SID_DMA1>;
+ tbus = <WIN2030_TBUID_DMA1>;
+ eswin,syscfg = <&d0_sys_con DMA1_SID_REG_OFFSET 0x370>;
+ numa-node-id = <0>;
+ };
+
+ d0_gmac0: ethernet@50400000 {
+ compatible = "eswin,win2030-qos-eth";
+ reg = <0x0 0x50400000 0x0 0x10000>;
+ interrupt-parent = <&plic0>;
+ interrupt-names = "macirq";
+ interrupts = <61>;
+ phy-mode = "rgmii";
+ numa-node-id = <0>;
+ id = <0>;
+ status = "disabled";
+ clocks = <&d0_clock WIN2030_CLK_HSP_ETH_APP_CLK>,
+ <&d0_clock WIN2030_CLK_HSP_ETH_CSR_CLK>,
+ <&d0_clock WIN2030_CLK_HSP_ETH0_CORE_CLK>;
+ clock-names = "app", "csr","tx";
+ resets = <&d0_reset HSPDMA_RST_CTRL SW_HSP_ETH0_ARSTN>;
+ reset-names = "ethrst";
+ iommus = <&smmu0 WIN2030_SID_ETH0>;
+ tbus = <WIN2030_TBUID_ETH>;
+ eswin,hsp_sp_csr = <&d0_hsp_sp_csr 0x1030 0x100 0x108>;
+ eswin,syscrg_csr = <&d0_sys_crg 0x148 0x14c>;
+ snps,axi-config = <&d0_stmmac_axi_setup>;
+ d0_stmmac_axi_setup: stmmac-axi-config {
+ snps,blen = <0 0 0 0 16 8 4>;
+ snps,rd_osr_lmt = <2>;
+ snps,wr_osr_lmt = <2>;
+ snps,lpi_en = <0>;
+ };
+ };
+
+ d0_gmac1: ethernet@50410000 {
+ compatible = "eswin,win2030-qos-eth";
+ reg = <0x0 0x50410000 0x0 0x10000>;
+ interrupt-parent = <&plic0>;
+ interrupt-names = "macirq";
+ interrupts = <70>;
+ phy-mode = "rgmii";
+ numa-node-id = <0>;
+ id = <1>;
+ status = "disabled";
+ clocks = <&d0_clock WIN2030_CLK_HSP_ETH_APP_CLK>,
+ <&d0_clock WIN2030_CLK_HSP_ETH_CSR_CLK>,
+ <&d0_clock WIN2030_CLK_HSP_ETH1_CORE_CLK>;
+ clock-names = "app", "csr","tx";
+ resets = <&d0_reset HSPDMA_RST_CTRL SW_HSP_ETH1_ARSTN>;
+ reset-names = "ethrst";
+ iommus = <&smmu0 WIN2030_SID_ETH1>;
+ tbus = <WIN2030_TBUID_ETH>;
+ eswin,hsp_sp_csr = <&d0_hsp_sp_csr 0x1034 0x200 0x208>;
+ eswin,syscrg_csr = <&d0_sys_crg 0x148 0x14c>;
+ snps,axi-config = <&d0_stmmac_axi_setup_gmac1>;
+ d0_stmmac_axi_setup_gmac1: stmmac-axi-config {
+ snps,blen = <0 0 0 0 16 8 4>;
+ snps,rd_osr_lmt = <2>;
+ snps,wr_osr_lmt = <2>;
+ snps,lpi_en = <0>;
+ };
+ };
+ noc {
+ compatible = "eswin,noc","simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ #include "eswin-win2030-die0-noc.dtsi"
+ };
+
+ d0_nvdla: nvdla-controller@51c00000 {
+ compatible = "eswin,npu0";
+ reg = <0x0 0x51c00000 0x0 0x400000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <387 16>;
+ spram-region = <&npu0_reserved>;
+ #size-cells = <2>;
+ dma-ranges = <0x1 0x0 0x0 0xc0000000 0x1ff 0x0>;
+ iommus = <&smmu0 WIN2030_SID_NPU_DMA>;
+ tbus = <WIN2030_TBUID_NPU>;
+ dsp-avail-num = <1>;
+ spram-size = <0x400000>;
+ npu_mbox = <&d0_mbox2>;
+
+ resets = <&d0_reset NPU_RST_CTRL SW_NPU_E31CORE_RSTN>;
+ reset-names = "e31_core";
+
+ numa-node-id = <0>;
+ };
+
+ dev_llc_d0: llc@51c00000 {
+ compatible = "eswin,llc";
+ reg = <0x0 0x51c00000 0x0 0x400000>;
+ eswin,syscfg = <&d0_sys_con 0x324>;
+ eswin,syscrg_csr = <&d0_sys_crg>;
+ clocks = <&d0_clock WIN2030_CLK_NPU_ACLK>,
+ <&d0_clock WIN2030_CLK_NPU_CFG_CLK>,
+ <&d0_clock WIN2030_CLK_NPU_LLC_ACLK>,
+ <&d0_clock WIN2030_CLK_NPU_CLK>,
+ <&d0_clock WIN2030_MUX_U_NPU_CORE_3MUX1_GFREE>,
+ <&d0_clock WIN2030_SPLL2_FOUT2>;
+ clock-names = "aclk", "cfg_clk", "llc_clk", "core_clk",
+ "mux_u_npu_core_3mux1_gfree", "fixed_rate_clk_spll2_fout2";
+ resets = <&d0_reset NPU_RST_CTRL SW_NPU_AXI_RSTN>,
+ <&d0_reset NPU_RST_CTRL SW_NPU_CFG_RSTN>,
+ <&d0_reset NPU_RST_CTRL SW_NPU_CORE_RSTN>,
+ <&d0_reset NPU_RST_CTRL SW_NPU_LLC_RSTN>;
+ reset-names = "axi", "cfg", "core", "llc";
+ numa-node-id = <0>;
+ spram-region = <&npu0_reserved>;
+ };
+
+ d0_dsp_subsys:dsp_subsys@52280400 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x52280400 0x0 0x10000>,
+ <0x0 0x51810000 0x0 0x8000>;
+ ranges;
+ compatible = "es-dsp-subsys", "simple-bus";
+ clocks = <&d0_clock WIN2030_CLK_DSPT_CFG_CLK>;
+ clock-names = "cfg_clk";
+ resets = <&d0_reset DSP_RST_CTRL SW_DSP_AXI_RSTN>,
+ <&d0_reset DSP_RST_CTRL SW_DSP_CFG_RSTN>,
+ <&d0_reset DSP_RST_CTRL SW_DSP_DIV4_RSTN>,
+ <&d0_reset DSP_RST_CTRL SW_DSP_DIV_RSTN_0>,
+ <&d0_reset DSP_RST_CTRL SW_DSP_DIV_RSTN_1>,
+ <&d0_reset DSP_RST_CTRL SW_DSP_DIV_RSTN_2>,
+ <&d0_reset DSP_RST_CTRL SW_DSP_DIV_RSTN_3>;
+ reset-names = "axi", "cfg", "div4", "div_0", "div_1", "div_2","div_3";
+ d0_dsp0:es_dsp@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "eswin-dsp", "cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0 0x5b000000 0x8000
+ 0x28100000 0 0x5b100000 0x20000
+ 0x28120000 0 0x5b120000 0x20000>;
+ clocks = <&d0_clock WIN2030_CLK_DSP_ACLK_0>;
+ clock-names = "aclk";
+ dsp_mbox = <&d0_mbox4>;
+ device-irq = <11
+ ESWIN_MAILBOX_DSP_0_TO_U84_REG_BASE
+ ESWIN_MAILBOX_WR_LOCK_BIT_DSP_0
+ ESWIN_MAILBOX_U84_TO_DSP_0_REG_BASE
+ ESWIN_MAIBOX_U84_IRQ_BIT>;
+ device-uart = <0x50910000>;
+ device-irq-mode = <1>;
+ host-irq-mode = <1>;
+ firmware-name = "eic7700_dsp_fw";
+ process-id = <0>;
+ dma-ranges = <0x30000000 0x0 0xc0000000 0xce000000>;
+ iommus = <&smmu0 WIN2030_SID_DSP_0>;
+ tbus = <WIN2030_TBUID_DSP0>;
+ numa-node-id = <0>;
+ aux-e31-dtim = <0x5a110000>;
+ dsp@0 {
+ };
+ };
+ d0_dsp1:es_dsp@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "eswin-dsp", "cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0 0x5b008000 0x8000
+ 0x28100000 0 0x5b140000 0x20000
+ 0x28120000 0 0x5b160000 0x20000>;
+ clocks = <&d0_clock WIN2030_CLK_DSP_ACLK_1>;
+ clock-names = "aclk";
+ dsp_mbox = <&d0_mbox5>;
+ device-irq = <13
+ ESWIN_MAILBOX_DSP_1_TO_U84_REG_BASE
+ ESWIN_MAILBOX_WR_LOCK_BIT_DSP_1
+ ESWIN_MAILBOX_U84_TO_DSP_1_REG_BASE
+ ESWIN_MAIBOX_U84_IRQ_BIT>;
+ device-uart = <0x50910000>;
+ device-irq-mode = <1>;
+ host-irq-mode = <1>;
+ firmware-name = "eic7700_dsp_fw";
+ process-id = <1>;
+ dma-ranges = <0x30000000 0x0 0xc0000000 0xce000000>;
+ iommus = <&smmu0 WIN2030_SID_DSP_1>;
+ tbus = <WIN2030_TBUID_DSP1>;
+ numa-node-id = <0>;
+ aux-e31-dtim = <0x5a110000>;
+ dsp@0 {
+ };
+ };
+ d0_dsp2:es_dsp@2 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "eswin-dsp", "cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0 0x5b010000 0x8000
+ 0x28100000 0 0x5b180000 0x20000
+ 0x28120000 0 0x5b1a0000 0x20000>;
+ clocks = <&d0_clock WIN2030_CLK_DSP_ACLK_2>;
+ clock-names = "aclk";
+ dsp_mbox = <&d0_mbox6>;
+ device-irq = <15
+ ESWIN_MAILBOX_DSP_2_TO_U84_REG_BASE
+ ESWIN_MAILBOX_WR_LOCK_BIT_DSP_2
+ ESWIN_MAILBOX_U84_TO_DSP_2_REG_BASE
+ ESWIN_MAIBOX_U84_IRQ_BIT>;
+ device-uart = <0x50910000>;
+ device-irq-mode = <1>;
+ host-irq-mode = <1>;
+ firmware-name = "eic7700_dsp_fw";
+ process-id = <2>;
+ dma-ranges = <0x30000000 0x0 0xc0000000 0xce000000>;
+ iommus = <&smmu0 WIN2030_SID_DSP_2>;
+ tbus = <WIN2030_TBUID_DSP2>;
+ numa-node-id = <0>;
+ aux-e31-dtim = <0x5a110000>;
+ dsp@0 {
+ };
+ };
+ d0_dsp3:es_dsp@3 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "eswin-dsp", "cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0 0x5b018000 0x8000
+ 0x28100000 0 0x5b1c0000 0x20000
+ 0x28120000 0 0x5b1e0000 0x20000>;
+ clocks = <&d0_clock WIN2030_CLK_DSP_ACLK_3>;
+ clock-names = "aclk";
+ dsp_mbox = <&d0_mbox7>;
+ device-irq = <17
+ ESWIN_MAILBOX_DSP_3_TO_U84_REG_BASE
+ ESWIN_MAILBOX_WR_LOCK_BIT_DSP_3
+ ESWIN_MAILBOX_U84_TO_DSP_3_REG_BASE
+ ESWIN_MAIBOX_U84_IRQ_BIT>;
+ device-uart = <0x50910000>;
+ device-irq-mode = <1>;
+ host-irq-mode = <1>;
+ firmware-name = "eic7700_dsp_fw";
+ process-id = <3>;
+ dma-ranges = <0x30000000 0x0 0xc0000000 0xce000000>;
+ iommus = <&smmu0 WIN2030_SID_DSP_3>;
+ tbus = <WIN2030_TBUID_DSP3>;
+ numa-node-id = <0>;
+ aux-e31-dtim = <0x5a110000>;
+ dsp@0 {
+ };
+ };
+ d0_sofdsp: sofdsp@4 {
+ #sound-dai-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "eswin,vision-dsp";
+ reg = <0x0 0x5b000000 0x0 0x10000>,
+ <0x0 0x5b100000 0x0 0x40000>;
+ /* memory-region = <&dsp_reserved0>; */
+ mbox-names = "sof-dsp0";
+ mboxes = <&d0_mbox4 0>;
+ tplg-name = "sof-win2030-es8316.tplg";
+ machine-drv-name = "asoc-simple-card";
+ clocks = <&d0_clock WIN2030_CLK_DSP_ACLK_0>;
+ clock-names = "aclk";
+ process-id = <0>;
+ dma-ranges = <0x0 0x40000000 0x0 0xc0000000 0x0 0xc0000000>;
+ iommus = <&smmu0 WIN2030_SID_DSP_0>;
+ mailbox-dsp-to-u84-addr = <ESWIN_MAILBOX_DSP_0_TO_U84_REG_BASE>;
+ mailbox-u84-to-dsp-addr = <ESWIN_MAILBOX_U84_TO_DSP_0_REG_BASE>;
+ dsp-uart = <&d0_uart1>;
+ ringbuffer-region = <&dsp_reserved1>;
+ };
+ };
+
+ gc820: g2d@50140000 {
+ compatible = "eswin,galcore_d0";
+ clocks = <&d0_clock WIN2030_CLK_VC_ACLK>,
+ <&d0_clock WIN2030_CLK_VC_CFG_CLK>,
+ <&d0_clock WIN2030_CLK_G2D_CFG_CLK>,
+ <&d0_clock WIN2030_CLK_CLK_G2D_ST2>,
+ <&d0_clock WIN2030_CLK_G2D_CLK>,
+ <&d0_clock WIN2030_CLK_G2D_ACLK>,
+ <&d0_clock WIN2030_CLK_VC_MON_PCLK>;
+ clock-names = "vc_aclk", "vc_cfg", "g2d_cfg", "g2d_st2", "g2d_clk", "g2d_aclk", "mon_pclk";
+ resets = <&d0_reset VC_RST_CTRL SW_VC_AXI_RSTN>,
+ <&d0_reset VC_RST_CTRL SW_VC_CFG_RSTN>,
+ <&d0_reset VC_RST_CTRL SW_VC_MONCFG_RSTN>,
+ <&d0_reset G2D_RST_CTRL SW_G2D_CORE_RSTN>,
+ <&d0_reset G2D_RST_CTRL SW_G2D_CFG_RSTN>,
+ <&d0_reset G2D_RST_CTRL SW_G2D_AXI_RSTN>;
+ reset-names = "axi", "cfg", "moncfg", "g2d_core", "g2d_cfg", "g2d_axi";
+ reg = <0 0x50140000 0 0x40000>, <0 0x50180000 0 0x40000>;
+ reg-names = "core_2d", "core_2d1";
+ fe-apb-offset = <0x800>;
+ interrupt-parent = <&plic0>;
+ interrupts = <49>, <50>;
+ interrupt-names = "core_2d", "core_2d1";
+ enable-mmu = <1>;
+ contiguous-size = <0xa00000>;
+ recovery = <0>;
+ };
+
+ gpu0: gpu@51400000 {
+ compatible = "img,gpu";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x51400000 0x0 0xFFFFF>;
+ clocks = <&d0_clock WIN2030_CLK_GPU_ACLK>,
+ <&d0_clock WIN2030_CLK_GPU_GRAY_CLK>,
+ <&d0_clock WIN2030_CLK_GPU_CFG_CLK>;
+ clock-names = "aclk", "gray_clk", "cfg_clk";
+ resets =<&d0_reset GPU_RST_CTRL SW_GPU_AXI_RSTN>,
+ <&d0_reset GPU_RST_CTRL SW_GPU_CFG_RSTN>,
+ <&d0_reset GPU_RST_CTRL SW_GPU_GRAY_RSTN>,
+ <&d0_reset GPU_RST_CTRL SW_GPU_JONES_RSTN>,
+ <&d0_reset GPU_RST_CTRL SW_GPU_SPU_RSTN>;
+ reset-names = "axi", "cfg", "gray", "jones","spu";
+ interrupt-parent = <&plic0>;
+ interrupts = <15>;
+ };
+
+ d0_sata: sata@0x50420000{
+ compatible = "snps,eswin-ahci";
+ reg = <0x0 0x50420000 0x0 0x10000>;
+ interrupt-parent = <&plic0>;
+ interrupt-names = "intrq", "msi", "pme";
+ interrupts = <58>, <59>, <60>;
+ ports-implemented = <0x1>;
+ resets = <&d0_reset HSPDMA_RST_CTRL SW_SATA_ASIC0_RSTN>,
+ <&d0_reset HSPDMA_RST_CTRL SW_SATA_OOB_RSTN>,
+ <&d0_reset HSPDMA_RST_CTRL SW_SATA_PMALIVE_RSTN>,
+ <&d0_reset HSPDMA_RST_CTRL SW_SATA_RBC_RSTN>;
+ reset-names = "asic0", "oob", "pmalive", "rbc";
+ #size-cells = <2>;
+ iommus = <&smmu0 WIN2030_SID_SATA>;
+ tbus = <WIN2030_TBUID_SATA>;
+ dma-ranges = <0x0 0x0 0x0 0xc0000000 0x200 0x0>;
+ eswin,hsp_sp_csr = <&d0_hsp_sp_csr 0x1050>;
+ eswin,syscrg_csr = <&d0_sys_crg 0x41c>;
+ numa-node-id = <0>;
+ };
+
+ pcie: pcie@0x54000000 {
+ compatible = "eswin,win2030-pcie";
+ clocks = <&d0_clock WIN2030_CLK_PCIET_ACLK>,
+ <&d0_clock WIN2030_CLK_PCIET_CFG_CLK>,
+ <&d0_clock WIN2030_CLK_PCIET_CR_CLK>,
+ <&d0_clock WIN2030_CLK_PCIET_AUX_CLK>;
+ clock-names = "pcie_aclk", "pcie_cfg_clk", "pcie_cr_clk", "pcie_aux_clk";
+
+ reset-names = "pcie_cfg", "pcie_powerup", "pcie_pwren";
+ resets = <&d0_reset PCIE_RST_CTRL SW_PCIE_CFG_RSTN>,
+ <&d0_reset PCIE_RST_CTRL SW_PCIE_POWERUP_RSTN>,
+ <&d0_reset PCIE_RST_CTRL SW_PCIE_PERST_N>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ reg = <0x0 0x54000000 0x0 0x4000000>, /* IP registers */
+ <0x0 0x40000000 0x0 0x800000>, /* Configuration space */
+ <0x0 0x50000000 0x0 0x100000>;
+ reg-names = "dbi", "config", "mgmt";
+ device_type = "pci";
+ /* dma-coherent; */
+ bus-range = <0x0 0xff>;
+
+ ranges = <0x81000000 0x0 0x40800000 0x0 0x40800000 0x0 0x800000>, /* I/O */
+ <0x82000000 0x0 0x41000000 0x0 0x41000000 0x0 0xf000000>, /* mem */
+ <0xc3000000 0x80 0x00000000 0x80 0x00000000 0x20 0x00000000>; /* mem prefetchable */
+
+ /* num-lanes = <0x4>; */
+ /**********************************
+ msi_ctrl_io[0~31] : 188~219
+ msi_ctrl_int : 220
+ **********************************/
+ interrupts = <220>;
+ interrupt-names = "msi";
+ interrupt-parent = <&plic0>;
+ iommus = <&smmu0 0xfe0000>;
+ iommu-map = <0x0 &smmu0 0xff0000 0xffffff>;
+ #ifdef PLATFORM_HAPS
+ gen-x = <1>;
+ #else
+ gen-x = <3>;
+ #endif
+ lane-x = <4>;
+ tbus = <WIN2030_TBUID_PCIE>;
+ status = "disabled";
+ numa-node-id = <0>;
+ };
+
+ ssi0: spi0@50810000 {
+ compatible = "snps,win2030-spi";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x50810000 0x0 0x4000>;
+ spi-max-frequency = <4800000>;
+ clocks = <&d0_clock WIN2030_CLK_LSP_SSI0_PCLK>;
+ clock-names = "clk";
+ interrupt-parent = <&plic0>;
+ interrupts = <91>;
+ resets = <&d0_reset SSI_RST_CTRL SW_SSI_RST_N_0>;
+ reset-names = "spi";
+ eswin,spi_dma = <&d0_aon_dmac>;
+ dmas = <&d0_aon_dmac 38 3>, <&d0_aon_dmac 39 3>;
+ dma-names = "rx", "tx";
+ numa-node-id = <0>;
+ status = "disabled";
+ };
+
+ ssi1: spi1@50814000 {
+ compatible = "snps,win2030-spi";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x50814000 0x0 0x4000>;
+ spi-max-frequency = <4800000>;
+ clocks = <&d0_clock WIN2030_CLK_LSP_SSI1_PCLK>;
+ clock-names = "clk";
+ interrupt-parent = <&plic0>;
+ interrupts = <92>;
+ resets = <&d0_reset SSI_RST_CTRL SW_SSI_RST_N_1>;
+ reset-names = "spi";
+ eswin,spi_dma = <&d0_aon_dmac>;
+ dmas = <&d0_aon_dmac 36 4>, <&d0_aon_dmac 37 4>;
+ dma-names = "rx", "tx";
+ numa-node-id = <0>;
+ status = "disabled";
+ };
+
+ sdhci_emmc: mmc@50450000 {
+ compatible = "eswin,emmc-sdhci-5.1";
+ reg = <0x0 0x50450000 0x0 0x10000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <79>;
+ assigned-clocks = <&d0_clock WIN2030_CLK_HSP_MSHC0_CORE_CLK>;
+ assigned-clock-rates = <200000000>;
+ clocks = <&d0_clock WIN2030_CLK_HSP_MSHC0_CORE_CLK>, <&d0_clock WIN2030_CLK_HSP_CFG_CLK>;
+ clock-names = "clk_xin", "clk_ahb";
+ clock-output-names = "emmc_cardclock";
+ #clock-cells = <0>;
+
+ resets = <&d0_reset HSPDMA_RST_CTRL SW_MSHC0_TXRX_RSTN>,
+ <&d0_reset HSPDMA_RST_CTRL SW_MSHC0_PHY_RSTN>,
+ <&d0_reset HSPDMA_RST_CTRL SW_HSP_EMMC_PRSTN>,
+ <&d0_reset HSPDMA_RST_CTRL SW_HSP_EMMC_ARSTN>;
+ reset-names = "txrx_rst", "phy_rst", "emmc_prstn", "emmc_arstn";
+ delay_code = <0x17>;
+ drive-impedance-ohm = <50>;
+ enable-data-pullup;
+
+ disable-cqe-dcmd;
+ bus-width = <8>;
+ non-removable;
+ /*mmc-ddr-1_8v;*/
+ mmc-hs400-1_8v;
+ max-frequency = <200000000>;
+ /* sdhci-caps-mask = <0x0 0x3200000>; */
+ /* sdhci-caps-mask = <0x2 0x3000000>; */
+ /* smmu */
+ #size-cells = <2>;
+ iommus = <&smmu0 WIN2030_SID_EMMC0>;
+ tbus = <WIN2030_TBUID_EMMC>;
+ dma-ranges = <0x0 0x00000000 0x0 0xc0000000 0x1 0x0>;
+ eswin,hsp_sp_csr = <&d0_hsp_sp_csr 0x1038>;
+ status = "disabled";
+ numa-node-id = <0>;
+ };
+
+ sdio0: mmc@0x50460000{
+ compatible = "eswin,sdhci-sdio";
+ reg = <0x0 0x50460000 0x0 0x10000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <81>;
+ clocks =<&d0_clock WIN2030_CLK_HSP_MSHC1_CORE_CLK>,
+ <&d0_clock WIN2030_CLK_HSP_CFG_CLK>,
+ <&d0_clock WIN2030_SPLL2_FOUT3>,
+ <&d0_clock WIN2030_MUX_U_MSHCORE_ROOT_3MUX1_1>;
+ clock-names ="clk_xin","clk_ahb","clk_spll2_fout3","clk_mux1_1";
+ clock-output-names = "sdio_cardclock";
+ #clock-cells = <0>;
+ resets = <&d0_reset HSPDMA_RST_CTRL SW_MSHC1_TXRX_RSTN>,
+ <&d0_reset HSPDMA_RST_CTRL SW_MSHC1_PHY_RSTN>,
+ <&d0_reset HSPDMA_RST_CTRL SW_HSP_SD0_PRSTN>,
+ <&d0_reset HSPDMA_RST_CTRL SW_HSP_SD0_ARSTN>;
+ reset-names = "txrx_rst","phy_rst","prstn","arstn";
+
+ delay_code = <0x28>;
+ drive-impedance-ohm = <50>;
+ enable-data-pullup;
+
+ core-clk-reg = <0x51828164>;
+ clock-frequency = <208000000>;
+ max-frequency = <208000000>;
+ #size-cells = <2>;
+ dma-ranges = <0x0 0x20000000 0x0 0xc0000000 0x0 0x40000000>;
+ iommus = <&smmu0 WIN2030_SID_SD0>;
+ tbus = <WIN2030_TBUID_SD>;
+ eswin,hsp_sp_csr = <&d0_hsp_sp_csr 0x103c>;
+ bus-width = <4>;
+ sdio-id = <0>;
+ numa-node-id = <0>;
+ status = "disabled";
+ };
+
+ sdio1: mmc@0x50470000{
+ compatible = "eswin,sdhci-sdio";
+ reg = <0x0 0x50470000 0x0 0x10000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <83>;
+ clocks =<&d0_clock WIN2030_CLK_HSP_MSHC2_CORE_CLK>,
+ <&d0_clock WIN2030_CLK_HSP_CFG_CLK>,
+ <&d0_clock WIN2030_SPLL2_FOUT3>,
+ <&d0_clock WIN2030_MUX_U_MSHCORE_ROOT_3MUX1_1>;
+ clock-names ="clk_xin","clk_ahb","clk_spll2_fout3","clk_mux1_1";
+ clock-output-names = "sdio_cardclock";
+ #clock-cells = <0>;
+ resets = <&d0_reset HSPDMA_RST_CTRL SW_MSHC2_TXRX_RSTN>,
+ <&d0_reset HSPDMA_RST_CTRL SW_MSHC2_PHY_RSTN>,
+ <&d0_reset HSPDMA_RST_CTRL SW_HSP_SD1_PRSTN>,
+ <&d0_reset HSPDMA_RST_CTRL SW_HSP_SD1_ARSTN>;
+ reset-names = "txrx_rst","phy_rst","prstn","arstn";
+
+ delay_code = <0x28>;
+ drive-impedance-ohm = <50>;
+ enable-data-pullup;
+
+ core-clk-reg = <0x51828168>;
+ clock-frequency = <208000000>;
+ max-frequency = <208000000>;
+ #size-cells = <2>;
+ dma-ranges = <0x0 0x20000000 0x0 0xc0000000 0x0 0x40000000>;
+ iommus = <&smmu0 WIN2030_SID_SD1>;
+ tbus = <WIN2030_TBUID_SD>;
+ eswin,hsp_sp_csr = <&d0_hsp_sp_csr 0x1040>;
+ bus-width = <4>;
+ sdio-id = <1>;
+ numa-node-id = <0>;
+ status = "disabled";
+ };
+
+ vdec0: video-decoder0@50100000 {
+ compatible = "eswin,video-decoder0";
+ clocks = <&d0_clock WIN2030_CLK_VC_ACLK>,
+ <&d0_clock WIN2030_CLK_VC_CFG_CLK>,
+ <&d0_clock WIN2030_CLK_VC_JD_CLK>,
+ <&d0_clock WIN2030_CLK_VC_VD_CLK>,
+ <&d0_clock WIN2030_MUX_U_VCACLK_ROOT_2MUX1_GFREE>,
+ <&d0_clock WIN2030_SPLL0_FOUT1>,
+ <&d0_clock WIN2030_SPLL2_FOUT1>,
+ <&d0_clock WIN2030_CLK_VC_JD_PCLK>,
+ <&d0_clock WIN2030_CLK_VC_VD_PCLK>,
+ <&d0_clock WIN2030_CLK_VC_MON_PCLK>;
+ clock-names = "aclk", "cfg_clk", "jd_clk", "vd_clk", "vc_mux", "spll0_fout1", "spll2_fout1", "jd_pclk", "vd_pclk", "mon_pclk";
+ resets = <&d0_reset VC_RST_CTRL SW_VC_AXI_RSTN>,
+ <&d0_reset VC_RST_CTRL SW_VC_CFG_RSTN>,
+ <&d0_reset VC_RST_CTRL SW_VC_MONCFG_RSTN>,
+ <&d0_reset JD_RST_CTRL SW_JD_CFG_RSTN>,
+ <&d0_reset JD_RST_CTRL SW_JD_AXI_RSTN>,
+ <&d0_reset VD_RST_CTRL SW_VD_CFG_RSTN>,
+ <&d0_reset VD_RST_CTRL SW_VD_AXI_RSTN>;
+ reset-names = "axi", "cfg", "moncfg", "jd_cfg", "jd_axi", "vd_cfg", "vd_axi";
+ eswin,syscfg = <&d0_sys_con 0x0 0x4>;
+
+ vcmd-core = <0 0x6c>;
+ axife-core = <0x200 0x100>;
+ vdec-core = <0x800 0xc00>;
+ interrupt-parent = <&plic0>;
+ #size-cells = <2>;
+ dma-ranges = <0x0 0x0 0x0 0x80000000 0x200 0x0>;
+ iommus = <&smmu0 WIN2030_SID_VDEC>;
+ vccsr-reg = <0x0 0x501c0000 0x0 0x1000>;
+ numa-node-id = <0>;
+ tbus = <WIN2030_TBUID_VDEC>, <WIN2030_TBUID_JDEC>;
+
+ vdec_0: vdec0@50100000 {
+ core-name = "video-dec0";
+ base-addr = <0x50100000>;
+ interrupts = <236>;
+ };
+
+ jdec_0: jdec0@50120000 {
+ core-name = "jpeg-dec0";
+ base-addr = <0x50120000>;
+ interrupts = <237>;
+ };
+ };
+
+ venc0: video-encoder@50110000 {
+ compatible = "eswin,video-encoder0";
+ clocks = <&d0_clock WIN2030_CLK_VC_ACLK>,
+ <&d0_clock WIN2030_CLK_VC_CFG_CLK>,
+ <&d0_clock WIN2030_CLK_VC_JE_CLK>,
+ <&d0_clock WIN2030_CLK_VC_VE_CLK>,
+ <&d0_clock WIN2030_MUX_U_VCACLK_ROOT_2MUX1_GFREE>,
+ <&d0_clock WIN2030_SPLL0_FOUT1>,
+ <&d0_clock WIN2030_SPLL2_FOUT1>,
+ <&d0_clock WIN2030_CLK_VC_JE_PCLK>,
+ <&d0_clock WIN2030_CLK_VC_VE_PCLK>,
+ <&d0_clock WIN2030_CLK_VC_MON_PCLK>;
+ clock-names = "aclk", "cfg_clk", "je_clk", "ve_clk", "vc_mux", "spll0_fout1", "spll2_fout1", "je_pclk", "ve_pclk", "mon_pclk";
+ resets = <&d0_reset VC_RST_CTRL SW_VC_AXI_RSTN>,
+ <&d0_reset VC_RST_CTRL SW_VC_CFG_RSTN>,
+ <&d0_reset VC_RST_CTRL SW_VC_MONCFG_RSTN>,
+ <&d0_reset JE_RST_CTRL SW_JE_CFG_RSTN>,
+ <&d0_reset JE_RST_CTRL SW_JE_AXI_RSTN>,
+ <&d0_reset VE_RST_CTRL SW_VE_CFG_RSTN>,
+ <&d0_reset VE_RST_CTRL SW_VE_AXI_RSTN>;
+ reset-names = "axi", "cfg", "moncfg", "je_cfg", "je_axi", "ve_cfg", "ve_axi";
+ eswin,syscfg = <&d0_sys_con 0x0 0x4>;
+
+ vcmd-core = <0 0x6c>;
+ axife-core = <0x2000 0x7d0>;
+ venc-core = <0x1000 0x87c>;
+ interrupt-parent = <&plic0>;
+ #size-cells = <2>;
+ dma-ranges = <0x0 0x0 0x0 0x80000000 0x200 0x0>;
+ iommus = <&smmu0 WIN2030_SID_VENC>;
+ vccsr-reg = <0x0 0x501c0000 0x0 0x1000>;
+ numa-node-id = <0>;
+ tbus = <WIN2030_TBUID_VENC>, <WIN2030_TBUID_JENC>;
+
+ venc_0: venc0@50110000 {
+ core-name = "video-enc0";
+ base-addr = <0x50110000>;
+ interrupts = <229>;
+ };
+
+ jenc_0: jenc0@50130000 {
+ core-name = "jpeg-enc0";
+ base-addr = <0x50130000>;
+ interrupts = <232>;
+ };
+ };
+
+ /*mailbox between u84 & scpu*/
+ d0_mbox0: mbox@50a00000 {
+ compatible = "eswin,win2030-mailbox";
+ reg = <0 ESWIN_MAILBOX_U84_TO_SCPU_REG_BASE 0 0x10000>,
+ <0 ESWIN_MAILBOX_SCPU_TO_U84_REG_BASE 0 0x10000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <117>;
+ #mbox-cells = <1>;
+ clocks = <&d0_clock WIN2030_CLK_MAILBOX_0>,
+ <&d0_clock WIN2030_CLK_MAILBOX_1>;
+ clock-names = "pclk_mailbox_host", "pclk_mailbox_device";
+ resets = <&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_0>,
+ <&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_1>;
+ reset-names = "rst", "rst_device";
+ lock-bit = <ESWIN_MAILBOX_WR_LOCK_BIT_U84>;
+ irq-bit = <ESWIN_MAIBOX_SCPU_IRQ_BIT>;
+ };
+
+ /*mailbox between u84 & lpcpu*/
+ d0_mbox1: mbox@50a20000 {
+ compatible = "eswin,win2030-mailbox";
+ reg = <0 ESWIN_MAILBOX_U84_TO_LPCPU_REG_BASE 0 0x10000>,
+ <0 ESWIN_MAILBOX_LPCPU_TO_U84_REG_BASE 0 0x10000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <119>;
+ #mbox-cells = <1>;
+ clocks = <&d0_clock WIN2030_CLK_MAILBOX_2>,
+ <&d0_clock WIN2030_CLK_MAILBOX_3>;
+ clock-names = "pclk_mailbox_host", "pclk_mailbox_device";
+ resets = <&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_2>,
+ <&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_3>;
+ reset-names = "rst", "rst_device";
+ lock-bit = <ESWIN_MAILBOX_WR_LOCK_BIT_U84>;
+ irq-bit = <ESWIN_MAIBOX_LPCPU_IRQ_BIT>;
+ };
+
+ /*mailbox between u84 & npu_0*/
+ d0_mbox2: mbox@50a40000 {
+ compatible = "eswin,npu0-mailbox";
+ reg = <0 ESWIN_MAILBOX_U84_TO_NPU_0_REG_BASE 0 0x10000>,
+ <0 ESWIN_MAILBOX_NPU_0_TO_U84_REG_BASE 0 0x10000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <121>;
+ #mbox-cells = <1>;
+ clocks = <&d0_clock WIN2030_CLK_MAILBOX_4>,
+ <&d0_clock WIN2030_CLK_MAILBOX_5>;
+ clock-names = "pclk_mailbox_host", "pclk_mailbox_device";
+ resets = <&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_4>,
+ <&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_5>;
+ reset-names = "rst", "rst_device";
+ lock-bit = <ESWIN_MAILBOX_WR_LOCK_BIT_U84>;
+ irq-bit = <ESWIN_MAIBOX_NPU_0_IRQ_BIT>;
+ };
+
+ /*mailbox between u84 & npu_1*/
+ d0_mbox3: mbox@50a60000 {
+ compatible = "eswin,win2030-mailbox";
+ reg = <0 ESWIN_MAILBOX_U84_TO_NPU_1_REG_BASE 0 0x10000>,
+ <0 ESWIN_MAILBOX_NP1_0_TO_U84_REG_BASE 0 0x10000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <123>;
+ #mbox-cells = <1>;
+ clocks = <&d0_clock WIN2030_CLK_MAILBOX_6>,
+ <&d0_clock WIN2030_CLK_MAILBOX_7>;
+ clock-names = "pclk_mailbox_host", "pclk_mailbox_device";
+ resets = <&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_6>,
+ <&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_7>;
+ reset-names = "rst", "rst_device";
+ lock-bit = <ESWIN_MAILBOX_WR_LOCK_BIT_U84>;
+ irq-bit = <ESWIN_MAIBOX_NPU_1_IRQ_BIT>;
+ };
+
+ /*mailbox between u84 & dsp_0*/
+ d0_mbox4: mbox@50a80000 {
+ compatible = "eswin,dsp0-mailbox";
+ reg = <0 ESWIN_MAILBOX_U84_TO_DSP_0_REG_BASE 0 0x10000>,
+ <0 ESWIN_MAILBOX_DSP_0_TO_U84_REG_BASE 0 0x10000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <125>;
+ #mbox-cells = <1>;
+ clocks = <&d0_clock WIN2030_CLK_MAILBOX_8>,
+ <&d0_clock WIN2030_CLK_MAILBOX_9>;
+ clock-names = "pclk_mailbox_host", "pclk_mailbox_device";
+ resets = <&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_8>,
+ <&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_9>;
+ reset-names = "rst", "rst_device";
+ lock-bit = <ESWIN_MAILBOX_WR_LOCK_BIT_U84>;
+ irq-bit = <ESWIN_MAIBOX_DSP_0_IRQ_BIT>;
+ };
+
+ /*mailbox between u84 & dsp_1*/
+ d0_mbox5: mbox@50aa0000 {
+ compatible = "eswin,dsp1-mailbox";
+ reg = <0 ESWIN_MAILBOX_U84_TO_DSP_1_REG_BASE 0 0x10000>,
+ <0 ESWIN_MAILBOX_DSP_1_TO_U84_REG_BASE 0 0x10000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <127>;
+ #mbox-cells = <1>;
+ clocks = <&d0_clock WIN2030_CLK_MAILBOX_10>,
+ <&d0_clock WIN2030_CLK_MAILBOX_11>;
+ clock-names = "pclk_mailbox_host", "pclk_mailbox_device";
+ resets = <&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_10>,
+ <&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_11>;
+ reset-names = "rst", "rst_device";
+ lock-bit = <ESWIN_MAILBOX_WR_LOCK_BIT_U84>;
+ irq-bit = <ESWIN_MAIBOX_DSP_1_IRQ_BIT>;
+ };
+
+ /*mailbox between u84 & dsp_2*/
+ d0_mbox6: mbox@50ac0000 {
+ compatible = "eswin,dsp2-mailbox";
+ reg = <0 ESWIN_MAILBOX_U84_TO_DSP_2_REG_BASE 0 0x10000>,
+ <0 ESWIN_MAILBOX_DSP_2_TO_U84_REG_BASE 0 0x10000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <129>;
+ #mbox-cells = <1>;
+ clocks = <&d0_clock WIN2030_CLK_MAILBOX_12>,
+ <&d0_clock WIN2030_CLK_MAILBOX_13>;
+ clock-names = "pclk_mailbox_host", "pclk_mailbox_device";
+ resets = <&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_12>,
+ <&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_13>;
+ reset-names = "rst", "rst_device";
+ lock-bit = <ESWIN_MAILBOX_WR_LOCK_BIT_U84>;
+ irq-bit = <ESWIN_MAIBOX_DSP_2_IRQ_BIT>;
+ };
+
+ /*mailbox between u84 & dsp_3*/
+ d0_mbox7: mbox@50ae0000 {
+ compatible = "eswin,dsp3-mailbox";
+ reg = <0 ESWIN_MAILBOX_U84_TO_DSP_3_REG_BASE 0 0x10000>,
+ <0 ESWIN_MAILBOX_DSP_3_TO_U84_REG_BASE 0 0x10000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <131>;
+ #mbox-cells = <1>;
+ clocks = <&d0_clock WIN2030_CLK_MAILBOX_14>,
+ <&d0_clock WIN2030_CLK_MAILBOX_15>;
+ clock-names = "pclk_mailbox_host", "pclk_mailbox_device";
+ resets = <&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_14>,
+ <&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_15>;
+ reset-names = "rst", "rst_device";
+ lock-bit = <ESWIN_MAILBOX_WR_LOCK_BIT_U84>;
+ irq-bit = <ESWIN_MAIBOX_DSP_3_IRQ_BIT>;
+ };
+
+ d0_ipc_scpu:ipc@0 {
+ compatible = "eswin,win2030-ipc";
+ #size-cells = <2>;
+ dma-ranges = <0x0 0x80000000 0x0 0xc0000000 0x0 0x80000000>;
+ iommus = <&smmu0 WIN2030_SID_SCPU>, <&smmu0 WIN2030_SID_CRYPT>;
+ tbus = <WIN2030_TBUID_SCPU>;
+ eswin,syscfg = <&d0_sys_con SCPU_SID_REG_OFFSET 0>,
+ <&d0_sys_con CRYPT_SID_REG_OFFSET 0>;
+ mboxes = <&d0_mbox0 0>;
+ mbox-names = "u84_scpu";
+ numa-node-id = <0>;
+ };
+
+ d0_lpcpu:lpcpu@0 {
+ compatible = "eswin,win2030-lpcpu";
+ fw-region = <&lpcpu0_reserved>;
+ clocks = <&d0_clock WIN2030_CLK_CLK_LPCPU_CORE>,
+ <&d0_clock WIN2030_CLK_CLK_LPCPU_BUS>;
+ clock-names = "core_clk", "bus_clk";
+
+ reset-names = "core_rst", "bus_rst", "dbg_rst";
+ resets = <&d0_reset LPCPU_RST_CTRL SW_LPCPU_CORE_RSTN>,
+ <&d0_reset LPCPU_RST_CTRL SW_LPCPU_BUS_RSTN>,
+ <&d0_reset LPCPU_RST_CTRL SW_LPCPU_DBG_RSTN>;
+ #size-cells = <2>;
+
+ dma-ranges = <0x0 0xb0000000 0x0 0xc0000000 0x0 0x50000000>;
+ iommus = <&smmu0 WIN2030_SID_LCPU>;
+ eswin,syscfg = <&d0_sys_con LCPU_SID_REG_OFFSET 0>;
+ tbus = <WIN2030_TBUID_LPCPU>;
+ mboxes = <&d0_mbox1 0>;
+ mbox-names = "u84_lpcpu";
+ numa-node-id = <0>;
+ status = "disabled";
+ };
+
+ pvt0: pvt@0x50b00000 {
+ compatible = "eswin,eswin-pvt";
+ clocks = <&d0_clock WIN2030_CLK_PVT_CLK_0>;
+ clock-names = "pvt_clk";
+ resets = <&d0_reset PVT_RST_CTRL SW_PVT_RST_N_0>;
+ reset-names = "pvt_rst";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x50b00000 0x0 0x10000>;
+ interrupts = <349>;
+ interrupt-parent = <&plic0>;
+ status = "disabled";
+ };
+ pvt1: pvt@0x52360000 {
+ compatible = "eswin,eswin-pvt";
+ clocks = <&d0_clock WIN2030_CLK_PVT_CLK_1>;
+ clock-names = "pvt_clk";
+ resets = <&d0_reset PVT_RST_CTRL SW_PVT_RST_N_1>;
+ reset-names = "pvt_rst";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x52360000 0x0 0x20000>;
+ interrupts = <350>;
+ interrupt-parent = <&plic0>;
+ status = "disabled";
+ };
+
+ fan_control: fan_control@50b50000 {
+ compatible = "eswin-fan-control";
+ reg = <0x0 0x50b50000 0x0 0x10000>;
+ clocks = <&d0_clock WIN2030_CLK_LSP_FAN_PCLK>;
+ clock-names = "pclk";
+ resets = <&d0_reset FAN_RST_CTRL SW_FAN_RST_N>;
+ reset-names = "fan_rst";
+ interrupt-parent = <&plic0>;
+ interrupt-names = "fanirq";
+ interrupts = <354>;
+ pulses-per-revolution = <1>;
+ pwm-minimun-period = <3000000>;
+ pwms = <&pwm0 0 200>;
+ status = "disabled";
+ };
+
+ d0_i2c0: i2c@50950000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ clocks = <&d0_clock WIN2030_CLK_LSP_I2C0_PCLK>;
+ clock-names = "pclk";
+ resets = <&d0_reset I2C_RST_CTRL SW_I2C_RST_N_0>;
+ reset-names = "rst";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x50950000 0x0 0x8000>;
+ interrupts = <105>;
+ interrupt-parent = <&plic0>;
+ };
+ d0_i2c1: i2c@50960000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ clocks = <&d0_clock WIN2030_CLK_LSP_I2C1_PCLK>;
+ clock-names = "pclk";
+ resets = <&d0_reset I2C_RST_CTRL SW_I2C_RST_N_1>;
+ reset-names = "rst";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x50960000 0x0 0x10000>;
+ interrupts = <106>;
+ interrupt-parent = <&plic0>;
+ };
+ d0_i2c2: i2c@50970000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ clocks = <&d0_clock WIN2030_CLK_LSP_I2C2_PCLK>;
+ clock-names = "pclk";
+ resets = <&d0_reset I2C_RST_CTRL SW_I2C_RST_N_2>;
+ reset-names = "rst";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x50970000 0x0 0x8000>;
+ interrupts = <107>;
+ interrupt-parent = <&plic0>;
+ };
+ d0_i2c3: i2c@50980000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ clocks = <&d0_clock WIN2030_CLK_LSP_I2C3_PCLK>;
+ clock-names = "pclk";
+ resets = <&d0_reset I2C_RST_CTRL SW_I2C_RST_N_3>;
+ reset-names = "rst";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x50980000 0x0 0x8000>;
+ interrupts = <108>;
+ interrupt-parent = <&plic0>;
+ };
+ d0_i2c4: i2c@50990000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ clocks = <&d0_clock WIN2030_CLK_LSP_I2C4_PCLK>;
+ clock-names = "pclk";
+ resets = <&d0_reset I2C_RST_CTRL SW_I2C_RST_N_4>;
+ reset-names = "rst";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x50990000 0x0 0x8000>;
+ interrupts = <109>;
+ interrupt-parent = <&plic0>;
+ };
+ d0_i2c5: i2c@509a0000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ clocks = <&d0_clock WIN2030_CLK_LSP_I2C5_PCLK>;
+ clock-names = "pclk";
+ resets = <&d0_reset I2C_RST_CTRL SW_I2C_RST_N_5>;
+ reset-names = "rst";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x509a0000 0x0 0x8000>;
+ interrupts = <110>;
+ interrupt-parent = <&plic0>;
+ };
+ d0_i2c6: i2c@509b0000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ clocks = <&d0_clock WIN2030_CLK_LSP_I2C6_PCLK>;
+ clock-names = "pclk";
+ resets = <&d0_reset I2C_RST_CTRL SW_I2C_RST_N_6>;
+ reset-names = "rst";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x509b0000 0x0 0x8000>;
+ interrupts = <111>;
+ interrupt-parent = <&plic0>;
+ };
+ d0_i2c7: i2c@509c0000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ clocks = <&d0_clock WIN2030_CLK_LSP_I2C7_PCLK>;
+ clock-names = "pclk";
+ resets = <&d0_reset I2C_RST_CTRL SW_I2C_RST_N_7>;
+ reset-names = "rst";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x509c0000 0x0 0x8000>;
+ interrupts = <112>;
+ interrupt-parent = <&plic0>;
+ };
+ d0_i2c8: i2c@509d0000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ clocks = <&d0_clock WIN2030_CLK_LSP_I2C8_PCLK>;
+ clock-names = "pclk";
+ resets = <&d0_reset I2C_RST_CTRL SW_I2C_RST_N_8>;
+ reset-names = "rst";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x509d0000 0x0 0x8000>;
+ interrupts = <113>;
+ interrupt-parent = <&plic0>;
+ };
+ d0_i2c9: i2c@509e0000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ clocks = <&d0_clock WIN2030_CLK_LSP_I2C9_PCLK>;
+ clock-names = "pclk";
+ resets = <&d0_reset I2C_RST_CTRL SW_I2C_RST_N_9>;
+ reset-names = "rst";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x509e0000 0x0 0x8000>;
+ interrupts = <114>;
+ interrupt-parent = <&plic0>;
+ };
+ d0_aon_i2c0: i2c@51830000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ clocks = <&d0_clock WIN2030_CLK_AON_I2C0_PCLK>;
+ clock-names = "pclk";
+ resets = <&d0_reset I2C0_RST_CTRL SW_I2C0_PRSTN>;
+ reset-names = "rst";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x51830000 0x0 0x8000>;
+ interrupts = <290>;
+ interrupt-parent = <&plic0>;
+ eswin,i2c_dma = <&d0_aon_dmac>;
+ dma-names = "rx", "tx";
+ /*
+ * dmas : DMA specifiers
+ * &d0_aon_dmac : dma controller
+ * 41 : i2c0 aon dma handshake number
+ * 0xff : no need to select to dma controller
+ */
+ dmas = <&d0_aon_dmac 41 0xff>, <&d0_aon_dmac 42 0xff>;
+ };
+ d0_aon_i2c1: i2c@51838000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ clocks = <&d0_clock WIN2030_CLK_AON_I2C1_PCLK>;
+ clock-names = "pclk";
+ resets = <&d0_reset I2C1_RST_CTRL SW_I2C1_PRSTN>;
+ reset-names = "rst";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x51838000 0x0 0x8000>;
+ interrupts = <291>;
+ interrupt-parent = <&plic0>;
+ };
+ pinctrl: pinctrl@0x51600080 {
+ compatible = "eswin,eic7700-pinctrl";
+ reg = <0x0 0x51600080 0x0 0x1FFF80>;
+ status = "disabled";
+ pinctrl_pwm0_default: pwm0-default{
+ mux{
+ groups = "pwm0_group";
+ function = "pwm0_func";
+ };
+ conf {
+ groups = "pwm0_group";
+ drive-strength = <5>;
+ bias-pull-up = <1>;
+ input-enable = <0>;
+ };
+ };
+ pinctrl_pwm1_default: pwm1-default{
+ mux{
+ groups = "pwm1_group";
+ function = "pwm1_func";
+ };
+ conf {
+ groups = "pwm1_group";
+ drive-strength = <6>;
+ bias-pull-up = <0>;
+ input-enable = <1>;
+ };
+ };
+ pinctrl_pwm2_default: pwm2-default{
+ mux{
+ groups = "pwm2_group";
+ function = "pwm2_func";
+ };
+ conf {
+ groups = "pwm2_group";
+ drive-strength = <7>;
+ bias-pull-down = <0>;
+ input-enable = <0>;
+ };
+ };
+ };
+
+ gpio0: gpio@51600000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x0 0x51600000 0x0 0x80>;
+
+ porta: gpio-port@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-parent = <&plic0>;
+ interrupts = <303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318
+ 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334>;
+ };
+
+ portb: gpio-port@1 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <1>;
+ };
+
+ portc: gpio-port@2 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <2>;
+ };
+
+ portd: gpio-port@3 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ reg = <3>;
+ };
+ };
+ // gpio0: gpio@0x51600000 {
+ // #address-cells = <1>;
+ // #size-cells = <0>;
+ // compatible = "eswin,win2030-gpio";
+ // reg = <0x0 0x51600000 0x0 0x80>;
+ // status = "disabled";
+ // eswin,syscfg = <&d0_sys_con 0x3c0>;
+
+ // porta: gpio-port@0 {
+ // compatible = "eswin,win2030-gpio-port";
+ // gpio-controller;
+ // #gpio-cells = <2>;
+ // ngpios = <32>;
+ // reg = <0>;
+ // interrupts = <303>;
+ // interrupt-parent = <&plic0>;
+ // interrupt-state = <0 1 1 1>;
+ // direction-input = <5 8 9 16>;
+ // direction-output = <1 0 3 1>;
+ // gpio-state = <11 1 12 1>;
+ // };
+
+ // portb: gpio-port@1 {
+ // compatible = "eswin,win2030-gpio-port";
+ // gpio-controller;
+ // #gpio-cells = <2>;
+ // ngpios = <32>;
+ // reg = <1>;
+ // direction-input = <5 13 9 25>;
+ // direction-output = <26 0 3 1>;
+ // gpio-state = <11 1 17 1>;
+ // };
+
+ // portc: gpio-port@2 {
+ // compatible = "eswin,win2030-gpio-port";
+ // gpio-controller;
+ // #gpio-cells = <2>;
+ // ngpios = <32>;
+ // reg = <2>;
+ // direction-input = <5 13 9 25>;
+ // direction-output = <26 0 3 1>;
+ // gpio-state = <11 1 17 1>;
+ // };
+
+ // portd: gpio-port@3 {
+ // compatible = "eswin,win2030-gpio-port";
+ // gpio-controller;
+ // #gpio-cells = <2>;
+ // ngpios = <16>;
+ // reg = <3>;
+ // direction-input = <9 1 8 1>;
+ // direction-output = <3 1 15 1>;
+ // gpio-state = <6 1 5 1>;
+ // };
+ // };
+
+ pwm0: pwm@0x50818000 {
+ compatible = "eswin,pwm-eswin";
+ reg = <0x0 0x50818000 0x0 0x4000>;
+ clock-names = "pwm","pclk";
+ clocks = <&d0_clock WIN2030_CLK_LSP_TIMER_PCLK>;
+ clock-frequency = <200000000>;
+ resets = <&d0_reset TIMER_RST_CTRL SW_TIMER_RST_N>;
+ reset-names = "pwmrst";
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default &pinctrl_pwm2_default>;
+ status = "disabled";
+ };
+
+ wdt0: watchdog@0x50800000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0x50800000 0x0 0x4000>;
+ clocks =<&d0_clock WIN2030_CLK_LSP_WDT0_PCLK>;
+ clock-names = "pclk";
+ resets = <&d0_reset WDT_RST_CTRL SW_WDT_RST_N_0>;
+ reset-names = "rst";
+ interrupts = <87>;
+ interrupt-parent = <&plic0>;
+ status = "disabled";
+ };
+
+ wdt1: watchdog@0x50804000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0x50804000 0x0 0x4000>;
+ clocks =<&d0_clock WIN2030_CLK_LSP_WDT1_PCLK>;
+ clock-names = "pclk";
+ resets = <&d0_reset WDT_RST_CTRL SW_WDT_RST_N_1>;
+ reset-names = "rst";
+ interrupts = <88>;
+ interrupt-parent = <&plic0>;
+ status = "disabled";
+ };
+
+ wdt2: watchdog@0x50808000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0x50808000 0x0 0x4000>;
+ clocks =<&d0_clock WIN2030_CLK_LSP_WDT2_PCLK>;
+ clock-names = "pclk";
+ resets = <&d0_reset WDT_RST_CTRL SW_WDT_RST_N_2>;
+ reset-names = "rst";
+ interrupts = <89>;
+ interrupt-parent = <&plic0>;
+ status = "disabled";
+ };
+
+ wdt3: watchdog@0x5080c000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0x5080c000 0x0 0x4000>;
+ clocks =<&d0_clock WIN2030_CLK_LSP_WDT3_PCLK>;
+ clock-names = "pclk";
+ resets = <&d0_reset WDT_RST_CTRL SW_WDT_RST_N_3>;
+ reset-names = "rst";
+ interrupts = <90>;
+ interrupt-parent = <&plic0>;
+ status = "disabled";
+ };
+
+ timer0: timer@0x51840000 {
+ compatible = "eswin,eswin-timer";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x51840000 0x0 0x8000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <345>;
+ clock-names = "pclk","timer_aclk";
+ clocks = <&d0_clock WIN2030_CLK_TIMER_PCLK_0>,
+ <&d0_clock WIN2030_CLK_TIMER_CLK_0>;
+ resets = <&d0_reset TIMER0_RST_CTRL SW_TIMER0_RSTN_0>,
+ <&d0_reset TIMER0_RST_CTRL SW_TIMER0_RSTN_1>,
+ <&d0_reset TIMER0_RST_CTRL SW_TIMER0_RSTN_2>,
+ <&d0_reset TIMER0_RST_CTRL SW_TIMER0_RSTN_3>,
+ <&d0_reset TIMER0_RST_CTRL SW_TIMER0_RSTN_4>,
+ <&d0_reset TIMER0_RST_CTRL SW_TIMER0_RSTN_5>,
+ <&d0_reset TIMER0_RST_CTRL SW_TIMER0_RSTN_6>,
+ <&d0_reset TIMER0_RST_CTRL SW_TIMER0_RSTN_7>,
+ <&d0_reset TIMER0_RST_CTRL SW_TIMER0_PRSTN>;
+ reset-names = "trst0","trst1","trst2","trst3","trst4","trst5","trst6","trst7","prst";
+ };
+
+ timer1: timer@0x51848000 {
+ compatible = "eswin,eswin-timer";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x51848000 0x0 0x8000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <346>;
+ clock-names = "pclk","timer_aclk";
+ clocks = <&d0_clock WIN2030_CLK_TIMER_PCLK_1>,
+ <&d0_clock WIN2030_CLK_TIMER_CLK_1>;
+ resets = <&d0_reset TIMER1_RST_CTRL SW_TIMER1_RSTN_0>,
+ <&d0_reset TIMER1_RST_CTRL SW_TIMER1_RSTN_1>,
+ <&d0_reset TIMER1_RST_CTRL SW_TIMER1_RSTN_2>,
+ <&d0_reset TIMER1_RST_CTRL SW_TIMER1_RSTN_3>,
+ <&d0_reset TIMER1_RST_CTRL SW_TIMER1_RSTN_4>,
+ <&d0_reset TIMER1_RST_CTRL SW_TIMER1_RSTN_5>,
+ <&d0_reset TIMER1_RST_CTRL SW_TIMER1_RSTN_6>,
+ <&d0_reset TIMER1_RST_CTRL SW_TIMER1_RSTN_7>,
+ <&d0_reset TIMER1_RST_CTRL SW_TIMER1_PRSTN>;
+ reset-names = "trst0","trst1","trst2","trst3","trst4","trst5","trst6","trst7","prst";
+ };
+
+ timer2: timer@0x51850000 {
+ compatible = "eswin,eswin-timer";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x51850000 0x0 0x8000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <347>;
+ clock-names = "pclk","timer_aclk";
+ clocks = <&d0_clock WIN2030_CLK_TIMER_PCLK_2>,
+ <&d0_clock WIN2030_CLK_TIMER_CLK_2>;
+ resets = <&d0_reset TIMER2_RST_CTRL SW_TIMER2_RSTN_0>,
+ <&d0_reset TIMER2_RST_CTRL SW_TIMER2_RSTN_1>,
+ <&d0_reset TIMER2_RST_CTRL SW_TIMER2_RSTN_2>,
+ <&d0_reset TIMER2_RST_CTRL SW_TIMER2_RSTN_3>,
+ <&d0_reset TIMER2_RST_CTRL SW_TIMER2_RSTN_4>,
+ <&d0_reset TIMER2_RST_CTRL SW_TIMER2_RSTN_5>,
+ <&d0_reset TIMER2_RST_CTRL SW_TIMER2_RSTN_6>,
+ <&d0_reset TIMER2_RST_CTRL SW_TIMER2_RSTN_7>,
+ <&d0_reset TIMER2_RST_CTRL SW_TIMER2_PRSTN>;
+ reset-names = "trst0","trst1","trst2","trst3","trst4","trst5","trst6","trst7","prst";
+ };
+
+ timer3: timer@0x51858000 {
+ compatible = "eswin,eswin-timer";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x51858000 0x0 0x8000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <348>;
+ clock-names = "pclk","timer_aclk","timer3_clk8";
+ clocks = <&d0_clock WIN2030_CLK_TIMER_PCLK_3>,
+ <&d0_clock WIN2030_CLK_TIMER_CLK_3>,
+ <&d0_clock WIN2030_CLK_TIMER3_CLK8>;
+ resets = <&d0_reset TIMER3_RST_CTRL SW_TIMER3_RSTN_0>,
+ <&d0_reset TIMER3_RST_CTRL SW_TIMER3_RSTN_1>,
+ <&d0_reset TIMER3_RST_CTRL SW_TIMER3_RSTN_2>,
+ <&d0_reset TIMER3_RST_CTRL SW_TIMER3_RSTN_3>,
+ <&d0_reset TIMER3_RST_CTRL SW_TIMER3_RSTN_4>,
+ <&d0_reset TIMER3_RST_CTRL SW_TIMER3_RSTN_5>,
+ <&d0_reset TIMER3_RST_CTRL SW_TIMER3_RSTN_6>,
+ <&d0_reset TIMER3_RST_CTRL SW_TIMER3_RSTN_7>,
+ <&d0_reset TIMER3_RST_CTRL SW_TIMER3_PRSTN>;
+ reset-names = "trst0","trst1","trst2","trst3","trst4","trst5","trst6","trst7","prst";
+ };
+
+ die0_rtc: rtc@51818000 {
+ compatible = "eswin,win2030-rtc";
+ reg = <0x0 0x51818000 0x0 0x400>;
+ eswin,syscfg = <&d0_sys_con 0x3c0>;
+ interrupt-parent = <&plic0>;
+ interrupts = <292>;
+ clocks = <&d0_clock WIN2030_CLK_CLK_RTC>;
+ clock-names = "rtcclk";
+ clock-frequency = <15624>;
+ resets = <&d0_reset RTC_RST_CTRL SW_RTC_RSTN>;
+ reset-names = "rtcrst";
+ status = "disabled";
+ };
+
+ d0_i2s0: i2s0@50200000 {
+ //compatible = "eswin,i2s-dsp";
+ compatible = "snps,i2s";
+ clocks = <&d0_clock WIN2030_CLK_VO_I2S_MCLK>;
+ clock-names = "mclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <0x00000000>;
+ reg = <0x0 0x50200000 0x0 0x10000>;
+ dma-names = "rx", "tx";
+ dmas = <&d0_aon_dmac 4 0>, <&d0_aon_dmac 5 0>;
+ memory-region = <&dsp_reserved1>;
+ vo_mclk_sel,syscrg = <&d0_sys_crg 0x1bc>;
+ resets = <&d0_reset VO_I2SRST_CTRL SW_VO_I2S_RSTN>,
+ <&d0_reset VO_I2SRST_CTRL SW_VO_I2S_PRSTN>,
+ <&d0_reset VO_PHYRST_CTRL SW_VO_PRSTN>;
+ reset-names = "i2srst", "i2sprst", "voprst";
+ };
+
+ d0_i2s1: i2s1@50210000 {
+ compatible = "snps,i2s";
+ clocks = <&d0_clock WIN2030_CLK_VO_I2S_MCLK>;
+ clock-names = "mclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <0x00000000>;
+ reg = <0x0 0x50210000 0x0 0x10000>;
+ dma-names = "rx", "tx";
+ dmas = <&d0_aon_dmac 2 1>, <&d0_aon_dmac 3 1>;
+ vo_mclk_sel,syscrg = <&d0_sys_crg 0x1bc>;
+ resets = <&d0_reset VO_I2SRST_CTRL SW_VO_I2S_RSTN>,
+ <&d0_reset VO_I2SRST_CTRL SW_VO_I2S_PRSTN>,
+ <&d0_reset VO_PHYRST_CTRL SW_VO_PRSTN>;
+ reset-names = "i2srst", "i2sprst", "voprst";
+ };
+
+ d0_i2s2: i2s2@50220000 {
+ compatible = "snps,i2s";
+ clocks = <&d0_clock WIN2030_CLK_VO_I2S_MCLK>;
+ clock-names = "mclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <0x00000000>;
+ reg = <0x0 0x50220000 0x0 0x10000>;
+ dma-names = "rx", "tx";
+ dmas = <&d0_aon_dmac 0 2>, <&d0_aon_dmac 1 2>;
+ vo_mclk_sel,syscrg = <&d0_sys_crg 0x1bc>;
+ resets = <&d0_reset VO_I2SRST_CTRL SW_VO_I2S_RSTN>,
+ <&d0_reset VO_I2SRST_CTRL SW_VO_I2S_PRSTN>,
+ <&d0_reset VO_PHYRST_CTRL SW_VO_PRSTN>;
+ reset-names = "i2srst", "i2sprst", "voprst";
+ };
+
+ d0_soundcard: soundcard {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "Eswin sound card";
+ simple-audio-card,widgets = "Headphone", "Headphone Jack";
+ simple-audio-card,dai-link@0 {
+ format = "i2s";
+ cpu {
+ sound-dai = <&d0_sofdsp 0>;
+ };
+ codec {
+ sound-dai = <&d0_thruout 0>;
+ };
+ };
+
+ simple-audio-card,dai-link@1 {
+ format = "i2s";
+ cpu {
+ sound-dai = <&d0_sofdsp 1>;
+ };
+ codec {
+ sound-dai = <&d0_thruout 1>;
+ };
+ };
+
+ simple-audio-card,dai-link@2 {
+ format = "i2s";
+ cpu {
+ sound-dai = <&d0_i2s0>;
+ };
+ codec {
+ //sound-dai = <&d0_es8316>;
+ //system-clock-frequency = <12288000>;
+ };
+ plat {
+ sound-dai = <&d0_sofdsp 2>;
+ };
+ };
+ };
+
+ d0_graphcard0: graphcard0 {
+ compatible = "audio-graph-card";
+ };
+
+ d0_graphcard1: graphcard1 {
+ compatible = "audio-graph-card";
+ };
+
+ d0_graphcard2: graphcard2 {
+ compatible = "audio-graph-card";
+ };
+
+ video_output: display-subsystem {
+ compatible = "verisilicon,display-subsystem";
+ ports = <&dc_out>;
+ };
+
+ dvb_widgets: dvb-subsystem {
+ compatible = "amlogic,dvb_widgets";
+ status = "disabled";
+ };
+
+ dc8k: dc8000@502c0000 {
+ compatible = "verisilicon,dc8000";
+ reg = <0x0 0x502c0000 0x0 0x100>, <0x0 0x502c0180 0x0 0x700>, <0x0 0x502c1400 0x0 0x1400>;
+ interrupt-parent = <&plic0>;
+ interrupts = <238>;
+
+ clocks = <&d0_clock WIN2030_CLK_VO_CFG_CLK>,
+ <&d0_clock WIN2030_CLK_VO_PIXEL_CLK>,
+ <&d0_clock WIN2030_CLK_VO_ACLK>,
+ <&d0_clock WIN2030_SPLL0_FOUT1>,
+ <&d0_clock WIN2030_MUX_U_VO_ACLK_ROOT_2MUX1_GFREE>;
+ clock-names = "cfg_clk", "pix_clk", "axi_clk", "spll0_fout1", "vo_mux";
+ resets = <&d0_reset VO_RST_CTRL SW_VO_AXI_RSTN>,
+ <&d0_reset VO_RST_CTRL SW_VO_CFG_RSTN>,
+ <&d0_reset VO_RST_CTRL SW_VO_DC_RSTN>,
+ <&d0_reset VO_RST_CTRL SW_VO_DC_PRSTN>;
+ reset-names = "vo_arst", "vo_prst", "dc_arst", "dc_prst";
+
+ dc_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dc_out_dpi0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dsi_input0>;
+ };
+
+ dc_out_dpi1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vd_input>;
+ };
+
+ dc_out_hdmi: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&hdmi_in_dc8k>;
+ };
+ };
+ };
+
+ virtual_display: vs_wb {
+ compatible = "verisilicon,virtual_display";
+ bpp = /bits/ 8 <8>;
+
+ port {
+ vd_input: endpoint {
+ remote-endpoint = <&dc_out_dpi1>;
+ };
+ };
+ };
+
+ dsi_output: dsi-output {
+ compatible = "verisilicon,dsi-encoder";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* input */
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ dsi_input0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dc_out_dpi0>;
+ };
+ };
+
+ /* output */
+ port@1 {
+ reg = <1>;
+ dsi_out:endpoint {
+ remote-endpoint = <&mipi_dsi_in>;
+ };
+ };
+ };
+ };
+
+ dsi_controller: mipi_dsi@50270000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "verisilicon,dw-mipi-dsi";
+ reg = <0x0 0x50270000 0x0 0x10000>;
+ clocks = <&d0_clock WIN2030_CLK_CLK_MIPI_TXESC>;
+ clock-names = "pclk";
+
+ /*
+ phys = <&dphy>;
+ phy-names = "dphy";
+ */
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ mipi_dsi_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mipi_dsi_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+
+ panel@1 {
+ compatible = "eswin,generic-panel";
+ reg = <0>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&mipi_dsi_out>;
+ };
+ };
+ };
+ };
+
+ dc8k_test: dc8ktest@502c0000 {
+ compatible = "eswin,dc8000";
+ reg = <0x0 0x502c0000 0x0 0x10000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <238>;
+ };
+
+ dw_hdmi: hdmi@502a0000 {
+ compatible = "eswin,eswin-dw-hdmi";
+ reg = <0x0 0x502a0000 0x0 0x20000>;
+ pinctrl-names = "default";
+ //pinctrl-0 = <&hdmi_i2c_xfer>;
+ interrupt-parent = <&plic0>;
+ interrupts = <274>;
+ clocks = <&d0_clock WIN2030_CLK_VO_CFG_CLK>, <&d0_clock WIN2030_CLK_VO_PIXEL_CLK>,
+ <&d0_clock WIN2030_CLK_VO_CEC_CLK>, <&d0_clock WIN2030_CLK_VO_CR_CLK>;
+ clock-names = "iahb", "vpll", "cec", "isfr";
+ //power-domains = <&power WIN2030_PD_HDCP>;
+ reg-io-width = <4>;
+ ddc-i2c-scl-high-time-ns = <4708>;
+ ddc-i2c-scl-low-time-ns = <4916>;
+ #sound-dai-cells = <0>;
+ resets = <&d0_reset VO_PHYRST_CTRL SW_VO_HDMI_PRSTN>,
+ <&d0_reset VO_PHYRST_CTRL SW_HDMI_PHYCTRL_RSTN>,
+ <&d0_reset VO_PHYRST_CTRL SW_VO_HDMI_RSTN>;
+ reset-names = "prstn", "phyrstn", "rstn";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ hdmi_in_dc8k: endpoint@0 {
+ remote-endpoint = <&dc_out_hdmi>;
+ };
+ };
+ };
+ };
+
+ dw_hdmi_hdcp2: hdmi-hdcp2@50290000 {
+ compatible = "eswin,dw-hdmi-hdcp2";
+ reg = <0x0 0x50290000 0x0 0x10000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <275>;
+ clocks = <&d0_clock WIN2030_CLK_VO_CFG_CLK>,
+ <&d0_clock WIN2030_CLK_VO_HDMI_IESMCLK>;
+ clock-names ="pclk_hdcp2", "hdcp2_clk_hdmi";
+ };
+
+ d0_dummy_codec:codec@0x50230000 {
+ reg = <0x00000000 0x50230000 0x00000000 0x00000100>;
+ #sound-dai-cells = <0x00000000>;
+ compatible = "eswin_dummy_codec";
+ };
+ d0_thruout: thru-out {
+ compatible = "eswin,thru-out";
+ #sound-dai-cells = <1>;
+ memory-region = <&dsp_reserved1>;
+ };
+ d0_dummy_pf: dummy@0x50400000{
+ compatible = "eswin,dummy-dai";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <0x00000000>;
+ reg = <0x0 0x50400000 0x0 0x10000>;
+ status = "disabled";
+ };
+
+ d0_usbdrd3_0: usb0@50480000 {
+ compatible = "eswin,win2030-dwc3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ clocks =<&d0_clock WIN2030_GATE_HSP_USB0_SUSPEND_CLK>;
+ clock-names = "suspend";
+ eswin,hsp_sp_csr = <&d0_hsp_sp_csr 0x800 0x808 0x83c 0x840>;
+ resets = <&d0_reset HSPDMA_RST_CTRL SW_USB0_VAUX_RSTN>;
+ reset-names = "vaux";
+ ranges;
+ status = "disabled";
+ d0_usbdrd_dwc3_0: dwc3@50480000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x50480000 0x0 0x10000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&plic0>;
+ interrupts = <85>;
+ interrupt-names = "peripheral";
+ dr_mode = "peripheral";
+ phy_type = "utmi";
+ maximum-speed = "high-speed";
+ iommus = <&smmu0 WIN2030_SID_USB0>;
+ eswin,hsp_sp_csr = <&d0_hsp_sp_csr 0x1044>;
+ dma-ranges = <0x0 0x0 0x0 0xc0000000 0x200 0x0>;
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,tx-ipgap-linecheck-dis-quirk;
+ snps,xhci-slow-suspend-quirk;
+ snps,xhci-trb-ent-quirk;
+ snps,usb3-warm-reset-on-resume-quirk;
+ status = "disabled";
+ numa-node-id = <0>;
+ tbus = <WIN2030_TBUID_USB>;
+ };
+ };
+
+ d0_usbdrd3_1: usb1@50490000 {
+ compatible = "eswin,win2030-dwc3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ clocks =<&d0_clock WIN2030_GATE_HSP_USB1_SUSPEND_CLK>;
+ clock-names = "suspend";
+ eswin,hsp_sp_csr = <&d0_hsp_sp_csr 0x900 0x908 0x93c 0x940>;
+ resets = <&d0_reset HSPDMA_RST_CTRL SW_USB1_VAUX_RSTN>;
+ reset-names = "vaux";
+ ranges;
+ status = "disabled";
+ d0_usbdrd_dwc3_1: dwc3@50490000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x50490000 0x0 0x10000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&plic0>;
+ interrupts = <86>;
+ interrupt-names = "host";
+ dr_mode = "host";
+ phy_type = "utmi";
+ maximum-speed = "high-speed";
+ iommus = <&smmu0 WIN2030_SID_USB1>;
+ eswin,hsp_sp_csr = <&d0_hsp_sp_csr 0x1048>;
+ dma-ranges = <0x0 0x0 0x0 0xc0000000 0x200 0x0>;
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,tx-ipgap-linecheck-dis-quirk;
+ snps,xhci-slow-suspend-quirk;
+ snps,xhci-trb-ent-quirk;
+ snps,usb3-warm-reset-on-resume-quirk;
+ status = "disabled";
+ numa-node-id = <0>;
+ tbus = <WIN2030_TBUID_USB>;
+ };
+ };
+
+ vi_top_csr: vi_common_top_csr@0x51030000 {
+ compatible = "esw,vi-common-csr", "syscon";
+ clocks = <&d0_clock WIN2030_CLK_VI_ACLK>,
+ <&d0_clock WIN2030_CLK_VI_CFG_CLK>,
+ <&d0_clock WIN2030_CLK_VI_DIG_ISP_CLK>,
+ <&d0_clock WIN2030_CLK_VI_DVP_CLK>,
+ <&d0_clock WIN2030_CLK_VI_PHY_CFG>,
+ <&d0_clock WIN2030_CLK_VI_PHY_TXCLKESC>,
+ <&d0_clock WIN2030_CLK_VI_SHUTTER_0>,
+ <&d0_clock WIN2030_CLK_VI_SHUTTER_1>,
+ <&d0_clock WIN2030_CLK_VI_SHUTTER_2>,
+ <&d0_clock WIN2030_CLK_VI_SHUTTER_3>,
+ <&d0_clock WIN2030_CLK_VI_SHUTTER_4>,
+ <&d0_clock WIN2030_CLK_VI_SHUTTER_5>,
+ <&d0_clock WIN2030_MUX_U_VI_ACLK_ROOT_2MUX1_GFREE>,
+ <&d0_clock WIN2030_MUX_U_VI_DVP_ROOT_2MUX1_GFREE>,
+ <&d0_clock WIN2030_MUX_U_VI_DIG_ISP_ROOT_2MUX1_GFREE>,
+ <&d0_clock WIN2030_SPLL0_FOUT1>,
+ <&d0_clock WIN2030_VPLL_FOUT1>;
+ clock-names = "aclk", "cfg_clk", "isp_aclk", "dvp_clk", "phy_cfg",
+ "phy_escclk", "sht0", "sht1", "sht2", "sht3", "sht4",
+ "sht5", "aclk_mux", "dvp_mux", "isp_mux", "spll0_fout1", "vpll_fout1";
+ resets = <&d0_reset VI_RST_CTRL SW_VI_AXI_RSTN>,
+ <&d0_reset VI_RST_CTRL SW_VI_CFG_RSTN>,
+ <&d0_reset ISP0_RST_CTRL SW_VI_ISP0_RSTN>,
+ <&d0_reset ISP1_RST_CTRL SW_VI_ISP1_RSTN>,
+ <&d0_reset DVP_RST_CTRL SW_VI_DVP_RSTN>,
+ <&d0_reset SHUTTER_RST_CTRL SW_VI_SHUTTER_RSTN_0>,
+ <&d0_reset SHUTTER_RST_CTRL SW_VI_SHUTTER_RSTN_1>,
+ <&d0_reset SHUTTER_RST_CTRL SW_VI_SHUTTER_RSTN_2>,
+ <&d0_reset SHUTTER_RST_CTRL SW_VI_SHUTTER_RSTN_3>,
+ <&d0_reset SHUTTER_RST_CTRL SW_VI_SHUTTER_RSTN_4>,
+ <&d0_reset SHUTTER_RST_CTRL SW_VI_SHUTTER_RSTN_5>;
+ reset-names = "axi", "cfg", "isp0", "isp1", "dvp", "sht0", "sht1", "sht2", "sht3", "sht4", "sht5";
+
+ id = <0>;
+ #size-cells = <2>;
+ reg = <0x0 0x51030000 0x0 0x10000>;
+ };
+
+ isp_0: isp@0x51000000 {
+ compatible = "esw,win2030-isp";
+
+ reg = <0x0 0x51000000 0x0 0x10000>;
+ interrupts = <21 19 20>;
+ interrupt-parent = <&plic0>;
+ id = <0>;
+ #size-cells = <2>;
+ dma-ranges = <0x0 0x20000000 0x0 0x80000000 0x0 0x40000000>;
+ iommus = <&smmu0 WIN2030_SID_ISP0>;
+ tbus = <WIN2030_TBUID_ISP>;
+ eswin,vi_top_csr = <&vi_top_csr 0x1000>;
+ numa-node-id = <0>;
+ };
+
+ isp_1: isp@0x51010000 {
+ compatible = "esw,win2030-isp";
+
+ reg = <0x0 0x51010000 0x0 0x10000>;
+ interrupts = <24 22 23>;
+ interrupt-parent = <&plic0>;
+ id = <1>;
+ #size-cells = <2>;
+ dma-ranges = <0x0 0x20000000 0x0 0x80000000 0x0 0x40000000>;
+ iommus = <&smmu0 WIN2030_SID_ISP1>;
+ tbus = <WIN2030_TBUID_ISP>;
+ eswin,vi_top_csr = <&vi_top_csr 0x1004>;
+ numa-node-id = <0>;
+ };
+
+ dw200: dw200@51020000 {
+ compatible = "eswin,dw200";
+ clocks = <&d0_clock WIN2030_CLK_VI_ACLK>,
+ <&d0_clock WIN2030_CLK_VI_CFG_CLK>,
+ <&d0_clock WIN2030_CLK_VI_DIG_DW_CLK>,
+ <&d0_clock WIN2030_MUX_U_VI_ACLK_ROOT_2MUX1_GFREE>,
+ <&d0_clock WIN2030_MUX_U_VI_DW_ROOT_2MUX1>,
+ <&d0_clock WIN2030_SPLL0_FOUT1>,
+ <&d0_clock WIN2030_VPLL_FOUT1>;
+ clock-names = "aclk", "cfg_clk", "dw_aclk", "aclk_mux", "dw_mux", "spll0_fout1", "vpll_fout1";
+ resets = <&d0_reset VI_RST_CTRL SW_VI_AXI_RSTN>,
+ <&d0_reset VI_RST_CTRL SW_VI_CFG_RSTN>,
+ <&d0_reset VI_RST_CTRL SW_VI_DWE_RSTN>;
+ reset-names = "axi", "cfg", "dwe";
+
+ interrupt-parent = <&plic0>;
+ interrupts = <26 25>;
+ #size-cells = <2>;
+ dma-ranges = <0x0 0x20000000 0x0 0x80000000 0x0 0x40000000>;
+ iommus = <&smmu0 WIN2030_SID_DW>;
+ tbus = <WIN2030_TBUID_DW>;
+ eswin,vi_top_csr = <&vi_top_csr 0x1008>;
+ reg = <0x0 0x51020000 0x0 0xc00>, <0x0 0x51020c00 0x0 0x120>;
+ numa-node-id = <0>;
+ };
+
+ mipi_dphy_rx: dphy@510c0000 {
+ compatible = "snps,dw-dphy-rx";
+ #phy-cells = <1>;
+ bus-width = <8>;
+ snps,dphy-frequency = <300000>;
+ snps,phy_type = <8>;
+ reg = <0x0 0x510c0000 0x0 0x20000>;
+ numa-node-id = <0>;
+ };
+
+ csi_dma0: csidma@0x52048000 {
+ compatible = "eswin,csi-video";
+ interrupt-parent = <&plic0>;
+ interrupts = <29>;
+ reg = <0x0 0x52048000 0x0 0x1000>;
+ numa-node-id = <0>;
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi_dmar_0: endpoint@0 {
+ reg = <0>;
+ bus-type = <4>;
+ remote-endpoint = <&csi2_dma_0_3>;
+ };
+ };
+ };
+
+ csi_dma1: csidma@0x52058000 {
+ compatible = "eswin,csi-video";
+ interrupt-parent = <&plic0>;
+ interrupts = <30>;
+ reg = <0x0 0x52058000 0x0 0x1000>;
+ numa-node-id = <0>;
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi_dmar_1: endpoint@0 {
+ reg = <0>;
+ bus-type = <4>;
+ remote-endpoint = <&csi2_dma_1_3>;
+ };
+ };
+ };
+
+ csi2_0: csi2@51050000 {
+ compatible = "snps,dw-csi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&plic0>;
+ interrupts = <29>;
+ snps,output-type = <0>;
+ reg = <0x0 0x51050000 0x0 0x1000>;
+ /*phys = <&mipi_dphy_rx 1>;*/
+ numa-node-id = <0>;
+
+ /* MIPI CONFIG */
+ snps,en-ppi-width = <0>;/* 0: ppi8, 1: ppi16 */
+ snps,en-phy-mode = <0>;/* 0: D-PHY, 1: C-PHY */
+
+ ipi2_en = <0>;/* for virtual channel */
+ ipi2_vcid = <0>;/* virtual channel id */
+ ipi3_en = <0>;
+ ipi3_vcid = <0>;
+
+ #ifdef MIPI_CSI2_IMX290_ENBALE
+ port@1 {
+ reg = <1>;
+ csi2_0_1: endpoint {
+ bus-type = <4>;
+ clock-lanes = <0>;
+ #ifdef MIPI_CSI2_2LINE_ENABLE
+ data-lanes = <1 2>;
+ #else
+ data-lanes = <1 2 3 4>;
+ #endif
+ //remote-endpoint = <&imx290_csi2>;
+ };
+ };
+ #endif
+
+ port@2 {
+ reg = <2>;
+ csi2_dma_0_3: endpoint {
+ bus-type = <5>;
+ remote-endpoint = <&csi_dmar_0>;
+ };
+ };
+ };
+
+ csi2_1: csi2@51060000 {
+ compatible = "snps,dw-csi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&plic0>;
+ interrupts = <30>;
+ snps,output-type = <0>;
+ reg = <0x0 0x51060000 0x0 0x1000>;
+ /*phys = <&mipi_dphy_rx 1>;*/
+ numa-node-id = <0>;
+
+ /* MIPI CONFIG */
+ snps,en-ppi-width = <0>;/* 0: ppi8, 1: ppi16 */
+ snps,en-phy-mode = <0>;/* 0: D-PHY, 1: C-PHY */
+
+ ipi2_en = <0>;/* for virtual channel */
+ ipi2_vcid = <0>;/* virtual channel id */
+ ipi3_en = <0>;
+ ipi3_vcid = <0>;
+
+ #ifdef MIPI_CSI2_IMX290_ENBALE
+ port@1 {
+ reg = <1>;
+ csi2_1_1: endpoint {
+ bus-type = <4>;
+ clock-lanes = <0>;
+ #ifdef MIPI_CSI2_2LINE_ENABLE
+ data-lanes = <1 2>;
+ #else
+ data-lanes = <1 2 3 4>;
+ #endif
+ //remote-endpoint = <&imx290_csi2>;
+ };
+ };
+ #endif
+
+ port@2 {
+ reg = <2>;
+ csi2_dma_1_3: endpoint {
+ bus-type = <5>;
+ remote-endpoint = <&csi_dmar_1>;
+ };
+ };
+ };
+
+ dc8k_test: dc8ktest@502c0000 {
+ compatible = "eswin,dc8000";
+ reg = <0x0 0x502c0000 0x0 0x10000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <238>;
+ };
+
+ d0_numa_sample:numa_sample@0 {
+ compatible = "eswin,numa-sample","simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-ranges = <0x0 0x80000000 0x0 0xc0000000 0x0 0x80000000>;
+ iommus = <&smmu0 WIN2030_SID_SCPU>;
+ tbus = <WIN2030_TBUID_0xF00>;
+ numa-node-id = <0>;
+ status = "disabled";
+ };
+
+ ddr0: ddr-controller@0 {
+ compatible = "eswin,ddrc-1.20a";
+ interrupt-parent = <&plic0>;
+ interrupts = <10>;
+ interrupt-names = "ddr-ecc";
+ reg = <0x0 0x52300000 0x0 0x40000>;
+ ctrl-id = <0>;
+ status = "disabled";
+ };
+
+ ddr1: ddr-controller@1 {
+ compatible = "eswin,ddrc-1.20a";
+ interrupt-parent = <&plic0>;
+ interrupts = <299>;
+ interrupt-names = "ddr-ecc";
+ reg = <0x0 0x52380000 0x0 0x40000>;
+ ctrl-id = <1>;
+ status = "disabled";
+ };
+};
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-noc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-noc.dtsi
new file mode 100644
index 000000000000..e1f621d9889e
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-noc.dtsi
@@ -0,0 +1,2804 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Include file for Die1 NOC monitor of Eswin EIC770x family SoC.
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ */
+
+d1_cfg_noc:d1_cfg_noc{
+ compatible = "eswin,win2030-noc";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ reg = <0 0x72060000 0 0x4000>;
+
+ interrupts = <446>;
+ interrupt-names = "error";
+ interrupt-parent = <&plic1>;
+ errlogger,idx = <0 1 3 5>;
+
+ sideband_manager@72061000{
+ compatible = "eswin,win2xxx-noc-sideband-manager";
+ reg = <0 0x72061000 0 0x10>;
+ SenseIn0 =
+ <SBM_CLMM OFFSET0>,
+ <SBM_CNOC_AON OFFSET1>,
+ <SBM_CNOC_DDRT0_CTRL OFFSET2>,
+ <SBM_CNOC_DDRT0_PHY OFFSET3>,
+ <SBM_CNOC_DDRT1_CTRL OFFSET4>,
+ <SBM_CNOC_DDRT1_PHY OFFSET5>,
+ <SBM_CNOC_DSPT OFFSET6>,
+ <SBM_CNOC_GPU OFFSET7>,
+ <SBM_CNOC_HSP OFFSET8>,
+ <SBM_CNOC_LSP_APB2 OFFSET9>,
+ <SBM_CNOC_LSP_APB3 OFFSET10>,
+ <SBM_CNOC_LSP_APB4 OFFSET11>,
+ <SBM_CNOC_LSP_APB6 OFFSET12>,
+ <SBM_CNOC_MCPUT_D2D OFFSET13>,
+ <SBM_CNOC_NPU OFFSET14>,
+ <SBM_CNOC_PCIET_P OFFSET15>,
+ <SBM_CNOC_PCIET_X OFFSET16>,
+ <SBM_CNOC_TCU OFFSET17>,
+ <SBM_CNOC_VC OFFSET18>,
+ <SBM_CNOC_VI OFFSET19>,
+ <SBM_CNOC_VO OFFSET20>;
+ bf-name =
+ "SBM_CLMM",
+ "SBM_CNOC_AON",
+ "SBM_CNOC_DDRT0_CTRL",
+ "SBM_CNOC_DDRT0_PHY ",
+ "SBM_CNOC_DDRT1_CTRL",
+ "SBM_CNOC_DDRT1_PHY",
+ "SBM_CNOC_DSPT",
+ "SBM_CNOC_GPU",
+ "SBM_CNOC_HSP",
+ "SBM_CNOC_LSP_APB2",
+ "SBM_CNOC_LSP_APB3",
+ "SBM_CNOC_LSP_APB4",
+ "SBM_CNOC_LSP_APB6",
+ "SBM_CNOC_MCPUT_D2D",
+ "SBM_CNOC_NPU",
+ "SBM_CNOC_PCIET_P",
+ "SBM_CNOC_PCIET_X",
+ "SBM_CNOC_TCU",
+ "SBM_CNOC_VC",
+ "SBM_CNOC_VI",
+ "SBM_CNOC_VO";
+ };
+ ErrorLogger0 {
+ compatible = "eswin,win2030,register";
+ offset,length = < 0x14 32 >;
+ description = "Register 0 to log errors";
+ lock {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0 1>;
+ lut = "Not Locked", "Locked";
+ };
+ OpCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 1 4>;
+ lut = "RD: data read with incrementing address",
+ "RDW: data read with wrapping address",
+ "RDL: allocates monitor in the Target with incrementing address",
+ "RDX: exclusive read with incrementing address",
+ "WR: data write with incrementing address",
+ "WRW: data write with wrapping address",
+ "WRC: conditional write if matching monitor in Target is found",
+ "RSV: reserved",
+ "PRE: preamble packet of linked sequence (locked sequence)",
+ "URG: urgency packet used for QoS (status must be REQ)";
+ };
+ ErrCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 8 3 >;
+ lut = "SLV (error source: Target): error detected by the Slave without any information or no Error",
+ "DEC (error source: Initiator NIU): decode error",
+ "UNS (error source: Target NIU): unsupported access type",
+ "DISC (error source: Power Disconnect): disconnected Target or NoC domain",
+ "SEC (error source: Initiator NIU or Firewall): security error",
+ "HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator",
+ "TMO (error source: Target NIU): time-out",
+ "RSV: reserved";
+
+ };
+ Len1 {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 16 12 >;
+ };
+ Format {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 31 1 >;
+ lut = "NTTP v3.0 (Invalid)", "NTTP v3.5 (Ok)";
+ };
+ };
+
+ ErrorLogger1 {
+ compatible = "eswin,win2030,register", "eswin,win2030,noc,filter,routeid";
+ offset,length = < 0x18 32>;
+ description = "Register 1 to log errors";
+ InitFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 15 1 >; /*bit 15 will aloways be 0, then we will always get "snoc_cnoc/I/0"*/
+ lut =
+ "snoc_cnoc/I/0";
+ };
+
+ TargetFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 10 5 >;
+ lut =
+ "clmm/T/0",
+ "cnoc_aon/T/0",
+ "cnoc_ddrt0_ctrl/T/0",
+ "cnoc_ddrt0_phy/T/0",
+ "cnoc_ddrt1_ctrl/T/0",
+ "cnoc_ddrt1_phy/T/0",
+ "cnoc_dspt/T/0",
+ "cnoc_gpu/T/0",
+ "cnoc_hsp/T/0",
+ "cnoc_lsp_apb2/T/0",
+ "cnoc_lsp_apb3/T/0",
+ "cnoc_lsp_apb4/T/0",
+ "cnoc_lsp_apb6/T/0",
+ "cnoc_mcput_d2d/T/0",
+ "cnoc_npu/T/0",
+ "cnoc_pciet_p/T/0",
+ "cnoc_pciet_x/T/0",
+ "cnoc_service/T/0",
+ "cnoc_tcu/T/0",
+ "cnoc_vc/T/0",
+ "cnoc_vi/T/0",
+ "cnoc_vo/T/0",
+ "RESERVED",
+ "RESERVED",
+ "RESERVED",
+ "RESERVED",
+ "RESERVED",
+ "RESERVED",
+ "RESERVED",
+ "RESERVED",
+ "RESERVED",
+ "RESERVED";
+ };
+
+ TargetSubRange {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 8 2 >;
+ };
+
+ SeqId {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0 8 >;
+ };
+ };
+
+ ErrorLogger3 {
+ /* This register does not really include a bitfield or its bitfield is 32 bits and it provides an offset address */
+ /* To calculate the absolute address, you must use the initflow:targetflow:subrange from ErrorLogger1 register */
+ /* And use it as an index in the aperture table. Then you must add the value of this register to the value given */
+ /* by the table to get the absolute address. */
+ compatible = "eswin,win2030,register";
+ offset,length = <0x20 32>;
+ description = "Register 3 to log errors";
+ aperture-link = <1>; /* link to ErrorLogger1 whose information are required to calculate real absolute address */
+ AbsoluteAddress {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 8 8 >; /* bitfield initflow:targeflow:subrange from aperture-link register */
+ aperture-size= < 46 >; /* Number of line in the aperture table below */
+ aperture-idx,aperture-base = /* Aperture_idx is concatenation of initflow:targetflow:subrange bitfield from ErrorLogger1 */
+ /bits/ 64 <0x0 0x0 0x0 0x51600000>,
+ /bits/ 64 <0x0 0x0 0x1 0x71600000>,
+ /bits/ 64 <0x0 0x1 0x0 0x51800000>,
+ /bits/ 64 <0x0 0x1 0x1 0x71800000>,
+ /bits/ 64 <0x0 0x1 0x2 0x0 >,
+ /bits/ 64 <0x0 0x1 0x3 0x0 >,
+ /bits/ 64 <0x0 0x2 0x0 0x52300000>,
+ /bits/ 64 <0x0 0x2 0x1 0x72300000>,
+ /bits/ 64 <0x0 0x3 0x0 0x53000000>,
+ /bits/ 64 <0x0 0x3 0x1 0x73000000>,
+ /bits/ 64 <0x0 0x4 0x0 0x52380000>,
+ /bits/ 64 <0x0 0x4 0x1 0x72380000>,
+ /bits/ 64 <0x0 0x5 0x0 0x53800000>,
+ /bits/ 64 <0x0 0x5 0x1 0x73800000>,
+ /bits/ 64 <0x0 0x6 0x0 0x52200000>,
+ /bits/ 64 <0x0 0x6 0x1 0x72200000>,
+ /bits/ 64 <0x0 0x7 0x0 0x51400000>,
+ /bits/ 64 <0x0 0x7 0x1 0x71400000>,
+ /bits/ 64 <0x0 0x8 0x0 0x50400000>,
+ /bits/ 64 <0x0 0x8 0x1 0x70400000>,
+ /bits/ 64 <0x0 0x9 0x0 0x50800000>,
+ /bits/ 64 <0x0 0x9 0x1 0x70800000>,
+ /bits/ 64 <0x0 0xa 0x0 0x50900000>,
+ /bits/ 64 <0x0 0xa 0x1 0x70900000>,
+ /bits/ 64 <0x0 0xb 0x0 0x50a00000>,
+ /bits/ 64 <0x0 0xb 0x1 0x70a00000>,
+ /bits/ 64 <0x0 0xc 0x0 0x50b00000>,
+ /bits/ 64 <0x0 0xc 0x1 0x70b00000>,
+ /bits/ 64 <0x0 0xd 0x0 0x52100000>,
+ /bits/ 64 <0x0 0xd 0x1 0x72100000>,
+ /bits/ 64 <0x0 0xe 0x0 0x51c00000>,
+ /bits/ 64 <0x0 0xe 0x1 0x71c00000>,
+ /bits/ 64 <0x0 0xf 0x0 0x50000000>,
+ /bits/ 64 <0x0 0xf 0x1 0x70000000>,
+ /bits/ 64 <0x0 0x10 0x0 0x54000000>,
+ /bits/ 64 <0x0 0x10 0x1 0x74000000>,
+ /bits/ 64 <0x0 0x11 0x0 0x52060000>,
+ /bits/ 64 <0x0 0x11 0x1 0x72060000>,
+ /bits/ 64 <0x0 0x12 0x0 0x50c00000>,
+ /bits/ 64 <0x0 0x12 0x1 0x70c00000>,
+ /bits/ 64 <0x0 0x13 0x0 0x50100000>,
+ /bits/ 64 <0x0 0x13 0x1 0x70100000>,
+ /bits/ 64 <0x0 0x14 0x0 0x51000000>,
+ /bits/ 64 <0x0 0x14 0x1 0x71000000>,
+ /bits/ 64 <0x0 0x15 0x0 0x50200000>,
+ /bits/ 64 <0x0 0x15 0x1 0x70200000>;
+ };
+ };
+
+ ErrorLogger5 {
+ compatible = "eswin,win2030,register";
+ offset,length = < 0x28 32>;
+ description = "Register 5 to log errors";
+
+ User_flag {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0x0 7 >;
+ lut =
+ "Cache_0",
+ "Cache_1",
+ "Cache_2",
+ "Cache_3",
+ "Prot_0",
+ "Prot_1",
+ "Prot_2";
+ };
+ };
+};
+
+d1_llc_noc:d1_llc_noc@72081400 {
+ compatible = "eswin,win2030-noc";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ reg = <0 0x72081400 0 0x4000>;
+ interrupts = <441>;
+ interrupt-names = "error";
+ interrupt-parent = <&plic1>;
+ errlogger,idx = <0 1 3 4 5>;
+#ifdef PLATFORM_HAPS
+ clock,rate = <5000000>; /*haps ddr controller clk*/
+#endif
+ sideband_manager@72082000 {
+ compatible = "eswin,win2xxx-noc-sideband-manager";
+ reg = <0 0x72082000 0 0x10>;
+ SenseIn0 =
+ <SBM_LNOC_NPU_LLC0 OFFSET0>,
+ <SBM_LNOC_NPU_LLC1 OFFSET1>,
+ <SBM_LNOC_DDRT0_P0 OFFSET2>,
+ <SBM_LNOC_DDRT1_P0 OFFSET3>;
+ bf-name =
+ "SBM_LNOC_NPU_LLC0",
+ "SBM_LNOC_NPU_LLC1",
+ "SBM_LNOC_DDRT0_P0",
+ "SBM_LNOC_DDRT1_P0";
+ };
+
+ llcnoc_packet_ddr0_p0_req_probe@72080000 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0 0x72080000 0 0x4000>;
+ clocks = <&d1_clock WIN2030_CLK_DDRT0_P0_ACLK>;
+ clock-names = "clk";
+ interrupts = <445>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic1>;
+ filter,nr = <1>;
+ counter,nr = <2>;
+ portsel = "ddr0_p0_req";
+ };
+ llcnoc_packet_ddr1_p0_req_probe@72080800 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0 0x72080800 0 0x4000>;
+ clocks =<&d1_clock WIN2030_CLK_DDRT1_P0_ACLK>;
+ clock-names = "clk";
+ interrupts = <443>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic1>;
+ filter,nr = <1>;
+ counter,nr = <2>;
+ portsel = "ddr1_p0_req";
+ };
+ llcnoc_trans_probe@72081000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ compatible = "eswin,win2xxx-noc-trans-probe";
+ reg = <0 0x72081000 0 0x4000>;
+ clocks =<&d1_clock WIN2030_CLK_NOC_NSP_CLK>;
+ clock-names = "clk";
+ interrupts = <441>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic1>;
+ filter,nr = <2>;
+ counter,nr = <8>;
+ profiler,nr = <1>;
+ portsel = "npu_llc0", "npu_llc1";
+ llcnoc_trans_npu_llc0_filter@72081480 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x72081480 0 0x80>;
+ };
+ llcnoc_trans_npu_llc1_filter@72081500 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x72081500 0 0x80>;
+ };
+ llcnoc_trans_profiler@72081580 {
+ compatible = "eswin,win2xxx-noc-trans-profiler";
+ reg = <0 0x72081580 0 0x80>;
+ };
+ };
+ ErrorLogger0 {
+ compatible = "eswin,win2030,register";
+ offset,length = < 0x14 32 >;
+ description = "Register 0 to log errors";
+ lock {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0 1 >;
+ lut = "Not Locked", "Locked";
+ };
+ OpCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 1 4 >;
+ lut = "RD: data read with incrementing address",
+ "RDW: data read with wrapping address",
+ "RDL: allocates monitor in the Target with incrementing address",
+ "RDX: exclusive read with incrementing address",
+ "WR: data write with incrementing address",
+ "WRW: data write with wrapping address",
+ "WRC: conditional write if matching monitor in Target is found",
+ "RSV: reserved",
+ "PRE: preamble packet of linked sequence (locked sequence)",
+ "URG: urgency packet used for QoS (status must be REQ)";
+ };
+ ErrCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 8 3 >;
+ lut = "SLV (error source: Target): error detected by the Slave without any information or no Error",
+ "DEC (error source: Initiator NIU): decode error",
+ "UNS (error source: Target NIU): unsupported access type",
+ "DISC (error source: Power Disconnect): disconnected Target or NoC domain",
+ "SEC (error source: Initiator NIU or Firewall): security error",
+ "HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator",
+ "TMO (error source: Target NIU): time-out",
+ "RSV: reserved";
+
+ };
+ Len1 {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 16 12 >;
+ };
+ Format {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 31 1 >;
+ lut = "NTTP v3.0 (Invalid)", "NTTP v3.5 (Ok)";
+ };
+ };
+
+ ErrorLogger1 {
+ compatible = "eswin,win2030,register", "eswin,win2030,noc,filter,routeid";
+ offset,length = < 0x18 32>;
+ description = "Register 1 to log errors";
+ InitFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 14 2 >;
+ lut =
+ "npu_lnoc_llc0/I/0",
+ "npu_lnoc_llc1/I/0",
+ "snoc_lnoc/I/0",
+ "RESERVED";
+ };
+
+ TargetFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 12 2 >;
+ lut =
+ "lnoc_ddrt0_p0/T/0",
+ "lnoc_ddrt1_p0/T/0",
+ "lnoc_service/T/0",
+ "RESERVED";
+ };
+
+ TargetSubRange {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 8 4 >;
+ };
+
+ SeqId {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0 8 >;
+ };
+ };
+
+ ErrorLogger3 {
+ /* This register does not really include a bitfield or its bitfield is 32 bits and it provides an offset address */
+ /* To calculate the absolute address, you must use the initflow:targetflow:subrange from ErrorLogger1 register */
+ /* And use it as an index in the aperture table. Then you must add the value of this register to the value given */
+ /* by the table to get the absolute address. */
+ compatible = "eswin,win2030,register";
+ offset,length = <0x20 32>;
+ description = "Register 3 to log errors";
+ aperture-link = <1>; /* link to ErrorLogger whose information are required to calculate real absolute address */
+ msb-link = <4>; /*indicate which ErrorLogger contains the msb addrs, -1 means no*/
+ AbsoluteAddress {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 8 8 >; /* bitfield initflow:targeflow:subrange from aperture-link register */
+ aperture-size= < 53 >; /* Number of line in the aperture table below */
+ aperture-idx,aperture-base = /* Aperture_idx is concatenation of initflow:targetflow:subrange bitfield from ErrorLogger1 */
+ /bits/ 64 <0x0 0x0 0x0 0x80000000 >,
+ /bits/ 64 <0x0 0x0 0x1 0x100000000 >,
+ /bits/ 64 <0x0 0x0 0x2 0x200000000 >,
+ /bits/ 64 <0x0 0x0 0x3 0x400000000 >,
+ /bits/ 64 <0x0 0x0 0x4 0x800000000 >,
+ /bits/ 64 <0x0 0x0 0x5 0x2000000000 >,
+ /bits/ 64 <0x0 0x0 0x6 0xc000000000 >,
+ /bits/ 64 <0x0 0x0 0x7 0xe000000000 >,
+ /bits/ 64 <0x0 0x0 0x8 0x4000000000 >,
+ /bits/ 64 <0x0 0x0 0x9 0x4000000100 >,
+ /bits/ 64 <0x0 0x0 0xa 0x10000000000 >,
+ /bits/ 64 <0x0 0x0 0xb 0x10000000100 >,
+ /bits/ 64 <0x0 0x0 0xc 0x0 >,
+ /bits/ 64 <0x0 0x1 0x0 0x80000080 >,
+ /bits/ 64 <0x0 0x1 0x1 0x100000080 >,
+ /bits/ 64 <0x0 0x1 0x2 0x200000080 >,
+ /bits/ 64 <0x0 0x1 0x3 0x400000080 >,
+ /bits/ 64 <0x0 0x1 0x4 0x800000080 >,
+ /bits/ 64 <0x0 0x1 0x5 0x2000000080 >,
+ /bits/ 64 <0x0 0x1 0x6 0xc000000080 >,
+ /bits/ 64 <0x0 0x1 0x7 0xe000000080 >,
+ /bits/ 64 <0x0 0x1 0x8 0x4000000080 >,
+ /bits/ 64 <0x0 0x1 0x9 0x4000000180 >,
+ /bits/ 64 <0x0 0x1 0xa 0x10000000080 >,
+ /bits/ 64 <0x0 0x1 0xb 0x10000000180 >,
+ /bits/ 64 <0x1 0x0 0x0 0x80000000 >,
+ /bits/ 64 <0x1 0x0 0x1 0x100000000 >,
+ /bits/ 64 <0x1 0x0 0x2 0x200000000 >,
+ /bits/ 64 <0x1 0x0 0x3 0x400000000 >,
+ /bits/ 64 <0x1 0x0 0x4 0x800000000 >,
+ /bits/ 64 <0x1 0x0 0x5 0x2000000000 >,
+ /bits/ 64 <0x1 0x0 0x6 0xc000000000 >,
+ /bits/ 64 <0x1 0x0 0x7 0xe000000000 >,
+ /bits/ 64 <0x1 0x0 0x8 0x4000000000 >,
+ /bits/ 64 <0x1 0x0 0x9 0x4000000100 >,
+ /bits/ 64 <0x1 0x0 0xa 0x10000000000 >,
+ /bits/ 64 <0x1 0x0 0xb 0x10000000100 >,
+ /bits/ 64 <0x1 0x0 0xc 0x0 >,
+ /bits/ 64 <0x1 0x1 0x0 0x80000080 >,
+ /bits/ 64 <0x1 0x1 0x1 0x100000080 >,
+ /bits/ 64 <0x1 0x1 0x2 0x200000080 >,
+ /bits/ 64 <0x1 0x1 0x3 0x400000080 >,
+ /bits/ 64 <0x1 0x1 0x4 0x800000080 >,
+ /bits/ 64 <0x1 0x1 0x5 0x2000000080 >,
+ /bits/ 64 <0x1 0x1 0x6 0xc000000080 >,
+ /bits/ 64 <0x1 0x1 0x7 0xe000000080 >,
+ /bits/ 64 <0x1 0x1 0x8 0x4000000080 >,
+ /bits/ 64 <0x1 0x1 0x9 0x4000000180 >,
+ /bits/ 64 <0x1 0x1 0xa 0x10000000080 >,
+ /bits/ 64 <0x1 0x1 0xb 0x10000000180 >,
+ /bits/ 64 <0x2 0x2 0x0 0x52080000 >,
+ /bits/ 64 <0x2 0x2 0x1 0x72080000 >,
+ /bits/ 64 <0x2 0x2 0x2 0x0 >;
+ };
+ };
+
+ ErrorLogger4 {
+ compatible = "eswin,win2030,register";
+ offset,length = < 0x24 32>;
+ description = "Register 4 to log errors";
+ addr_msb {
+ compatible = "eswin,win2030,bitfield";
+ description = "Stores NTTP packet header field Addr (MSBs) of the logged error";
+ offset,length = < 0 9 >;
+ };
+ };
+
+ ErrorLogger5 {
+ compatible = "eswin,win2030,register";
+ offset,length = < 0x28 32 >;
+ description = "Register 5 to log errors";
+
+ User_flag {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0x0 16 >;
+ lut =
+ "Cache_0",
+ "Cache_1",
+ "Cache_2",
+ "Cache_3",
+ "Prot_0",
+ "Prot_1",
+ "Prot_2",
+ "Qos_0",
+ "Qos_1",
+ "Qos_2",
+ "Qos_3",
+ "User_0",
+ "User_1",
+ "User_2",
+ "User_3",
+ "User_4";
+ };
+ };
+};
+
+d1_sys_noc:d1_sys_noc@72002C00 {
+ compatible = "eswin,win2030-noc";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ reg = <0 0x72002C00 0 0x4000>;
+ interrupts = <431>;
+ interrupt-names = "error";
+ interrupt-parent = <&plic1>;
+ errlogger,idx = <0 1 3 4 5>;
+
+ eswin,qos-configs = "DSPT", "NPU", "SPISLV_TBU3";
+#ifdef PLATFORM_HAPS
+ eswin,DSPT-qos-base = <0x72002C80>;
+ eswin,DSPT-qos-settings = <
+ 0x8 0x4 /* prio */
+ 0xC 0x1 /* mode 0:fixed 1:limiter 2:bypass 3:regulator*/
+ /* a number of (1/256)th of Bytes/cycle.
+ Ex:DSP AXI clk=5MHz, BW=1MB/s, register value = (1/5)*256 = 0x33
+ */
+ 0x10 0x33 /* bandwidth. 1MB/s */
+ /*
+ Saturation(B) = ((Requried Bandwidth)*(Windows Time of Bandwidth Calculation))/16
+ Ex:16 byte saturation for BW=1MB/s means 16us window time.
+ The desired value is number of saturation bytes divided by 16(ex,1 for 16byte B)
+ */
+ 0x14 0x1 /* saturation, 16us*/
+ 0x18 0x0>; /* QoSEn */
+
+ eswin,NPU-qos-base = <0x72002D00>;
+ eswin,NPU-qos-settings = <
+ 0x8 0x4 /* prio */
+ 0xC 0x1 /* mode */
+ 0x10 0x18 /* bandwidth */
+ 0x14 0x10 /* saturation */
+ 0x18 0x0>; /* QoSEn */
+
+ eswin,SPISLV_TBU3-qos-base = <0x72002D80>;
+ eswin,SPISLV_TBU3-qos-settings = <
+ 0x8 0x4 /* prio */
+ 0xC 0x1 /* mode */
+ 0x10 0x18 /* bandwidth */
+ 0x14 0x10 /* saturation */
+ 0x18 0x0>; /* QoSEn */
+ clock,rate = <5000000>; /*haps ddr controller axi clk*/
+#else
+ eswin,DSPT-qos-base = <0x52002C80>;
+ eswin,DSPT-qos-settings = <
+ 0x8 0x4 /* prio */
+ 0xC 0x2 /* mode 0:fixed 1:limiter 2:bypass 3:regulator*/
+ /* a number of (1/256)th of Bytes/cycle.
+ Ex:zebu zdfi design feature, dsp AXI Clk=1040MHz, BW=12.1875MB/s, register value = (9.375/1040)*256 = 0x03
+ */
+ 0x10 0x03 /* bandwidth. 12.1875MB/s */
+ /*
+ Saturation(B) = ((Requried Bandwidth)*(Windows Time of Bandwidth Calculation))/16
+ Ex:16 byte saturation for BW=12.1875MB/s means 1.313us window time.
+ The desired value is number of saturation bytes divided by 16(ex,1 for 16byte B)
+ */
+ 0x14 0x1 /* saturation, 1.313us*/
+ 0x18 0x1>; /* QoSEn */
+
+ eswin,NPU-qos-base = <0x72002D00>;
+ eswin,NPU-qos-settings = <
+ 0x8 0x4 /* prio */
+ 0xC 0x2 /* mode */
+ 0x10 0x18 /* bandwidth */
+ 0x14 0x10 /* saturation */
+ 0x18 0x1>; /* QoSEn */
+
+ eswin,SPISLV_TBU3-qos-base = <0x72002D80>;
+ eswin,SPISLV_TBU3-qos-settings = <
+ 0x8 0x4 /* prio */
+ 0xC 0x2 /* mode */
+ 0x10 0x18 /* bandwidth */
+ 0x14 0x10 /* saturation */
+ 0x18 0x1>; /* QoSEn */
+#endif
+ sideband_manager@72004000 {
+ compatible = "eswin,win2xxx-noc-sideband-manager";
+ reg = <0 0x72004000 0 0x10>;
+ SenseIn0 =
+ <SBM_AON_SNOC_SP0 OFFSET0>,
+ <SBM_DSPT_SNOC OFFSET1>,
+ <SBM_JTAG_SNOC OFFSET2>,
+ <SBM_MCPUT_SNOC_D2D OFFSET3>,
+ <SBM_MCPUT_SNOC_MP OFFSET4>,
+ <SBM_MCPUT_SNOC_SP0 OFFSET5>,
+ <SBM_MCPUT_SNOC_SP1 OFFSET6>,
+ <SBM_NPU_SNOC_SP0 OFFSET7>,
+ <SBM_NPU_SNOC_SP1 OFFSET8>,
+ <SBM_PCIET_SNOC_P OFFSET9>,
+ <SBM_SPISLV_PCIET_SNOC OFFSET10>,
+ <SBM_TBU4_SNOC OFFSET11>,
+ <SBM_TCU_SNOC OFFSET12>,
+ <SBM_SNOC_AON OFFSET13>,
+ <SBM_SNOC_DDR0_P1 OFFSET14>,
+ <SBM_SNOC_DDR0_P2 OFFSET15>,
+ <SBM_SNOC_DDR1_P1 OFFSET16>,
+ <SBM_SNOC_DDR1_P2 OFFSET17>,
+ <SBM_SNOC_DSPT OFFSET18>,
+ <SBM_SNOC_MCPUT_D2D OFFSET19>,
+ <SBM_SNOC_NPU OFFSET20>,
+ <SBM_SNOC_PCIET OFFSET21>;
+ bf-name =
+ "SBM_AON_SNOC_SP0",
+ "SBM_DSPT_SNOC",
+ "SBM_JTAG_SNOC",
+ "SBM_MCPUT_SNOC_D2D ",
+ "SBM_MCPUT_SNOC_MP",
+ "SBM_MCPUT_SNOC_SP0",
+ "SBM_MCPUT_SNOC_SP1",
+ "SBM_NPU_SNOC_SP0",
+ "SBM_NPU_SNOC_SP1",
+ "SBM_PCIET_SNOC_P",
+ "SBM_SPISLV_PCIET_SNOC",
+ "SBM_TBU4_SNOC",
+ "SBM_TCU_SNOC",
+ "SBM_SNOC_AON",
+ "SBM_SNOC_DDR0_P1",
+ "SBM_SNOC_DDR0_P2",
+ "SBM_SNOC_DDR1_P1",
+ "SBM_SNOC_DDR1_P2",
+ "SBM_SNOC_DSPT",
+ "SBM_SNOC_MCPUT_D2D",
+ "SBM_SNOC_NPU",
+ "SBM_SNOC_PCIET";
+ };
+ sysnoc_packet_ddr0_p1_req_probe@72000000 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0 0x72000000 0 0x4000>;
+ clocks =<&d1_clock WIN2030_CLK_DDRT0_P1_ACLK>;
+ clock-names = "clk";
+ interrupts = <439>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic1>;
+ filter,nr = <1>;
+ counter,nr = <2>;
+ portsel = "ddr0_p1_req";
+ };
+ sysnoc_packet_ddr0_p2_req_probe@72000800 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0 0x72000800 0 0x4000>;
+ clocks =<&d1_clock WIN2030_CLK_DDRT0_P2_ACLK>;
+ clock-names = "clk";
+ interrupts = <437>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic1>;
+ filter,nr = <1>;
+ counter,nr = <2>;
+ portsel = "ddr0_p2_req";
+ };
+ sysnoc_packet_ddr1_p1_req_probe@72001000 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0 0x72001000 0 0x4000>;
+ clocks =<&d1_clock WIN2030_CLK_DDRT1_P1_ACLK>;
+ clock-names = "clk";
+ interrupts = <435>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic1>;
+ filter,nr = <1>;
+ counter,nr = <2>;
+ portsel = "ddr1_p1_req";
+ };
+ sysnoc_packet_ddr1_p2_req_probe@72001800 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0 0x72001800 0 0x4000>;
+ clocks =<&d1_clock WIN2030_CLK_DDRT1_P2_ACLK>;
+ clock-names = "clk";
+ interrupts = <433>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic1>;
+ filter,nr = <1>;
+ counter,nr = <2>;
+ portsel = "ddr1_p2_req";
+ };
+ sysnoc_trans_probe_0@72002000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ compatible = "eswin,win2xxx-noc-trans-probe";
+ reg = <0 0x72002000 0 0x4000>;
+ clocks =<&d1_clock WIN2030_CLK_NOC_NSP_CLK>;
+ clock-names = "clk";
+ interrupts = <430>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic1>;
+ filter,nr = <2>;
+ counter,nr = <8>;
+ profiler,nr = <1>;
+ portsel = "dspt_snoc", "npu_sp1";
+ sysnoc_trans_dspt_filter@72002E00 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x72002E00 0 0x80>;
+ };
+ sysnoc_trans_npu_sp1_filter@72002F80 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x72002F80 0 0x80>;
+ };
+ sysnoc_trans_profiler@72003180 {
+ compatible = "eswin,win2xxx-noc-trans-profiler";
+ reg = <0 0x72003180 0 0x80>;
+ };
+ };
+ sysnoc_trans_probe_1@72002400 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ compatible = "eswin,win2xxx-noc-trans-probe";
+ reg = <0 0x72002400 0 0x4000>;
+ clocks =<&d1_clock WIN2030_CLK_NOC_NSP_CLK>;
+ clock-names = "clk";
+ interrupts = <429>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic1>;
+ filter,nr = <3>;
+ counter,nr = <12>;
+ profiler,nr = <1>;
+ portsel = "mcput_mp", "mcput_sp1", "tcu";
+ sysnoc_trans_mcput_mp_filter@72002E80 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x72002E80 0 0x80>;
+ };
+ sysnoc_trans_mcput_sp1_filter@72002F00 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x72002F00 0 0x80>;
+ };
+ sysnoc_trans_tcu_filter@72003100 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x72003100 0 0x80>;
+ };
+ sysnoc_trans_profiler@72003200 {
+ compatible = "eswin,win2xxx-noc-trans-profiler";
+ reg = <0 0x72003200 0 0x80>;
+ };
+ };
+ sysnoc_trans_probe_2@72002800 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ compatible = "eswin,win2xxx-noc-trans-probe";
+ reg = <0 0x72002800 0 0x4000>;
+ clocks =<&d1_clock WIN2030_CLK_NOC_NSP_CLK>;
+ clock-names = "clk";
+ interrupts = <428>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic1>;
+ filter,nr = <2>;
+ counter,nr = <8>;
+ profiler,nr = <1>;
+ portsel = "spislv_tbu3", "tbu4_snoc";
+ sysnoc_trans_spislv_tbu3_filter@72003000 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x72003000 0 0x80>;
+ };
+ sysnoc_trans_tbu4_filter@72003080 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x72003080 0 0x80>;
+ };
+ sysnoc_trans_profiler@72003280 {
+ compatible = "eswin,win2xxx-noc-trans-profiler";
+ reg = <0 0x72003280 0 0x80>;
+ };
+ };
+ ErrorLogger0 {
+ compatible = "eswin,win2030,register";
+ offset,length = < 0x14 32 >;
+ description = "Register 0 to log errors";
+ lock {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0 1>;
+ lut = "Not Locked", "Locked";
+ };
+ OpCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 1 4>;
+ lut = "RD: data read with incrementing address",
+ "RDW: data read with wrapping address",
+ "RDL: allocates monitor in the Target with incrementing address",
+ "RDX: exclusive read with incrementing address",
+ "WR: data write with incrementing address",
+ "WRW: data write with wrapping address",
+ "WRC: conditional write if matching monitor in Target is found",
+ "RSV: reserved",
+ "PRE: preamble packet of linked sequence (locked sequence)",
+ "URG: urgency packet used for QoS (status must be REQ)";
+ };
+ ErrCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 8 3 >;
+ lut = "SLV (error source: Target): error detected by the Slave without any information or no Error",
+ "DEC (error source: Initiator NIU): decode error",
+ "UNS (error source: Target NIU): unsupported access type",
+ "DISC (error source: Power Disconnect): disconnected Target or NoC domain",
+ "SEC (error source: Initiator NIU or Firewall): security error",
+ "HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator",
+ "TMO (error source: Target NIU): time-out",
+ "RSV: reserved";
+
+ };
+ Len1 {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 16 12 >;
+ };
+ Format {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 31 1 >;
+ lut = "NTTP v3.0 (Invalid)", "NTTP v3.5 (Ok)";
+ };
+ };
+
+ ErrorLogger1 {
+ compatible = "eswin,win2030,register", "eswin,win2030,noc,filter,routeid";
+ offset,length = < 0x18 32>;
+ description = "Register 1 to log errors";
+ InitFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 19 4 >;
+ lut =
+ "aon_snoc_sp0/I/0",
+ "dspt_snoc/I/0",
+#ifdef PLATFORM_HAPS
+ "fpga_snoc/I/0",
+#endif
+ "jtag_snoc/I/0",
+ "mcput_snoc_d2d/I/0",
+ "mcput_snoc_mp/I/0",
+ "mcput_snoc_sp0/I/0",
+ "mcput_snoc_sp1/I/0",
+ "mnoc_snoc/I/0",
+ "npu_snoc_sp0/I/0",
+ "npu_snoc_sp1/I/0",
+ "pciet_snoc_p/I/0",
+ "rnoc_snoc/I/0",
+ "spislv_tbu3_snoc/I/0",
+ "tbu4_snoc/I/0",
+ "tcu_snoc/I/0",
+ "RESERVED0";
+ };
+
+ TargetFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 15 4 >;
+ lut =
+ "snoc_aon/T/0",
+ "snoc_cnoc/T/0",
+ "snoc_ddrt0_p1/T/0",
+ "snoc_ddrt0_p2/T/0",
+ "snoc_ddrt1_p1/T/0",
+ "snoc_ddrt1_p2/T/0",
+ "snoc_dspt/T/0",
+ "snoc_lnoc/T/0",
+ "snoc_mcput_d2d/T/0",
+ "snoc_mnoc/T/0",
+ "snoc_npu/T/0",
+ "snoc_pciet/T/0",
+ "snoc_rnoc/T/0",
+ "snoc_service/T/0",
+ "RESERVED1",
+ "RESERVED2";
+ };
+
+ TargetSubRange {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 9 6 >;
+ };
+
+ SeqId {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0 9 >;
+ };
+ };
+
+ ErrorLogger3 {
+ /* This register does not really include a bitfield or its bitfield is 32 bits and it provides an offset address */
+ /* To calculate the absolute address, you must use the initflow:targetflow:subrange from ErrorLogger1 register */
+ /* And use it as an index in the aperture table. Then you must add the value of this register to the value given */
+ /* by the table to get the absolute address. */
+ compatible = "eswin,win2030,register";
+ offset,length = <0x20 32>;
+ description = "Register 3 to log errors";
+ aperture-link = <1>; /* link to ErrorLogger whose information are required to calculate real absolute address */
+ msb-link = <4>; /*indicate which ErrorLogger contains the msb addrs, -1 means no*/
+ AbsoluteAddress {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 9 14 >; /* bitfield initflow:targeflow:subrange from aperture-link register */
+ aperture-size= < 1181 >; /* Number of line in the aperture table below */
+ aperture-idx,aperture-base = /* Aperture_idx is concatenation of initflow:targetflow:subrange bitfield from ErrorLogger1 */
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0x0 0x52060000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0x1 0x72060000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0x2 0x52100000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0x3 0x52200000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0x4 0x52300000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0x5 0x72100000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0x6 0x72200000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0x7 0x72300000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0x8 0x53000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0x9 0x73000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0xa 0x50000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0xb 0x70000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0xc 0x54000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0xd 0x74000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0xe 0x0 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0xf 0x0 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_cnoc_T_O 0x10 0x0 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_dspt_T_O 0x0 0x520e0000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_dspt_T_O 0x1 0x720e0000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_dspt_T_O 0x2 0x5b000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_dspt_T_O 0x3 0x7b000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_lnoc_T_O 0x0 0x52080000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_lnoc_T_O 0x1 0x72080000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x0 0x58400000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x1 0x78400000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x2 0x58800000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x3 0x78800000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x4 0x59000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x5 0x5a000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x6 0x5b000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x7 0x79000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x8 0x7a000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x9 0x7b000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mcput_d2d_T_O 0xa 0x50000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mcput_d2d_T_O 0xb 0x70000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mcput_d2d_T_O 0xc 0x40000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mcput_d2d_T_O 0xd 0x60000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mnoc_T_O 0x0 0x52020000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_mnoc_T_O 0x1 0x72020000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_npu_T_O 0x0 0x52080000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_npu_T_O 0x1 0x72080000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_npu_T_O 0x2 0x59000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_npu_T_O 0x3 0x5a000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_npu_T_O 0x4 0x79000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_npu_T_O 0x5 0x7a000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_pciet_T_O 0x0 0x40000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_pciet_T_O 0x1 0x60000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_rnoc_T_O 0x0 0x52040000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_rnoc_T_O 0x1 0x72040000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_service_T_O 0x0 0x52000000 >,
+ /bits/ 64 <aon_snoc_sp0_I_O snoc_service_T_O 0x1 0x72000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_aon_T_O 0x0 0x520c0000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_aon_T_O 0x1 0x720c0000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_aon_T_O 0x2 0x58400000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_aon_T_O 0x3 0x78400000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_aon_T_O 0x4 0x14000400000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_aon_T_O 0x5 0x14008400000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_aon_T_O 0x6 0x58800000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_aon_T_O 0x7 0x78800000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_aon_T_O 0x8 0x14000800000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_aon_T_O 0x9 0x14008800000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_aon_T_O 0xa 0x5c000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_aon_T_O 0xb 0x7c000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_aon_T_O 0xc 0x14004000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_aon_T_O 0xd 0x1400c000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0x0 0x52060000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0x1 0x72060000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0x2 0x52100000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0x3 0x52200000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0x4 0x52300000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0x5 0x72100000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0x6 0x72200000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0x7 0x72300000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0x8 0x53000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0x9 0x73000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0xa 0x50000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0xb 0x70000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0xc 0x54000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0xd 0x74000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_cnoc_T_O 0xe 0x0 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt0_p2_T_O 0x0 0x80000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt0_p2_T_O 0x1 0x100000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt0_p2_T_O 0x2 0x200000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt0_p2_T_O 0x3 0x400000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt0_p2_T_O 0x4 0x800000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt0_p2_T_O 0x5 0x2000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt0_p2_T_O 0x6 0xc000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt0_p2_T_O 0x7 0xe000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt0_p2_T_O 0x8 0x4000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt0_p2_T_O 0x9 0x4000000100 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt0_p2_T_O 0xa 0x10000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt0_p2_T_O 0xb 0x10000000100 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt1_p2_T_O 0x0 0x80000080 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt1_p2_T_O 0x1 0x100000080 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt1_p2_T_O 0x2 0x200000080 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt1_p2_T_O 0x3 0x400000080 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt1_p2_T_O 0x4 0x800000080 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt1_p2_T_O 0x5 0x2000000080 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt1_p2_T_O 0x6 0xc000000080 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt1_p2_T_O 0x7 0xe000000080 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt1_p2_T_O 0x8 0x4000000080 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt1_p2_T_O 0x9 0x4000000180 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt1_p2_T_O 0xa 0x10000000080 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_ddrt1_p2_T_O 0xb 0x10000000180 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x0 0x58400000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x1 0x78400000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x2 0x14000400000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x3 0x14008400000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x4 0x58800000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x5 0x78800000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x6 0x14000800000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x7 0x14008800000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x8 0x59000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x9 0x5a000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0xa 0x5b000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0xb 0x79000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0xc 0x7a000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0xd 0x7b000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0xe 0x14001000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0xf 0x14002000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x10 0x14003000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x11 0x14009000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x12 0x1400a000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x13 0x1400b000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x14 0x50000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x15 0x70000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x16 0x40000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x17 0x60000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x18 0x80000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x19 0x100000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x1a 0x200000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x1b 0x400000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x1c 0x800000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x1d 0x1800000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x1e 0x3800000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x1f 0xd800000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x20 0xf800000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x21 0x2000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x22 0x7000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x23 0x7000000100 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x24 0xc000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x25 0xe000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x26 0x13000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x27 0x13000000100 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x28 0x4000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x29 0x4000000100 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x2a 0x8000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x2b 0xa000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x2c 0x10000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_mcput_d2d_T_O 0x2d 0x10000000100 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0x0 0x52080000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0x1 0x72080000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0x2 0x59000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0x3 0x5a000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0x4 0x79000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0x5 0x7a000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0x6 0x14001000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0x7 0x14002000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0x8 0x14009000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0x9 0x1400a000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0xa 0x1800000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0xb 0x3800000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0xc 0xd800000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0xd 0xf800000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0xe 0x7000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0xf 0x7000000100 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0x10 0x13000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_npu_T_O 0x11 0x13000000100 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_pciet_T_O 0x0 0x40000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_pciet_T_O 0x1 0x60000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_pciet_T_O 0x2 0x8000000000 >,
+ /bits/ 64 <dspt_snoc_I_O snoc_pciet_T_O 0x3 0xa000000000 >,
+#ifdef PLATFORM_HAPS
+ /bits/ 64 <fpga_snoc_I_O snoc_aon_T_O 0x0 0x520c0000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_aon_T_O 0x1 0x720c0000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_aon_T_O 0x2 0x58400000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_aon_T_O 0x3 0x78400000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_aon_T_O 0x4 0x14000400000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_aon_T_O 0x5 0x14008400000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_aon_T_O 0x6 0x58800000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_aon_T_O 0x7 0x78800000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_aon_T_O 0x8 0x14000800000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_aon_T_O 0x9 0x14008800000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_aon_T_O 0xa 0x5c000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_aon_T_O 0xb 0x7c000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_aon_T_O 0xc 0x14004000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_aon_T_O 0xd 0x1400c000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0x0 0x52060000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0x1 0x72060000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0x2 0x52100000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0x3 0x52200000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0x4 0x52300000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0x5 0x72100000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0x6 0x72200000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0x7 0x72300000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0x8 0x53000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0x9 0x73000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0xa 0x50000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0xb 0x70000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0xc 0x54000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0xd 0x74000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_cnoc_T_O 0xe 0x0 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt0_p2_T_O 0x0 0x80000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt0_p2_T_O 0x1 0x100000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt0_p2_T_O 0x2 0x200000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt0_p2_T_O 0x3 0x400000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt0_p2_T_O 0x4 0x800000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt0_p2_T_O 0x5 0x2000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt0_p2_T_O 0x6 0xc000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt0_p2_T_O 0x7 0xe000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt0_p2_T_O 0x8 0x4000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt0_p2_T_O 0x9 0x4000000100 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt0_p2_T_O 0xa 0x10000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt0_p2_T_O 0xb 0x10000000100 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt1_p2_T_O 0x0 0x80000080 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt1_p2_T_O 0x1 0x100000080 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt1_p2_T_O 0x2 0x200000080 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt1_p2_T_O 0x3 0x400000080 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt1_p2_T_O 0x4 0x800000080 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt1_p2_T_O 0x5 0x2000000080 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt1_p2_T_O 0x6 0xc000000080 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt1_p2_T_O 0x7 0xe000000080 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt1_p2_T_O 0x8 0x4000000080 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt1_p2_T_O 0x9 0x4000000180 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt1_p2_T_O 0xa 0x10000000080 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_ddrt1_p2_T_O 0xb 0x10000000180 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_dspt_T_O 0x0 0x520e0000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_dspt_T_O 0x1 0x720e0000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_dspt_T_O 0x2 0x5b000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_dspt_T_O 0x3 0x7b000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_dspt_T_O 0x4 0x14003000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_dspt_T_O 0x5 0x1400b000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_lnoc_T_O 0x0 0x52080000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_lnoc_T_O 0x1 0x72080000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x0 0x58400000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x1 0x78400000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x2 0x14000400000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x3 0x14008400000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x4 0x58800000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x5 0x78800000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x6 0x14000800000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x7 0x14008800000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x8 0x59000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x9 0x5a000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0xa 0x5b000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0xb 0x79000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0xc 0x7a000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0xd 0x7b000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0xe 0x14001000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0xf 0x14002000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x10 0x14003000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x11 0x14009000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x12 0x1400a000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x13 0x1400b000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x14 0x50000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x15 0x70000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x16 0x40000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x17 0x60000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x18 0x80000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x19 0x100000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x1a 0x200000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x1b 0x400000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x1c 0x800000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x1d 0x1800000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x1e 0x3800000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x1f 0xd800000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x20 0xf800000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x21 0x2000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x22 0x7000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x23 0x7000000100 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x24 0xc000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x25 0xe000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x26 0x13000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x27 0x13000000100 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x28 0x4000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x29 0x4000000100 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x2a 0x8000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x2b 0xa000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x2c 0x10000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mcput_d2d_T_O 0x2d 0x10000000100 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mnoc_T_O 0x0 0x52020000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_mnoc_T_O 0x1 0x72020000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0x0 0x52080000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0x1 0x72080000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0x2 0x59000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0x3 0x5a000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0x4 0x79000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0x5 0x7a000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0x6 0x14001000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0x7 0x14002000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0x8 0x14009000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0x9 0x1400a000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0xa 0x1800000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0xb 0x3800000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0xc 0xd800000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0xd 0xf800000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0xe 0x7000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0xf 0x7000000100 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0x10 0x13000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_npu_T_O 0x11 0x13000000100 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_pciet_T_O 0x0 0x40000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_pciet_T_O 0x1 0x60000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_pciet_T_O 0x2 0x8000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_pciet_T_O 0x3 0xa000000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_rnoc_T_O 0x0 0x52040000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_rnoc_T_O 0x1 0x72040000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_service_T_O 0x0 0x52000000 >,
+ /bits/ 64 <fpga_snoc_I_O snoc_service_T_O 0x1 0x72000000 >,
+#endif
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0x0 0x52060000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0x1 0x72060000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0x2 0x52100000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0x3 0x52200000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0x4 0x52300000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0x5 0x72100000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0x6 0x72200000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0x7 0x72300000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0x8 0x53000000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0x9 0x73000000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0xa 0x50000000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0xb 0x70000000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0xc 0x54000000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0xd 0x74000000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0xe 0x0 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0xf 0x0 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_cnoc_T_O 0x10 0x0 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_lnoc_T_O 0x0 0x52080000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_lnoc_T_O 0x1 0x72080000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_mnoc_T_O 0x0 0x52020000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_mnoc_T_O 0x1 0x72020000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_rnoc_T_O 0x0 0x52040000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_rnoc_T_O 0x1 0x72040000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_service_T_O 0x0 0x52000000 >,
+ /bits/ 64 <jtag_snoc_I_O snoc_service_T_O 0x1 0x72000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_aon_T_O 0x0 0x520c0000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_aon_T_O 0x1 0x720c0000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_aon_T_O 0x2 0x58400000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_aon_T_O 0x3 0x78400000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_aon_T_O 0x4 0x14000400000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_aon_T_O 0x5 0x14008400000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_aon_T_O 0x6 0x58800000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_aon_T_O 0x7 0x78800000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_aon_T_O 0x8 0x14000800000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_aon_T_O 0x9 0x14008800000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_aon_T_O 0xa 0x5c000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_aon_T_O 0xb 0x7c000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_aon_T_O 0xc 0x14004000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_aon_T_O 0xd 0x1400c000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0x0 0x52060000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0x1 0x72060000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0x2 0x52100000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0x3 0x52200000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0x4 0x52300000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0x5 0x72100000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0x6 0x72200000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0x7 0x72300000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0x8 0x53000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0x9 0x73000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0xa 0x50000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0xb 0x70000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0xc 0x54000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0xd 0x74000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_cnoc_T_O 0xe 0x0 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt0_p2_T_O 0x0 0x80000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt0_p2_T_O 0x1 0x100000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt0_p2_T_O 0x2 0x200000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt0_p2_T_O 0x3 0x400000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt0_p2_T_O 0x4 0x800000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt0_p2_T_O 0x5 0x2000000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt0_p2_T_O 0x6 0xc000000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt0_p2_T_O 0x7 0xe000000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt0_p2_T_O 0x8 0x4000000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt0_p2_T_O 0x9 0x4000000100 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt0_p2_T_O 0xa 0x10000000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt0_p2_T_O 0xb 0x10000000100 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt1_p2_T_O 0x0 0x80000080 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt1_p2_T_O 0x1 0x100000080 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt1_p2_T_O 0x2 0x200000080 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt1_p2_T_O 0x3 0x400000080 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt1_p2_T_O 0x4 0x800000080 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt1_p2_T_O 0x5 0x2000000080 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt1_p2_T_O 0x6 0xc000000080 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt1_p2_T_O 0x7 0xe000000080 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt1_p2_T_O 0x8 0x4000000080 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt1_p2_T_O 0x9 0x4000000180 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt1_p2_T_O 0xa 0x10000000080 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_ddrt1_p2_T_O 0xb 0x10000000180 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_dspt_T_O 0x0 0x520e0000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_dspt_T_O 0x1 0x720e0000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_dspt_T_O 0x2 0x5b000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_dspt_T_O 0x3 0x7b000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_dspt_T_O 0x4 0x14003000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_dspt_T_O 0x5 0x1400b000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_lnoc_T_O 0x0 0x52080000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_lnoc_T_O 0x1 0x72080000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_mnoc_T_O 0x0 0x52020000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_mnoc_T_O 0x1 0x72020000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0x0 0x52080000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0x1 0x72080000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0x2 0x59000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0x3 0x5a000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0x4 0x79000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0x5 0x7a000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0x6 0x14001000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0x7 0x14002000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0x8 0x14009000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0x9 0x1400a000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0xa 0x1800000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0xb 0x3800000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0xc 0xd800000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0xd 0xf800000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0xe 0x7000000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0xf 0x7000000100 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0x10 0x13000000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_npu_T_O 0x11 0x13000000100 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_pciet_T_O 0x0 0x40000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_pciet_T_O 0x1 0x60000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_pciet_T_O 0x2 0x8000000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_pciet_T_O 0x3 0xa000000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_rnoc_T_O 0x0 0x52040000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_rnoc_T_O 0x1 0x72040000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_service_T_O 0x0 0x52000000 >,
+ /bits/ 64 <mcput_snoc_d2d_I_O snoc_service_T_O 0x1 0x72000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt0_p1_T_O 0x0 0x80000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt0_p1_T_O 0x1 0x100000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt0_p1_T_O 0x2 0x200000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt0_p1_T_O 0x3 0x400000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt0_p1_T_O 0x4 0x800000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt0_p1_T_O 0x5 0x2000000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt0_p1_T_O 0x6 0x4000000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt0_p1_T_O 0x7 0x4000000100 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt1_p1_T_O 0x0 0x80000080 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt1_p1_T_O 0x1 0x100000080 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt1_p1_T_O 0x2 0x200000080 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt1_p1_T_O 0x3 0x400000080 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt1_p1_T_O 0x4 0x800000080 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt1_p1_T_O 0x5 0x2000000080 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt1_p1_T_O 0x6 0x4000000080 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_ddrt1_p1_T_O 0x7 0x4000000180 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_npu_T_O 0x0 0x52080000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_npu_T_O 0x1 0x72080000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_npu_T_O 0x2 0x59000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_npu_T_O 0x3 0x5a000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_npu_T_O 0x4 0x79000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_npu_T_O 0x5 0x7a000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_npu_T_O 0x6 0x1800000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_npu_T_O 0x7 0x3800000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_npu_T_O 0x8 0x7000000000 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_npu_T_O 0x9 0x7000000100 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_npu_T_O 0xa 0x0 >,
+ /bits/ 64 <mcput_snoc_mp_I_O snoc_npu_T_O 0xb 0x0 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_aon_T_O 0x0 0x520c0000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_aon_T_O 0x1 0x720c0000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_aon_T_O 0x2 0x58400000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_aon_T_O 0x3 0x78400000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_aon_T_O 0x4 0x58800000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_aon_T_O 0x5 0x78800000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_aon_T_O 0x6 0x5c000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_aon_T_O 0x7 0x7c000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0x0 0x52060000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0x1 0x72060000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0x2 0x52100000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0x3 0x52200000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0x4 0x52300000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0x5 0x72100000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0x6 0x72200000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0x7 0x72300000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0x8 0x53000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0x9 0x73000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0xa 0x50000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0xb 0x70000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0xc 0x54000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0xd 0x74000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_cnoc_T_O 0xe 0x0 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_dspt_T_O 0x0 0x520e0000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_dspt_T_O 0x1 0x720e0000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_dspt_T_O 0x2 0x5b000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_dspt_T_O 0x3 0x7b000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_lnoc_T_O 0x0 0x52080000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_lnoc_T_O 0x1 0x72080000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x0 0x58400000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x1 0x78400000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x2 0x58800000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x3 0x78800000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x4 0x59000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x5 0x5a000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x6 0x5b000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x7 0x79000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x8 0x7a000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x9 0x7b000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mcput_d2d_T_O 0xa 0x50000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mcput_d2d_T_O 0xb 0x70000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mcput_d2d_T_O 0xc 0x40000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mcput_d2d_T_O 0xd 0x60000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mnoc_T_O 0x0 0x52020000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_mnoc_T_O 0x1 0x72020000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_npu_T_O 0x0 0x52080000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_npu_T_O 0x1 0x72080000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_npu_T_O 0x2 0x59000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_npu_T_O 0x3 0x5a000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_npu_T_O 0x4 0x79000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_npu_T_O 0x5 0x7a000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_pciet_T_O 0x0 0x40000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_pciet_T_O 0x1 0x60000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_rnoc_T_O 0x0 0x52040000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_rnoc_T_O 0x1 0x72040000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_service_T_O 0x0 0x52000000 >,
+ /bits/ 64 <mcput_snoc_sp0_I_O snoc_service_T_O 0x1 0x72000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0x0 0x520c0000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0x1 0x720c0000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0x2 0x58400000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0x3 0x78400000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0x4 0x14000400000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0x5 0x14008400000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0x6 0x58800000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0x7 0x78800000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0x8 0x14000800000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0x9 0x14008800000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0xa 0x5c000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0xb 0x7c000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0xc 0x14004000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0xd 0x1400c000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0xe 0x0 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_aon_T_O 0xf 0x0 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x0 0x80000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x1 0x100000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x2 0x200000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x3 0x400000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x4 0x800000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x5 0x2000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x6 0xc000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x7 0xe000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x8 0x4000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x9 0x4000000100 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0xa 0x10000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0xb 0x10000000100 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x0 0x80000080 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x1 0x100000080 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x2 0x200000080 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x3 0x400000080 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x4 0x800000080 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x5 0x2000000080 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x6 0xc000000080 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x7 0xe000000080 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x8 0x4000000080 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x9 0x4000000180 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0xa 0x10000000080 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0xb 0x10000000180 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_dspt_T_O 0x0 0x520e0000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_dspt_T_O 0x1 0x720e0000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_dspt_T_O 0x2 0x5b000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_dspt_T_O 0x3 0x7b000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_dspt_T_O 0x4 0x14003000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_dspt_T_O 0x5 0x1400b000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x0 0x58400000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x1 0x78400000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x2 0x14000400000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x3 0x14008400000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x4 0x58800000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x5 0x78800000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x6 0x14000800000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x7 0x14008800000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x8 0x59000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x9 0x5a000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0xa 0x5b000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0xb 0x79000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0xc 0x7a000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0xd 0x7b000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0xe 0x14001000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0xf 0x14002000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x10 0x14003000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x11 0x14009000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x12 0x1400a000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x13 0x1400b000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x14 0x50000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x15 0x70000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x16 0x40000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x17 0x60000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x18 0x80000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x19 0x100000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x1a 0x200000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x1b 0x400000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x1c 0x800000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x1d 0x1800000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x1e 0x3800000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x1f 0xd800000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x20 0xf800000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x21 0x2000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x22 0x7000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x23 0x7000000100 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x24 0xc000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x25 0xe000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x26 0x13000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x27 0x13000000100 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x28 0x4000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x29 0x4000000100 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x2a 0x8000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x2b 0xa000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x2c 0x10000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x2d 0x10000000100 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0x0 0x52080000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0x1 0x72080000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0x2 0x59000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0x3 0x5a000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0x4 0x79000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0x5 0x7a000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0x6 0x14001000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0x7 0x14002000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0x8 0x14009000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0x9 0x1400a000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0xa 0x1800000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0xb 0x3800000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0xc 0xd800000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0xd 0xf800000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0xe 0x7000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0xf 0x7000000100 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0x10 0x13000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_npu_T_O 0x11 0x13000000100 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_pciet_T_O 0x0 0x40000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_pciet_T_O 0x1 0x60000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_pciet_T_O 0x2 0x8000000000 >,
+ /bits/ 64 <mcput_snoc_sp1_I_O snoc_pciet_T_O 0x3 0xa000000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0x0 0x52060000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0x1 0x72060000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0x2 0x52100000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0x3 0x52200000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0x4 0x52300000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0x5 0x72100000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0x6 0x72200000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0x7 0x72300000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0x8 0x53000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0x9 0x73000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0xa 0x50000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0xb 0x70000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0xc 0x54000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0xd 0x74000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_cnoc_T_O 0xe 0x0 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_dspt_T_O 0x0 0x520e0000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_dspt_T_O 0x1 0x720e0000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_dspt_T_O 0x2 0x5b000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_dspt_T_O 0x3 0x7b000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_dspt_T_O 0x4 0x14003000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_dspt_T_O 0x5 0x1400b000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x0 0x58400000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x1 0x78400000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x2 0x14000400000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x3 0x14008400000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x4 0x58800000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x5 0x78800000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x6 0x14000800000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x7 0x14008800000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x8 0x59000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x9 0x5a000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0xa 0x5b000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0xb 0x79000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0xc 0x7a000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0xd 0x7b000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0xe 0x14001000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0xf 0x14002000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x10 0x14003000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x11 0x14009000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x12 0x1400a000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x13 0x1400b000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x14 0x50000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x15 0x70000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x16 0x40000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x17 0x60000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x18 0x80000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x19 0x100000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x1a 0x200000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x1b 0x400000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x1c 0x800000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x1d 0x1800000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x1e 0x3800000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x1f 0xd800000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x20 0xf800000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x21 0x2000000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x22 0x7000000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x23 0x7000000100 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x24 0xc000000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x25 0xe000000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x26 0x13000000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x27 0x13000000100 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x28 0x4000000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x29 0x4000000100 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x2a 0x8000000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x2b 0xa000000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x2c 0x10000000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_mcput_d2d_T_O 0x2d 0x10000000100 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0x0 0x52080000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0x1 0x72080000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0x2 0x59000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0x3 0x5a000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0x4 0x79000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0x5 0x7a000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0x6 0x14001000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0x7 0x14002000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0x8 0x14009000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0x9 0x1400a000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0xa 0x1800000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0xb 0x3800000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0xc 0xd800000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0xd 0xf800000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0xe 0x7000000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0xf 0x7000000100 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0x10 0x13000000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_npu_T_O 0x11 0x13000000100 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_pciet_T_O 0x0 0x40000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_pciet_T_O 0x1 0x60000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_pciet_T_O 0x2 0x8000000000 >,
+ /bits/ 64 <mnoc_snoc_I_O snoc_pciet_T_O 0x3 0xa000000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_aon_T_O 0x0 0x520c0000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_aon_T_O 0x1 0x720c0000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_aon_T_O 0x2 0x58400000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_aon_T_O 0x3 0x78400000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_aon_T_O 0x4 0x58800000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_aon_T_O 0x5 0x78800000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_aon_T_O 0x6 0x5c000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_aon_T_O 0x7 0x7c000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0x0 0x52060000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0x1 0x72060000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0x2 0x52100000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0x3 0x52200000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0x4 0x52300000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0x5 0x72100000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0x6 0x72200000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0x7 0x72300000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0x8 0x53000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0x9 0x73000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0xa 0x50000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0xb 0x70000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0xc 0x54000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0xd 0x74000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0xe 0x0 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0xf 0x0 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_cnoc_T_O 0x10 0x0 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_dspt_T_O 0x0 0x520e0000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_dspt_T_O 0x1 0x720e0000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_dspt_T_O 0x2 0x5b000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_dspt_T_O 0x3 0x7b000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_lnoc_T_O 0x0 0x52080000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_lnoc_T_O 0x1 0x72080000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x0 0x58400000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x1 0x78400000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x2 0x58800000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x3 0x78800000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x4 0x59000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x5 0x5a000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x6 0x5b000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x7 0x79000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x8 0x7a000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mcput_d2d_T_O 0x9 0x7b000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mcput_d2d_T_O 0xa 0x50000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mcput_d2d_T_O 0xb 0x70000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mcput_d2d_T_O 0xc 0x40000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mcput_d2d_T_O 0xd 0x60000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mnoc_T_O 0x0 0x52020000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_mnoc_T_O 0x1 0x72020000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_pciet_T_O 0x0 0x40000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_pciet_T_O 0x1 0x60000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_rnoc_T_O 0x0 0x52040000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_rnoc_T_O 0x1 0x72040000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_service_T_O 0x0 0x52000000 >,
+ /bits/ 64 <npu_snoc_sp0_I_O snoc_service_T_O 0x1 0x72000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0x0 0x520c0000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0x1 0x720c0000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0x2 0x58400000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0x3 0x78400000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0x4 0x14000400000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0x5 0x14008400000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0x6 0x58800000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0x7 0x78800000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0x8 0x14000800000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0x9 0x14008800000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0xa 0x5c000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0xb 0x7c000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0xc 0x14004000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0xd 0x1400c000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0xe 0x0 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_aon_T_O 0xf 0x0 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x0 0x80000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x1 0x100000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x2 0x200000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x3 0x400000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x4 0x800000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x5 0x2000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x6 0xc000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x7 0xe000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x8 0x4000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0x9 0x4000000100 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0xa 0x10000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt0_p2_T_O 0xb 0x10000000100 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x0 0x80000080 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x1 0x100000080 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x2 0x200000080 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x3 0x400000080 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x4 0x800000080 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x5 0x2000000080 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x6 0xc000000080 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x7 0xe000000080 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x8 0x4000000080 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0x9 0x4000000180 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0xa 0x10000000080 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_ddrt1_p2_T_O 0xb 0x10000000180 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_dspt_T_O 0x0 0x520e0000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_dspt_T_O 0x1 0x720e0000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_dspt_T_O 0x2 0x5b000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_dspt_T_O 0x3 0x7b000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_dspt_T_O 0x4 0x14003000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_dspt_T_O 0x5 0x1400b000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x0 0x58400000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x1 0x78400000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x2 0x14000400000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x3 0x14008400000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x4 0x58800000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x5 0x78800000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x6 0x14000800000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x7 0x14008800000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x8 0x59000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x9 0x5a000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0xa 0x5b000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0xb 0x79000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0xc 0x7a000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0xd 0x7b000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0xe 0x14001000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0xf 0x14002000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x10 0x14003000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x11 0x14009000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x12 0x1400a000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x13 0x1400b000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x14 0x50000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x15 0x70000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x16 0x40000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x17 0x60000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x18 0x80000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x19 0x100000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x1a 0x200000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x1b 0x400000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x1c 0x800000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x1d 0x1800000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x1e 0x3800000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x1f 0xd800000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x20 0xf800000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x21 0x2000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x22 0x7000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x23 0x7000000100 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x24 0xc000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x25 0xe000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x26 0x13000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x27 0x13000000100 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x28 0x4000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x29 0x4000000100 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x2a 0x8000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x2b 0xa000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x2c 0x10000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_mcput_d2d_T_O 0x2d 0x10000000100 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_pciet_T_O 0x0 0x40000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_pciet_T_O 0x1 0x60000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_pciet_T_O 0x2 0x8000000000 >,
+ /bits/ 64 <npu_snoc_sp1_I_O snoc_pciet_T_O 0x3 0xa000000000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0x0 0x52060000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0x1 0x72060000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0x2 0x52100000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0x3 0x52200000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0x4 0x52300000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0x5 0x72100000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0x6 0x72200000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0x7 0x72300000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0x8 0x53000000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0x9 0x73000000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0xa 0x50000000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0xb 0x70000000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0xc 0x54000000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0xd 0x74000000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0xe 0x0 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0xf 0x0 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_cnoc_T_O 0x10 0x0 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_lnoc_T_O 0x0 0x52080000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_lnoc_T_O 0x1 0x72080000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_mnoc_T_O 0x0 0x52020000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_mnoc_T_O 0x1 0x72020000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_rnoc_T_O 0x0 0x52040000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_rnoc_T_O 0x1 0x72040000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_service_T_O 0x0 0x52000000 >,
+ /bits/ 64 <pciet_snoc_p_I_O snoc_service_T_O 0x1 0x72000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0x0 0x52080000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0x1 0x72080000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0x2 0x59000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0x3 0x5a000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0x4 0x79000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0x5 0x7a000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0x6 0x14001000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0x7 0x14002000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0x8 0x14009000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0x9 0x1400a000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0xa 0x1800000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0xb 0x3800000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0xc 0xd800000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0xd 0xf800000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0xe 0x7000000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0xf 0x7000000100 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0x10 0x13000000000 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0x11 0x13000000100 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0x12 0x0 >,
+ /bits/ 64 <rnoc_snoc_I_O snoc_npu_T_O 0x13 0x0 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_aon_T_O 0x0 0x520c0000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_aon_T_O 0x1 0x720c0000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_aon_T_O 0x2 0x58400000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_aon_T_O 0x3 0x78400000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_aon_T_O 0x4 0x14000400000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_aon_T_O 0x5 0x14008400000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_aon_T_O 0x6 0x58800000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_aon_T_O 0x7 0x78800000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_aon_T_O 0x8 0x14000800000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_aon_T_O 0x9 0x14008800000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_aon_T_O 0xa 0x5c000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_aon_T_O 0xb 0x7c000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_aon_T_O 0xc 0x14004000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_aon_T_O 0xd 0x1400c000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0x0 0x52060000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0x1 0x72060000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0x2 0x52100000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0x3 0x52200000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0x4 0x52300000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0x5 0x72100000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0x6 0x72200000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0x7 0x72300000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0x8 0x53000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0x9 0x73000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0xa 0x50000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0xb 0x70000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0xc 0x54000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0xd 0x74000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_cnoc_T_O 0xe 0x0 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O 0x0 0x80000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O 0x1 0x100000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O 0x2 0x200000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O 0x3 0x400000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O 0x4 0x800000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O 0x5 0x2000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O 0x6 0xc000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O 0x7 0xe000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O 0x8 0x4000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O 0x9 0x4000000100 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O 0xa 0x10000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O 0xb 0x10000000100 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O 0x0 0x80000080 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O 0x1 0x100000080 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O 0x2 0x200000080 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O 0x3 0x400000080 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O 0x4 0x800000080 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O 0x5 0x2000000080 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O 0x6 0xc000000080 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O 0x7 0xe000000080 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O 0x8 0x4000000080 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O 0x9 0x4000000180 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O 0xa 0x10000000080 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O 0xb 0x10000000180 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_dspt_T_O 0x0 0x520e0000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_dspt_T_O 0x1 0x720e0000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_dspt_T_O 0x2 0x5b000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_dspt_T_O 0x3 0x7b000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_dspt_T_O 0x4 0x14003000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_dspt_T_O 0x5 0x1400b000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_lnoc_T_O 0x0 0x52080000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_lnoc_T_O 0x1 0x72080000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x0 0x58400000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x1 0x78400000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x2 0x14000400000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x3 0x14008400000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x4 0x58800000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x5 0x78800000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x6 0x14000800000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x7 0x14008800000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x8 0x59000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x9 0x5a000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0xa 0x5b000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0xb 0x79000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0xc 0x7a000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0xd 0x7b000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0xe 0x14001000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0xf 0x14002000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x10 0x14003000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x11 0x14009000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x12 0x1400a000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x13 0x1400b000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x14 0x50000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x15 0x70000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x16 0x40000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x17 0x60000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x18 0x80000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x19 0x100000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x1a 0x200000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x1b 0x400000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x1c 0x800000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x1d 0x1800000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x1e 0x3800000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x1f 0xd800000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x20 0xf800000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x21 0x2000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x22 0x7000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x23 0x7000000100 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x24 0xc000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x25 0xe000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x26 0x13000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x27 0x13000000100 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x28 0x4000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x29 0x4000000100 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x2a 0x8000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x2b 0xa000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x2c 0x10000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x2d 0x10000000100 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mnoc_T_O 0x0 0x52020000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_mnoc_T_O 0x1 0x72020000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0x0 0x52080000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0x1 0x72080000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0x2 0x59000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0x3 0x5a000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0x4 0x79000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0x5 0x7a000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0x6 0x14001000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0x7 0x14002000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0x8 0x14009000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0x9 0x1400a000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0xa 0x1800000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0xb 0x3800000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0xc 0xd800000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0xd 0xf800000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0xe 0x7000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0xf 0x7000000100 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0x10 0x13000000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_npu_T_O 0x11 0x13000000100 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_rnoc_T_O 0x0 0x52040000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_rnoc_T_O 0x1 0x72040000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_service_T_O 0x0 0x52000000 >,
+ /bits/ 64 <spislv_tbu3_snoc_I_O snoc_service_T_O 0x1 0x72000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt0_p2_T_O 0x0 0x80000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt0_p2_T_O 0x1 0x100000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt0_p2_T_O 0x2 0x200000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt0_p2_T_O 0x3 0x400000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt0_p2_T_O 0x4 0x800000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt0_p2_T_O 0x5 0x2000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt0_p2_T_O 0x6 0xc000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt0_p2_T_O 0x7 0xe000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt0_p2_T_O 0x8 0x4000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt0_p2_T_O 0x9 0x4000000100 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt0_p2_T_O 0xa 0x10000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt0_p2_T_O 0xb 0x10000000100 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt1_p2_T_O 0x0 0x80000080 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt1_p2_T_O 0x1 0x100000080 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt1_p2_T_O 0x2 0x200000080 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt1_p2_T_O 0x3 0x400000080 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt1_p2_T_O 0x4 0x800000080 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt1_p2_T_O 0x5 0x2000000080 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt1_p2_T_O 0x6 0xc000000080 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt1_p2_T_O 0x7 0xe000000080 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt1_p2_T_O 0x8 0x4000000080 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt1_p2_T_O 0x9 0x4000000180 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt1_p2_T_O 0xa 0x10000000080 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_ddrt1_p2_T_O 0xb 0x10000000180 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_dspt_T_O 0x0 0x520e0000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_dspt_T_O 0x1 0x720e0000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_dspt_T_O 0x2 0x5b000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_dspt_T_O 0x3 0x7b000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_dspt_T_O 0x4 0x14003000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_dspt_T_O 0x5 0x1400b000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x0 0x58400000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x1 0x78400000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x2 0x14000400000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x3 0x14008400000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x4 0x58800000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x5 0x78800000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x6 0x14000800000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x7 0x14008800000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x8 0x59000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x9 0x5a000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0xa 0x5b000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0xb 0x79000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0xc 0x7a000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0xd 0x7b000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0xe 0x14001000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0xf 0x14002000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x10 0x14003000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x11 0x14009000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x12 0x1400a000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x13 0x1400b000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x14 0x50000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x15 0x70000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x16 0x40000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x17 0x60000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x18 0x80000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x19 0x100000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x1a 0x200000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x1b 0x400000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x1c 0x800000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x1d 0x1800000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x1e 0x3800000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x1f 0xd800000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x20 0xf800000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x21 0x2000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x22 0x7000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x23 0x7000000100 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x24 0xc000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x25 0xe000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x26 0x13000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x27 0x13000000100 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x28 0x4000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x29 0x4000000100 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x2a 0x8000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x2b 0xa000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x2c 0x10000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_mcput_d2d_T_O 0x2d 0x10000000100 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0x0 0x52080000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0x1 0x72080000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0x2 0x59000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0x3 0x5a000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0x4 0x79000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0x5 0x7a000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0x6 0x14001000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0x7 0x14002000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0x8 0x14009000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0x9 0x1400a000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0xa 0x1800000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0xb 0x3800000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0xc 0xd800000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0xd 0xf800000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0xe 0x7000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0xf 0x7000000100 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0x10 0x13000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0x11 0x13000000100 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0x12 0x0 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_npu_T_O 0x13 0x0 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_pciet_T_O 0x0 0x40000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_pciet_T_O 0x1 0x60000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_pciet_T_O 0x2 0x8000000000 >,
+ /bits/ 64 <tbu4_snoc_I_O snoc_pciet_T_O 0x3 0xa000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt0_p2_T_O 0x0 0x80000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt0_p2_T_O 0x1 0x100000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt0_p2_T_O 0x2 0x200000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt0_p2_T_O 0x3 0x400000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt0_p2_T_O 0x4 0x800000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt0_p2_T_O 0x5 0x2000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt0_p2_T_O 0x6 0xc000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt0_p2_T_O 0x7 0xe000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt0_p2_T_O 0x8 0x4000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt0_p2_T_O 0x9 0x4000000100 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt0_p2_T_O 0xa 0x10000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt0_p2_T_O 0xb 0x10000000100 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt1_p2_T_O 0x0 0x80000080 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt1_p2_T_O 0x1 0x100000080 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt1_p2_T_O 0x2 0x200000080 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt1_p2_T_O 0x3 0x400000080 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt1_p2_T_O 0x4 0x800000080 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt1_p2_T_O 0x5 0x2000000080 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt1_p2_T_O 0x6 0xc000000080 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt1_p2_T_O 0x7 0xe000000080 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt1_p2_T_O 0x8 0x4000000080 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt1_p2_T_O 0x9 0x4000000180 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt1_p2_T_O 0xa 0x10000000080 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_ddrt1_p2_T_O 0xb 0x10000000180 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_dspt_T_O 0x0 0x520e0000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_dspt_T_O 0x1 0x720e0000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_dspt_T_O 0x2 0x5b000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_dspt_T_O 0x3 0x7b000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_dspt_T_O 0x4 0x14003000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_dspt_T_O 0x5 0x1400b000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x0 0x58400000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x1 0x78400000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x2 0x14000400000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x3 0x14008400000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x4 0x58800000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x5 0x78800000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x6 0x14000800000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x7 0x14008800000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x8 0x59000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x9 0x5a000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0xa 0x5b000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0xb 0x79000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0xc 0x7a000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0xd 0x7b000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0xe 0x14001000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0xf 0x14002000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x10 0x14003000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x11 0x14009000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x12 0x1400a000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x13 0x1400b000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x14 0x50000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x15 0x70000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x16 0x40000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x17 0x60000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x18 0x80000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x19 0x100000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x1a 0x200000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x1b 0x400000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x1c 0x800000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x1d 0x1800000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x1e 0x3800000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x1f 0xd800000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x20 0xf800000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x21 0x2000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x22 0x7000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x23 0x7000000100 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x24 0xc000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x25 0xe000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x26 0x13000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x27 0x13000000100 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x28 0x4000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x29 0x4000000100 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x2a 0x8000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x2b 0xa000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x2c 0x10000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_mcput_d2d_T_O 0x2d 0x10000000100 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0x0 0x52080000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0x1 0x72080000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0x2 0x59000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0x3 0x5a000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0x4 0x79000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0x5 0x7a000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0x6 0x14001000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0x7 0x14002000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0x8 0x14009000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0x9 0x1400a000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0xa 0x1800000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0xb 0x3800000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0xc 0xd800000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0xd 0xf800000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0xe 0x7000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0xf 0x7000000100 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0x10 0x13000000000 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0x11 0x13000000100 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0x12 0x0 >,
+ /bits/ 64 <tcu_snoc_I_O snoc_npu_T_O 0x13 0x0 >;
+ };
+ };
+
+ ErrorLogger4 {
+ compatible = "eswin,win2030,register";
+ offset,length = < 0x24 32>;
+ description = "Register 4 to log errors";
+ addr_msb {
+ compatible = "eswin,win2030,bitfield";
+ description = "Stores NTTP packet header field Addr (MSBs) of the logged error";
+ offset,length = < 0 9 >;
+ };
+ };
+
+ ErrorLogger5 {
+ compatible = "eswin,win2030,register";
+ offset,length = < 0x28 32>;
+ description = "Register 5 to log errors";
+
+ User_flag {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0x0 18 >;
+ lut =
+ "Cache_0",
+ "Cache_1",
+ "Cache_2",
+ "Cache_3",
+ "Prot_0 ",
+ "Prot_1 ",
+ "Prot_2 ",
+ "User_0 ",
+ "User_1 ",
+ "User_2 ",
+ "User_3 ",
+ "User_4 ",
+ "User_5 ",
+ "User_6 ",
+ "qos0",
+ "qos1",
+ "qos2",
+ "qos3";
+ };
+ };
+};
+
+d1_media_noc:d1_media_noc@72021400 {
+ compatible = "eswin,win2030-noc";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ reg = <0 0x72021400 0 0x4000>;
+ interrupts = <454>;
+ interrupt-names = "error";
+ interrupt-parent = <&plic1>;
+ errlogger,idx = <0 1 3 4 5>;
+ eswin,qos-configs = "GPU", "TBU2", "VC";
+ eswin,GPU-qos-base = <0x72021480>;
+ eswin,GPU-qos-settings = <
+ 0x8 0x4 /* prio */
+ 0xC 0x2 /* mode */
+ 0x10 0x1E0 /* bandwidth */
+ 0x14 0x1 /* saturation */
+ 0x18 0x1>; /* QoSEn */
+
+ eswin,TBU2-qos-base = <0x72021500>;
+ eswin,TBU2-qos-settings = <
+ 0x8 0x4 /* prio */
+ 0xC 0x2 /* mode */
+ 0x10 0x18 /* bandwidth */
+ 0x14 0x10 /* saturation */
+ 0x18 0x1>; /* QoSEn */
+
+ eswin,VC-qos-base = <0x72021580>;
+ eswin,VC-qos-settings = <
+ 0x8 0x4 /* prio */
+ 0xC 0x2 /* mode */
+ 0x10 0x18 /* bandwidth */
+ 0x14 0x10 /* saturation */
+ 0x18 0x1>; /* QoSEn */
+#ifdef PLATFORM_HAPS
+ clock,rate = <5000000>; /*haps ddr controller clk*/
+#endif
+ sideband_manager@72022000 {
+ compatible = "eswin,win2xxx-noc-sideband-manager";
+ reg = <0 0x72022000 0 0x10>;
+ SenseIn0 =
+ <SBM_MNOC_GPU OFFSET0>,
+ <SBM_MNOC_TBU2 OFFSET1>,
+ <SBM_MNOC_VC OFFSET2>,
+ <SBM_MNOC_DDRT0_P3 OFFSET3>,
+ <SBM_MNOC_DDRT1_P3 OFFSET4>;
+ bf-name =
+ "SBM_MNOC_GPU",
+ "SBM_MNOC_TBU2",
+ "SBM_MNOC_VC",
+ "SBM_MNOC_DDRT0_P3",
+ "SBM_MNOC_DDRT1_P3";
+ };
+
+ mnoc_packet_ddr0_p3_req_probe@72020000 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0 0x72020000 0 0x4000>;
+ clocks = <&d1_clock WIN2030_CLK_DDRT0_P3_ACLK>;
+ clock-names = "clk";
+ interrupts = <458>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic1>;
+ filter,nr = <1>;
+ counter,nr = <2>;
+ portsel = "ddr0_p3_req";
+ };
+ mnoc_packet_ddr1_p3_req_probe@72020800 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0 0x72020800 0 0x4000>;
+ clocks =<&d1_clock WIN2030_CLK_DDRT1_P3_ACLK>;
+ clock-names = "clk";
+ interrupts = <456>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic1>;
+ filter,nr = <1>;
+ counter,nr = <2>;
+ portsel = "ddr1_p3_req";
+ };
+ mnoc_trans_probe@72021000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ compatible = "eswin,win2xxx-noc-trans-probe";
+ reg = <0 0x72021000 0 0x4000>;
+ clocks =<&d1_clock WIN2030_CLK_NOC_NSP_CLK>;
+ clock-names = "clk";
+ interrupts = <453>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic1>;
+ filter,nr = <3>;
+ counter,nr = <12>;
+ profiler,nr = <1>;
+ portsel = "gpu", "tbu2", "vc";
+ mnoc_trans_gpu_filter@72021600 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x72021600 0 0x80>;
+ };
+ mnoc_trans_tbu2_filter@72021680 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x72021680 0 0x80>;
+ };
+ mnoc_trans_vc_filter@72021700 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x72021700 0 0x80>;
+ };
+ mnoc_trans_profiler@72021780 {
+ compatible = "eswin,win2xxx-noc-trans-profiler";
+ reg = <0 0x72021780 0 0x80>;
+ };
+ };
+ ErrorLogger0 {
+ compatible = "eswin,win2030,register";
+ offset,length = < 0x14 32 >;
+ description = "Register 0 to log errors";
+ lock {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0 1 >;
+ lut = "Not Locked", "Locked";
+ };
+ OpCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 1 4 >;
+ lut = "RD: data read with incrementing address",
+ "RDW: data read with wrapping address",
+ "RDL: allocates monitor in the Target with incrementing address",
+ "RDX: exclusive read with incrementing address",
+ "WR: data write with incrementing address",
+ "WRW: data write with wrapping address",
+ "WRC: conditional write if matching monitor in Target is found",
+ "RSV: reserved",
+ "PRE: preamble packet of linked sequence (locked sequence)",
+ "URG: urgency packet used for QoS (status must be REQ)";
+ };
+ ErrCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 8 3 >;
+ lut = "SLV (error source: Target): error detected by the Slave without any information or no Error",
+ "DEC (error source: Initiator NIU): decode error",
+ "UNS (error source: Target NIU): unsupported access type",
+ "DISC (error source: Power Disconnect): disconnected Target or NoC domain",
+ "SEC (error source: Initiator NIU or Firewall): security error",
+ "HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator",
+ "TMO (error source: Target NIU): time-out",
+ "RSV: reserved";
+
+ };
+ Len1 {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 16 12 >;
+ };
+ Format {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 31 1 >;
+ lut = "NTTP v3.0 (Invalid)", "NTTP v3.5 (Ok)";
+ };
+ };
+
+ ErrorLogger1 {
+ compatible = "eswin,win2030,register", "eswin,win2030,noc,filter,routeid";
+ offset,length = < 0x18 32>;
+ description = "Register 1 to log errors";
+ InitFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 14 2 >;
+ lut =
+ "gpu_mnoc/I/0",
+ "snoc_mnoc/I/0",
+ "tbu2_mnoc/I/0",
+ "vc_mnoc/I/0";
+ };
+
+ TargetFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 12 2 >;
+ lut =
+ "mnoc_ddrt0_p3/T/0",
+ "mnoc_ddrt1_p3/T/0",
+ "mnoc_service/T/0",
+ "mnoc_snoc/T/0";
+ };
+
+ TargetSubRange {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 9 3 >;
+ };
+
+ SeqId {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0 9 >;
+ };
+ };
+
+ ErrorLogger3 {
+ /* This register does not really include a bitfield or its bitfield is 32 bits and it provides an offset address */
+ /* To calculate the absolute address, you must use the initflow:targetflow:subrange from ErrorLogger1 register */
+ /* And use it as an index in the aperture table. Then you must add the value of this register to the value given */
+ /* by the table to get the absolute address. */
+ compatible = "eswin,win2030,register";
+ offset,length = <0x20 32>;
+ description = "Register 3 to log errors";
+ aperture-link = <1>; /* link to ErrorLogger whose information are required to calculate real absolute address */
+ msb-link = <4>; /*indicate which ErrorLogger contains the msb addrs, -1 means no*/
+ AbsoluteAddress {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 9 7 >; /* bitfield initflow:targeflow:subrange from aperture-link register */
+ aperture-size= < 55 >; /* Number of line in the aperture table below */
+ aperture-idx,aperture-base = /* Aperture_idx is concatenation of initflow:targetflow:subrange bitfield from ErrorLogger1 */
+ /bits/ 64 <0x0 0x0 0x0 0x80000000 >,
+ /bits/ 64 <0x0 0x0 0x1 0x100000000 >,
+ /bits/ 64 <0x0 0x0 0x2 0x200000000 >,
+ /bits/ 64 <0x0 0x0 0x3 0x400000000 >,
+ /bits/ 64 <0x0 0x0 0x4 0x800000000 >,
+ /bits/ 64 <0x0 0x0 0x5 0x2000000000 >,
+ /bits/ 64 <0x0 0x0 0x6 0x4000000000 >,
+ /bits/ 64 <0x0 0x0 0x7 0x4000000100 >,
+ /bits/ 64 <0x0 0x1 0x0 0x80000080 >,
+ /bits/ 64 <0x0 0x1 0x1 0x100000080 >,
+ /bits/ 64 <0x0 0x1 0x2 0x200000080 >,
+ /bits/ 64 <0x0 0x1 0x3 0x400000080 >,
+ /bits/ 64 <0x0 0x1 0x4 0x800000080 >,
+ /bits/ 64 <0x0 0x1 0x5 0x2000000080 >,
+ /bits/ 64 <0x0 0x1 0x6 0x4000000080 >,
+ /bits/ 64 <0x0 0x1 0x7 0x4000000180 >,
+ /bits/ 64 <0x0 0x3 0x0 0x0 >,
+ /bits/ 64 <0x1 0x2 0x0 0x52020000 >,
+ /bits/ 64 <0x1 0x2 0x1 0x72020000 >,
+ /bits/ 64 <0x1 0x2 0x2 0x0 >,
+ /bits/ 64 <0x1 0x2 0x3 0x0 >,
+ /bits/ 64 <0x2 0x0 0x0 0x80000000 >,
+ /bits/ 64 <0x2 0x0 0x1 0x100000000 >,
+ /bits/ 64 <0x2 0x0 0x2 0x200000000 >,
+ /bits/ 64 <0x2 0x0 0x3 0x400000000 >,
+ /bits/ 64 <0x2 0x0 0x4 0x800000000 >,
+ /bits/ 64 <0x2 0x0 0x5 0x2000000000 >,
+ /bits/ 64 <0x2 0x0 0x6 0x4000000000 >,
+ /bits/ 64 <0x2 0x0 0x7 0x4000000100 >,
+ /bits/ 64 <0x2 0x1 0x0 0x80000080 >,
+ /bits/ 64 <0x2 0x1 0x1 0x100000080 >,
+ /bits/ 64 <0x2 0x1 0x2 0x200000080 >,
+ /bits/ 64 <0x2 0x1 0x3 0x400000080 >,
+ /bits/ 64 <0x2 0x1 0x4 0x800000080 >,
+ /bits/ 64 <0x2 0x1 0x5 0x2000000080 >,
+ /bits/ 64 <0x2 0x1 0x6 0x4000000080 >,
+ /bits/ 64 <0x2 0x1 0x7 0x4000000180 >,
+ /bits/ 64 <0x2 0x3 0x0 0x0 >,
+ /bits/ 64 <0x3 0x0 0x0 0x80000000 >,
+ /bits/ 64 <0x3 0x0 0x1 0x100000000 >,
+ /bits/ 64 <0x3 0x0 0x2 0x200000000 >,
+ /bits/ 64 <0x3 0x0 0x3 0x400000000 >,
+ /bits/ 64 <0x3 0x0 0x4 0x800000000 >,
+ /bits/ 64 <0x3 0x0 0x5 0x2000000000 >,
+ /bits/ 64 <0x3 0x0 0x6 0x4000000000 >,
+ /bits/ 64 <0x3 0x0 0x7 0x4000000100 >,
+ /bits/ 64 <0x3 0x1 0x0 0x80000080 >,
+ /bits/ 64 <0x3 0x1 0x1 0x100000080 >,
+ /bits/ 64 <0x3 0x1 0x2 0x200000080 >,
+ /bits/ 64 <0x3 0x1 0x3 0x400000080 >,
+ /bits/ 64 <0x3 0x1 0x4 0x800000080 >,
+ /bits/ 64 <0x3 0x1 0x5 0x2000000080 >,
+ /bits/ 64 <0x3 0x1 0x6 0x4000000080 >,
+ /bits/ 64 <0x3 0x1 0x7 0x4000000180 >,
+ /bits/ 64 <0x3 0x3 0x0 0x0 >;
+ };
+ };
+
+ ErrorLogger4 {
+ compatible = "eswin,win2030,register";
+ offset,length = < 0x24 32>;
+ description = "Register 4 to log errors";
+ addr_msb {
+ compatible = "eswin,win2030,bitfield";
+ description = "Stores NTTP packet header field Addr (MSBs) of the logged error";
+ offset,length = < 0 9 >;
+ };
+ };
+
+ ErrorLogger5 {
+ compatible = "eswin,win2030,register";
+ offset,length = < 0x28 32 >;
+ description = "Register 5 to log errors";
+
+ User_flag {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0x0 18 >;
+ lut =
+ "Cache_0",
+ "Cache_1",
+ "Cache_2",
+ "Cache_3",
+ "Prot_0 ",
+ "Prot_1 ",
+ "Prot_2 ",
+ "User_0 ",
+ "User_1 ",
+ "User_2 ",
+ "User_3 ",
+ "User_4 ",
+ "User_5 ",
+ "User_6 ",
+ "qos0",
+ "qos1",
+ "qos2",
+ "qos3";
+ };
+ };
+};
+
+d1_realtime_noc:d1_realtime_noc@72041400 {
+ compatible = "eswin,win2030-noc";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ reg = <0 0x72041400 0 0x4000>;
+ interrupts = <448>;
+ interrupt-names = "error";
+ interrupt-parent = <&plic1>;
+ errlogger,idx = <0 1 3 4 5>;
+ eswin,qos-configs = "TBU0", "VO";
+ eswin,TBU0-qos-base = <0x72041480>;
+ eswin,TBU0-qos-settings = <
+ 0x8 0x4 /* prio */
+ 0xC 0x2 /* mode */
+ 0x10 0x1E0 /* bandwidth */
+ 0x14 0x1 /* saturation */
+ 0x18 0x1>; /* QoSEn */
+
+ eswin,VO-qos-base = <0x72041500>;
+ eswin,VO-qos-settings = <
+ 0x8 0x4 /* prio */
+ 0xC 0x2 /* mode */
+ 0x10 0x18 /* bandwidth */
+ 0x14 0x10 /* saturation */
+ 0x18 0x1>; /* QoSEn */
+#ifdef PLATFORM_HAPS
+ clock,rate = <5000000>; /*haps ddr controller clk*/
+#endif
+ sideband_manager@72042000 {
+ compatible = "eswin,win2xxx-noc-sideband-manager";
+ reg = <0 0x72042000 0 0x10>;
+ SenseIn0 =
+ <SBM_RNOC_TBU0 OFFSET0>,
+ <SBM_RNOC_VO OFFSET1>,
+ <SBM_RNOC_DDRT0_P4 OFFSET2>,
+ <SBM_RNOC_DDRT1_P4 OFFSET3>;
+ bf-name =
+ "SBM_RNOC_TBU0",
+ "SBM_RNOC_VO",
+ "SBM_RNOC_DDRT0_P4",
+ "SBM_RNOC_DDRT1_P4";
+ };
+
+ rnoc_packet_ddr0_p4_req_probe@72040000 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0 0x72040000 0 0x4000>;
+ clocks = <&d1_clock WIN2030_CLK_DDRT0_P4_ACLK>;
+ clock-names = "clk";
+ interrupts = <452>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic1>;
+ filter,nr = <1>;
+ counter,nr = <2>;
+ portsel = "ddr0_p4_req";
+ };
+ rnoc_packet_ddr1_p4_req_probe@72040800 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0 0x72040800 0 0x4000>;
+ clocks =<&d1_clock WIN2030_CLK_DDRT1_P4_ACLK>;
+ clock-names = "clk";
+ interrupts = <450>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic1>;
+ filter,nr = <1>;
+ counter,nr = <2>;
+ portsel = "ddr1_p4_req";
+ };
+ rnoc_trans_probe@72041000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ compatible = "eswin,win2xxx-noc-trans-probe";
+ reg = <0 0x72041000 0 0x4000>;
+ clocks =<&d1_clock WIN2030_CLK_NOC_NSP_CLK>;
+ clock-names = "clk";
+ interrupts = <447>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic1>;
+ filter,nr = <2>;
+ counter,nr = <8>;
+ profiler,nr = <1>;
+ portsel = "tbu0", "vo";
+ rnoc_trans_tbu0_filter@72041580 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x72041580 0 0x80>;
+ };
+ rnoc_trans_vo_filter@72041600 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x72041600 0 0x80>;
+ };
+ rnoc_trans_profiler@72041680 {
+ compatible = "eswin,win2xxx-noc-trans-profiler";
+ reg = <0 0x72041680 0 0x80>;
+ };
+ };
+ ErrorLogger0 {
+ compatible = "eswin,win2030,register";
+ offset,length = < 0x14 32 >;
+ description = "Register 0 to log errors";
+ lock {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0 1 >;
+ lut = "Not Locked", "Locked";
+ };
+ OpCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 1 4 >;
+ lut = "RD: data read with incrementing address",
+ "RDW: data read with wrapping address",
+ "RDL: allocates monitor in the Target with incrementing address",
+ "RDX: exclusive read with incrementing address",
+ "WR: data write with incrementing address",
+ "WRW: data write with wrapping address",
+ "WRC: conditional write if matching monitor in Target is found",
+ "RSV: reserved",
+ "PRE: preamble packet of linked sequence (locked sequence)",
+ "URG: urgency packet used for QoS (status must be REQ)";
+ };
+ ErrCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 8 3 >;
+ lut = "SLV (error source: Target): error detected by the Slave without any information or no Error",
+ "DEC (error source: Initiator NIU): decode error",
+ "UNS (error source: Target NIU): unsupported access type",
+ "DISC (error source: Power Disconnect): disconnected Target or NoC domain",
+ "SEC (error source: Initiator NIU or Firewall): security error",
+ "HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator",
+ "TMO (error source: Target NIU): time-out",
+ "RSV: reserved";
+
+ };
+ Len1 {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 16 12 >;
+ };
+ Format {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 31 1 >;
+ lut = "NTTP v3.0 (Invalid)", "NTTP v3.5 (Ok)";
+ };
+ };
+
+ ErrorLogger1 {
+ compatible = "eswin,win2030,register", "eswin,win2030,noc,filter,routeid";
+ offset,length = < 0x18 32>;
+ description = "Register 1 to log errors";
+ InitFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 14 2 >;
+ lut =
+ "snoc_rnoc/I/0",
+ "tbu0_rnoc/I/0",
+ "vo_rnoc/I/0",
+ "RESERVED0";
+ };
+
+ TargetFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 12 2 >;
+ lut =
+ "rnoc_ddrt0_p4/T/0",
+ "rnoc_ddrt1_p4/T/0",
+ "rnoc_service/T/0",
+ "rnoc_snoc/T/0";
+ };
+
+ TargetSubRange {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 9 3 >;
+ };
+
+ SeqId {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0 9 >;
+ };
+ };
+
+ ErrorLogger3 {
+ /* This register does not really include a bitfield or its bitfield is 32 bits and it provides an offset address */
+ /* To calculate the absolute address, you must use the initflow:targetflow:subrange from ErrorLogger1 register */
+ /* And use it as an index in the aperture table. Then you must add the value of this register to the value given */
+ /* by the table to get the absolute address. */
+ compatible = "eswin,win2030,register";
+ offset,length = <0x20 32>;
+ description = "Register 3 to log errors";
+ aperture-link = <1>; /* link to ErrorLogger whose information are required to calculate real absolute address */
+ msb-link = <4>; /*indicate which ErrorLogger contains the msb addrs, -1 means no*/
+ AbsoluteAddress {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 9 7 >; /* bitfield initflow:targeflow:subrange from aperture-link register */
+ aperture-size= < 40 >; /* Number of line in the aperture table below */
+ aperture-idx,aperture-base = /* Aperture_idx is concatenation of initflow:targetflow:subrange bitfield from ErrorLogger1 */
+ /bits/ 64 <0x0 0x2 0x0 0x52040000 >,
+ /bits/ 64 <0x0 0x2 0x1 0x72040000 >,
+ /bits/ 64 <0x0 0x2 0x2 0x0 >,
+ /bits/ 64 <0x0 0x2 0x3 0x0 >,
+ /bits/ 64 <0x1 0x0 0x0 0x80000000 >,
+ /bits/ 64 <0x1 0x0 0x1 0x100000000 >,
+ /bits/ 64 <0x1 0x0 0x2 0x200000000 >,
+ /bits/ 64 <0x1 0x0 0x3 0x400000000 >,
+ /bits/ 64 <0x1 0x0 0x4 0x800000000 >,
+ /bits/ 64 <0x1 0x0 0x5 0x2000000000 >,
+ /bits/ 64 <0x1 0x1 0x0 0x80000080 >,
+ /bits/ 64 <0x1 0x1 0x1 0x100000080 >,
+ /bits/ 64 <0x1 0x1 0x2 0x200000080 >,
+ /bits/ 64 <0x1 0x1 0x3 0x400000080 >,
+ /bits/ 64 <0x1 0x1 0x4 0x800000080 >,
+ /bits/ 64 <0x1 0x1 0x5 0x2000000080 >,
+ /bits/ 64 <0x1 0x3 0x0 0x59000000 >,
+ /bits/ 64 <0x1 0x3 0x1 0x79000000 >,
+ /bits/ 64 <0x1 0x3 0x2 0x14001000000 >,
+ /bits/ 64 <0x1 0x3 0x3 0x14009000000 >,
+ /bits/ 64 <0x1 0x3 0x4 0x0 >,
+ /bits/ 64 <0x1 0x3 0x5 0x0 >,
+ /bits/ 64 <0x2 0x0 0x0 0x80000000 >,
+ /bits/ 64 <0x2 0x0 0x1 0x100000000 >,
+ /bits/ 64 <0x2 0x0 0x2 0x200000000 >,
+ /bits/ 64 <0x2 0x0 0x3 0x400000000 >,
+ /bits/ 64 <0x2 0x0 0x4 0x800000000 >,
+ /bits/ 64 <0x2 0x0 0x5 0x2000000000 >,
+ /bits/ 64 <0x2 0x1 0x0 0x80000080 >,
+ /bits/ 64 <0x2 0x1 0x1 0x100000080 >,
+ /bits/ 64 <0x2 0x1 0x2 0x200000080 >,
+ /bits/ 64 <0x2 0x1 0x3 0x400000080 >,
+ /bits/ 64 <0x2 0x1 0x4 0x800000080 >,
+ /bits/ 64 <0x2 0x1 0x5 0x2000000080 >,
+ /bits/ 64 <0x2 0x3 0x0 0x59000000 >,
+ /bits/ 64 <0x2 0x3 0x1 0x79000000 >,
+ /bits/ 64 <0x2 0x3 0x2 0x14001000000 >,
+ /bits/ 64 <0x2 0x3 0x3 0x14009000000 >,
+ /bits/ 64 <0x2 0x3 0x4 0x0 >,
+ /bits/ 64 <0x2 0x3 0x5 0x0 >;
+ };
+ };
+
+ ErrorLogger4 {
+ compatible = "eswin,win2030,register";
+ offset,length = < 0x24 32>;
+ description = "Register 4 to log errors";
+ addr_msb {
+ compatible = "eswin,win2030,bitfield";
+ description = "Stores NTTP packet header field Addr (MSBs) of the logged error";
+ offset,length = < 0 9 >;
+ };
+ };
+
+ ErrorLogger5 {
+ compatible = "eswin,win2030,register";
+ offset,length = < 0x28 32 >;
+ description = "Register 5 to log errors";
+
+ User_flag {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = < 0x0 16 >;
+ lut =
+ "Cache_0",
+ "Cache_1",
+ "Cache_2",
+ "Cache_3",
+ "Prot_0 ",
+ "Prot_1 ",
+ "Prot_2 ",
+ "User_0 ",
+ "User_1 ",
+ "User_2 ",
+ "User_3 ",
+ "User_4 ",
+ "qos0",
+ "qos1",
+ "qos2",
+ "qos3";
+ };
+ };
+};
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
new file mode 100644
index 000000000000..6c887ecdc68a
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
@@ -0,0 +1,2322 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Include file for Die1 System peripherals of Eswin EIC770x family SoC.
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#include "eswin-win2030-platform.dtsi"
+
+#include "eswin-win2030-arch-d2d.dtsi"
+
+
+#include <dt-bindings/memory/eswin-win2030-sid.h>
+#include <dt-bindings/mailbox/eswin-mailbox.h>
+#include <dt-bindings/reset/eswin,win2030-syscrg.h>
+#include <dt-bindings/clock/win2030-clock.h>
+#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/interconnect/eswin,win2030.h>
+
+/ {
+#if (CHIPLET_AND_DIE == 0x1)
+ aliases {
+ serial0 = &d1_uart0;
+ ethernet0 = &d1_gmac0;
+ ethernet1 = &d1_gmac1;
+ };
+#endif
+ d1_cpu_opp_table: opp-table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-24000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_24M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-100000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_100M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-200000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_200M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_400M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_500M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_600M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-700000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_700M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-800000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_800M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-900000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_900M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1000M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1200M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-1300000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1300M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1400M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1500M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-1600000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1600M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1700M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1800M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ };
+};
+
+&SOC {
+ d1_uart0: serial@0x70900000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x70900000 0x0 0x10000>;
+ clock-frequency = <LSPCLK_FREQ>;
+ interrupt-parent = <&plic1>;
+ interrupts = <UART0_INT>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ numa-node-id = <1>;
+ };
+
+ d1_uart1: serial@0x70910000 {
+ reg = <0x0 0x70910000 0x0 0x10000>;
+ };
+
+ d1_sys_con: scu_sys_con@0x71810000 {
+ compatible = "eswin,win2030-scu-sys-con", "syscon";
+ #syscon-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x71810000 0x0 0x8000>;
+ numa-node-id = <1>;
+ d1_noc_wdt:noc@71810324 {
+ compatible = "eswin,win2030-noc-wdt";
+ interrupt-parent = <&plic1>;
+ interrupts = <392>, <393>, <394>, <395>,
+ <396>, <397>, <398>, <399>, <400>,
+ <401>, <402>, <403>, <404>, <405>,
+ <406>, <407>, <408>, <409>, <410>,
+ <411>, <412>, <413>, <414>, <415>,
+ <416>, <417>, <418>, <419>, <420>,
+ <421>, <422>, <423>, <424>, <425>,
+ <426>;
+ };
+ };
+
+ d1_sys_crg: sys-crg@71828000 {
+ compatible = "eswin,win2030-sys-crg", "syscon", "simple-mfd";
+ reg = <0x000000 0x71828000 0x000000 0x80000>;
+ numa-node-id = <1>;
+ d1_reset: reset-controller {
+ compatible = "eswin,win2030-reset";
+ #reset-cells = <2>;
+ };
+ d1_clock: clock-controller {
+ compatible = "eswin,win2030-clock";
+ #clock-cells = <1>;
+ };
+ };
+
+ d1_hsp_sp_csr: hsp_sp_top_csr@0x70440000 {
+ compatible = "eswin,win2030-hsp-sp-csr", "syscon";
+ #size-cells = <2>;
+ reg = <0x0 0x70440000 0x0 0x2000>;
+ };
+
+ smmu1: iommu@70c00000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x0 0x70c00000 0x0 0x100000>;
+ eswin,syscfg = <&d1_sys_con 0x3fc>;
+ interrupt-parent = <&plic1>;
+ interrupts = <356>,
+ <360>,
+ <357>,
+ <358>;
+ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
+ #iommu-cells = <1>;
+ resets = <&d1_reset TCU_RST_CTRL SW_TCU_AXI_RSTN>,
+ <&d1_reset TCU_RST_CTRL SW_TCU_CFG_RSTN>,
+ <&d1_reset TCU_RST_CTRL TBU_RSTN_0>,
+ <&d1_reset TCU_RST_CTRL TBU_RSTN_1>,
+ <&d1_reset TCU_RST_CTRL TBU_RSTN_2>,
+ <&d1_reset TCU_RST_CTRL TBU_RSTN_3>,
+ <&d1_reset TCU_RST_CTRL TBU_RSTN_4>,
+ <&d1_reset TCU_RST_CTRL TBU_RSTN_5>,
+ <&d1_reset TCU_RST_CTRL TBU_RSTN_6>,
+ <&d1_reset TCU_RST_CTRL TBU_RSTN_7>;
+ reset-names = "axi_rst", "cfg_rst", "tbu0_rst", "tbu1_rst", "tbu2_rst", "tbu3_rst",
+ "tbu4_rst", "tbu5_rst", "tbu6_rst", "tbu7_rst";
+ status = "disabled";
+ numa-node-id = <1>;
+ };
+
+ smmu_pmu1: pmu@70c02000 {
+ compatible = "arm,smmu-v3-pmcg";
+ reg = <0x0 0x70c02000 0x0 0x1000>,
+ <0x0 0x70c22000 0x0 0x1000>;
+ eswin,syscfg = <&d1_sys_con 0x3fc>;
+ interrupt-parent = <&plic1>;
+ interrupts = <363>;
+ status = "disabled";
+ numa-node-id = <1>;
+ };
+
+ dev_foo_for_die1_mapping: E21@2 {
+ compatible = "riscv,dev-foo-die1";
+ #size-cells = <2>;
+ dma-ranges = <0x0 0x20000000 0x0 0xc0000000 0x0 0x40000000>;
+ iommus = <&smmu1 WIN2030_SID_DEV_FOO_FOR_DIE1>;
+ status = "disabled";
+ numa-node-id = <1>;
+ };
+
+ d1_pmu: power-controller@71808000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "eswin,win2030-pmu-controller";
+ reg = <0x0 0x71808000 0x0 0x8000>;
+ numa-node-id = <1>;
+
+ d1_pmu_pcie: win2030-pmu-controller-port@0 {
+ compatible = "eswin,win2030-pmu-controller-port";
+ reg_base = <0x0>;
+ power_status = <1>;
+ power_delay = <6 6 3 3>;
+ clock_delay = <4 2 2 2>;
+ reset_delay = <2 4 2 2>;
+ clamp_delay = <3 3 2 2>;
+ label = "D1_PCIE";
+ };
+ d1_pmu_dsp1: win2030-pmu-controller-port@40 {
+ compatible = "eswin,win2030-pmu-controller-port";
+ reg_base = <0x40>;
+ power_status = <0>;
+ power_delay = <6 6 3 3>;
+ clock_delay = <4 2 2 2>;
+ reset_delay = <2 4 2 2>;
+ clamp_delay = <3 3 2 2>;
+ label = "D1_DSP1";
+ };
+ d1_pmu_vi: win2030-pmu-controller-port@80 {
+ compatible = "eswin,win2030-pmu-controller-port";
+ reg_base = <0x80>;
+ power_status = <1>;
+ power_delay = <6 6 3 3>;
+ clock_delay = <4 2 2 2>;
+ reset_delay = <2 4 2 2>;
+ clamp_delay = <3 3 2 2>;
+ label = "D1_VI";
+ };
+ d1_pmu_vo: win2030-pmu-controller-port@c0 {
+ compatible = "eswin,win2030-pmu-controller-port";
+ reg_base = <0xc0>;
+ power_status = <0>;
+ power_delay = <6 6 3 3>;
+ clock_delay = <4 2 2 2>;
+ reset_delay = <2 4 2 2>;
+ clamp_delay = <3 3 2 2>;
+ label = "D1_VO";
+ };
+ d1_pmu_codec: win2030-pmu-controller-port@140 {
+ compatible = "eswin,win2030-pmu-controller-port";
+ reg_base = <0x140>;
+ power_status = <0>;
+ power_delay = <6 6 3 3>;
+ clock_delay = <4 2 2 2>;
+ reset_delay = <2 4 2 2>;
+ clamp_delay = <3 3 2 2>;
+ label = "D1_CODEC";
+ };
+ d1_pmu_dsp2: win2030-pmu-controller-port@200 {
+ compatible = "eswin,win2030-pmu-controller-port";
+ reg_base = <0x200>;
+ power_status = <0>;
+ power_delay = <6 6 3 3>;
+ clock_delay = <4 2 2 2>;
+ reset_delay = <2 4 2 2>;
+ clamp_delay = <3 3 2 2>;
+ label = "D1_DSP2";
+ };
+ d1_pmu_dsp3: win2030-pmu-controller-port@240 {
+ compatible = "eswin,win2030-pmu-controller-port";
+ reg_base = <0x240>;
+ power_status = <0>;
+ power_delay = <6 6 3 3>;
+ clock_delay = <4 2 2 2>;
+ reset_delay = <2 4 2 2>;
+ clamp_delay = <3 3 2 2>;
+ label = "D1_DSP3";
+ };
+ };
+
+ d1_dmac0: dma-controller-hsp@0x70430000 {
+ compatible = "snps,axi-dma-1.01a";
+ reg = <0x0 0x70430000 0x0 0x10000>;
+ interrupt-parent = <&plic1>;
+ interrupts = <57>;
+ #dma-cells = <2>; // change dma-cells value <1> to <2>, to support peripheral selection dma-controller,See the parameter dmas for details;
+ clocks = <&d1_clock WIN2030_CLK_HSP_DMA0_CLK>;
+ clock-names = "core-clk";
+ resets = <&d1_reset HSPDMA_RST_CTRL SW_HSP_DMA0_RSTN>,
+ <&d1_reset HSPDMA_RST_CTRL SW_HSP_DMA_PRSTN>;
+ reset-names = "arst", "prst";
+ dma-channels = <12>;
+ snps,dma-masters = <1>;
+ snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11>;
+ snps,data-width = <2>;
+ snps,block-size = <0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000>;
+ snps,axi-max-burst-len = <16>;
+ snps,max-msize = <64>;
+ iommus = <&smmu1 WIN2030_SID_DMA0>;
+ tbus = <WIN2030_TBUID_DMA0>;
+ eswin,hsp_sp_csr = <&d1_hsp_sp_csr 0x104c>;
+ eswin,syscfg = <&d1_sys_con DMA1_SID_REG_OFFSET 0x370>;
+ numa-node-id = <1>;
+ };
+
+ d1_aon_dmac: dma-controller-aon@0x718c0000 {
+ compatible = "snps,axi-dma-1.01a";
+ reg = <0x0 0x718c0000 0x0 0x10000>;
+ interrupt-parent = <&plic1>;
+ interrupts = <289>;
+ #dma-cells = <2>; // change dma-cells value <1> to <2>, to support peripheral selection dma-controller,See the parameter dmas for details;
+ clocks = <&d1_clock WIN2030_CLK_AONDMA_ACLK>;
+ clock-names = "core-clk";
+ resets = <&d1_reset DMA1_RST_CTRL SW_DMA1_ARSTN>,
+ <&d1_reset DMA1_RST_CTRL SW_DMA1_HRSTN>;
+ reset-names = "arst", "prst";
+ dma-channels = <16>;
+ snps,dma-masters = <2>;
+ snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
+ snps,data-width = <3>;
+ snps,block-size = <0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000>;
+ snps,axi-max-burst-len = <32>;
+ snps,max-msize = <64>;
+ #size-cells = <2>;
+ #address-cells = <2>;
+ dma-ranges = <0x0 0x80000000 0x0 0x80000000 0x100 0x0>;
+ iommus = <&smmu1 WIN2030_SID_DMA1>;
+ tbus = <WIN2030_TBUID_DMA1>;
+ eswin,syscfg = <&d1_sys_con DMA1_SID_REG_OFFSET 0x370>;
+ numa-node-id = <1>;
+ };
+ noc {
+ compatible = "eswin,noc","simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ #include "eswin-win2030-die1-noc.dtsi"
+ };
+ vdec1: video-decoder1@70100000 {
+ compatible = "eswin,video-decoder1";
+ clocks = <&d1_clock WIN2030_CLK_VC_ACLK>,
+ <&d1_clock WIN2030_CLK_VC_CFG_CLK>,
+ <&d1_clock WIN2030_CLK_VC_JD_CLK>,
+ <&d1_clock WIN2030_CLK_VC_VD_CLK>,
+ <&d1_clock WIN2030_MUX_U_VCACLK_ROOT_2MUX1_GFREE>,
+ <&d1_clock WIN2030_SPLL0_FOUT1>,
+ <&d1_clock WIN2030_SPLL2_FOUT1>,
+ <&d1_clock WIN2030_CLK_VC_JD_PCLK>,
+ <&d1_clock WIN2030_CLK_VC_VD_PCLK>,
+ <&d1_clock WIN2030_CLK_VC_MON_PCLK>;
+ clock-names = "aclk", "cfg_clk", "jd_clk", "vd_clk", "vc_mux", "spll0_fout1", "spll2_fout1", "jd_pclk", "vd_pclk", "mon_pclk";
+ resets = <&d1_reset VC_RST_CTRL SW_VC_AXI_RSTN>,
+ <&d1_reset VC_RST_CTRL SW_VC_CFG_RSTN>,
+ <&d1_reset VC_RST_CTRL SW_VC_MONCFG_RSTN>,
+ <&d1_reset JD_RST_CTRL SW_JD_CFG_RSTN>,
+ <&d1_reset JD_RST_CTRL SW_JD_AXI_RSTN>,
+ <&d1_reset VD_RST_CTRL SW_VD_CFG_RSTN>,
+ <&d1_reset VD_RST_CTRL SW_VD_AXI_RSTN>;
+ reset-names = "axi", "cfg", "moncfg", "jd_cfg", "jd_axi", "vd_cfg", "vd_axi";
+ eswin,syscfg = <&d1_sys_con 0x0 0x4>;
+
+ vcmd-core = <0 0x6c>;
+ axife-core = <0x200 0x100>;
+ vdec-core = <0x800 0xc00>;
+ interrupt-parent = <&plic1>;
+ #size-cells = <2>;
+ dma-ranges = <0x0 0x0 0x0 0x80000000 0x200 0x0>;
+ iommus = <&smmu1 WIN2030_SID_VDEC>;
+ vccsr-reg = <0x0 0x701c0000 0x0 0x1000>;
+ numa-node-id = <1>;
+ tbus = <WIN2030_TBUID_VDEC>, <WIN2030_TBUID_JDEC>;
+
+ vdec_1: vdec1@70100000 {
+ core-name = "video-dec0";
+ base-addr = <0x70100000>;
+ interrupts = <236>;
+ };
+
+ jdec_1: jdec1@70120000 {
+ core-name = "jpeg-dec0";
+ base-addr = <0x70120000>;
+ interrupts = <237>;
+ };
+ };
+
+ venc1: video-encoder@70110000 {
+ compatible = "eswin,video-encoder1";
+ clocks = <&d1_clock WIN2030_CLK_VC_ACLK>,
+ <&d1_clock WIN2030_CLK_VC_CFG_CLK>,
+ <&d1_clock WIN2030_CLK_VC_JE_CLK>,
+ <&d1_clock WIN2030_CLK_VC_VE_CLK>,
+ <&d1_clock WIN2030_MUX_U_VCACLK_ROOT_2MUX1_GFREE>,
+ <&d1_clock WIN2030_SPLL0_FOUT1>,
+ <&d1_clock WIN2030_SPLL2_FOUT1>,
+ <&d1_clock WIN2030_CLK_VC_JE_PCLK>,
+ <&d1_clock WIN2030_CLK_VC_VE_PCLK>,
+ <&d1_clock WIN2030_CLK_VC_MON_PCLK>;
+ clock-names = "aclk", "cfg_clk", "je_clk", "ve_clk", "vc_mux", "spll0_fout1", "spll2_fout1", "je_pclk", "ve_pclk", "mon_pclk";
+ resets = <&d1_reset VC_RST_CTRL SW_VC_AXI_RSTN>,
+ <&d1_reset VC_RST_CTRL SW_VC_CFG_RSTN>,
+ <&d1_reset VC_RST_CTRL SW_VC_MONCFG_RSTN>,
+ <&d1_reset JE_RST_CTRL SW_JE_CFG_RSTN>,
+ <&d1_reset JE_RST_CTRL SW_JE_AXI_RSTN>,
+ <&d1_reset VE_RST_CTRL SW_VE_CFG_RSTN>,
+ <&d1_reset VE_RST_CTRL SW_VE_AXI_RSTN>;
+ reset-names = "axi", "cfg", "moncfg", "je_cfg", "je_axi", "ve_cfg", "ve_axi";
+ eswin,syscfg = <&d1_sys_con 0x0 0x4>;
+
+ vcmd-core = <0 0x6c>;
+ axife-core = <0x2000 0x7d0>;
+ venc-core = <0x1000 0x87c>;
+ interrupt-parent = <&plic1>;
+ #size-cells = <2>;
+ dma-ranges = <0x0 0x0 0x0 0x80000000 0x200 0x0>;
+ iommus = <&smmu1 WIN2030_SID_VENC>;
+ vccsr-reg = <0x0 0x701c0000 0x0 0x1000>;
+ numa-node-id = <1>;
+ tbus = <WIN2030_TBUID_VENC>, <WIN2030_TBUID_JENC>;
+
+ venc_1: venc0@70110000 {
+ core-name = "video-enc0";
+ base-addr = <0x70110000>;
+ interrupts = <229>;
+ };
+
+ jenc_1: jenc0@70130000 {
+ core-name = "jpeg-enc0";
+ base-addr = <0x70130000>;
+ interrupts = <232>;
+ };
+ };
+ /*mailbox between u84 & scpu*/
+ d1_mbox0: mbox@70a00000 {
+ compatible = "eswin,win2030-mailbox";
+ reg = <0 (ESWIN_MAILBOX_U84_TO_SCPU_REG_BASE + 0x20000000) 0 0x10000>,
+ <0 (ESWIN_MAILBOX_SCPU_TO_U84_REG_BASE + 0x20000000) 0 0x10000>;
+ interrupt-parent = <&plic1>;
+ interrupts = <117>;
+ #mbox-cells = <1>;
+ clocks = <&d1_clock WIN2030_CLK_MAILBOX_0>,
+ <&d1_clock WIN2030_CLK_MAILBOX_1>;
+ clock-names = "pclk_mailbox_host", "pclk_mailbox_device";
+ resets = <&d1_reset MBOX_RST_CTRL SW_MBOX_RST_N_0>,
+ <&d1_reset MBOX_RST_CTRL SW_MBOX_RST_N_1>;
+ reset-names = "rst", "rst_device";
+ lock-bit = <ESWIN_MAILBOX_WR_LOCK_BIT_U84>;
+ irq-bit = <ESWIN_MAIBOX_SCPU_IRQ_BIT>;
+ };
+
+ /*mailbox between u84 & lpcpu*/
+ d1_mbox1: mbox@70a20000 {
+ compatible = "eswin,win2030-mailbox";
+ reg = <0 (ESWIN_MAILBOX_U84_TO_LPCPU_REG_BASE + 0x20000000) 0 0x10000>,
+ <0 (ESWIN_MAILBOX_LPCPU_TO_U84_REG_BASE + 0x20000000) 0 0x10000>;
+ interrupt-parent = <&plic1>;
+ interrupts = <119>;
+ #mbox-cells = <1>;
+ clocks = <&d1_clock WIN2030_CLK_MAILBOX_2>,
+ <&d1_clock WIN2030_CLK_MAILBOX_3>;
+ resets = <&d1_reset MBOX_RST_CTRL SW_MBOX_RST_N_2>,
+ <&d1_reset MBOX_RST_CTRL SW_MBOX_RST_N_3>;
+ reset-names = "rst", "rst_device";
+ clock-names = "pclk_mailbox_host", "pclk_mailbox_device";
+ lock-bit = <ESWIN_MAILBOX_WR_LOCK_BIT_U84>;
+ irq-bit = <ESWIN_MAIBOX_LPCPU_IRQ_BIT>;
+ };
+
+ /*mailbox between u84 & npu_0*/
+ d1_mbox2: mbox@70a40000 {
+ compatible = "eswin,win2030-mailbox";
+ reg = <0 (ESWIN_MAILBOX_U84_TO_NPU_0_REG_BASE + 0x20000000) 0 0x10000>,
+ <0 (ESWIN_MAILBOX_NPU_0_TO_U84_REG_BASE + 0x20000000) 0 0x10000>;
+ interrupt-parent = <&plic1>;
+ interrupts = <121>;
+ #mbox-cells = <1>;
+ clocks = <&d1_clock WIN2030_CLK_MAILBOX_4>,
+ <&d1_clock WIN2030_CLK_MAILBOX_5>;
+ clock-names = "pclk_mailbox_host", "pclk_mailbox_device";
+ resets = <&d1_reset MBOX_RST_CTRL SW_MBOX_RST_N_4>,
+ <&d1_reset MBOX_RST_CTRL SW_MBOX_RST_N_5>;
+ reset-names = "rst", "rst_device";
+ lock-bit = <ESWIN_MAILBOX_WR_LOCK_BIT_U84>;
+ irq-bit = <ESWIN_MAIBOX_NPU_0_IRQ_BIT>;
+ };
+
+ /*mailbox between u84 & npu_1*/
+ d1_mbox3: mbox@70a60000 {
+ compatible = "eswin,win2030-mailbox";
+ reg = <0 (ESWIN_MAILBOX_U84_TO_NPU_1_REG_BASE + 0x20000000) 0 0x10000>,
+ <0 (ESWIN_MAILBOX_NP1_0_TO_U84_REG_BASE + 0x20000000) 0 0x10000>;
+ interrupt-parent = <&plic1>;
+ interrupts = <123>;
+ #mbox-cells = <1>;
+ clocks = <&d1_clock WIN2030_CLK_MAILBOX_6>,
+ <&d1_clock WIN2030_CLK_MAILBOX_7>;
+ clock-names = "pclk_mailbox_host", "pclk_mailbox_device";
+ resets = <&d1_reset MBOX_RST_CTRL SW_MBOX_RST_N_6>,
+ <&d1_reset MBOX_RST_CTRL SW_MBOX_RST_N_7>;
+ reset-names = "rst", "rst_device";
+ lock-bit = <ESWIN_MAILBOX_WR_LOCK_BIT_U84>;
+ irq-bit = <ESWIN_MAIBOX_NPU_1_IRQ_BIT>;
+ };
+
+ /*mailbox between u84 & dsp_0*/
+ d1_mbox4: mbox@70a80000 {
+ compatible = "eswin,dsp0-mailbox";
+ reg = <0 (ESWIN_MAILBOX_U84_TO_DSP_0_REG_BASE + 0x20000000) 0 0x10000>,
+ <0 (ESWIN_MAILBOX_DSP_0_TO_U84_REG_BASE + 0x20000000) 0 0x10000>;
+ interrupt-parent = <&plic1>;
+ interrupts = <125>;
+ #mbox-cells = <1>;
+ clocks = <&d1_clock WIN2030_CLK_MAILBOX_8>,
+ <&d1_clock WIN2030_CLK_MAILBOX_9>;
+ clock-names = "pclk_mailbox_host", "pclk_mailbox_device";
+ resets = <&d1_reset MBOX_RST_CTRL SW_MBOX_RST_N_8>,
+ <&d1_reset MBOX_RST_CTRL SW_MBOX_RST_N_9>;
+ reset-names = "rst", "rst_device";
+ lock-bit = <ESWIN_MAILBOX_WR_LOCK_BIT_U84>;
+ irq-bit = <ESWIN_MAIBOX_DSP_0_IRQ_BIT>;
+ };
+
+ /*mailbox between u84 & dsp_1*/
+ d1_mbox5: mbox@70aa0000 {
+ compatible = "eswin,dsp1-mailbox";
+ reg = <0 (ESWIN_MAILBOX_U84_TO_DSP_1_REG_BASE + 0x20000000) 0 0x10000>,
+ <0 (ESWIN_MAILBOX_DSP_1_TO_U84_REG_BASE + 0x20000000) 0 0x10000>;
+ interrupt-parent = <&plic1>;
+ interrupts = <127>;
+ #mbox-cells = <1>;
+ clocks = <&d1_clock WIN2030_CLK_MAILBOX_10>,
+ <&d1_clock WIN2030_CLK_MAILBOX_11>;
+ clock-names = "pclk_mailbox_host", "pclk_mailbox_device";
+ resets = <&d1_reset MBOX_RST_CTRL SW_MBOX_RST_N_10>,
+ <&d1_reset MBOX_RST_CTRL SW_MBOX_RST_N_11>;
+ reset-names = "rst", "rst_device";
+ lock-bit = <ESWIN_MAILBOX_WR_LOCK_BIT_U84>;
+ irq-bit = <ESWIN_MAIBOX_DSP_1_IRQ_BIT>;
+ };
+
+ /*mailbox between u84 & dsp_2*/
+ d1_mbox6: mbox@70ac0000 {
+ compatible = "eswin,dsp2-mailbox";
+ reg = <0 (ESWIN_MAILBOX_U84_TO_DSP_2_REG_BASE + 0x20000000) 0 0x10000>,
+ <0 (ESWIN_MAILBOX_DSP_2_TO_U84_REG_BASE + 0x20000000) 0 0x10000>;
+ interrupt-parent = <&plic1>;
+ interrupts = <129>;
+ #mbox-cells = <1>;
+ clocks = <&d1_clock WIN2030_CLK_MAILBOX_12>,
+ <&d1_clock WIN2030_CLK_MAILBOX_13>;
+ clock-names = "pclk_mailbox_host", "pclk_mailbox_device";
+ resets = <&d1_reset MBOX_RST_CTRL SW_MBOX_RST_N_12>,
+ <&d1_reset MBOX_RST_CTRL SW_MBOX_RST_N_13>;
+ reset-names = "rst", "rst_device";
+ lock-bit = <ESWIN_MAILBOX_WR_LOCK_BIT_U84>;
+ irq-bit = <ESWIN_MAIBOX_DSP_2_IRQ_BIT>;
+ };
+
+ /*mailbox between u84 & dsp_3*/
+ d1_mbox7: mbox@70ae0000 {
+ compatible = "eswin,dsp3-mailbox";
+ reg = <0 (ESWIN_MAILBOX_U84_TO_DSP_3_REG_BASE + 0x20000000) 0 0x10000>,
+ <0 (ESWIN_MAILBOX_DSP_3_TO_U84_REG_BASE + 0x20000000) 0 0x10000>;
+ interrupt-parent = <&plic1>;
+ interrupts = <131>;
+ #mbox-cells = <1>;
+ clocks = <&d1_clock WIN2030_CLK_MAILBOX_14>,
+ <&d1_clock WIN2030_CLK_MAILBOX_15>;
+ clock-names = "pclk_mailbox_host", "pclk_mailbox_device";
+ resets = <&d1_reset MBOX_RST_CTRL SW_MBOX_RST_N_14>,
+ <&d1_reset MBOX_RST_CTRL SW_MBOX_RST_N_15>;
+ reset-names = "rst", "rst_device";
+ lock-bit = <ESWIN_MAILBOX_WR_LOCK_BIT_U84>;
+ irq-bit = <ESWIN_MAIBOX_DSP_3_IRQ_BIT>;
+ };
+
+ d1_ipc_scpu:ipc@1 {
+ compatible = "eswin,win2030-ipc";
+ #size-cells = <2>;
+ dma-ranges = <0x0 0x80000000 0x0 0xc0000000 0x0 0x80000000>;
+ iommus = <&smmu1 WIN2030_SID_SCPU>, <&smmu1 WIN2030_SID_CRYPT>;
+ eswin,syscfg = <&d1_sys_con SCPU_SID_REG_OFFSET 0>,
+ <&d1_sys_con CRYPT_SID_REG_OFFSET 0>;
+ mboxes = <&d1_mbox0 0>;
+ mbox-names = "u84_scpu";
+ numa-node-id = <1>;
+ };
+
+ d1_lpcpu:lpcpu@1 {
+ compatible = "eswin,win2030-lpcpu";
+ fw-region = <&lpcpu1_reserved>;
+ clocks = <&d1_clock WIN2030_CLK_CLK_LPCPU_CORE>,
+ <&d1_clock WIN2030_CLK_CLK_LPCPU_BUS>;
+ clock-names = "core_clk", "bus_clk";
+
+ reset-names = "core_rst", "bus_rst", "dbg_rst";
+ resets = <&d1_reset LPCPU_RST_CTRL SW_LPCPU_CORE_RSTN>,
+ <&d1_reset LPCPU_RST_CTRL SW_LPCPU_BUS_RSTN>,
+ <&d1_reset LPCPU_RST_CTRL SW_LPCPU_DBG_RSTN>;
+ #size-cells = <2>;
+
+ dma-ranges = <0x0 0xb0000000 0x0 0xc0000000 0x0 0x50000000>;
+ iommus = <&smmu1 WIN2030_SID_LCPU>;
+ eswin,syscfg = <&d1_sys_con LCPU_SID_REG_OFFSET 0>;
+ tbus = <WIN2030_TBUID_LPCPU>;
+ mboxes = <&d1_mbox1 0>;
+ mbox-names = "u84_lpcpu";
+ numa-node-id = <1>;
+ status = "disabled";
+ };
+
+ d1_pvt0: pvt@0x70b00000 {
+ compatible = "eswin,eswin-pvt";
+ clocks = <&d1_clock WIN2030_CLK_PVT_CLK_0>;
+ clock-names = "pvt_clk";
+ resets = <&d1_reset PVT_RST_CTRL SW_PVT_RST_N_0>;
+ reset-names = "pvt_rst";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x70b00000 0x0 0x10000>;
+ interrupts = <349>;
+ interrupt-parent = <&plic1>;
+ status = "disabled";
+ };
+ d1_pvt1: pvt@0x72360000 {
+ compatible = "eswin,eswin-pvt";
+ clocks = <&d1_clock WIN2030_CLK_PVT_CLK_1>;
+ clock-names = "pvt_clk";
+ resets = <&d1_reset PVT_RST_CTRL SW_PVT_RST_N_1>;
+ reset-names = "pvt_rst";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x72360000 0x0 0x20000>;
+ interrupts = <350>;
+ interrupt-parent = <&plic1>;
+ status = "disabled";
+ };
+
+ d1_fan_control: fan_control@70b50000 {
+ compatible = "eswin-fan-control";
+ reg = <0x0 0x70b50000 0x0 0x10000>;
+ clocks = <&d1_clock WIN2030_CLK_LSP_FAN_PCLK>;
+ clock-names = "pclk";
+ resets = <&d1_reset FAN_RST_CTRL SW_FAN_RST_N>;
+ reset-names = "fan_rst";
+ interrupt-parent = <&plic1>;
+ interrupt-names = "fanirq";
+ interrupts = <354>;
+ pulses-per-revolution = <1>;
+ pwm-minimun-period = <3000000>;
+ pwms = <&d1_pwm0 0 200>;
+ status = "disabled";
+ };
+
+ d1_i2c0: i2c@70950000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ clocks = <&d1_clock WIN2030_CLK_LSP_I2C0_PCLK>;
+ clock-names = "pclk";
+ resets = <&d1_reset I2C_RST_CTRL SW_I2C_RST_N_0>;
+ reset-names = "rst";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x70950000 0x0 0x10000>;
+ interrupts = <105>;
+ interrupt-parent = <&plic1>;
+ status = "disabled";
+ eswin,i2c_dma = <&d1_aon_dmac>;
+ dma-names = "rx", "tx";
+ /*
+ * dmas : DMA specifiers
+ * &d1_aon_dmac : dma controller
+ * 24 : i2c0 aon dma handshake number
+ * 6 : i2c0 dma controller sel bit in sys_son dma_cfg reg(offset 0x370)
+ */
+ dmas = <&d1_aon_dmac 24 6>, <&d1_aon_dmac 25 6>;
+ };
+ d1_i2c1: i2c@70960000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ clocks = <&d1_clock WIN2030_CLK_LSP_I2C1_PCLK>;
+ clock-names = "pclk";
+ resets = <&d1_reset I2C_RST_CTRL SW_I2C_RST_N_1>;
+ reset-names = "rst";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x70960000 0x0 0x10000>;
+ interrupts = <106>;
+ interrupt-parent = <&plic1>;
+ status = "disabled";
+ };
+ d1_i2c2: i2c@70970000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ clocks = <&d1_clock WIN2030_CLK_LSP_I2C2_PCLK>;
+ clock-names = "pclk";
+ resets = <&d1_reset I2C_RST_CTRL SW_I2C_RST_N_2>;
+ reset-names = "rst";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x70970000 0x0 0x10000>;
+ interrupts = <107>;
+ interrupt-parent = <&plic1>;
+ status = "disabled";
+ d1_es8316: es8316@10 {
+ compatible = "everest,es8316";
+ reg = <0x10>;
+ interrupts = <107>;
+ interrupt-parent = <&plic1>;
+ #sound-dai-cells = <0>;
+ port {
+ d1_codec_endpoint: endpoint {
+ system-clock-frequency = <12288000>;
+ remote-endpoint = <&d1_i2s0_endpoint>;
+ };
+ };
+ };
+ };
+ d1_i2c3: i2c@70980000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ clocks = <&d1_clock WIN2030_CLK_LSP_I2C3_PCLK>;
+ clock-names = "pclk";
+ resets = <&d1_reset I2C_RST_CTRL SW_I2C_RST_N_3>;
+ reset-names = "rst";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x70980000 0x0 0x10000>;
+ interrupts = <108>;
+ interrupt-parent = <&plic1>;
+ status = "disabled";
+ };
+ d1_i2c4: i2c@70990000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ clocks = <&d1_clock WIN2030_CLK_LSP_I2C4_PCLK>;
+ clock-names = "pclk";
+ resets = <&d1_reset I2C_RST_CTRL SW_I2C_RST_N_4>;
+ reset-names = "rst";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x70990000 0x0 0x10000>;
+ interrupts = <109>;
+ interrupt-parent = <&plic1>;
+ status = "disabled";
+ };
+ d1_i2c5: i2c@709a0000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ clocks = <&d1_clock WIN2030_CLK_LSP_I2C5_PCLK>;
+ clock-names = "pclk";
+ resets = <&d1_reset I2C_RST_CTRL SW_I2C_RST_N_5>;
+ reset-names = "rst";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x709a0000 0x0 0x10000>;
+ interrupts = <110>;
+ interrupt-parent = <&plic1>;
+ status = "disabled";
+ };
+ d1_i2c6: i2c@709b0000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ clocks = <&d1_clock WIN2030_CLK_LSP_I2C6_PCLK>;
+ clock-names = "pclk";
+ resets = <&d1_reset I2C_RST_CTRL SW_I2C_RST_N_6>;
+ reset-names = "rst";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x709b0000 0x0 0x10000>;
+ interrupts = <111>;
+ interrupt-parent = <&plic1>;
+ status = "disabled";
+ };
+ d1_i2c7: i2c@709c0000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ clocks = <&d1_clock WIN2030_CLK_LSP_I2C7_PCLK>;
+ clock-names = "pclk";
+ resets = <&d1_reset I2C_RST_CTRL SW_I2C_RST_N_7>;
+ reset-names = "rst";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x709c0000 0x0 0x10000>;
+ interrupts = <112>;
+ interrupt-parent = <&plic1>;
+ status = "disabled";
+ };
+ d1_i2c8: i2c@709d0000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ clocks = <&d1_clock WIN2030_CLK_LSP_I2C8_PCLK>;
+ clock-names = "pclk";
+ resets = <&d1_reset I2C_RST_CTRL SW_I2C_RST_N_8>;
+ reset-names = "rst";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x709d0000 0x0 0x10000>;
+ interrupts = <113>;
+ interrupt-parent = <&plic1>;
+ status = "disabled";
+ };
+ d1_i2c9: i2c@709e0000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ clocks = <&d1_clock WIN2030_CLK_LSP_I2C9_PCLK>;
+ clock-names = "pclk";
+ resets = <&d1_reset I2C_RST_CTRL SW_I2C_RST_N_9>;
+ reset-names = "rst";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x709e0000 0x0 0x10000>;
+ interrupts = <114>;
+ interrupt-parent = <&plic1>;
+ status = "disabled";
+ };
+
+ d1_aon_i2c0: i2c@71830000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ clocks = <&d1_clock WIN2030_CLK_AON_I2C0_PCLK>;
+ clock-names = "pclk";
+ resets = <&d1_reset I2C0_RST_CTRL SW_I2C0_PRSTN>;
+ reset-names = "rst";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x71830000 0x0 0x10000>;
+ interrupts = <290>;
+ interrupt-parent = <&plic1>;
+ eswin,i2c_dma = <&d1_aon_dmac>;
+ dma-names = "rx", "tx";
+ /*
+ * dmas : DMA specifiers
+ * &d1_aon_dmac : dma controller
+ * 41 : i2c0 aon dma handshake number
+ * 0xff : no need to select to dma controller
+ */
+ dmas = <&d1_aon_dmac 41 0xff>, <&d1_aon_dmac 42 0xff>;
+ };
+ d1_aon_i2c1: i2c@71838000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ clocks = <&d1_clock WIN2030_CLK_AON_I2C1_PCLK>;
+ clock-names = "pclk";
+ resets = <&d1_reset I2C1_RST_CTRL SW_I2C1_PRSTN>;
+ reset-names = "rst";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x71838000 0x0 0x10000>;
+ interrupts = <291>;
+ interrupt-parent = <&plic1>;
+ };
+
+ d1_nvdla: nvdla-controller@71c00000 {
+ compatible = "eswin,npu1";
+ reg = <0x0 0x71c00000 0x0 0x400000>;
+ interrupt-parent = <&plic1>;
+ interrupts = <387 16>;
+ spram-region = <&npu1_reserved>;
+ #size-cells = <2>;
+ dma-ranges = <0x1 0x0 0x0 0xc0000000 0x1ff 0x0>;
+ iommus = <&smmu1 WIN2030_SID_NPU_DMA>;
+ tbus = <WIN2030_TBUID_NPU>;
+ dsp-avail-num = <1>;
+ spram-size = <0x400000>;
+ npu_mbox = <&d1_mbox2>;
+
+ resets = <&d1_reset NPU_RST_CTRL SW_NPU_E31CORE_RSTN>;
+ reset-names = "e31_core";
+
+ numa-node-id = <1>;
+ };
+
+ dev_llc_d1: llc@71c00000 {
+ compatible = "eswin,llc";
+ reg = <0x0 0x71c00000 0x0 0x400000>;
+ eswin,syscfg = <&d1_sys_con 0x324>;
+ eswin,syscrg_csr = <&d1_sys_crg>;
+ clocks = <&d1_clock WIN2030_CLK_NPU_ACLK>,
+ <&d1_clock WIN2030_CLK_NPU_CFG_CLK>,
+ <&d1_clock WIN2030_CLK_NPU_LLC_ACLK>,
+ <&d1_clock WIN2030_CLK_NPU_CLK>,
+ <&d1_clock WIN2030_MUX_U_NPU_CORE_3MUX1_GFREE>,
+ <&d1_clock WIN2030_SPLL2_FOUT2>;
+ clock-names = "aclk", "cfg_clk", "llc_clk", "core_clk",
+ "mux_u_npu_core_3mux1_gfree", "fixed_rate_clk_spll2_fout2";
+ resets = <&d1_reset NPU_RST_CTRL SW_NPU_AXI_RSTN>,
+ <&d1_reset NPU_RST_CTRL SW_NPU_CFG_RSTN>,
+ <&d1_reset NPU_RST_CTRL SW_NPU_CORE_RSTN>,
+ <&d1_reset NPU_RST_CTRL SW_NPU_LLC_RSTN>;
+ reset-names = "axi", "cfg", "core", "llc";
+ numa-node-id = <1>;
+ spram-region = <&npu1_reserved>;
+ };
+
+ d1_gpu: gpu@71400000 {
+ compatible = "img,gpu";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x71400000 0x0 0xFFFFF>;
+ clocks = <&d1_clock WIN2030_CLK_GPU_ACLK>,
+ <&d1_clock WIN2030_CLK_GPU_GRAY_CLK>,
+ <&d1_clock WIN2030_CLK_GPU_CFG_CLK>;
+ clock-names = "aclk", "gray_clk", "cfg_clk";
+ resets =<&d1_reset GPU_RST_CTRL SW_GPU_AXI_RSTN>,
+ <&d1_reset GPU_RST_CTRL SW_GPU_CFG_RSTN>,
+ <&d1_reset GPU_RST_CTRL SW_GPU_GRAY_RSTN>,
+ <&d1_reset GPU_RST_CTRL SW_GPU_JONES_RSTN>,
+ <&d1_reset GPU_RST_CTRL SW_GPU_SPU_RSTN>;
+ reset-names = "axi", "cfg", "gray", "jones","spu";
+ interrupt-parent = <&plic1>;
+ interrupts = <15>;
+ };
+
+ d1_sata: sata@0x70420000 {
+ compatible = "snps,eswin-ahci";
+ reg = <0x0 0x70420000 0x0 0x10000>;
+ interrupt-parent = <&plic1>;
+ interrupt-names = "intrq", "msi", "pme";
+ interrupts = <58>, <59>, <60>;
+ ports-implemented = <0x1>;
+ resets = <&d1_reset HSPDMA_RST_CTRL SW_SATA_ASIC0_RSTN>,
+ <&d1_reset HSPDMA_RST_CTRL SW_SATA_OOB_RSTN>,
+ <&d1_reset HSPDMA_RST_CTRL SW_SATA_PMALIVE_RSTN>,
+ <&d1_reset HSPDMA_RST_CTRL SW_SATA_RBC_RSTN>;
+ reset-names = "asic0", "oob", "pmalive", "rbc";
+ #size-cells = <2>;
+ iommus = <&smmu1 WIN2030_SID_SATA>;
+ tbus = <WIN2030_TBUID_SATA>;
+ dma-ranges = <0x0 0x0 0x0 0xc0000000 0x200 0x0>;
+ eswin,hsp_sp_csr = <&d1_hsp_sp_csr 0x1050>;
+ eswin,syscrg_csr = <&d1_sys_crg 0x41c>;
+ numa-node-id = <1>;
+ };
+
+ d1_pinctrl: pinctrl@0x71600080 {
+ compatible = "eswin,win2030-pinctrl";
+ reg = <0x0 0x71600080 0x0 0x1FFF80>;
+ status = "disabled";
+ d1_pinctrl_pwm0_default: pwm0-default{
+ mux{
+ groups = "pwm0_group";
+ function = "pwm0_func";
+ };
+ conf {
+ groups = "pwm0_group";
+ drive-strength = <5>;
+ bias-pull-up = <1>;
+ input-enable = <0>;
+ };
+ };
+ d1_pinctrl_pwm1_default: pwm1-default{
+ mux{
+ groups = "pwm1_group";
+ function = "pwm1_func";
+ };
+ conf {
+ groups = "pwm1_group";
+ drive-strength = <6>;
+ bias-pull-up = <0>;
+ input-enable = <1>;
+ };
+ };
+ d1_pinctrl_pwm2_default: pwm2-default{
+ mux{
+ groups = "pwm2_group";
+ function = "pwm2_func";
+ };
+ conf {
+ groups = "pwm2_group";
+ drive-strength = <7>;
+ bias-pull-down = <0>;
+ input-enable = <0>;
+ };
+ };
+ };
+
+ d1_gpio0: gpio@0x71600000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "eswin,win2030-gpio";
+ reg = <0x0 0x71600000 0x0 0x80>;
+ status = "disabled";
+ eswin,syscfg = <&d1_sys_con 0x3c0>;
+
+ d1_porta: gpio-port@0 {
+ compatible = "eswin,win2030-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupts = <303>;
+ interrupt-parent = <&plic1>;
+ interrupt-state = <0 1 1 1>;
+ direction-input = <5 8 9 16>;
+ direction-output = <1 0 3 1>;
+ gpio-state = <11 1 12 1>;
+ };
+ d1_portb: gpio-port@1 {
+ compatible = "eswin,win2030-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <1>;
+ direction-input = <5 13 9 25>;
+ direction-output = <26 0 3 1>;
+ gpio-state = <11 1 17 1>;
+ };
+
+ d1_portc: gpio-port@2 {
+ compatible = "eswin,win2030-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <2>;
+ direction-input = <5 13 9 25>;
+ direction-output = <26 0 3 1>;
+ gpio-state = <11 1 17 1>;
+ };
+
+ d1_portd: gpio-port@3 {
+ compatible = "eswin,win2030-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ reg = <3>;
+ direction-input = <9 1 8 1>;
+ direction-output = <3 1 15 1>;
+ gpio-state = <6 1 5 1>;
+ };
+ };
+
+ d1_timer0: timer@0x71840000 {
+ compatible = "eswin,eswin-timer";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x71840000 0x0 0x8000>;
+ interrupt-parent = <&plic1>;
+ interrupts = <345>;
+ clock-names = "pclk","timer_aclk";
+ clocks = <&d1_clock WIN2030_CLK_TIMER_PCLK_0>,
+ <&d1_clock WIN2030_CLK_TIMER_CLK_0>;
+ resets = <&d1_reset TIMER0_RST_CTRL SW_TIMER0_RSTN_0>,
+ <&d1_reset TIMER0_RST_CTRL SW_TIMER0_RSTN_1>,
+ <&d1_reset TIMER0_RST_CTRL SW_TIMER0_RSTN_2>,
+ <&d1_reset TIMER0_RST_CTRL SW_TIMER0_RSTN_3>,
+ <&d1_reset TIMER0_RST_CTRL SW_TIMER0_RSTN_4>,
+ <&d1_reset TIMER0_RST_CTRL SW_TIMER0_RSTN_5>,
+ <&d1_reset TIMER0_RST_CTRL SW_TIMER0_RSTN_6>,
+ <&d1_reset TIMER0_RST_CTRL SW_TIMER0_RSTN_7>,
+ <&d1_reset TIMER0_RST_CTRL SW_TIMER0_PRSTN>;
+ reset-names = "trst0","trst1","trst2","trst3","trst4","trst5","trst6","trst7","prst";
+ };
+
+ d1_timer1: timer@0x71848000 {
+ compatible = "eswin,eswin-timer";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x71848000 0x0 0x8000>;
+ interrupt-parent = <&plic1>;
+ interrupts = <346>;
+ clock-names = "pclk","timer_aclk";
+ clocks = <&d1_clock WIN2030_CLK_TIMER_PCLK_1>,
+ <&d1_clock WIN2030_CLK_TIMER_CLK_1>;
+ resets = <&d1_reset TIMER1_RST_CTRL SW_TIMER1_RSTN_0>,
+ <&d1_reset TIMER1_RST_CTRL SW_TIMER1_RSTN_1>,
+ <&d1_reset TIMER1_RST_CTRL SW_TIMER1_RSTN_2>,
+ <&d1_reset TIMER1_RST_CTRL SW_TIMER1_RSTN_3>,
+ <&d1_reset TIMER1_RST_CTRL SW_TIMER1_RSTN_4>,
+ <&d1_reset TIMER1_RST_CTRL SW_TIMER1_RSTN_5>,
+ <&d1_reset TIMER1_RST_CTRL SW_TIMER1_RSTN_6>,
+ <&d1_reset TIMER1_RST_CTRL SW_TIMER1_RSTN_7>,
+ <&d1_reset TIMER1_RST_CTRL SW_TIMER1_PRSTN>;
+ reset-names = "trst0","trst1","trst2","trst3","trst4","trst5","trst6","trst7","prst";
+ };
+
+
+ d1_timer2: timer@0x71850000 {
+ compatible = "eswin,eswin-timer";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x71850000 0x0 0x8000>;
+ interrupt-parent = <&plic1>;
+ interrupts = <347>;
+ clock-names = "pclk","timer_aclk";
+ clocks = <&d1_clock WIN2030_CLK_TIMER_PCLK_2>,
+ <&d1_clock WIN2030_CLK_TIMER_CLK_2>;
+ resets = <&d1_reset TIMER2_RST_CTRL SW_TIMER2_RSTN_0>,
+ <&d1_reset TIMER2_RST_CTRL SW_TIMER2_RSTN_1>,
+ <&d1_reset TIMER2_RST_CTRL SW_TIMER2_RSTN_2>,
+ <&d1_reset TIMER2_RST_CTRL SW_TIMER2_RSTN_3>,
+ <&d1_reset TIMER2_RST_CTRL SW_TIMER2_RSTN_4>,
+ <&d1_reset TIMER2_RST_CTRL SW_TIMER2_RSTN_5>,
+ <&d1_reset TIMER2_RST_CTRL SW_TIMER2_RSTN_6>,
+ <&d1_reset TIMER2_RST_CTRL SW_TIMER2_RSTN_7>,
+ <&d1_reset TIMER2_RST_CTRL SW_TIMER2_PRSTN>;
+ reset-names = "trst0","trst1","trst2","trst3","trst4","trst5","trst6","trst7","prst";
+ };
+
+ d1_timer3: timer@0x71858000 {
+ compatible = "eswin,eswin-timer";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x71858000 0x0 0x8000>;
+ interrupt-parent = <&plic1>;
+ interrupts = <348>;
+ clock-names = "pclk","timer_aclk","timer3_clk8";
+ clocks = <&d1_clock WIN2030_CLK_TIMER_PCLK_3>,
+ <&d1_clock WIN2030_CLK_TIMER_CLK_3>,
+ <&d1_clock WIN2030_CLK_TIMER3_CLK8>;
+ resets = <&d1_reset TIMER3_RST_CTRL SW_TIMER3_RSTN_0>,
+ <&d1_reset TIMER3_RST_CTRL SW_TIMER3_RSTN_1>,
+ <&d1_reset TIMER3_RST_CTRL SW_TIMER3_RSTN_2>,
+ <&d1_reset TIMER3_RST_CTRL SW_TIMER3_RSTN_3>,
+ <&d1_reset TIMER3_RST_CTRL SW_TIMER3_RSTN_4>,
+ <&d1_reset TIMER3_RST_CTRL SW_TIMER3_RSTN_5>,
+ <&d1_reset TIMER3_RST_CTRL SW_TIMER3_RSTN_6>,
+ <&d1_reset TIMER3_RST_CTRL SW_TIMER3_RSTN_7>,
+ <&d1_reset TIMER3_RST_CTRL SW_TIMER3_PRSTN>;
+ reset-names = "trst0","trst1","trst2","trst3","trst4","trst5","trst6","trst7","prst";
+ };
+
+ d1_pwm0: pwm@0x70818000 {
+ compatible = "eswin,pwm-eswin";
+ reg = <0x0 0x70818000 0x0 0x4000>;
+ clock-names = "pwm","pclk";
+ clocks = <&d1_clock WIN2030_CLK_LSP_TIMER_PCLK>;
+ clock-frequency = <200000000>;
+ resets = <&d1_reset TIMER_RST_CTRL SW_TIMER_RST_N>;
+ reset-names = "pwmrst";
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&d1_pinctrl_pwm0_default &d1_pinctrl_pwm1_default &d1_pinctrl_pwm2_default>;
+ status = "disabled";
+ };
+
+ d1_i2s0: i2s0@70200000 {
+ compatible = "eswin,i2s-dsp";
+ clocks = <&d1_clock WIN2030_CLK_VO_I2S_MCLK>;
+ clock-names = "mclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <0x00000000>;
+ reg = <0x0 0x70200000 0x0 0x10000>;
+ dma-names = "rx", "tx";
+ dmas = <&d1_aon_dmac 4 0>, <&d1_aon_dmac 5 0>;
+ memory-region = <&dsp_reserved1>;
+ vo_mclk_sel,syscrg = <&d1_sys_crg 0x1bc>;
+ resets = <&d1_reset VO_I2SRST_CTRL SW_VO_I2S_RSTN>,
+ <&d1_reset VO_I2SRST_CTRL SW_VO_I2S_PRSTN>;
+ reset-names = "i2srst", "i2sprst";
+ ports {
+ d1_i2s0_port: port@0 {
+ d1_i2s0_endpoint: endpoint {
+ remote-endpoint = <&d1_codec_endpoint>;
+ dai-format = "i2s";
+ };
+ };
+ };
+ };
+
+ d1_i2s1: i2s1@70210000 {
+ compatible = "snps,i2s";
+ clocks = <&d1_clock WIN2030_CLK_VO_I2S_MCLK>;
+ clock-names = "mclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <0x00000000>;
+ reg = <0x0 0x70210000 0x0 0x10000>;
+ dma-names = "rx", "tx";
+ dmas = <&d1_aon_dmac 2 1>, <&d1_aon_dmac 3 1>;
+ vo_mclk_sel,syscrg = <&d1_sys_crg 0x1bc>;
+ resets = <&d1_reset VO_I2SRST_CTRL SW_VO_I2S_RSTN>,
+ <&d1_reset VO_I2SRST_CTRL SW_VO_I2S_PRSTN>;
+ reset-names = "i2srst", "i2sprst";
+ ports {
+ d1_i2s1_port: port@0 {
+ d1_i2s1_endpoint: endpoint {
+ remote-endpoint = <&d1_dummy_endpoint1>;
+ dai-format = "i2s";
+ };
+ };
+ };
+ };
+
+ d1_i2s2: i2s@70220000 {
+ compatible = "snps,i2s";
+ clocks = <&d1_clock WIN2030_CLK_VO_I2S_MCLK>;
+ clock-names = "mclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <0x00000000>;
+ reg = <0x0 0x70220000 0x0 0x10000>;
+ dma-names = "rx", "tx";
+ dmas = <&d1_aon_dmac 0 2>, <&d1_aon_dmac 1 2>;
+ vo_mclk_sel,syscrg = <&d1_sys_crg 0x1bc>;
+ resets = <&d1_reset VO_I2SRST_CTRL SW_VO_I2S_RSTN>,
+ <&d1_reset VO_I2SRST_CTRL SW_VO_I2S_PRSTN>;
+ reset-names = "i2srst", "i2sprst";
+ ports {
+ d1_i2s2_port: port@0 {
+ d1_i2s2_endpoint: endpoint {
+ remote-endpoint = <&d1_dummy_endpoint2>;
+ dai-format = "i2s";
+ };
+ };
+ };
+ };
+
+ d1_dsp_subsys:dsp_subsys@72280400 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x72280400 0x0 0x10000>,
+ <0x0 0x71810000 0x0 0x8000>;
+ ranges;
+ compatible = "es-dsp-subsys", "simple-bus";
+ clocks = <&d1_clock WIN2030_CLK_DSPT_CFG_CLK>;
+ clock-names = "cfg_clk";
+ resets = <&d1_reset DSP_RST_CTRL SW_DSP_AXI_RSTN>,
+ <&d1_reset DSP_RST_CTRL SW_DSP_CFG_RSTN>,
+ <&d1_reset DSP_RST_CTRL SW_DSP_DIV4_RSTN>,
+ <&d1_reset DSP_RST_CTRL SW_DSP_DIV_RSTN_0>,
+ <&d1_reset DSP_RST_CTRL SW_DSP_DIV_RSTN_1>,
+ <&d1_reset DSP_RST_CTRL SW_DSP_DIV_RSTN_2>,
+ <&d1_reset DSP_RST_CTRL SW_DSP_DIV_RSTN_3>;
+ reset-names = "axi", "cfg", "div4", "div_0", "div_1", "div_2","div_3";
+ d1_dsp0:es_dsp@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "eswin-dsp", "cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0 0x7b000000 0x8000
+ 0x28100000 0 0x7b100000 0x20000
+ 0x28120000 0 0x7b120000 0x20000>;
+ clocks = <&d1_clock WIN2030_CLK_DSP_ACLK_0>;
+ clock-names = "aclk";
+ dsp_mbox = <&d1_mbox4>;
+ device-irq = <11
+ (ESWIN_MAILBOX_DSP_0_TO_U84_REG_BASE + 0x20000000)
+ ESWIN_MAILBOX_WR_LOCK_BIT_DSP_0
+ (ESWIN_MAILBOX_U84_TO_DSP_0_REG_BASE + 0x20000000)
+ ESWIN_MAIBOX_U84_IRQ_BIT>;
+ device-uart = <0x70910000>;
+ device-irq-mode = <1>;
+ host-irq-mode = <1>;
+ firmware-name = "eic7702_dsp_fw";
+ process-id = <0>;
+ dma-ranges = <0x30000000 0x0 0xc0000000 0xce000000>;
+ iommus = <&smmu1 WIN2030_SID_DSP_0>;
+ tbus = <WIN2030_TBUID_DSP0>;
+ numa-node-id = <1>;
+ aux-e31-dtim = <0x7a110000>;
+ dsp@0 {
+ };
+ };
+ d1_dsp1:es_dsp@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "eswin-dsp", "cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0 0x7b008000 0x8000
+ 0x28100000 0 0x7b140000 0x20000
+ 0x28120000 0 0x7b160000 0x20000>;
+ clocks = <&d1_clock WIN2030_CLK_DSP_ACLK_1>;
+ clock-names = "aclk";
+ dsp_mbox = <&d1_mbox5>;
+ device-irq = <13
+ (ESWIN_MAILBOX_DSP_1_TO_U84_REG_BASE + 0x20000000)
+ ESWIN_MAILBOX_WR_LOCK_BIT_DSP_1
+ (ESWIN_MAILBOX_U84_TO_DSP_1_REG_BASE + 0x20000000)
+ ESWIN_MAIBOX_U84_IRQ_BIT>;
+ device-uart = <0x70910000>;
+ device-irq-mode = <1>;
+ host-irq-mode = <1>;
+ firmware-name = "eic7702_dsp_fw";
+ process-id = <1>;
+ dma-ranges = <0x30000000 0x0 0xc0000000 0xce000000>;
+ iommus = <&smmu1 WIN2030_SID_DSP_1>;
+ tbus = <WIN2030_TBUID_DSP1>;
+ numa-node-id = <1>;
+ aux-e31-dtim = <0x7a110000>;
+ dsp@0 {
+ };
+ };
+ d1_dsp2:es_dsp@2 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "eswin-dsp", "cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0 0x7b010000 0x8000
+ 0x28100000 0 0x7b180000 0x20000
+ 0x28120000 0 0x7b1a0000 0x20000>;
+ clocks = <&d1_clock WIN2030_CLK_DSP_ACLK_2>;
+ clock-names = "aclk";
+ dsp_mbox = <&d1_mbox6>;
+ device-irq = <15
+ (ESWIN_MAILBOX_DSP_2_TO_U84_REG_BASE + 0x20000000)
+ ESWIN_MAILBOX_WR_LOCK_BIT_DSP_2
+ (ESWIN_MAILBOX_U84_TO_DSP_2_REG_BASE + 0x20000000)
+ ESWIN_MAIBOX_U84_IRQ_BIT>;
+ device-uart = <0x70910000>;
+ device-irq-mode = <1>;
+ host-irq-mode = <1>;
+ firmware-name = "eic7702_dsp_fw";
+ process-id = <2>;
+ dma-ranges = <0x30000000 0x0 0xc0000000 0xce000000>;
+ iommus = <&smmu1 WIN2030_SID_DSP_2>;
+ tbus = <WIN2030_TBUID_DSP2>;
+ numa-node-id = <1>;
+ aux-e31-dtim = <0x7a110000>;
+ dsp@0 {
+ };
+ };
+ d1_dsp3:es_dsp@3 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "eswin-dsp", "cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0 0x7b018000 0x8000
+ 0x28100000 0 0x7b1c0000 0x20000
+ 0x28120000 0 0x7b1e0000 0x20000>;
+ clocks = <&d1_clock WIN2030_CLK_DSP_ACLK_3>;
+ clock-names = "aclk";
+ dsp_mbox = <&d1_mbox7>;
+ device-irq = <17
+ (ESWIN_MAILBOX_DSP_3_TO_U84_REG_BASE + 0x20000000)
+ ESWIN_MAILBOX_WR_LOCK_BIT_DSP_3
+ (ESWIN_MAILBOX_U84_TO_DSP_3_REG_BASE + 0x20000000)
+ ESWIN_MAIBOX_U84_IRQ_BIT>;
+ device-uart = <0x70910000>;
+ device-irq-mode = <1>;
+ host-irq-mode = <1>;
+ firmware-name = "eic7702_dsp_fw";
+ process-id = <3>;
+ dma-ranges = <0x30000000 0x0 0xc0000000 0xce000000>;
+ iommus = <&smmu1 WIN2030_SID_DSP_3>;
+ tbus = <WIN2030_TBUID_DSP3>;
+ numa-node-id = <1>;
+ aux-e31-dtim = <0x7a110000>;
+ dsp@0 {
+ };
+ };
+ d1_sofdsp: sofdsp@4 {
+ #sound-dai-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "eswin,vision-dsp";
+ reg = <0x0 0x7b000000 0x0 0x10000>,
+ <0x0 0x7b100000 0x0 0x40000>;
+ /* memory-region = <&dsp_reserved0>; */
+ mbox-names = "sof-dsp0";
+ mboxes = <&d1_mbox4 0>;
+ tplg-name = "sof-win2030-es8316.tplg";
+ machine-drv-name = "asoc-simple-card";
+ clocks = <&d1_clock WIN2030_CLK_DSP_ACLK_0>;
+ clock-names = "aclk";
+ process-id = <0>;
+ dma-ranges = <0x0 0x40000000 0x0 0xc0000000 0x0 0xc0000000>;
+ iommus = <&smmu1 WIN2030_SID_DSP_0>;
+ mailbox-dsp-to-u84-addr = <ESWIN_MAILBOX_DSP_0_TO_U84_REG_BASE>;
+ mailbox-u84-to-dsp-addr = <ESWIN_MAILBOX_U84_TO_DSP_0_REG_BASE>;
+ dsp-uart = <&d1_uart1>;
+ ringbuffer-region = <&dsp_reserved1>;
+ numa-node-id = <1>;
+ };
+ };
+ die1_rtc: rtc@71818000 {
+ compatible = "eswin,win2030-rtc";
+ reg = <0x0 0x71818000 0x0 0x400>;
+ eswin,syscfg = <&d1_sys_con 0x3c0>;
+ interrupt-parent = <&plic1>;
+ interrupts = <292>;
+ clocks = <&d1_clock WIN2030_CLK_CLK_RTC>;
+ clock-names = "rtcclk";
+ clock-frequency = <15624>;
+ resets = <&d1_reset RTC_RST_CTRL SW_RTC_RSTN>;
+ reset-names = "rtcrst";
+ status = "disabled";
+ };
+
+ pcie_die1: pcie@0x74000000 {
+ compatible = "eswin,win2030-pcie";
+ clocks = <&d1_clock WIN2030_CLK_PCIET_ACLK>,
+ <&d1_clock WIN2030_CLK_PCIET_CFG_CLK>,
+ <&d1_clock WIN2030_CLK_PCIET_CR_CLK>,
+ <&d1_clock WIN2030_CLK_PCIET_AUX_CLK>;
+ clock-names = "pcie_aclk", "pcie_cfg_clk", "pcie_cr_clk", "pcie_aux_clk";
+
+ reset-names = "pcie_cfg", "pcie_powerup", "pcie_pwren";
+ resets = <&d1_reset PCIE_RST_CTRL SW_PCIE_CFG_RSTN>,
+ <&d1_reset PCIE_RST_CTRL SW_PCIE_POWERUP_RSTN>,
+ <&d1_reset PCIE_RST_CTRL SW_PCIE_PERST_N>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ reg = <0x0 0x74000000 0x0 0x4000000>, /* IP registers */
+ <0x0 0x60000000 0x0 0x800000>, /* Configuration space */
+ <0x0 0x70000000 0x0 0x100000>;
+ reg-names = "dbi", "config", "mgmt";
+ device_type = "pci";
+ /* dma-coherent; */
+ bus-range = <0x0 0xff>;
+
+ ranges = <0x81000000 0x0 0x60800000 0x0 0x60800000 0x0 0x800000>, /* I/O */
+ <0x82000000 0x0 0x61000000 0x0 0x61000000 0x0 0xf000000>, /* mem */
+ <0xc3000000 0xa0 0x00000000 0xa0 0x00000000 0x20 0x00000000>; /* mem prefetchable */
+
+ /* num-lanes = <0x4>; */
+ /**********************************
+ msi_ctrl_io[0~31] : 188~219
+ msi_ctrl_int : 220
+ **********************************/
+ interrupts = <220>;
+ interrupt-names = "msi";
+ interrupt-parent = <&plic1>;
+ iommus = <&smmu1 0xfe0000>;
+ iommu-map = <0x0 &smmu1 0xff0000 0xffffff>;
+ #ifdef PLATFORM_HAPS
+ gen-x = <1>;
+ #else
+ gen-x = <3>;
+ #endif
+ lane-x = <4>;
+ tbus = <WIN2030_TBUID_PCIE>;
+ status = "disabled";
+ numa-node-id = <1>;
+ };
+
+ d1_gmac0: ethernet@70400000 {
+ compatible = "eswin,win2030-qos-eth";
+ reg = <0x0 0x70400000 0x0 0x10000>;
+ interrupt-parent = <&plic1>;
+ interrupt-names = "macirq";
+ interrupts = <61>;
+ phy-mode = "rgmii";
+ numa-node-id = <1>;
+ id = <2>;
+ status = "disabled";
+ clocks = <&d1_clock WIN2030_CLK_HSP_ETH_APP_CLK>,
+ <&d1_clock WIN2030_CLK_HSP_ETH_CSR_CLK>,
+ <&d1_clock WIN2030_CLK_HSP_ETH0_CORE_CLK>;
+ clock-names = "app", "csr","tx";
+ resets = <&d1_reset HSPDMA_RST_CTRL SW_HSP_ETH0_ARSTN>;
+ reset-names = "ethrst";
+ iommus = <&smmu1 WIN2030_SID_ETH0>;
+ tbus = <WIN2030_TBUID_ETH>;
+ eswin,hsp_sp_csr = <&d1_hsp_sp_csr 0x1030 0x100 0x108>;
+ eswin,syscrg_csr = <&d1_sys_crg 0x148 0x14c>;
+ snps,axi-config = <&d1_stmmac_axi_setup>;
+ d1_stmmac_axi_setup: stmmac-axi-config {
+ snps,blen = <0 0 0 0 16 8 4>;
+ snps,rd_osr_lmt = <2>;
+ snps,wr_osr_lmt = <2>;
+ snps,lpi_en = <0>;
+ };
+ };
+
+ d1_gmac1: ethernet@70410000 {
+ compatible = "eswin,win2030-qos-eth";
+ reg = <0x0 0x70410000 0x0 0x10000>;
+ interrupt-parent = <&plic1>;
+ interrupt-names = "macirq";
+ interrupts = <70>;
+ phy-mode = "rgmii";
+ numa-node-id = <1>;
+ id = <3>;
+ status = "disabled";
+ clocks = <&d1_clock WIN2030_CLK_HSP_ETH_APP_CLK>,
+ <&d1_clock WIN2030_CLK_HSP_ETH_CSR_CLK>,
+ <&d1_clock WIN2030_CLK_HSP_ETH1_CORE_CLK>;
+ clock-names = "app", "csr","tx";
+ resets = <&d1_reset HSPDMA_RST_CTRL SW_HSP_ETH1_ARSTN>;
+ reset-names = "ethrst";
+ iommus = <&smmu1 WIN2030_SID_ETH1>;
+ tbus = <WIN2030_TBUID_ETH>;
+ eswin,hsp_sp_csr = <&d1_hsp_sp_csr 0x1034 0x200 0x208>;
+ eswin,syscrg_csr = <&d1_sys_crg 0x148 0x14c>;
+ snps,axi-config = <&d1_stmmac_axi_setup_gmac1>;
+ d1_stmmac_axi_setup_gmac1: stmmac-axi-config {
+ snps,blen = <0 0 0 0 16 8 4>;
+ snps,rd_osr_lmt = <2>;
+ snps,wr_osr_lmt = <2>;
+ snps,lpi_en = <0>;
+ };
+ };
+
+ d1_sdio0: mmc@0x70460000{
+ compatible = "eswin,sdhci-sdio";
+ reg = <0x0 0x70460000 0x0 0x10000>;
+ interrupt-parent = <&plic1>;
+ interrupts = <81>;
+ clocks =<&d1_clock WIN2030_CLK_HSP_MSHC1_CORE_CLK>,
+ <&d1_clock WIN2030_CLK_HSP_CFG_CLK>,
+ <&d1_clock WIN2030_SPLL2_FOUT3>,
+ <&d1_clock WIN2030_MUX_U_MSHCORE_ROOT_3MUX1_1>;
+ clock-names ="clk_xin","clk_ahb","clk_spll2_fout3","clk_mux1_1";
+ clock-output-names = "sdio_cardclock";
+ #clock-cells = <0>;
+ resets = <&d1_reset HSPDMA_RST_CTRL SW_MSHC1_TXRX_RSTN>,
+ <&d1_reset HSPDMA_RST_CTRL SW_MSHC1_PHY_RSTN>,
+ <&d1_reset HSPDMA_RST_CTRL SW_HSP_SD0_PRSTN>,
+ <&d1_reset HSPDMA_RST_CTRL SW_HSP_SD0_ARSTN>;
+ reset-names = "txrx_rst","phy_rst","prstn","arstn";
+
+ delay_code = <0x28>;
+ drive-impedance-ohm = <50>;
+ enable-data-pullup;
+
+ clock-frequency = <208000000>;
+ max-frequency = <208000000>;
+ #size-cells = <2>;
+ dma-ranges = <0x0 0x20000000 0x0 0xc0000000 0x0 0x40000000>;
+ iommus = <&smmu1 WIN2030_SID_SD0>;
+ tbus = <WIN2030_TBUID_SD>;
+ eswin,hsp_sp_csr = <&d1_hsp_sp_csr 0x103c>;
+ bus-width = <4>;
+ sdio-id = <0>;
+ numa-node-id = <1>;
+ status = "disabled";
+ };
+
+ d1_sdio1: mmc@0x70470000{
+ compatible = "eswin,sdhci-sdio";
+ reg = <0x0 0x70470000 0x0 0x10000>;
+ interrupt-parent = <&plic1>;
+ interrupts = <83>;
+ clocks =<&d1_clock WIN2030_CLK_HSP_MSHC2_CORE_CLK>,
+ <&d1_clock WIN2030_CLK_HSP_CFG_CLK>,
+ <&d1_clock WIN2030_SPLL2_FOUT3>,
+ <&d1_clock WIN2030_MUX_U_MSHCORE_ROOT_3MUX1_1>;
+ clock-names ="clk_xin","clk_ahb","clk_spll2_fout3","clk_mux1_1";
+ clock-output-names = "sdio_cardclock";
+ #clock-cells = <0>;
+ resets = <&d1_reset HSPDMA_RST_CTRL SW_MSHC2_TXRX_RSTN>,
+ <&d1_reset HSPDMA_RST_CTRL SW_MSHC2_PHY_RSTN>,
+ <&d1_reset HSPDMA_RST_CTRL SW_HSP_SD1_PRSTN>,
+ <&d1_reset HSPDMA_RST_CTRL SW_HSP_SD1_ARSTN>;
+ reset-names = "txrx_rst","phy_rst","prstn","arstn";
+
+ delay_code = <0x28>;
+ drive-impedance-ohm = <50>;
+ enable-data-pullup;
+
+ clock-frequency = <208000000>;
+ max-frequency = <208000000>;
+ #size-cells = <2>;
+ dma-ranges = <0x0 0x20000000 0x0 0xc0000000 0x0 0x40000000>;
+ iommus = <&smmu1 WIN2030_SID_SD1>;
+ tbus = <WIN2030_TBUID_SD>;
+ eswin,hsp_sp_csr = <&d1_hsp_sp_csr 0x1040>;
+ bus-width = <4>;
+ sdio-id = <1>;
+ numa-node-id = <1>;
+ status = "disabled";
+ };
+
+ d1_ssi0: spi1@70810000 {
+ compatible = "snps,win2030-spi";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x70810000 0x0 0x5000>;
+ spi-max-frequency = <4800000>;
+ clocks = <&d1_clock WIN2030_CLK_LSP_SSI0_PCLK>;
+ clock-names = "clk";
+ interrupt-parent = <&plic1>;
+ interrupts = <91>;
+ resets = <&d1_reset SSI_RST_CTRL SW_SSI_RST_N_0>;
+ reset-names = "spi";
+ eswin,spi_dma = <&d1_aon_dmac>;
+ dmas = <&d1_aon_dmac 38 3>, <&d1_aon_dmac 39 3>;
+ dma-names = "rx", "tx";
+ numa-node-id = <1>;
+ status = "disabled";
+ d1_spi_demo: spi-demo@0 {
+ compatible = "eswin,demo-spi";
+ reg = <0 0 0 0>;
+ spi-max-frequency = <4800000>;
+ };
+ };
+
+ d1_video_output: display-subsystem {
+ compatible = "verisilicon,display-subsystem";
+ ports = <&d1_dc_out>;
+ };
+
+ d1_dc8k: dc8000@702c0000 {
+ compatible = "verisilicon,dc8000";
+ reg = <0x0 0x702c0000 0x0 0x100>, <0x0 0x702c0180 0x0 0x700>, <0x0 0x702c1400 0x0 0x1400>;
+ interrupt-parent = <&plic1>;
+ interrupts = <238>;
+
+ clocks = <&d1_clock WIN2030_CLK_VO_CFG_CLK>,
+ <&d1_clock WIN2030_CLK_VO_PIXEL_CLK>,
+ <&d1_clock WIN2030_CLK_VO_ACLK>,
+ <&d1_clock WIN2030_SPLL0_FOUT1>,
+ <&d1_clock WIN2030_MUX_U_VO_ACLK_ROOT_2MUX1_GFREE>;
+ clock-names = "cfg_clk", "pix_clk", "axi_clk", "spll0_fout1", "vo_mux";
+ resets = <&d1_reset VO_RST_CTRL SW_VO_AXI_RSTN>,
+ <&d1_reset VO_RST_CTRL SW_VO_CFG_RSTN>,
+ <&d1_reset VO_RST_CTRL SW_VO_DC_RSTN>,
+ <&d1_reset VO_RST_CTRL SW_VO_DC_PRSTN>;
+ reset-names = "vo_arst", "vo_prst", "dc_arst", "dc_prst";
+
+
+ d1_dc_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ d1_dc_out_dpi0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&d1_dsi_input0>;
+ };
+
+ d1_dc_out_dpi1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&d1_vd_input>;
+ };
+
+ d1_dc_out_hdmi: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&d1_hdmi_in_dc8k>;
+ };
+ };
+ };
+
+ d1_virtual_display: vs_wb {
+ compatible = "verisilicon,virtual_display";
+ bpp = /bits/ 8 <8>;
+
+ port {
+ d1_vd_input: endpoint {
+ remote-endpoint = <&d1_dc_out_dpi1>;
+ };
+ };
+ };
+
+ d1_dsi_output: dsi-output {
+ compatible = "verisilicon,dsi-encoder";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* input */
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ d1_dsi_input0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&d1_dc_out_dpi0>;
+ };
+ };
+
+ /* output */
+ port@1 {
+ reg = <1>;
+ d1_dsi_out:endpoint {
+ remote-endpoint = <&d1_mipi_dsi_in>;
+ };
+ };
+ };
+ };
+
+ d1_dsi_controller: mipi_dsi@70270000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "verisilicon,dw-mipi-dsi";
+ reg = <0x0 0x70270000 0x0 0x10000>;
+ clocks = <&d1_clock WIN2030_CLK_CLK_MIPI_TXESC>;
+ clock-names = "pclk";
+
+ /*
+ phys = <&dphy>;
+ phy-names = "dphy";
+ */
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ d1_mipi_dsi_in: endpoint {
+ remote-endpoint = <&d1_dsi_out>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ d1_mipi_dsi_out: endpoint {
+ remote-endpoint = <&d1_panel_in>;
+ };
+ };
+ };
+
+ panel@1 {
+ compatible = "eswin,generic-panel";
+ reg = <0>;
+
+ port {
+ d1_panel_in: endpoint {
+ remote-endpoint = <&d1_mipi_dsi_out>;
+ };
+ };
+ };
+ };
+
+ d1_dc8k_test: dc8ktest@702c0000 {
+ compatible = "eswin,dc8000";
+ reg = <0x0 0x702c0000 0x0 0x10000>;
+ interrupt-parent = <&plic1>;
+ interrupts = <238>;
+ };
+
+ d1_dw_hdmi: hdmi@702a0000 {
+ compatible = "eswin,eswin-dw-hdmi";
+ reg = <0x0 0x702a0000 0x0 0x20000>;
+ pinctrl-names = "default";
+ //pinctrl-0 = <&hdmi_i2c_xfer>;
+ interrupt-parent = <&plic1>;
+ interrupts = <274>;
+ clocks = <&d1_clock WIN2030_CLK_VO_CFG_CLK>, <&d1_clock WIN2030_CLK_VO_PIXEL_CLK>,
+ <&d1_clock WIN2030_CLK_VO_CEC_CLK>, <&d1_clock WIN2030_CLK_VO_CR_CLK>;
+ clock-names = "iahb", "vpll", "cec", "isfr";
+ //power-domains = <&power WIN2030_PD_HDCP>;
+ reg-io-width = <4>;
+ ddc-i2c-scl-high-time-ns = <4708>;
+ ddc-i2c-scl-low-time-ns = <4916>;
+ #sound-dai-cells = <0>;
+ resets = <&d1_reset VO_PHYRST_CTRL SW_VO_HDMI_PRSTN>,
+ <&d1_reset VO_PHYRST_CTRL SW_HDMI_PHYCTRL_RSTN>,
+ <&d1_reset VO_PHYRST_CTRL SW_VO_HDMI_RSTN>;
+ reset-names = "prstn", "phyrstn", "rstn";
+
+ ports {
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ d1_hdmi_in_dc8k: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&d1_dc_out_hdmi>;
+ };
+ };
+ port@1 {
+ reg = <2>;
+ d1_hdmi_endpoint: endpoint {
+ reg = <0>;
+ system-clock-frequency = <12288000>;
+ remote-endpoint = <&d1_i2s0_endpoint>;
+ };
+ };
+ };
+ };
+
+ d1_dw_hdmi_hdcp2: hdmi-hdcp2@70290000 {
+ compatible = "eswin,dw-hdmi-hdcp2";
+ reg = <0x0 0x70290000 0x0 0x10000>;
+ interrupt-parent = <&plic1>;
+ interrupts = <275>;
+ clocks = <&d1_clock WIN2030_CLK_VO_CFG_CLK>,
+ <&d1_clock WIN2030_CLK_VO_HDMI_IESMCLK>;
+ clock-names ="pclk_hdcp2", "hdcp2_clk_hdmi";
+ };
+
+ d1_wdt0: watchdog@0x70800000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0x70800000 0x0 0x4000>;
+ clocks =<&d1_clock WIN2030_CLK_LSP_WDT0_PCLK>;
+ clock-names = "pclk";
+ resets = <&d1_reset WDT_RST_CTRL SW_WDT_RST_N_0>;
+ reset-names = "rst";
+ interrupts = <87>;
+ interrupt-parent = <&plic1>;
+ status = "disabled";
+ };
+
+ d1_wdt1: watchdog@0x70804000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0x70804000 0x0 0x4000>;
+ clocks =<&d1_clock WIN2030_CLK_LSP_WDT1_PCLK>;
+ clock-names = "pclk";
+ resets = <&d1_reset WDT_RST_CTRL SW_WDT_RST_N_1>;
+ reset-names = "rst";
+ interrupts = <88>;
+ interrupt-parent = <&plic1>;
+ status = "disabled";
+ };
+
+ d1_wdt2: watchdog@0x70808000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0x70808000 0x0 0x4000>;
+ clocks =<&d1_clock WIN2030_CLK_LSP_WDT2_PCLK>;
+ clock-names = "pclk";
+ resets = <&d1_reset WDT_RST_CTRL SW_WDT_RST_N_2>;
+ reset-names = "rst";
+ interrupts = <89>;
+ interrupt-parent = <&plic1>;
+ status = "disabled";
+ };
+
+ d1_wdt3: watchdog@0x7080c000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0x7080c000 0x0 0x4000>;
+ clocks =<&d1_clock WIN2030_CLK_LSP_WDT3_PCLK>;
+ clock-names = "pclk";
+ resets = <&d1_reset WDT_RST_CTRL SW_WDT_RST_N_3>;
+ reset-names = "rst";
+ interrupts = <90>;
+ interrupt-parent = <&plic1>;
+ status = "disabled";
+ };
+
+ d1_gc820: g2d@70140000 {
+ compatible = "eswin,galcore_d1";
+ clocks = <&d1_clock WIN2030_CLK_VC_ACLK>,
+ <&d1_clock WIN2030_CLK_VC_CFG_CLK>,
+ <&d1_clock WIN2030_CLK_G2D_CFG_CLK>,
+ <&d1_clock WIN2030_CLK_CLK_G2D_ST2>,
+ <&d1_clock WIN2030_CLK_G2D_CLK>,
+ <&d1_clock WIN2030_CLK_G2D_ACLK>,
+ <&d1_clock WIN2030_CLK_VC_MON_PCLK>;
+ clock-names = "vc_aclk", "vc_cfg", "g2d_cfg", "g2d_st2", "g2d_clk", "g2d_aclk","mon_pclk";
+ resets = <&d1_reset VC_RST_CTRL SW_VC_AXI_RSTN>,
+ <&d1_reset VC_RST_CTRL SW_VC_CFG_RSTN>,
+ <&d1_reset VC_RST_CTRL SW_VC_MONCFG_RSTN>,
+ <&d1_reset G2D_RST_CTRL SW_G2D_CORE_RSTN>,
+ <&d1_reset G2D_RST_CTRL SW_G2D_CFG_RSTN>,
+ <&d1_reset G2D_RST_CTRL SW_G2D_AXI_RSTN>;
+ reset-names = "axi", "cfg", "moncfg", "g2d_core", "g2d_cfg", "g2d_axi";
+ reg = <0 0x70140000 0 0x40000>, <0 0x70180000 0 0x40000>;
+ reg-names = "core_2d", "core_2d1";
+ fe-apb-offset = <0x800>;
+ interrupt-parent = <&plic1>;
+ interrupts = <49>, <50>;
+ interrupt-names = "core_2d", "core_2d1";
+ enable-mmu = <1>;
+ contiguous-size = <0xa00000>;
+ recovery = <0>;
+ };
+
+ d1_sdhci_emmc: mmc@70450000 {
+ compatible = "eswin,emmc-sdhci-5.1";
+ reg = <0x0 0x70450000 0x0 0x10000>;
+ interrupt-parent = <&plic1>;
+ interrupts = <79>;
+ assigned-clocks = <&d1_clock WIN2030_CLK_HSP_MSHC0_CORE_CLK>;
+ assigned-clock-rates = <200000000>;
+ clocks = <&d1_clock WIN2030_CLK_HSP_MSHC0_CORE_CLK>, <&d1_clock WIN2030_CLK_HSP_CFG_CLK>;
+ clock-names = "clk_xin", "clk_ahb";
+ clock-output-names = "d1_emmc_cardclock";
+ #clock-cells = <0>;
+
+ resets = <&d1_reset HSPDMA_RST_CTRL SW_MSHC0_TXRX_RSTN>,
+ <&d1_reset HSPDMA_RST_CTRL SW_MSHC0_PHY_RSTN>,
+ <&d1_reset HSPDMA_RST_CTRL SW_HSP_EMMC_PRSTN>,
+ <&d1_reset HSPDMA_RST_CTRL SW_HSP_EMMC_ARSTN>;
+ reset-names = "txrx_rst", "phy_rst", "emmc_prstn", "emmc_arstn";
+
+ delay_code = <0x17>;
+ drive-impedance-ohm = <50>;
+ enable-data-pullup;
+
+ disable-cqe-dcmd;
+ bus-width = <8>;
+ non-removable;
+ /* mmc-ddr-1_8v; */
+ mmc-hs400-1_8v;
+ max-frequency = <200000000>;
+ /* sdhci-caps-mask = <0x0 0x3200000>; */
+ /* smmu */
+ #size-cells = <2>;
+ iommus = <&smmu1 WIN2030_SID_EMMC0>;
+ tbus = <WIN2030_TBUID_EMMC>;
+ dma-ranges = <0x0 0x00000000 0x0 0xc0000000 0x1 0x0>;
+ eswin,hsp_sp_csr = <&d1_hsp_sp_csr 0x1038>;
+ status = "disabled";
+ numa-node-id = <1>;
+ };
+
+ d1_soundcard: soundcard {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "Eswin sound card";
+ simple-audio-card,widgets = "Headphone", "Headphone Jack";
+ simple-audio-card,dai-link@0 {
+ format = "i2s";
+ cpu {
+ sound-dai = <&d1_sofdsp 0>;
+ };
+ codec {
+ sound-dai = <&d1_thruout 0>;
+ };
+ };
+
+ simple-audio-card,dai-link@1 {
+ format = "i2s";
+ cpu {
+ sound-dai = <&d1_sofdsp 1>;
+ };
+ codec {
+ sound-dai = <&d1_thruout 1>;
+ };
+ };
+
+ simple-audio-card,dai-link@2 {
+ format = "i2s";
+ cpu {
+ sound-dai = <&d1_i2s0>;
+ };
+ codec {
+ sound-dai = <&d1_es8316>;
+ system-clock-frequency = <12288000>;
+ };
+ plat {
+ sound-dai = <&d1_sofdsp 2>;
+ };
+ };
+ };
+
+ d1_graphcard: graphcard {
+ compatible = "audio-graph-card";
+ dais = <&d1_i2s0_port
+ &d1_i2s1_port
+ &d1_i2s2_port>;
+ };
+
+ d1_dummy_codec:codec@0x70230000 {
+ status = "disabled";
+ reg = <0x00000000 0x70230000 0x00000000 0x00000100>;
+ #sound-dai-cells = <0x00000000>;
+ compatible = "eswin_dummy_codec";
+ ports {
+ /*
+ port@0 {
+ d1_dummy_endpoint0: endpoint {
+ system-clock-frequency = <12288000>;
+ remote-endpoint = <&d1_i2s0_endpoint>;
+ };
+ };
+ */
+ port@1 {
+ d1_dummy_endpoint1: endpoint {
+ system-clock-frequency = <12288000>;
+ remote-endpoint = <&d1_i2s1_endpoint>;
+ };
+ };
+ port@2 {
+ d1_dummy_endpoint2: endpoint {
+ system-clock-frequency = <12288000>;
+ remote-endpoint = <&d1_i2s2_endpoint>;
+ };
+ };
+ };
+ };
+
+ d1_thruout: thru-out {
+ compatible = "eswin,thru-out";
+ #sound-dai-cells = <1>;
+ memory-region = <&dsp_reserved1>;
+ };
+
+ d1_usbdrd3_0: usb0@70480000 {
+ compatible = "eswin,win2030-dwc3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ clocks =<&d1_clock WIN2030_GATE_HSP_USB0_SUSPEND_CLK>;
+ clock-names = "suspend";
+ eswin,hsp_sp_csr = <&d1_hsp_sp_csr 0x800 0x808 0x83c 0x840>;
+ resets = <&d1_reset HSPDMA_RST_CTRL SW_USB0_VAUX_RSTN>;
+ reset-names = "vaux";
+ ranges;
+ status = "disabled";
+ d1_usbdrd_dwc3_0: dwc3@70480000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x70480000 0x0 0x10000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&plic1>;
+ interrupts = <85>;
+ interrupt-names = "peripheral";
+ dr_mode = "peripheral";
+ phy_type = "utmi";
+ maximum-speed = "high-speed";
+ iommus = <&smmu1 WIN2030_SID_USB0>;
+ eswin,hsp_sp_csr = <&d1_hsp_sp_csr 0x1044>;
+ dma-ranges = <0x0 0x0 0x0 0xc0000000 0x200 0x0>;
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,tx-ipgap-linecheck-dis-quirk;
+ snps,xhci-slow-suspend-quirk;
+ snps,xhci-trb-ent-quirk;
+ snps,usb3-warm-reset-on-resume-quirk;
+ status = "disabled";
+ numa-node-id = <1>;
+ tbus = <WIN2030_TBUID_USB>;
+ };
+ };
+
+ d1_usbdrd3_1: usb1@70490000 {
+ compatible = "eswin,win2030-dwc3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ clocks =<&d1_clock WIN2030_GATE_HSP_USB1_SUSPEND_CLK>;
+ clock-names = "suspend";
+ eswin,hsp_sp_csr = <&d1_hsp_sp_csr 0x900 0x908 0x93c 0x940>;
+ resets = <&d1_reset HSPDMA_RST_CTRL SW_USB1_VAUX_RSTN>;
+ reset-names = "vaux";
+ ranges;
+ status = "disabled";
+ d1_usbdrd_dwc3_1: dwc3@70490000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x70490000 0x0 0x10000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&plic1>;
+ interrupts = <86>;
+ interrupt-names = "host";
+ dr_mode = "host";
+ phy_type = "utmi";
+ maximum-speed = "high-speed";
+ iommus = <&smmu1 WIN2030_SID_USB1>;
+ eswin,hsp_sp_csr = <&d1_hsp_sp_csr 0x1048>;
+ dma-ranges = <0x0 0x0 0x0 0xc0000000 0x200 0x0>;
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,tx-ipgap-linecheck-dis-quirk;
+ snps,xhci-slow-suspend-quirk;
+ snps,xhci-trb-ent-quirk;
+ snps,usb3-warm-reset-on-resume-quirk;
+ status = "disabled";
+ numa-node-id = <1>;
+ tbus = <WIN2030_TBUID_USB>;
+ };
+ };
+
+ d1_vi_top_csr: vi_common_top_csr@0x71030000 {
+ compatible = "esw,vi-common-csr", "syscon";
+ clocks = <&d1_clock WIN2030_CLK_VI_ACLK>,
+ <&d1_clock WIN2030_CLK_VI_CFG_CLK>,
+ <&d1_clock WIN2030_CLK_VI_DIG_ISP_CLK>,
+ <&d1_clock WIN2030_CLK_VI_DVP_CLK>,
+ <&d1_clock WIN2030_CLK_VI_PHY_CFG>,
+ <&d1_clock WIN2030_CLK_VI_PHY_TXCLKESC>,
+ <&d1_clock WIN2030_CLK_VI_SHUTTER_0>,
+ <&d1_clock WIN2030_CLK_VI_SHUTTER_1>,
+ <&d1_clock WIN2030_CLK_VI_SHUTTER_2>,
+ <&d1_clock WIN2030_CLK_VI_SHUTTER_3>,
+ <&d1_clock WIN2030_CLK_VI_SHUTTER_4>,
+ <&d1_clock WIN2030_CLK_VI_SHUTTER_5>,
+ <&d1_clock WIN2030_MUX_U_VI_ACLK_ROOT_2MUX1_GFREE>,
+ <&d1_clock WIN2030_MUX_U_VI_DVP_ROOT_2MUX1_GFREE>,
+ <&d1_clock WIN2030_MUX_U_VI_DIG_ISP_ROOT_2MUX1_GFREE>,
+ <&d1_clock WIN2030_SPLL0_FOUT1>,
+ <&d1_clock WIN2030_VPLL_FOUT1>;
+ clock-names = "aclk", "cfg_clk", "isp_aclk", "dvp_clk", "phy_cfg",
+ "phy_escclk", "sht0", "sht1", "sht2", "sht3", "sht4",
+ "sht5", "aclk_mux", "dvp_mux", "isp_mux", "spll0_fout1", "vpll_fout1";
+ resets = <&d1_reset VI_RST_CTRL SW_VI_AXI_RSTN>,
+ <&d1_reset VI_RST_CTRL SW_VI_CFG_RSTN>,
+ <&d1_reset ISP0_RST_CTRL SW_VI_ISP0_RSTN>,
+ <&d1_reset ISP1_RST_CTRL SW_VI_ISP1_RSTN>,
+ <&d1_reset DVP_RST_CTRL SW_VI_DVP_RSTN>,
+ <&d1_reset SHUTTER_RST_CTRL SW_VI_SHUTTER_RSTN_0>,
+ <&d1_reset SHUTTER_RST_CTRL SW_VI_SHUTTER_RSTN_1>,
+ <&d1_reset SHUTTER_RST_CTRL SW_VI_SHUTTER_RSTN_2>,
+ <&d1_reset SHUTTER_RST_CTRL SW_VI_SHUTTER_RSTN_3>,
+ <&d1_reset SHUTTER_RST_CTRL SW_VI_SHUTTER_RSTN_4>,
+ <&d1_reset SHUTTER_RST_CTRL SW_VI_SHUTTER_RSTN_5>;
+ reset-names = "axi", "cfg", "isp0", "isp1", "dvp", "sht0", "sht1", "sht2", "sht3", "sht4", "sht5";
+
+ id = <0>;
+ #size-cells = <2>;
+ reg = <0x0 0x71030000 0x0 0x10000>;
+ };
+
+ d1_isp_0: isp@0x71000000 {
+ compatible = "esw,win2030-isp";
+ reg = <0x0 0x71000000 0x0 0x10000>;
+ interrupts = <21 19 20>;
+ interrupt-parent = <&plic1>;
+ id = <0>;
+ #size-cells = <2>;
+ dma-ranges = <0x0 0x20000000 0x0 0x80000000 0x0 0x40000000>;
+ iommus = <&smmu1 WIN2030_SID_ISP0>;
+ eswin,vi_top_csr = <&d1_vi_top_csr 0x1000>;
+ numa-node-id = <1>;
+ };
+
+ d1_isp_1: isp@0x71010000 {
+ compatible = "esw,win2030-isp";
+ reg = <0x0 0x71010000 0x0 0x10000>;
+ interrupts = <24 22 23>;
+ interrupt-parent = <&plic1>;
+ id = <1>;
+ #size-cells = <2>;
+ dma-ranges = <0x0 0x20000000 0x0 0x80000000 0x0 0x40000000>;
+ iommus = <&smmu1 WIN2030_SID_ISP1>;
+ eswin,vi_top_csr = <&d1_vi_top_csr 0x1004>;
+ numa-node-id = <1>;
+ };
+
+ d1_dw200: dw200@71020000 {
+ compatible = "eswin,dw200";
+ clocks = <&d1_clock WIN2030_CLK_VI_ACLK>,
+ <&d1_clock WIN2030_CLK_VI_CFG_CLK>,
+ <&d1_clock WIN2030_CLK_VI_DIG_DW_CLK>,
+ <&d1_clock WIN2030_MUX_U_VI_ACLK_ROOT_2MUX1_GFREE>,
+ <&d1_clock WIN2030_MUX_U_VI_DW_ROOT_2MUX1>,
+ <&d1_clock WIN2030_SPLL0_FOUT1>,
+ <&d1_clock WIN2030_VPLL_FOUT1>;
+ clock-names = "aclk", "cfg_clk", "dw_aclk", "aclk_mux", "dw_mux", "spll0_fout1", "vpll_fout1";
+ resets = <&d1_reset VI_RST_CTRL SW_VI_AXI_RSTN>,
+ <&d1_reset VI_RST_CTRL SW_VI_CFG_RSTN>,
+ <&d1_reset VI_RST_CTRL SW_VI_DWE_RSTN>;
+ reset-names = "axi", "cfg", "dwe";
+
+ interrupt-parent = <&plic1>;
+ interrupts = <26 25>;
+ #size-cells = <2>;
+ dma-ranges = <0x0 0x20000000 0x0 0x80000000 0x0 0x40000000>;
+ iommus = <&smmu1 WIN2030_SID_DW>;
+ eswin,vi_top_csr = <&d1_vi_top_csr 0x1008>;
+ reg = <0x0 0x71020000 0x0 0xc00>, <0x0 0x71020c00 0x0 0x120>;
+ numa-node-id = <1>;
+ };
+
+ d1_mipi_dphy_rx: dphy@710c0000 {
+ compatible = "snps,dw-dphy-rx";
+ #phy-cells = <1>;
+ bus-width = <8>;
+ snps,dphy-frequency = <300000>;
+ snps,phy_type = <8>;
+ reg = <0x0 0x710c0000 0x0 0x20000>;
+ numa-node-id = <1>;
+ };
+
+ d1_csi_dma0: csidma@0x72048000 {
+ compatible = "eswin,csi-video";
+ interrupt-parent = <&plic1>;
+ interrupts = <29>;
+ reg = <0x0 0x72048000 0x0 0x1000>;
+ numa-node-id = <1>;
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ d1_csi_dmar_0: endpoint@0 {
+ reg = <0>;
+ bus-type = <4>;
+ remote-endpoint = <&d1_csi2_dma_0_3>;
+ };
+ };
+ };
+
+ d1_csi_dma1: csidma@0x72058000 {
+ compatible = "eswin,csi-video";
+ interrupt-parent = <&plic1>;
+ interrupts = <30>;
+ reg = <0x0 0x72058000 0x0 0x1000>;
+ numa-node-id = <1>;
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ d1_csi_dmar_1: endpoint@0 {
+ reg = <0>;
+ bus-type = <4>;
+ remote-endpoint = <&d1_csi2_dma_1_3>;
+ };
+ };
+ };
+
+ d1_csi2_0: csi2@71050000 {
+ compatible = "snps,dw-csi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&plic1>;
+ interrupts = <29>;
+ snps,output-type = <0>;
+ reg = <0x0 0x71050000 0x0 0x1000>;
+ /*phys = <&mipi_dphy_rx 1>;*/
+ numa-node-id = <1>;
+
+ /* MIPI CONFIG */
+ snps,en-ppi-width = <0>;/* 0: ppi8, 1: ppi16 */
+ snps,en-phy-mode = <0>;/* 0: D-PHY, 1: C-PHY */
+
+ ipi2_en = <0>;/* for virtual channel */
+ ipi2_vcid = <0>;/* virtual channel id */
+ ipi3_en = <0>;
+ ipi3_vcid = <0>;
+
+ #ifdef MIPI_CSI2_IMX290_ENBALE
+ port@1 {
+ reg = <1>;
+ d1_csi2_0_1: endpoint {
+ bus-type = <4>;
+ clock-lanes = <0>;
+ #ifdef MIPI_CSI2_2LINE_ENABLE
+ data-lanes = <1 2>;
+ #else
+ data-lanes = <1 2 3 4>;
+ #endif
+ //remote-endpoint = <&imx290_csi2>;
+ };
+ };
+ #endif
+
+ port@2 {
+ reg = <2>;
+ d1_csi2_dma_0_3: endpoint {
+ bus-type = <5>;
+ remote-endpoint = <&d1_csi_dmar_0>;
+ };
+ };
+ };
+
+ d1_csi2_1: csi2@71060000 {
+ compatible = "snps,dw-csi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&plic1>;
+ interrupts = <30>;
+ snps,output-type = <0>;
+ reg = <0x0 0x71060000 0x0 0x1000>;
+ /*phys = <&mipi_dphy_rx 1>;*/
+ numa-node-id = <1>;
+
+ /* MIPI CONFIG */
+ snps,en-ppi-width = <0>;/* 0: ppi8, 1: ppi16 */
+ snps,en-phy-mode = <0>;/* 0: D-PHY, 1: C-PHY */
+
+ ipi2_en = <0>;/* for virtual channel */
+ ipi2_vcid = <0>;/* virtual channel id */
+ ipi3_en = <0>;
+ ipi3_vcid = <0>;
+
+ #ifdef MIPI_CSI2_IMX290_ENBALE
+ port@1 {
+ reg = <1>;
+ d1_csi2_1_1: endpoint {
+ bus-type = <4>;
+ clock-lanes = <0>;
+ #ifdef MIPI_CSI2_2LINE_ENABLE
+ data-lanes = <1 2>;
+ #else
+ data-lanes = <1 2 3 4>;
+ #endif
+ //remote-endpoint = <&imx290_csi2>;
+ };
+ };
+ #endif
+
+ port@2 {
+ reg = <2>;
+ d1_csi2_dma_1_3: endpoint {
+ bus-type = <5>;
+ remote-endpoint = <&d1_csi_dmar_1>;
+ };
+ };
+ };
+
+ d1_dc8k_test: dc8ktest@702c0000 {
+ compatible = "eswin,dc8000";
+ reg = <0x0 0x702c0000 0x0 0x10000>;
+ interrupt-parent = <&plic1>;
+ interrupts = <238>;
+ };
+
+ d1_numa_sample:numa_sample@1 {
+ compatible = "eswin,numa-sample","simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-ranges = <0x0 0x80000000 0x0 0xc0000000 0x0 0x80000000>;
+ iommus = <&smmu1 WIN2030_SID_SCPU>;
+ numa-node-id = <1>;
+ };
+};
+
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-platform.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-platform.dtsi
new file mode 100644
index 000000000000..6d8817dfc2b6
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-platform.dtsi
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Include file for Configuration of Eswin EIC770x family SoC.
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ */
+
+/*
+CHIPLET_AND_DIE = ((CHIPLET_NUM << 1) | AVAILABLE_DIE)
+BIT1 BIT0
+0 0 CHIPLET_1 | DIE0
+0 1 CHIPLET_1 | DIE1
+1 X CHIPLET_2 | X
+*/
+
+#define CHIPLET_NUM 0
+#define PLATFORM_HAPS
+#define MEMMODE_FLAT
+#define AVAILABLE_DIE 0
+
+#define CHIPLET_AND_DIE ((CHIPLET_NUM << 1) | AVAILABLE_DIE)
+
+/* VI related Macros */
+#define MIPI_CSI2_IMX290_ENBALE
+#define MIPI_CSI2_2LINE_ENABLE
+
+#if (CHIPLET_NUM==0)
+#if defined PLATFORM_HAPS
+#define RTCCLK_FREQ 1000000
+#define CPUCLK_FREQ 7500000
+#define LSPCLK_FREQ 5000000
+#define MEMORY_SIZE_H 0x2
+#define MEMORY_SIZE_L 0x0
+#define CMA_SIZE 0x10000000
+#elif defined PLATFORM_ZEBU
+#define RTCCLK_FREQ 1000000
+#define CPUCLK_FREQ 5000000
+#define LSPCLK_FREQ 5000000
+#define MEMORY_SIZE_H 0x2
+#define MEMORY_SIZE_L 0x0
+#define CMA_SIZE 0x10000000
+#elif defined PLATFORM_EIC7700_E_LX_G3_A1
+#define RTCCLK_FREQ 1000000
+#define CPUCLK_FREQ 5000000
+#define LSPCLK_FREQ 5000000
+#define MEMORY_SIZE_H 0x2
+#define MEMORY_SIZE_L 0x0
+#define CMA_SIZE 0x10000000
+#elif defined PLATFORM_EIC7700_E_L5_G2_A1
+#define RTCCLK_FREQ 1000000
+#define CPUCLK_FREQ 5000000
+#define LSPCLK_FREQ 5000000
+#define MEMORY_SIZE_H 0x1
+#define MEMORY_SIZE_L 0x0
+#define CMA_SIZE 0x10000000
+#endif
+#else /* CHIPLET_2 */
+#define RTCCLK_FREQ 1000000
+#define LSPCLK_FREQ 5000000
+#define CPUCLK_FREQ 5000000
+#ifdef MEMMODE_INTERLEAVE
+#define MEMORY_SIZE_H 0x4
+#define MEMORY_SIZE_L 0x0
+#define CMA_SIZE 0x8000000
+#else /* non-interleaving */
+#define MEMORY_SIZE_H 0x2
+#define MEMORY_SIZE_L 0x0
+#define CMA_SIZE 0x10000000
+#endif /* end of MEMMODE_INTERLEAVE */
+#endif /* end of (CHIPLET_NUM==0) */
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030.dts b/arch/riscv/boot/dts/eswin/eswin-win2030.dts
new file mode 100644
index 000000000000..88696f5cba89
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030.dts
@@ -0,0 +1,1503 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for Eswin EIC770x family SoC.
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+
+#include "eswin-win2030-platform.dtsi"
+#include "eic7700-pinctrl.dtsi"
+
+#if ((CHIPLET_AND_DIE & 0x2) || (CHIPLET_AND_DIE == 0x0))
+#include "eswin-win2030-die0-soc.dtsi"
+#endif
+
+#if ((CHIPLET_AND_DIE & 0x2) || (CHIPLET_AND_DIE == 0x1))
+#include "eswin-win2030-die1-soc.dtsi"
+#endif
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ /*model = "SiFive HiFive Unmatched A00";*/
+ model = "ESWIN WIN2030";
+ compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000",
+ "sifive,fu740";
+
+#if ((CHIPLET_AND_DIE & 0x2) || (CHIPLET_AND_DIE == 0x0))
+ aliases {
+ serial0 = &d0_uart0;
+ ethernet0 = &d0_gmac0;
+ ethernet1 = &d0_gmac1;
+ };
+#endif
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpus {
+ timebase-frequency = <RTCCLK_FREQ>;
+ };
+#if (CHIPLET_NUM == 1)
+#ifdef MEMMODE_INTERLEAVE
+ memory@59000000 {
+ device_type = "memory";
+ reg = <0x0 0x59000000 0x0 0x400000>;
+ numa-node-id = <0>;
+ };
+
+ memory@79000000 {
+ device_type = "memory";
+ reg = <0x0 0x79000000 0x0 0x400000>;
+ numa-node-id = <1>;
+ };
+
+ memory@4000000000 {
+ device_type = "memory";
+ reg = <0x40 0x00000000 MEMORY_SIZE_H MEMORY_SIZE_L>;
+ numa-node-id = <0>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 CMA_SIZE>;
+ alignment = <0x0 0x1000>;
+ alloc-ranges = <0x40 0x0 MEMORY_SIZE_H MEMORY_SIZE_L>;
+ linux,cma-default;
+ };
+
+ npu0_reserved: sprammemory@59000000 {
+ no-map;
+ reg = <0x0 0x59000000 0x0 0x400000>;
+ };
+ npu1_reserved: sprammemory@79000000 {
+ no-map;
+ reg = <0x0 0x79000000 0x0 0x400000>;
+ };
+ //WRAN: dsp reserved space is fixed to 0x90000000 and 0x91000000 in the code, the below space is not working for dsp,it's just for building
+ /*
+ dsp_reserved0: dsp@4010000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x40 0x10000000 0 0x1000000>;
+ reusable;
+ status = "okay";
+ };
+ */
+
+ dsp_reserved1: dsp@4011000000 {
+ reg = <0x40 0x11000000 0 0x200000>;
+ no-map;
+ };
+
+ smpmemtest_rsv0@4011200000 {
+ reg = <0x40 0x11200000 0 0x2000000>;
+ no-map;
+ };
+
+ smpmemtest_rsv1@4013200000 {
+ reg = <0x40 0x13200000 0 0x2000000>;
+ no-map;
+ };
+
+ lpcpu0_reserved: lpcpu@4020000000 {
+ no-map;
+ reg = <0x40 0x20000000 0x0 0x100000>;
+ };
+
+ lpcpu1_reserved: lpcpu@4020100000 {
+ no-map;
+ reg = <0x40 0x20100000 0x0 0x100000>;
+ };
+
+ secure_memory_part_0 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x40 0xb0000000 0x0 0x10000000>;
+ no-map;
+ };
+
+ secure_memory_part_1 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x40 0xc0000000 0x0 0x10000000>;
+ no-map;
+ };
+ };
+#else
+ memory@59000000 {
+ device_type = "memory";
+ reg = <0x0 0x59000000 0x0 0x400000>;
+ numa-node-id = <0>;
+ };
+
+ memory@79000000 {
+ device_type = "memory";
+ reg = <0x0 0x79000000 0x0 0x400000>;
+ numa-node-id = <1>;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 MEMORY_SIZE_H MEMORY_SIZE_L>;
+ numa-node-id = <0>;
+ };
+
+ memory@2000000000 {
+ device_type = "memory";
+ reg = <0x20 0x00000000 MEMORY_SIZE_H MEMORY_SIZE_L>;
+ numa-node-id = <1>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 CMA_SIZE>;
+ alignment = <0x0 0x1000>;
+ alloc-ranges = <0x20 0x00000000 MEMORY_SIZE_H MEMORY_SIZE_L>;
+ linux,cma-default;
+ };
+
+ npu0_reserved: sprammemory@59000000 {
+ no-map;
+ reg = <0x0 0x59000000 0x0 0x400000>;
+ };
+ npu1_reserved: sprammemory@79000000 {
+ no-map;
+ reg = <0x0 0x79000000 0x0 0x400000>;
+ };
+ /*
+ dsp_reserved0: dsp@90000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x90000000 0x0 0x1000000>;
+ reusable;
+ status = "okay";
+ };
+ */
+
+ dsp_reserved1: dsp@91000000 {
+ reg = <0 0x91000000 0 0x200000>;
+ no-map;
+ };
+
+ smpmemtest_rsv0@91200000 {
+ reg = <0 0x91200000 0 0x2000000>;
+ no-map;
+ };
+
+ secure_memory_nid_0_part_0 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x0 0xb0000000 0x0 0x8000000>;
+ no-map;
+ };
+
+ secure_memory_nid_0_part_1 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x0 (0xb0000000 + 0x8000000) 0x0 0x8000000>;
+ no-map;
+ };
+
+ mmz_nid_0_part_0 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x0 0xc0000000 0x0 0x40000000>;
+ no-map;
+ };
+
+ mmz_nid_0_part_1 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x1 0x0 0x0 0x40000000>;
+ no-map;
+ };
+
+ mmz_nid_1_part_0 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x20 0x0 0x0 0x40000000>;
+ no-map;
+ };
+
+ mmz_nid_1_part_1 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x20 0x40000000 0x0 0x40000000>;
+ no-map;
+ };
+
+ smpmemtest_rsv1@2000000000 {
+ reg = <0x20 0x80000000 0 0x2000000>;
+ no-map;
+ };
+
+ lpcpu0_reserved: lpcpu@a0000000 {
+ no-map;
+ reg = <0x0 0xa0000000 0x0 0x100000>;
+ };
+
+ lpcpu1_reserved: lpcpu@20a0000000 {
+ no-map;
+ reg = <0x20 0xa0000000 0x0 0x100000>;
+ };
+
+ secure_memory_nid_1_part_0 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x20 0xd0000000 0x0 0x8000000>;
+ no-map;
+ };
+
+ secure_memory_nid_1_part_1 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x20 (0xd0000000 + 0x8000000) 0x0 0x8000000>;
+ no-map;
+ };
+ };
+#endif
+ distance-map {
+ compatible = "numa-distance-map-v1";
+ distance-matrix = <0 0 10>,
+ <0 1 15>,
+ <1 0 15>,
+ <1 1 10>;
+ };
+#else //CHIPLET_1
+#if (AVAILABLE_DIE == 0)
+ memory@59000000 {
+ device_type = "memory";
+ reg = <0x0 0x59000000 0x0 0x400000>;
+ numa-node-id = <0>;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 MEMORY_SIZE_H MEMORY_SIZE_L>;
+ numa-node-id = <0>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 CMA_SIZE>;
+ alignment = <0x0 0x1000>;
+ alloc-ranges = <0x0 0x80000000 MEMORY_SIZE_H MEMORY_SIZE_L>;
+ linux,cma-default;
+ };
+
+ npu0_reserved: sprammemory@59000000 {
+ no-map;
+ reg = <0x0 0x59000000 0x0 0x400000>;
+ };
+
+ /*
+ dsp_reserved0: dsp@90000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x90000000 0x0 0x1000000>;
+ reusable;
+ status = "okay";
+ };
+ */
+
+ dsp_reserved1: dsp@91000000 {
+ reg = <0 0x91000000 0 0x200000>;
+ no-map;
+ };
+
+ smpmemtest_rsv0@91200000 {
+ reg = <0 0x91200000 0 0x2000000>;
+ no-map;
+ };
+
+ lpcpu0_reserved: lpcpu@a0000000 {
+ no-map;
+ reg = <0x0 0xa0000000 0x0 0x100000>;
+ };
+
+ secure_memory_nid_0_part_0 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x0 0xb0000000 0x0 0x8000000>;
+ no-map;
+ };
+
+ secure_memory_nid_0_part_1 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x0 (0xb0000000 + 0x8000000) 0x0 0x8000000>;
+ no-map;
+ };
+
+ mmz_nid_0_part_0 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x0 0xc0000000 0x1 0x40000000>;
+ no-map;
+ };
+
+ mmz_nid_0_part_1 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x2 0x0 0x0 0x8000000>;
+ no-map;
+ };
+ };
+
+ soc {
+ reset_test@1e00e000 {
+ compatible = "reset_test";
+ resets = <&d0_reset SCPU_RST_CTRL SW_SCPU_BUS_RSTN>,
+ <&d0_reset SCPU_RST_CTRL SW_SCPU_CORE_RSTN>,
+ <&d0_reset SCPU_RST_CTRL SW_SCPU_DBG_RSTN>;
+ reset-names = "bus", "core", "dbg";
+ };
+ };
+#else
+ memory@79000000 {
+ device_type = "memory";
+ reg = <0x0 0x79000000 0x0 0x400000>;
+ numa-node-id = <1>;
+ };
+
+ memory@2000000000 {
+ device_type = "memory";
+ reg = <0x20 0x0 MEMORY_SIZE_H MEMORY_SIZE_L>;
+ numa-node-id = <0>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 CMA_SIZE>;
+ alignment = <0x0 0x1000>;
+ alloc-ranges = <0x20 0x0 MEMORY_SIZE_H MEMORY_SIZE_L>;
+ linux,cma-default;
+ };
+
+ npu1_reserved: sprammemory@79000000 {
+ no-map;
+ reg = <0x0 0x79000000 0x0 0x400000>;
+ };
+ //WRAN: dsp reserved space is fixed to 0x90000000 and 0x91000000 in the code, the below space is not working for dsp,it's just for building
+ /*
+ dsp_reserved0: dsp@2010000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x20 0x10000000 0x0 0x1000000>;
+ reusable;
+ status = "okay";
+ };
+ */
+
+ dsp_reserved1: dsp@2011000000 {
+ reg = <0x20 0x11000000 0 0x200000>;
+ no-map;
+ };
+
+ smpmemtest_rsv0@2011200000 {
+ reg = <0x20 0x11200000 0 0x2000000>;
+ no-map;
+ };
+
+ mmz_nid_1_part_0 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x20 0x40000000 0x0 0x40000000>;
+ no-map;
+ };
+
+ mmz_nid_1_part_1 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x20 0x80000000 0x0 0x40000000>;
+ no-map;
+ };
+
+ lpcpu1_reserved: lpcpu@20c0000000 {
+ no-map;
+ reg = <0x20 0xc0000000 0x0 0x100000>;
+ };
+
+ secure_memory_nid_1_part_0 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x20 0xd0000000 0x0 0x8000000>;
+ no-map;
+ };
+
+ secure_memory_nid_1_part_1 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x20 (0xd0000000 + 0x8000000) 0x0 0x8000000>;
+ no-map;
+ };
+ };
+#endif /* end of (AVAILABLE_DIE == 0) */
+#endif /* end of (CHIPLET_NUM==1) */
+};
+
+#if ((CHIPLET_AND_DIE & 0x2) || (CHIPLET_AND_DIE == 0x0))
+&d0_uart0 {
+ status = "okay";
+};
+
+&d0_uart1 {
+ status = "okay";
+};
+
+&d0_uart2 {
+ status = "okay";
+};
+
+&d0_clock {
+ status = "okay";
+};
+
+&d0_reset {
+ status = "okay";
+};
+
+&smmu0 {
+ status = "okay";
+};
+
+&smmu_pmu0 {
+ status = "disabled";
+};
+
+&dev_foo_b {
+ status = "disabled";
+};
+
+&dev_foo_a {
+ status = "okay";
+};
+
+&d0_dmac0 {
+ status = "disabled";
+};
+
+&d0_aon_dmac {
+ status = "okay";
+};
+
+&d0_gmac0 {
+ status = "disabled";
+};
+
+&d0_gmac1 {
+ status = "disabled";
+};
+
+
+&d0_nvdla {
+ status = "okay";
+};
+
+&d0_dsp_subsys {
+ status = "okay";
+};
+
+&d0_dsp0 {
+ status = "okay";
+};
+
+&d0_dsp1 {
+ status = "disabled";
+};
+
+&d0_dsp2 {
+ status = "disabled";
+};
+
+&d0_dsp3 {
+ status = "disabled";
+};
+
+&d0_sofdsp {
+ status = "disabled";
+};
+
+&d0_i2s0 {
+ status = "disabled";
+ eswin-plat = <0>;
+ d0_i2s0_port: port {
+ d0_i2s0_endpoint: endpoint {
+ remote-endpoint = <&hdmi_in_i2s>;
+ dai-format = "i2s";
+ };
+ };
+};
+
+&d0_i2s1 {
+ status = "disabled";
+ eswin-plat = <0>;
+ d0_i2s1_port: port {
+ d0_i2s1_endpoint: endpoint {
+ remote-endpoint = <&d0_codec_endpoint>;
+ dai-format = "i2s";
+ };
+ };
+};
+
+&d0_i2s2 {
+ status = "disabled";
+ eswin-plat = <0>;
+ d0_i2s2_port: port {
+ d0_i2s2_endpoint: endpoint {
+ remote-endpoint = <&d0_dummy_endpoint2>;
+ dai-format = "i2s";
+ };
+ };
+};
+
+&d0_soundcard {
+ status = "disabled";
+};
+
+&d0_graphcard0 {
+ status = "disabled";
+ dais = <&d0_i2s0_port
+ &d0_i2s1_port
+ &d0_i2s2_port>;
+};
+
+&d0_graphcard1 {
+ status = "disabled";
+};
+
+&d0_graphcard2 {
+ status = "disabled";
+};
+
+&d0_dummy_codec {
+ status = "disabled";
+ ports {
+ /*port@0 {
+ d0_dummy_endpoint0: endpoint {
+ system-clock-frequency = <12288000>;
+ remote-endpoint = <&d0_i2s0_endpoint>;
+ };
+ };
+ */
+ /*
+ port@1 {
+ d0_dummy_endpoint1: endpoint {
+ system-clock-frequency = <12288000>;
+ remote-endpoint = <&d0_i2s1_endpoint>;
+ };
+ };
+ */
+ port@2 {
+ d0_dummy_endpoint2: endpoint {
+ system-clock-frequency = <12288000>;
+ remote-endpoint = <&d0_i2s2_endpoint>;
+ };
+ };
+ };
+};
+
+&d0_thruout{
+ status = "disabled";
+};
+
+&gc820 {
+ status = "disabled";
+};
+
+&gpu0 {
+ status = "disabled";
+};
+
+&pcie {
+ status = "disabled";
+};
+
+&ssi0 {
+ status = "disabled";
+};
+
+&sdhci_emmc {
+ status = "disabled";
+};
+
+&sdio0 {
+ status = "disabled";
+};
+
+&sdio1 {
+ status = "disabled";
+};
+
+&vdec0 {
+ status = "disabled";
+};
+
+&venc0 {
+ status = "disabled";
+};
+
+&d0_mbox0 {
+ status = "okay";
+};
+
+&d0_mbox1 {
+ status = "disabled";
+};
+
+&d0_mbox2 {
+ status = "okay";
+};
+
+&d0_mbox3 {
+ status = "disabled";
+};
+
+&d0_mbox4 {
+ status = "okay";
+};
+
+&d0_mbox5 {
+ status = "okay";
+};
+
+&d0_mbox6 {
+ status = "okay";
+};
+
+&d0_mbox7 {
+ status = "okay";
+};
+
+&d0_ipc_scpu {
+ status = "okay";
+};
+
+&d0_lpcpu {
+ status = "disabled";
+};
+
+&dvb_widgets {
+ status = "disabled";
+ dw_name = "dvb-widgets";
+ dw_num = <8>;
+ led-gpios = <&porta 27 GPIO_ACTIVE_HIGH>;
+};
+
+&pvt0 {
+ status = "disabled";
+};
+
+&pvt1 {
+ status = "disabled";
+};
+
+&fan_control {
+ status = "disabled";
+};
+
+&d0_i2c0 {
+ status = "disabled";
+ eeprom@50 {
+ compatible = "atmel,24c1024";
+ reg = <0x50>;
+ };
+};
+
+&d0_pmu {
+ status = "disabled";
+};
+
+&d0_i2c1 {
+ status = "disabled";
+};
+
+&d0_i2c2 {
+ status = "disabled";
+ d0_es8316: es8316@10 {
+ compatible = "everest,es8316";
+ reg = <0x10>;
+ interrupts = <107>;
+ interrupt-parent = <&plic0>;
+ #sound-dai-cells = <0>;
+ port {
+ d0_codec_endpoint: endpoint {
+ system-clock-frequency = <12288000>;
+ remote-endpoint = <&d0_i2s1_endpoint>;
+ };
+ };
+ };
+};
+
+&d0_i2c3 {
+ status = "disabled";
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ };
+};
+
+&d0_i2c4 {
+ status = "disabled";
+ i2c-slave-eeprom@51 {
+ compatible = "slave-24c02";
+ reg = <(I2C_OWN_SLAVE_ADDRESS | 0x51)>;
+ };
+};
+
+&d0_i2c5 {
+ status = "disabled";
+};
+
+&d0_i2c6 {
+ status = "disabled";
+};
+
+&d0_i2c7 {
+ status = "disabled";
+};
+
+&d0_i2c8 {
+ status = "disabled";
+};
+
+&d0_i2c9 {
+ status = "disabled";
+};
+
+&d0_aon_i2c0 {
+ status = "disabled";
+ aon_eeprom@50 {
+ compatible = "atmel,24c1024";
+ reg = <0x50>;
+ };
+};
+
+&d0_aon_i2c1 {
+ status = "disabled";
+};
+
+&pinctrl {
+ status = "disabled";
+ pinctrl_gpio27_default: gpio27-default{
+ mux{
+ groups = "gpio27_group";
+ function = "gpio27_func";
+ };
+ conf {
+ groups = "gpio27_group";
+ input-enable = <1>;
+ };
+ };
+};
+
+&gpio0 {
+ status = "disabled";
+ porta: gpio-port@0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio27_default>;
+ gpio-ranges = <&pinctrl 27 55 111>;
+ interrupts = <303>,<311>,<312>,<313>,<314>,<331>;
+ interrupt-state = <0 1 1 1>,<8 0 1 1>,<9 0 1 1>,
+ <10 0 1 1>,<11 0 1 1>,<28 0 1 1>;
+ direction-input = <0 8 9 10 11 28>;
+ direction-output = <7 1 16 0>;
+ gpio-state = <11 1 12 1>;
+ };
+ portb: gpio-port@1 {
+ direction-input = <5 13 9 25>;
+ direction-output = <26 0 3 1>;
+ gpio-state = <11 1 17 1>;
+ };
+
+ portc: gpio-port@2 {
+ direction-input = <5 13 9 25>;
+ direction-output = <30 0 3 1>;
+ gpio-state = <11 1 17 1>;
+ };
+
+ portd: gpio-port@3 {
+ direction-input = <9 1 8 1>;
+ direction-output = <10 1 11 1 12 1 13 1 14 1 15 0>;
+ gpio-state = <6 1 5 1>;
+ };
+};
+
+&pwm0 {
+ status = "disabled";
+};
+
+&wdt0 {
+ status = "disabled";
+};
+
+&wdt1 {
+ status = "disabled";
+};
+
+&wdt2 {
+ status = "disabled";
+};
+
+&wdt3 {
+ status = "disabled";
+};
+
+&timer0 {
+ status = "disabled";
+};
+
+&timer1 {
+ status = "disabled";
+};
+
+&timer2 {
+ status = "disabled";
+};
+
+&timer3 {
+ status = "disabled";
+};
+
+&die0_rtc {
+ status = "disabled";
+};
+
+&d0_sata {
+ status = "disabled";
+};
+
+&d0_cfg_noc {
+ status = "okay";
+};
+
+&d0_llc_noc {
+ status = "okay";
+ stat,0 = "TracePort:ddr0_p0_req";
+ stat,1 = "TracePort:ddr1_p0_req";
+ //latency,0 = "TracePort:llcnoc_trans_probe";
+ //pending,0 = "TracePort:llcnoc_trans_probe";
+};
+
+&d0_sys_noc {
+ status = "okay";
+
+ //eswin,DSPT-qos-owner;
+ //eswin,NPU-qos-owner;
+ //eswin,SPISLV_TBU3-qos-owner;
+
+ stat,0 = "TracePort:ddr0_p1_req",
+ "InitFlow:mcput_snoc_mp/I/0";
+
+ stat,1 = "TracePort:ddr0_p2_req",
+ "InitFlow:dspt_snoc/I/0",
+ "AddrBase:0x81000000", "AddrSize:0x30",
+ "Opcode:RdWrLockUrg", "Status:ReqRsp", "Length:0x8000", "Urgency:0x0";
+
+ stat,2 = "TracePort:ddr1_p1_req",
+ "Status:Req", "AddrSize:0x28";
+
+ stat,3 = "TracePort:ddr1_p2_req";
+
+ latency,0 = "TracePort:sysnoc_trans_probe_0", "AddrSize:0x0";
+ latency,1 = "TracePort:sysnoc_trans_probe_1","Mode:latency","AddrBase:0x82000000","AddrSize:0x28","Opcode:RdWr";
+ //latency,2 = "TracePort:sysnoc_trans_probe_2";
+
+ //pending,0 = "TracePort:sysnoc_trans_probe_0";
+ //pending,1 = "TracePort:sysnoc_trans_probe_1","Mode:latency","AddrBase:0x82000000","AddrSize:0x0","Opcode:RdWr";
+ pending,0 = "TracePort:sysnoc_trans_probe_2", "AddrSize:0x3";
+};
+
+&d0_noc_wdt {
+ status = "okay";
+};
+
+&video_output {
+ status = "disabled";
+};
+
+&dc8k {
+ status = "disabled";
+};
+
+&virtual_display {
+ status = "disabled";
+};
+
+&dsi_output {
+ status = "disabled";
+};
+
+&dsi_controller {
+ status = "disabled";
+};
+
+&dc8k_test {
+ status = "disabled";
+};
+
+&dw_hdmi {
+ status = "disabled";
+ eswin-plat = <0>;
+ ports {
+ port@2 {
+ reg = <2>;
+ hdmi_in_i2s: endpoint@1 {
+ system-clock-frequency = <12288000>;
+ remote-endpoint = <&d0_i2s0_endpoint>;
+ };
+ };
+ };
+};
+
+&dw_hdmi_hdcp2 {
+ status = "disabled";
+};
+
+&d0_media_noc {
+ status = "okay";
+
+ //eswin,GPU-qos-owner;
+ //eswin,TBU2-qos-owner;
+ //eswin,VC-qos-owner;
+
+ stat,0 = "TracePort:ddr0_p3_req";
+ stat,1 = "TracePort:ddr1_p3_req";
+ //latency,0 = "TracePort:mnoc_trans_probe";
+ //pending,0 = "TracePort:mnoc_trans_probe";
+};
+&d0_realtime_noc {
+ status = "okay";
+
+ //eswin,TBU0-qos-owner;
+ //eswin,VO-qos-owner;
+
+ stat,0 = "TracePort:ddr0_p4_req";
+ stat,1 = "TracePort:ddr1_p4_req";
+ //latency,0 = "TracePort:rnoc_trans_probe";
+ //pending,0 = "TracePort:rnoc_trans_probe";
+};
+
+&d0_usbdrd3_0 {
+ status = "disabled";
+};
+
+&d0_usbdrd_dwc3_0 {
+ status = "disabled";
+ dr_mode = "peripheral";
+};
+
+&d0_usbdrd3_1 {
+ status = "disabled";
+};
+
+&d0_usbdrd_dwc3_1 {
+ status = "disabled";
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+};
+
+&isp_0 {
+ status = "disabled";
+};
+
+&isp_1 {
+ status = "disabled";
+};
+
+&dw200 {
+ status = "disabled";
+};
+
+&mipi_dphy_rx {
+ status = "disabled";
+};
+
+&csi_dma0 {
+ status = "disabled";
+};
+
+&csi_dma1 {
+ status = "disabled";
+};
+
+&csi2_0 {
+ status = "disabled";
+};
+
+&csi2_1 {
+ status = "disabled";
+};
+
+&d0_numa_sample {
+ status = "disabled";
+};
+
+#endif
+
+/* Devices on Die 1 */
+#if ((CHIPLET_AND_DIE & 0x2) || (CHIPLET_AND_DIE == 0x1))
+
+&d1_uart0 {
+ status = "okay";
+};
+
+&smmu1 {
+ status = "okay";
+};
+
+&smmu_pmu1 {
+ status = "disabled";
+};
+
+&dev_foo_for_die1_mapping {
+ status = "okay";
+};
+
+&d1_reset {
+ status = "okay";
+};
+
+&d1_clock {
+ status = "okay";
+};
+
+&d1_dmac0 {
+ status = "disabled";
+};
+
+&d1_aon_dmac {
+ status = "okay";
+};
+
+&vdec1 {
+ status = "disabled";
+};
+
+&venc1 {
+ status = "disabled";
+};
+
+&d1_mbox0 {
+ status = "disabled";
+};
+
+&d1_mbox1 {
+ status = "disabled";
+};
+
+&d1_mbox2 {
+ status = "disabled";
+};
+
+&d1_mbox3 {
+ status = "disabled";
+};
+
+&d1_mbox4 {
+ status = "okay";
+};
+
+&d1_mbox5 {
+ status = "okay";
+};
+
+&d1_mbox6 {
+ status = "okay";
+};
+
+&d1_mbox7 {
+ status = "okay";
+};
+
+&d1_ipc_scpu {
+ status = "disabled";
+};
+
+&d1_lpcpu {
+ status = "disabled";
+};
+
+&d1_i2c0 {
+ status = "disabled";
+ eeprom@50 {
+ compatible = "atmel,24c1024";
+ reg = <0x50>;
+ };
+};
+
+&d1_pmu {
+ status = "disabled";
+};
+
+&d1_i2c1 {
+ status = "disabled";
+};
+
+&d1_i2c2 {
+ status = "disabled";
+};
+
+&d1_i2c3 {
+ status = "disabled";
+};
+
+&d1_i2c4 {
+ status = "disabled";
+};
+
+&d1_i2c5 {
+ status = "disabled";
+};
+
+&d1_i2c6 {
+ status = "disabled";
+};
+
+&d1_i2c7 {
+ status = "disabled";
+};
+
+&d1_i2c8 {
+ status = "disabled";
+};
+
+&d1_i2c9 {
+ status = "disabled";
+};
+
+&d1_i2s0 {
+ status = "disabled";
+};
+
+&d1_i2s1 {
+ status = "disabled";
+};
+
+&d1_i2s2 {
+ status = "disabled";
+};
+
+&d1_sofdsp {
+ status = "disabled";
+};
+
+&d1_soundcard {
+ status = "disabled";
+};
+
+&d1_graphcard {
+ status = "disabled";
+};
+
+&d1_dummy_codec {
+ status = "disabled";
+};
+
+&d1_thruout {
+ status = "disabled";
+};
+
+&d1_aon_i2c0 {
+ status = "disabled";
+ aon_eeprom@50 {
+ compatible = "atmel,24c1024";
+ reg = <0x50>;
+ };
+};
+
+&d1_aon_i2c1 {
+ status = "disabled";
+};
+
+&d1_nvdla {
+ status = "disabled";
+};
+
+&d1_dsp_subsys {
+ status = "disabled";
+};
+
+&d1_dsp0 {
+ status = "disabled";
+};
+
+&d1_dsp1 {
+ status = "disabled";
+};
+
+&d1_dsp2 {
+ status = "disabled";
+};
+
+&d1_dsp3 {
+ status = "disabled";
+};
+
+&pcie_die1 {
+ status = "disabled";
+};
+
+&d1_cfg_noc {
+ status = "okay";
+};
+
+&d1_llc_noc {
+ status = "okay";
+ stat,0 = "ddr0_p0_req";
+ stat,1 = "ddr1_p0_req";
+ //latency,0 = "llcnoc_trans_probe";
+ //pending,0 = "llcnoc_trans_probe";
+};
+
+&d1_sys_noc {
+ status = "okay";
+
+ //eswin,DSPT-qos-owner;
+ //eswin,NPU-qos-owner;
+ //eswin,SPISLV_TBU3-qos-owner;
+
+ stat,0 = "TracePort:ddr0_p1_req";
+ stat,1 = "TracePort:ddr0_p2_req";
+ stat,2 = "TracePort:ddr1_p1_req";
+ stat,3 = "TracePort:ddr1_p2_req";
+
+ //latency,0 = "TracePort:sysnoc_trans_probe_0";
+ latency,1 = "TracePort:sysnoc_trans_probe_1",
+ "Mode:latency","AddrBase:0x82000000","AddrSize:0x0","Opcode:RdWr";
+ //latency,2 = "TracePort:sysnoc_trans_probe_2";
+
+ pending,0 = "TracePort:sysnoc_trans_probe_0";
+ //pending,1 = "TracePort:sysnoc_trans_probe_1", "Mode:latency","AddrBase:0x82000000","AddrSize:0x0","Opcode:RdWr";
+ pending,2 = "TracePort:sysnoc_trans_probe_2";
+};
+
+&d1_media_noc {
+ status = "okay";
+
+ //eswin,GPU-qos-owner;
+ //eswin,TBU2-qos-owner;
+ //eswin,VC-qos-owner;
+
+ stat,0 = "TracePort:ddr0_p3_req";
+ stat,1 = "TracePort:ddr1_p3_req";
+ //latency,0 = "TracePort:mnoc_trans_probe";
+ //pending,0 = "TracePort:mnoc_trans_probe";
+};
+
+&d1_realtime_noc {
+ status = "okay";
+
+ //eswin,TBU0-qos-owner;
+ //eswin,VO-qos-owner;
+
+ stat,0 = "TracePort:ddr0_p4_req";
+ stat,1 = "TracePort:ddr1_p4_req";
+ //latency,0 = "TracePort:rnoc_trans_probe";
+ //pending,0 = "TracePort:rnoc_trans_probe";
+};
+
+&d1_gmac0 {
+ status = "disabled";
+};
+
+&d1_gmac1 {
+ status = "disabled";
+};
+
+&d1_sdio0 {
+ status = "disabled";
+};
+
+&d1_sdio1 {
+ status = "disabled";
+};
+
+&d1_ssi0 {
+ status = "disabled";
+};
+
+&d1_gpu {
+ status = "disabled";
+};
+
+&d1_sata {
+ status = "disabled";
+};
+
+&d1_pinctrl {
+ status = "disabled";
+};
+
+&d1_gpio0 {
+ status = "disabled";
+};
+
+&d1_timer0 {
+ status = "disabled";
+};
+
+&d1_timer1 {
+ status = "disabled";
+};
+
+&d1_timer2 {
+ status = "disabled";
+};
+
+&d1_timer3 {
+ status = "disabled";
+};
+
+&die1_rtc {
+ status = "disabled";
+};
+
+&d1_pwm0 {
+ status = "disabled";
+};
+
+&d1_pvt0 {
+ status = "disabled";
+};
+
+&d1_pvt1 {
+ status = "disabled";
+};
+
+&d1_fan_control {
+ status = "disabled";
+};
+
+&d1_sdhci_emmc {
+ status = "disabled";
+};
+
+&d1_wdt0 {
+ status = "disabled";
+};
+
+&d1_video_output {
+ status = "disabled";
+};
+
+&d1_dc8k {
+ status = "disabled";
+};
+
+&d1_virtual_display {
+ status = "disabled";
+};
+
+&d1_dsi_output {
+ status = "disabled";
+};
+
+&d1_dsi_controller {
+ status = "disabled";
+};
+
+&d1_dc8k_test {
+ status = "disabled";
+};
+
+&d1_dw_hdmi {
+ status = "disabled";
+};
+
+&d1_dw_hdmi_hdcp2 {
+ status = "disabled";
+};
+
+&d1_wdt1 {
+ status = "disabled";
+};
+
+&d1_wdt2 {
+ status = "disabled";
+};
+
+&d1_wdt3 {
+ status = "disabled";
+};
+
+&d1_gc820 {
+ status = "disabled";
+};
+
+&d1_usbdrd3_0 {
+ status = "disabled";
+};
+
+&d1_usbdrd_dwc3_0 {
+ status = "disabled";
+};
+
+&d1_usbdrd3_1 {
+ status = "disabled";
+};
+
+&d1_usbdrd_dwc3_1 {
+ status = "disabled";
+};
+
+&d1_isp_0 {
+ status = "disabled";
+};
+
+&d1_isp_1 {
+ status = "disabled";
+};
+
+&d1_dw200 {
+ status = "disabled";
+};
+
+&d1_mipi_dphy_rx {
+ status = "disabled";
+};
+
+&d1_csi_dma0 {
+ status = "disabled";
+};
+
+&d1_csi_dma1 {
+ status = "disabled";
+};
+
+&d1_csi2_0 {
+ status = "disabled";
+};
+
+&d1_csi2_1 {
+ status = "disabled";
+};
+
+&d1_numa_sample {
+ status = "disabled";
+};
+
+#endif
diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig
new file mode 100644
index 000000000000..d5ba4ef1772b
--- /dev/null
+++ b/arch/riscv/configs/win2030_defconfig
@@ -0,0 +1,327 @@
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BPF_SYSCALL=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_BPF=y
+CONFIG_NAMESPACES=y
+CONFIG_USER_NS=y
+CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="${BR_BINARIES_DIR}/rootfs.cpio"
+CONFIG_INITRAMFS_COMPRESSION_NONE=y
+CONFIG_EXPERT=y
+# CONFIG_SYSFS_SYSCALL is not set
+CONFIG_PERF_EVENTS=y
+CONFIG_SOC_SIFIVE=y
+CONFIG_SOC_VIRT=y
+CONFIG_SMP=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_RISCV_SBI_V01=y
+# CONFIG_RISCV_BOOT_SPINWAIT is not set
+CONFIG_CMDLINE="earlycon=sbi console=ttyS0,115200n8 clk_ignore_unused cma_pernuma=0x2000000 disable_bypass=false"
+CONFIG_CMDLINE_FORCE=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_JUMP_LABEL=y
+# CONFIG_GCC_PLUGINS is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_ESWIN_RSVMEM=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IPV6 is not set
+CONFIG_NET_SCHED=y
+CONFIG_NET_CLS_ACT=y
+# CONFIG_WIRELESS is not set
+CONFIG_PCI=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM_PERFORMANCE=y
+CONFIG_PCIE_PTM=y
+# CONFIG_PCI_QUIRKS is not set
+CONFIG_PCI_PRI=y
+CONFIG_PCI_PASID=y
+CONFIG_PCIE_ESWIN=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=2
+CONFIG_BLK_DEV_RAM_SIZE=32768
+CONFIG_VIRTIO_BLK=y
+CONFIG_BLK_DEV_NVME=y
+CONFIG_NVME_MULTIPATH=y
+CONFIG_LCPU_SMMU_TEST=y
+CONFIG_SCPU_DMAAPI_SMMU_TEST=y
+CONFIG_SMP_IPI_TEST=y
+CONFIG_ESWIN_NUMA_SAMPLE=m
+CONFIG_EEPROM_AT24=y
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_AHCI_ESWIN=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_ALACRITECH is not set
+# CONFIG_NET_VENDOR_AMAZON is not set
+# CONFIG_NET_VENDOR_AQUANTIA is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_ASIX is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CADENCE is not set
+# CONFIG_NET_VENDOR_CAVIUM is not set
+# CONFIG_NET_VENDOR_CORTINA is not set
+# CONFIG_NET_VENDOR_ENGLEDER is not set
+# CONFIG_NET_VENDOR_EZCHIP is not set
+# CONFIG_NET_VENDOR_GOOGLE is not set
+# CONFIG_NET_VENDOR_HUAWEI is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MICROSOFT is not set
+# CONFIG_NET_VENDOR_LITEX is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_MICROSEMI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+# CONFIG_NET_VENDOR_NI is not set
+# CONFIG_NET_VENDOR_PENSANDO is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_RENESAS is not set
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SOLARFLARE is not set
+# CONFIG_NET_VENDOR_SOCIONEXT is not set
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_SELFTESTS=y
+CONFIG_DWMAC_WIN2030=y
+# CONFIG_DWMAC_GENERIC is not set
+# CONFIG_NET_VENDOR_SYNOPSYS is not set
+# CONFIG_NET_VENDOR_VERTEXCOM is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_NET_VENDOR_XILINX is not set
+# CONFIG_WLAN is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
+CONFIG_HVC_RISCV_SBI=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_VIRTIO=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_HELPER_AUTO is not set
+CONFIG_I2C_DESIGNWARE_SLAVE=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_I2C_DESIGNWARE_ESWIN=y
+CONFIG_I2C_SLAVE_EEPROM=y
+CONFIG_SPI=y
+CONFIG_SPI_DESIGNWARE=y
+CONFIG_SPI_DW_DMA=y
+CONFIG_SPI_DW_MMIO=y
+CONFIG_SPI_DEMO=m
+# CONFIG_PTP_1588_CLOCK is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_EIC7700=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_ESWIN=y
+CONFIG_SENSORS_ESWIN_FAN_CONTROL=y
+CONFIG_SENSORS_ESWIN_PVT=y
+CONFIG_SENSORS_INA2XX=y
+CONFIG_WATCHDOG=y
+CONFIG_DW_WATCHDOG=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_MPQ8785=y
+# CONFIG_MEDIA_CEC_SUPPORT is not set
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_DRM=y
+CONFIG_DRM_I2C_NXP_TDA9950=y
+CONFIG_DRM_DISPLAY_CONNECTOR=y
+CONFIG_DRM_SIMPLE_BRIDGE=y
+CONFIG_DRM_TOSHIBA_TC358768=m
+CONFIG_DRM_LEGACY=y
+CONFIG_FB=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_SOF_TOPLEVEL=y
+CONFIG_SND_SOC_SOF_OF=y
+CONFIG_SND_SOC_SOF_ESWIN_TOPLEVEL=y
+CONFIG_SND_SOC_SOF_ESWIN=m
+CONFIG_SND_ESWIN_DW_I2S=y
+CONFIG_SND_ESWIN_DW_PCM=y
+CONFIG_SND_ESWIN_DAI=y
+CONFIG_SND_SOC_HDMI_CODEC=y
+CONFIG_SND_SOC_ES8316=y
+CONFIG_SND_SOC_THRU_OUT=y
+CONFIG_ESWIN_SND_SOC_CODECS=y
+CONFIG_ESWIN_SND_ES8388_CODEC=y
+CONFIG_ESWIN_SND_DUMMY_CODEC=y
+CONFIG_SND_SIMPLE_CARD=y
+CONFIG_SND_AUDIO_GRAPH_CARD=y
+CONFIG_USB_ULPI_BUS=y
+CONFIG_USB_CONN_GPIO=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+# CONFIG_USB_DEFAULT_PERSIST is not set
+CONFIG_USB_MON=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DBGCAP=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_ACM=y
+CONFIG_USB_WDM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_UAS=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_ULPI=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_CP210X=y
+CONFIG_USB_SERIAL_FTDI_SIO=y
+CONFIG_USB_SERIAL_KEYSPAN=y
+CONFIG_USB_SERIAL_PL2303=y
+CONFIG_USB_SERIAL_OTI6858=y
+CONFIG_USB_SERIAL_QUALCOMM=y
+CONFIG_USB_SERIAL_OPTION=y
+CONFIG_USB_TEST=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DEBUG_FILES=y
+CONFIG_USB_GADGET_VBUS_DRAW=500
+CONFIG_USB_CONFIGFS=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_F_LB_SS=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_ZERO=m
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_MMC=y
+CONFIG_MMC_TEST=y
+CONFIG_MMC_DEBUG=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_SDIO_FU800=y
+CONFIG_MMC_SDHCI_OF_FU800=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PCF8563=y
+CONFIG_RTC_DRV_ESWIN=y
+CONFIG_DMADEVICES=y
+CONFIG_DW_AXI_DMAC=y
+CONFIG_DMATEST=y
+CONFIG_DMATEST_UNITEST=y
+CONFIG_DMABUF_HEAPS_SYSTEM_COHERENT=y
+CONFIG_DMABUF_HEAPS_IMPORT_HELPER=y
+CONFIG_VIRTIO_BALLOON=y
+CONFIG_VIRTIO_INPUT=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_STAGING=y
+# CONFIG_DW200 is not set
+CONFIG_COMMON_CLK_WIN2030=y
+CONFIG_TIMER_ESWIN=y
+CONFIG_MAILBOX=y
+CONFIG_ESWIN_MBOX=y
+CONFIG_ESWIN_IPC_SCPU=m
+CONFIG_ESWIN_LPCPU=m
+CONFIG_ARM_SMMU_V3=y
+CONFIG_RPMSG_VIRTIO=y
+CONFIG_SIFIVE_L2=y
+CONFIG_SIFIVE_L2_FLUSH=y
+CONFIG_EXTCON=y
+CONFIG_PWM=y
+CONFIG_PWM_ESWIN=y
+CONFIG_RESET_ESWIN_WIN2030=y
+CONFIG_PHY_MIXEL_MIPI_DPHY=m
+CONFIG_ARM_SMMU_V3_PMU=y
+CONFIG_INTERCONNECT=y
+CONFIG_DSP=y
+CONFIG_ESWIN_DSP_SUBSYS=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_DEV_VIRTIO=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC7=y
+CONFIG_XZ_DEC=y
+CONFIG_PRINTK_TIME=y
+CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
+CONFIG_CONSOLE_LOGLEVEL_QUIET=15
+CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_PAGEALLOC=y
+CONFIG_SCHED_STACK_END_CHECK=y
+CONFIG_DEBUG_VM=y
+CONFIG_DEBUG_VM_PGFLAGS=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_PER_CPU_MAPS=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
+CONFIG_WQ_WATCHDOG=y
+CONFIG_DEBUG_TIMEKEEPING=y
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_MUTEXES=y
+CONFIG_DEBUG_RWSEMS=y
+CONFIG_DEBUG_ATOMIC_SLEEP=y
+CONFIG_STACKTRACE=y
+CONFIG_DEBUG_LIST=y
+CONFIG_DEBUG_PLIST=y
+CONFIG_DEBUG_SG=y
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_EQS_DEBUG=y
+# CONFIG_FTRACE is not set
+# CONFIG_RUNTIME_TESTING_MENU is not set
+CONFIG_MEMTEST=y
diff --git a/drivers/tty/serial/8250/8250_dwlib.c b/drivers/tty/serial/8250/8250_dwlib.c
index 8fc8b6753148..23bb5a2c9c25 100644
--- a/drivers/tty/serial/8250/8250_dwlib.c
+++ b/drivers/tty/serial/8250/8250_dwlib.c
@@ -262,12 +262,12 @@ void dw8250_setup_port(struct uart_port *p)
* If the Component Version Register returns zero, we know that
* ADDITIONAL_FEATURES are not enabled. No need to go any further.
*/
+ /*
reg = dw8250_readl_ext(p, DW_UART_UCV);
if (!reg)
return;
-
- dev_dbg(p->dev, "Designware UART version %c.%c%c\n",
- (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
+ */
+ dev_info(p->dev, "Designware UART version\n");
/* Preserve value written by firmware or bootloader */
old_dlf = dw8250_readl_ext(p, DW_UART_DLF);
diff --git a/include/dt-bindings/clock/win2030-clock.h b/include/dt-bindings/clock/win2030-clock.h
new file mode 100755
index 000000000000..6c85b4b980f2
--- /dev/null
+++ b/include/dt-bindings/clock/win2030-clock.h
@@ -0,0 +1,624 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ESWIN Clk Provider Driver
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Authors: HuangYiFeng<huangyifeng@eswincomputing.com>
+ */
+
+#ifndef __DTS_WIN2030_CLOCK_H
+#define __DTS_WIN2030_CLOCK_H
+
+#define WIN2030_NONE_CLOCK 0
+
+/* fixed rate */
+#define WIN2030_XTAL_24M 1
+#define WIN2030_XTAL_32K 2
+#define WIN2030_PLL_CPU 3 /*for cpu clk*/
+#define WIN2030_SPLL0_FOUT1 4
+#define WIN2030_SPLL0_FOUT2 5
+#define WIN2030_SPLL0_FOUT3 6
+#define WIN2030_SPLL1_FOUT1 7
+#define WIN2030_SPLL1_FOUT2 8
+#define WIN2030_SPLL1_FOUT3 9
+#define WIN2030_SPLL2_FOUT1 10
+#define WIN2030_SPLL2_FOUT2 11
+#define WIN2030_SPLL2_FOUT3 12
+#define WIN2030_VPLL_FOUT1 13
+#define WIN2030_VPLL_FOUT2 14
+#define WIN2030_VPLL_FOUT3 15
+#define WIN2030_APLL_FOUT1 16
+#define WIN2030_APLL_FOUT2 17
+#define WIN2030_APLL_FOUT3 18
+#define WIN2030_EXT_MCLK 19
+#define WIN2030_PLL_DDR 20
+#define WIN2030_LPDDR_REF_BAK 21
+
+
+/* mux clocks */
+#define WIN2030_MUX_U_CPU_ROOT_3MUX1_GFREE 30 /*for cpu clk*/
+#define WIN2030_MUX_U_CPU_ACLK_2MUX1_GFREE 31 /*for cpu clk*/
+#define WIN2030_MUX_U_DSP_ACLK_ROOT_2MUX1_GFREE 32
+#define WIN2030_MUX_U_D2D_ACLK_ROOT_2MUX1_GFREE 33
+#define WIN2030_MUX_U_MSHCORE_ROOT_3MUX1_0 34
+#define WIN2030_MUX_U_MSHCORE_ROOT_3MUX1_1 35
+#define WIN2030_MUX_U_MSHCORE_ROOT_3MUX1_2 36
+#define WIN2030_MUX_U_NPU_LLCLK_3MUX1_GFREE 37
+#define WIN2030_MUX_U_NPU_CORE_3MUX1_GFREE 38
+#define WIN2030_MUX_U_VI_ACLK_ROOT_2MUX1_GFREE 39
+#define WIN2030_MUX_U_VI_DVP_ROOT_2MUX1_GFREE 40
+#define WIN2030_MUX_U_VI_DIG_ISP_ROOT_2MUX1_GFREE 41
+#define WIN2030_MUX_U_VO_ACLK_ROOT_2MUX1_GFREE 42
+#define WIN2030_MUX_U_VO_PIXEL_ROOT_2MUX1 43
+#define WIN2030_MUX_U_VO_CEC_2MUX1 44
+#define WIN2030_MUX_U_VCDEC_ROOT_2MUX1_GFREE 45
+#define WIN2030_MUX_U_VCACLK_ROOT_2MUX1_GFREE 46
+#define WIN2030_MUX_U_RTC_2MUX1 47
+#define WIN2030_MUX_U_SYSCFG_CLK_ROOT_2MUX1_GFREE 48
+#define WIN2030_MUX_U_NOCNSP_XTAL_2MUX1 49
+#define WIN2030_MUX_U_BOOTSPI_CLK_2MUX1_GFREE 50
+#define WIN2030_MUX_U_SCPU_CORE_CLK_2MUX1_GFREE 51
+#define WIN2030_MUX_U_LPCPU_CORE_CLK_2MUX1_GFREE 52
+#define WIN2030_MUX_GPU_ACLK_XTAL_2MUX1 53
+#define WIN2030_MUX_U_DSP_ACLK_XTAL_2MUX1 54
+#define WIN2030_MUX_U_D2D_ACLK_XTAL_2MUX1 55
+#define WIN2030_MUX_U_HSP_ACLK_XTAL_2MUX1 56
+#define WIN2030_MUX_U_PCIE_ACLK_XTAL_2MUX1 57
+#define WIN2030_MUX_U_NPU_ACLK_XTAL_2MUX1 58
+#define WIN2030_MUX_U_NPU_LLC_XTAL_2MUX1 59
+#define WIN2030_MUX_U_NPU_CORE_XTAL_2MUX1 60
+#define WIN2030_MUX_U_VI_ACLK_XTAL_2MUX1 61
+#define WIN2030_MUX_U_VI_DVP_XTAL_2MUX1 62
+#define WIN2030_MUX_U_VI_DIG_ISP_XTAL_2MUX1 63
+#define WIN2030_MUX_U_VI_SHUTTER_XTAL_2MUX1_0 64
+#define WIN2030_MUX_U_VI_SHUTTER_XTAL_2MUX1_1 65
+#define WIN2030_MUX_U_VI_SHUTTER_XTAL_2MUX1_2 66
+#define WIN2030_MUX_U_VI_SHUTTER_XTAL_2MUX1_3 67
+#define WIN2030_MUX_U_VI_SHUTTER_XTAL_2MUX1_4 68
+#define WIN2030_MUX_U_VI_SHUTTER_XTAL_2MUX1_5 69
+#define WIN2030_MUX_U_VO_ACLK_XTAL_2MUX1 70
+#define WIN2030_MUX_U_IESMCLK_XTAL_2MUX1 71
+#define WIN2030_MUX_U_VO_PIXEL_XTAL_2MUX1 72
+#define WIN2030_MUX_U_VO_MCLK_2MUX_EXT_MCLK 73
+#define WIN2030_MUX_U_VC_ACLK_XTAL_2MUX1 74
+#define WIN2030_MUX_U_JD_XTAL_2MUX1 75
+#define WIN2030_MUX_U_JE_XTAL_2MUX1 76
+#define WIN2030_MUX_U_VE_XTAL_2MUX1 77
+#define WIN2030_MUX_U_VD_XTAL_2MUX1 78
+#define WIN2030_MUX_U_SATA_PHY_2MUX1 79
+#define WIN2030_MUX_U_AONDMA_AXI2MUX1_GFREE 80
+#define WIN2030_MUX_U_CRYPTO_XTAL_2MUX1 81
+#define WIN2030_MUX_U_RMII_REF_2MUX 82
+#define WIN2030_MUX_U_ETH_CORE_2MUX1 83
+#define WIN2030_MUX_U_VI_DW_ROOT_2MUX1 84
+#define WIN2030_MUX_U_VI_DW_XTAL_2MUX1 85
+#define WIN2030_MUX_U_NPU_E31_3MUX1_GFREE 86
+#define WIN2030_MUX_U_DDR_ACLK_ROOT_2MUX1_GFREE 87
+
+/* divider clocks */
+#define WIN2030_DIVDER_U_SYS_CFG_DIV_DYNM 100
+#define WIN2030_DIVDER_U_NOC_NSP_DIV_DYNM 101
+#define WIN2030_DIVDER_U_BOOTSPI_DIV_DYNM 102
+#define WIN2030_DIVDER_U_SCPU_CORE_DIV_DYNM 103
+#define WIN2030_DIVDER_U_LPCPU_CORE_DIV_DYNM 104
+#define WIN2030_DIVDER_U_GPU_ACLK_DIV_DYNM 105
+#define WIN2030_DIVDER_U_DSP_ACLK_DIV_DYNM 106
+#define WIN2030_DIVDER_U_D2D_ACLK_DIV_DYNM 107
+#define WIN2030_DIVDER_U_HSP_ACLK_DIV_DYNM 108
+#define WIN2030_DIVDER_U_ETH_TXCLK_DIV_DYNM_0 109
+#define WIN2030_DIVDER_U_ETH_TXCLK_DIV_DYNM_1 110
+#define WIN2030_DIVDER_U_MSHC_CORE_DIV_DYNM_0 111
+#define WIN2030_DIVDER_U_MSHC_CORE_DIV_DYNM_1 112
+#define WIN2030_DIVDER_U_MSHC_CORE_DIV_DYNM_2 113
+#define WIN2030_DIVDER_U_PCIE_ACLK_DIV_DYNM 114
+#define WIN2030_DIVDER_U_NPU_ACLK_DIV_DYNM 115
+#define WIN2030_DIVDER_U_NPU_LLC_SRC0_DIV_DYNM 116
+#define WIN2030_DIVDER_U_NPU_LLC_SRC1_DIV_DYNM 117
+#define WIN2030_DIVDER_U_NPU_CORECLK_DIV_DYNM 118
+#define WIN2030_DIVDER_U_VI_ACLK_DIV_DYNM 119
+#define WIN2030_DIVDER_U_VI_DVP_DIV_DYNM 120
+#define WIN2030_DIVDER_U_VI_DIG_ISP_DIV_DYNM 121
+#define WIN2030_DIVDER_U_VI_SHUTTER_DIV_DYNM_0 122
+#define WIN2030_DIVDER_U_VI_SHUTTER_DIV_DYNM_1 123
+#define WIN2030_DIVDER_U_VI_SHUTTER_DIV_DYNM_2 124
+#define WIN2030_DIVDER_U_VI_SHUTTER_DIV_DYNM_3 125
+#define WIN2030_DIVDER_U_VI_SHUTTER_DIV_DYNM_4 126
+#define WIN2030_DIVDER_U_VI_SHUTTER_DIV_DYNM_5 127
+#define WIN2030_DIVDER_U_VO_ACLK_DIV_DYNM 128
+#define WIN2030_DIVDER_U_IESMCLK_DIV_DYNM 129
+#define WIN2030_DIVDER_U_VO_PIXEL_DIV_DYNM 130
+#define WIN2030_DIVDER_U_VO_MCLK_DIV_DYNM 131
+#define WIN2030_DIVDER_U_VC_ACLK_DIV_DYNM 132
+#define WIN2030_DIVDER_U_JD_DIV_DYNM 133
+#define WIN2030_DIVDER_U_JE_DIV_DYNM 134
+#define WIN2030_DIVDER_U_VE_DIV_DYNM 135
+#define WIN2030_DIVDER_U_VD_DIV_DYNM 136
+#define WIN2030_DIVDER_U_G2D_DIV_DYNM 137
+#define WIN2030_DIVDER_U_AONDMA_AXI_DIV_DYNM 138
+#define WIN2030_DIVDER_U_CRYPTO_DIV_DYNM 139
+#define WIN2030_DIVDER_U_VI_DW_DIV_DYNM 140
+#define WIN2030_DIVDER_U_NPU_E31_DIV_DYNM 141
+#define WIN2030_DIVDER_U_SATA_PHY_REF_DIV_DYNM 142
+#define WIN2030_DIVDER_U_DSP_0_ACLK_DIV_DYNM 143
+#define WIN2030_DIVDER_U_DSP_1_ACLK_DIV_DYNM 144
+#define WIN2030_DIVDER_U_DSP_2_ACLK_DIV_DYNM 145
+#define WIN2030_DIVDER_U_DSP_3_ACLK_DIV_DYNM 146
+#define WIN2030_DIVDER_U_DDR_ACLK_DIV_DYNM 147
+#define WIN2030_DIVDER_U_AON_RTC_DIV_DYNM 148
+#define WIN2030_DIVDER_U_U84_RTC_TOGGLE_DIV_DYNM 149
+#define WIN2030_DIVDER_U_VO_CEC_DIV_DYNM 150
+
+
+/* gate clocks */
+#define WIN2030_GATE_CLK_CPU_EXT_SRC_CORE_CLK_0 200
+#define WIN2030_GATE_CLK_CPU_EXT_SRC_CORE_CLK_1 201
+#define WIN2030_GATE_CLK_CPU_EXT_SRC_CORE_CLK_2 202
+#define WIN2030_GATE_CLK_CPU_EXT_SRC_CORE_CLK_3 203
+#define WIN2030_GATE_CLK_CPU_TRACE_CLK_0 204
+#define WIN2030_GATE_CLK_CPU_TRACE_CLK_1 205
+#define WIN2030_GATE_CLK_CPU_TRACE_CLK_2 206
+#define WIN2030_GATE_CLK_CPU_TRACE_CLK_3 207
+#define WIN2030_GATE_CLK_CPU_DEBUG_CLK 208
+#define WIN2030_GATE_CLK_CPU_TRACE_COM_CLK 209
+#define WIN2030_GATE_CLK_CPU_CLK 210
+#define WIN2030_GATE_CLK_SPLL0_FOUT2 211
+#define WIN2030_GATE_CLK_VPLL_FOUT2 212
+#define WIN2030_GATE_CLK_VPLL_FOUT3 213
+#define WIN2030_GATE_CLK_APLL_FOUT1 214
+#define WIN2030_GATE_CLK_APLL_FOUT2 215
+#define WIN2030_GATE_CLK_APLL_FOUT3 216
+#define WIN2030_GATE_EXT_MCLK 217
+#define WIN2030_GATE_CLK_1M 218
+#define WIN2030_GATE_CLK_SYS_CFG 219
+#define WIN2030_GATE_CLK_MIPI_TXESC 220
+#define WIN2030_GATE_NOC_CFG_CLK 221
+#define WIN2030_GATE_NOC_NSP_CLK 222
+#define WIN2030_GATE_CLK_BOOTSPI 223
+#define WIN2030_GATE_CLK_BOOTSPI_CFG 224
+#define WIN2030_GATE_CLK_U84_CORE_LP 225
+#define WIN2030_GATE_CLK_SCPU_CORE 226
+#define WIN2030_GATE_CLK_SCPU_BUS 227
+#define WIN2030_GATE_CLK_LPCPU_CORE 228
+#define WIN2030_GATE_CLK_LPCPU_BUS 229
+#define WIN2030_GATE_GPU_ACLK 230
+#define WIN2030_GATE_GPU_GRAY_CLK 231
+#define WIN2030_GATE_GPU_CFG_CLK 232
+#define WIN2030_GATE_CLK_DSP_ROOT 233
+#define WIN2030_GATE_DSPT_ACLK 234
+#define WIN2030_GATE_DSPT_CFG_CLK 235
+#define WIN2030_GATE_CLK_D2DDR_ACLK 236
+#define WIN2030_GATE_D2D_ACLK 237
+#define WIN2030_GATE_D2D_CFG_CLK 238
+#define WIN2030_GATE_CLK_HSP_ACLK 239
+#define WIN2030_GATE_CLK_HSP_CFGCLK 240
+#define WIN2030_GATE_TCU_ACLK 241
+#define WIN2030_GATE_TCU_CFG_CLK 242
+#define WIN2030_GATE_DDRT_CFG_CLK 243
+#define WIN2030_GATE_DDRT1_CFG_CLK 244
+#define WIN2030_GATE_DDRT0_P0_ACLK 245
+#define WIN2030_GATE_DDRT0_P1_ACLK 246
+#define WIN2030_GATE_DDRT0_P2_ACLK 247
+#define WIN2030_GATE_DDRT0_P3_ACLK 248
+#define WIN2030_GATE_DDRT0_P4_ACLK 249
+#define WIN2030_GATE_DDRT1_P0_ACLK 250
+#define WIN2030_GATE_DDRT1_P1_ACLK 251
+#define WIN2030_GATE_DDRT1_P2_ACLK 252
+#define WIN2030_GATE_DDRT1_P3_ACLK 253
+#define WIN2030_GATE_DDRT1_P4_ACLK 254
+#define WIN2030_GATE_HSP_ACLK 255
+#define WIN2030_GATE_HSP_CFG_CLK 256
+#define WIN2030_GATE_HSP_SATA_RBC_CLK 257
+#define WIN2030_GATE_HSP_SATA_OOB_CLK 258
+#define WIN2030_GATE_HSP_SATA_PMALIVE_CLK 259
+#define WIN2030_GATE_HSP_ETH_APP_CLK 260
+#define WIN2030_GATE_HSP_ETH_CSR_CLK 261
+#define WIN2030_GATE_HSP_ETH0_CORE_CLK 262
+#define WIN2030_GATE_HSP_ETH1_CORE_CLK 263
+#define WIN2030_GATE_HSP_MSHC0_CORE_CLK 264
+#define WIN2030_GATE_HSP_MSHC1_CORE_CLK 265
+#define WIN2030_GATE_HSP_MSHC2_CORE_CLK 266
+#define WIN2030_GATE_HSP_MSHC0_TMR_CLK 267
+#define WIN2030_GATE_HSP_MSHC1_TMR_CLK 268
+#define WIN2030_GATE_HSP_MSHC2_TMR_CLK 269
+#define WIN2030_GATE_HSP_USB0_SUSPEND_CLK 270
+#define WIN2030_GATE_HSP_USB1_SUSPEND_CLK 271
+#define WIN2030_GATE_PCIET_ACLK 272
+#define WIN2030_GATE_PCIET_CFG_CLK 273
+#define WIN2030_GATE_PCIET_CR_CLK 274
+#define WIN2030_GATE_PCIET_AUX_CLK 275
+#define WIN2030_GATE_NPU_ACLK 276
+#define WIN2030_GATE_NPU_CFG_CLK 277
+#define WIN2030_GATE_CLK_NPU_LLC_SRC0 278
+#define WIN2030_GATE_CLK_NPU_LLC_SRC1 279
+#define WIN2030_GATE_NPU_LLC_ACLK 280
+#define WIN2030_GATE_CLK_NPU_CORE_ST1 281
+#define WIN2030_GATE_NPU_CLK 282
+#define WIN2030_GATE_NPU_E31_CLK 283
+#define WIN2030_GATE_CLK_VI_ACLK_ST1 284
+#define WIN2030_GATE_VI_ACLK 285
+#define WIN2030_GATE_VI_DVP_CLK 286
+#define WIN2030_GATE_VI_CFG_CLK 287
+#define WIN2030_GATE_VI_DIG_DW_CLK 288
+#define WIN2030_GATE_VI_DIG_ISP_CLK 289
+#define WIN2030_GATE_VI_SHUTTER_0 290
+#define WIN2030_GATE_VI_SHUTTER_1 291
+#define WIN2030_GATE_VI_SHUTTER_2 292
+#define WIN2030_GATE_VI_SHUTTER_3 293
+#define WIN2030_GATE_VI_SHUTTER_4 294
+#define WIN2030_GATE_VI_SHUTTER_5 295
+#define WIN2030_GATE_VI_PHY_TXCLKESC 296
+#define WIN2030_GATE_VI_PHY_CFG 297
+#define WIN2030_GATE_VO_ACLK 298
+#define WIN2030_GATE_VO_CFG_CLK 299
+#define WIN2030_GATE_VO_HDMI_IESMCLK 300
+#define WIN2030_GATE_VO_PIXEL_CLK 301
+#define WIN2030_GATE_VO_I2S_MCLK 302
+#define WIN2030_GATE_VO_CR_CLK 303
+#define WIN2030_GATE_VO_CEC_CLK 304
+#define WIN2030_GATE_CLK_VC_ROOT 305
+#define WIN2030_GATE_VC_ACLK 306
+#define WIN2030_GATE_VC_CFG_CLK 307
+#define WIN2030_GATE_VC_JE_CLK 308
+#define WIN2030_GATE_VC_JD_CLK 309
+#define WIN2030_GATE_VC_VE_CLK 310
+#define WIN2030_GATE_VC_VD_CLK 311
+#define WIN2030_GATE_G2D_CFG_CLK 312
+#define WIN2030_GATE_CLK_G2D_ST2 313
+#define WIN2030_GATE_G2D_CLK 314
+#define WIN2030_GATE_G2D_ACLK 315
+#define WIN2030_GATE_CLK_PVT_INNER 316
+#define WIN2030_GATE_PVT_CLK_0 317
+#define WIN2030_GATE_PVT_CLK_1 318
+#define WIN2030_GATE_PVT_CLK_2 319
+#define WIN2030_GATE_PVT_CLK_3 320
+#define WIN2030_GATE_PVT_CLK_4 321
+#define WIN2030_GATE_CLK_AONDMA_CFG 322
+#define WIN2030_GATE_CLK_AONDMA_AXI_ST3 323
+#define WIN2030_GATE_AONDMA_ACLK 324
+#define WIN2030_GATE_AON_ACLK 325
+#define WIN2030_GATE_TIMER_CLK_0 326
+#define WIN2030_GATE_TIMER_CLK_1 327
+#define WIN2030_GATE_TIMER_CLK_2 328
+#define WIN2030_GATE_TIMER_CLK_3 329
+#define WIN2030_GATE_TIMER_PCLK_0 330
+#define WIN2030_GATE_TIMER_PCLK_1 331
+#define WIN2030_GATE_TIMER_PCLK_2 332
+#define WIN2030_GATE_TIMER_PCLK_3 333
+#define WIN2030_GATE_TIMER3_CLK8 334
+#define WIN2030_GATE_CLK_RTC_CFG 335
+#define WIN2030_GATE_CLK_RTC 336
+#define WIN2030_GATE_HSP_RMII_REF_0 337
+#define WIN2030_GATE_HSP_RMII_REF_1 338
+#define WIN2030_GATE_CLK_PKA_CFG 339
+#define WIN2030_GATE_CLK_SPACC_CFG 340
+#define WIN2030_GATE_CLK_CRYPTO 341
+#define WIN2030_GATE_CLK_TRNG_CFG 342
+#define WIN2030_GATE_CLK_OTP_CFG 343
+#define WIN2030_GATE_CLMM_CFG_CLK 344
+#define WIN2030_GATE_CLMM_DEB_CLK 345
+#define WIN2030_GATE_CLK_MAILBOX_0 346
+#define WIN2030_GATE_CLK_MAILBOX_1 347
+#define WIN2030_GATE_CLK_MAILBOX_2 348
+#define WIN2030_GATE_CLK_MAILBOX_3 349
+#define WIN2030_GATE_CLK_MAILBOX_4 350
+#define WIN2030_GATE_CLK_MAILBOX_5 351
+#define WIN2030_GATE_CLK_MAILBOX_6 352
+#define WIN2030_GATE_CLK_MAILBOX_7 353
+#define WIN2030_GATE_CLK_MAILBOX_8 354
+#define WIN2030_GATE_CLK_MAILBOX_9 355
+#define WIN2030_GATE_CLK_MAILBOX_10 356
+#define WIN2030_GATE_CLK_MAILBOX_11 357
+#define WIN2030_GATE_CLK_MAILBOX_12 358
+#define WIN2030_GATE_CLK_MAILBOX_13 359
+#define WIN2030_GATE_CLK_MAILBOX_14 360
+#define WIN2030_GATE_CLK_MAILBOX_15 361
+#define WIN2030_GATE_CLK_APLL_TEST_OUT 362
+#define WIN2030_GATE_CLK_CPLL_TEST_OUT 363
+#define WIN2030_GATE_CLK_HSP_DFT150M 364
+#define WIN2030_GATE_CLK_HSP_DFT300M 365
+#define WIN2030_GATE_CLK_HSP_DFT600M 366
+#define WIN2030_GATE_CLK_VI_DFT400M 367
+#define WIN2030_GATE_CLK_VI_DFT500M 368
+#define WIN2030_GATE_CLK_VO_DFT300M 369
+#define WIN2030_GATE_CLK_VO_DFT600M 370
+#define WIN2030_GATE_CLK_D2D_DFT300M 371
+#define WIN2030_GATE_CLK_D2D_DFT600M 372
+#define WIN2030_GATE_CLK_PCIE_DFT125M 373
+#define WIN2030_GATE_CLK_PCIE_DFT200M 374
+#define WIN2030_GATE_CLK_DDR_PLL_BYP_CLK 375
+#define WIN2030_GATE_CLK_DDR_RX_TEST_CLK 376
+#define WIN2030_GATE_LSP_I2C0_PCLK 377
+#define WIN2030_GATE_LSP_I2C1_PCLK 378
+#define WIN2030_GATE_LSP_I2C2_PCLK 379
+#define WIN2030_GATE_LSP_I2C3_PCLK 380
+#define WIN2030_GATE_LSP_I2C4_PCLK 381
+#define WIN2030_GATE_LSP_I2C5_PCLK 382
+#define WIN2030_GATE_LSP_I2C6_PCLK 383
+#define WIN2030_GATE_LSP_I2C7_PCLK 384
+#define WIN2030_GATE_LSP_I2C8_PCLK 385
+#define WIN2030_GATE_LSP_I2C9_PCLK 386
+#define WIN2030_GATE_LSP_WDT0_PCLK 387
+#define WIN2030_GATE_LSP_WDT1_PCLK 388
+#define WIN2030_GATE_LSP_WDT2_PCLK 389
+#define WIN2030_GATE_LSP_WDT3_PCLK 390
+#define WIN2030_GATE_LSP_SSI0_PCLK 391
+#define WIN2030_GATE_LSP_SSI1_PCLK 392
+#define WIN2030_GATE_LSP_PVT_PCLK 393
+#define WIN2030_GATE_AON_I2C0_PCLK 394
+#define WIN2030_GATE_AON_I2C1_PCLK 395
+#define WIN2030_GATE_LSP_UART0_PCLK 396
+#define WIN2030_GATE_LSP_UART1_PCLK 397
+#define WIN2030_GATE_LSP_UART2_PCLK 398
+#define WIN2030_GATE_LSP_UART3_PCLK 399
+#define WIN2030_GATE_LSP_UART4_PCLK 400
+#define WIN2030_GATE_LSP_TIMER_PCLK 401
+#define WIN2030_GATE_LSP_FAN_PCLK 402
+#define WIN2030_GATE_LSP_PVT0_CLK 403
+#define WIN2030_GATE_LSP_PVT1_CLK 404
+#define WIN2030_GATE_RESERVED_1 405
+#define WIN2030_GATE_RESERVED_2 406
+#define WIN2030_GATE_RESERVED_3 407
+#define WIN2030_GATE_VC_JE_PCLK 408
+#define WIN2030_GATE_VC_JD_PCLK 409
+#define WIN2030_GATE_VC_VE_PCLK 410
+#define WIN2030_GATE_VC_VD_PCLK 411
+#define WIN2030_GATE_VC_MON_PCLK 412
+#define WIN2030_GATE_HSP_DMA0_CLK 413
+
+/*fixed factor clocks*/
+#define WIN2030_FIXED_FACTOR_U_CPU_DIV2 450
+#define WIN2030_FIXED_FACTOR_U_CLK_1M_DIV24 451
+#define WIN2030_FIXED_FACTOR_U_MIPI_TXESC_DIV10 452
+#define WIN2030_FIXED_FACTOR_U_U84_CORE_LP_DIV2 453
+#define WIN2030_FIXED_FACTOR_U_SCPU_BUS_DIV2 454
+#define WIN2030_FIXED_FACTOR_U_LPCPU_BUS_DIV2 455
+#define WIN2030_FIXED_FACTOR_U_PCIE_CR_DIV2 456
+#define WIN2030_FIXED_FACTOR_U_PCIE_AUX_DIV4 457
+#define WIN2030_FIXED_FACTOR_U_PVT_DIV20 458
+#define WIN2030_FIXED_FACTOR_U_DFT100M_DIV4 459
+#define WIN2030_FIXED_FACTOR_U_DFT125M_DIV2 460
+#define WIN2030_FIXED_FACTOR_U_DFT150M_DIV2 461
+#define WIN2030_FIXED_FACTOR_U_DFT100M_DIV2 462
+#define WIN2030_FIXED_FACTOR_U_DFT500M_DIV3 463
+#define WIN2030_FIXED_FACTOR_U_DFT500M_DIV2 464
+#define WIN2030_FIXED_FACTOR_SPLL0_TEST_DIV8 465
+#define WIN2030_FIXED_FACTOR_SPLL1_TEST_DIV6 466
+#define WIN2030_FIXED_FACTOR_SPLL2_TEST_DIV4 467
+#define WIN2030_FIXED_FACTOR_U_HSP_RMII_REF_DIV6 468
+#define WIN2030_FIXED_FACTOR_U_DRR_DIV8 469
+
+
+/*clocks list for consumer*/
+#define WIN2030_CLK_CPU_EXT_SRC_CORE_CLK_0 500
+#define WIN2030_CLK_CPU_EXT_SRC_CORE_CLK_1 501
+#define WIN2030_CLK_CPU_EXT_SRC_CORE_CLK_2 502
+#define WIN2030_CLK_CPU_EXT_SRC_CORE_CLK_3 503
+#define WIN2030_CLK_CPU_TRACE_CLK_0 504
+#define WIN2030_CLK_CPU_TRACE_CLK_1 505
+#define WIN2030_CLK_CPU_TRACE_CLK_2 506
+#define WIN2030_CLK_CPU_TRACE_CLK_3 507
+#define WIN2030_CLK_CPU_DEBUG_CLK 508
+#define WIN2030_CLK_CPU_TRACE_COM_CLK 509
+#define WIN2030_CLK_CPU_CLK 510
+#define WIN2030_CLK_CLK_1M 511
+#define WIN2030_CLK_CLK_SYS_CFG 512
+#define WIN2030_CLK_CLK_MIPI_TXESC 513
+#define WIN2030_CLK_NOC_CFG_CLK 514
+#define WIN2030_CLK_NOC_NSP_CLK 515
+#define WIN2030_CLK_CLK_BOOTSPI 516
+#define WIN2030_CLK_CLK_BOOTSPI_CFG 517
+#define WIN2030_CLK_CLK_U84_CORE_LP 518
+#define WIN2030_CLK_CLK_SCPU_CORE 519
+#define WIN2030_CLK_CLK_SCPU_BUS 520
+#define WIN2030_CLK_CLK_LPCPU_CORE 521
+#define WIN2030_CLK_CLK_LPCPU_BUS 522
+#define WIN2030_CLK_GPU_ACLK 523
+#define WIN2030_CLK_GPU_GRAY_CLK 524
+#define WIN2030_CLK_GPU_CFG_CLK 525
+#define WIN2030_CLK_CLK_DSP_ROOT 526
+#define WIN2030_CLK_DSPT_ACLK 527
+#define WIN2030_CLK_DSPT_CFG_CLK 528
+#define WIN2030_CLK_CLK_D2DDR_ACLK 529
+#define WIN2030_CLK_D2D_ACLK 530
+#define WIN2030_CLK_D2D_CFG_CLK 531
+#define WIN2030_CLK_TCU_ACLK 532
+#define WIN2030_CLK_TCU_CFG_CLK 533
+#define WIN2030_CLK_DDRT_CFG_CLK 534
+#define WIN2030_CLK_DDRT0_P0_ACLK 535
+#define WIN2030_CLK_DDRT0_P1_ACLK 536
+#define WIN2030_CLK_DDRT0_P2_ACLK 537
+#define WIN2030_CLK_DDRT0_P3_ACLK 538
+#define WIN2030_CLK_DDRT0_P4_ACLK 539
+#define WIN2030_CLK_DDRT1_P0_ACLK 540
+#define WIN2030_CLK_DDRT1_P1_ACLK 541
+#define WIN2030_CLK_DDRT1_P2_ACLK 542
+#define WIN2030_CLK_DDRT1_P3_ACLK 543
+#define WIN2030_CLK_DDRT1_P4_ACLK 544
+#define WIN2030_CLK_HSP_ACLK 545
+#define WIN2030_CLK_HSP_CFG_CLK 546
+#define WIN2030_CLK_HSP_SATA_RBC_CLK 547
+#define WIN2030_CLK_HSP_SATA_OOB_CLK 548
+#define WIN2030_CLK_HSP_SATA_PMALIVE_CLK 549
+#define WIN2030_CLK_HSP_ETH_APP_CLK 550
+#define WIN2030_CLK_HSP_ETH_CSR_CLK 551
+#define WIN2030_CLK_HSP_ETH0_CORE_CLK 552
+#define WIN2030_CLK_HSP_ETH1_CORE_CLK 553
+#define WIN2030_CLK_HSP_MSHC0_CORE_CLK 554
+#define WIN2030_CLK_HSP_MSHC1_CORE_CLK 555
+#define WIN2030_CLK_HSP_MSHC2_CORE_CLK 556
+#define WIN2030_CLK_HSP_MSHC0_TMR_CLK 557
+#define WIN2030_CLK_HSP_MSHC1_TMR_CLK 558
+#define WIN2030_CLK_HSP_MSHC2_TMR_CLK 559
+#define WIN2030_CLK_HSP_USB0_SUSPEND_CLK 560
+#define WIN2030_CLK_HSP_USB1_SUSPEND_CLK 561
+#define WIN2030_CLK_PCIET_ACLK 562
+#define WIN2030_CLK_PCIET_CFG_CLK 563
+#define WIN2030_CLK_PCIET_CR_CLK 564
+#define WIN2030_CLK_PCIET_AUX_CLK 565
+#define WIN2030_CLK_NPU_ACLK 566
+#define WIN2030_CLK_NPU_CFG_CLK 567
+#define WIN2030_CLK_CLK_NPU_LLC_SRC0 568
+#define WIN2030_CLK_CLK_NPU_LLC_SRC1 569
+#define WIN2030_CLK_NPU_LLC_ACLK 570
+#define WIN2030_CLK_CLK_NPU_CORE_ST1 571
+#define WIN2030_CLK_NPU_CLK 572
+#define WIN2030_CLK_NPU_E31_CLK 573
+#define WIN2030_CLK_CLK_VI_ACLK_ST1 574
+#define WIN2030_CLK_VI_ACLK 575
+#define WIN2030_CLK_VI_DVP_CLK 576
+#define WIN2030_CLK_VI_CFG_CLK 577
+#define WIN2030_CLK_VI_DIG_DW_CLK 578
+#define WIN2030_CLK_VI_DIG_ISP_CLK 579
+#define WIN2030_CLK_VI_SHUTTER_0 580
+#define WIN2030_CLK_VI_SHUTTER_1 581
+#define WIN2030_CLK_VI_SHUTTER_2 582
+#define WIN2030_CLK_VI_SHUTTER_3 583
+#define WIN2030_CLK_VI_SHUTTER_4 584
+#define WIN2030_CLK_VI_SHUTTER_5 585
+#define WIN2030_CLK_VI_PHY_TXCLKESC 586
+#define WIN2030_CLK_VI_PHY_CFG 587
+#define WIN2030_CLK_VO_ACLK 588
+#define WIN2030_CLK_VO_CFG_CLK 589
+#define WIN2030_CLK_VO_HDMI_IESMCLK 590
+#define WIN2030_CLK_VO_PIXEL_CLK 591
+#define WIN2030_CLK_VO_I2S_MCLK 592
+#define WIN2030_CLK_VO_CR_CLK 593
+#define WIN2030_CLK_VO_CEC_CLK 594
+#define WIN2030_CLK_CLK_VC_ROOT 595
+#define WIN2030_CLK_VC_ACLK 596
+#define WIN2030_CLK_VC_CFG_CLK 597
+#define WIN2030_CLK_VC_JE_CLK 598
+#define WIN2030_CLK_VC_JD_CLK 599
+#define WIN2030_CLK_VC_VE_CLK 600
+#define WIN2030_CLK_VC_VD_CLK 601
+#define WIN2030_CLK_G2D_CFG_CLK 602
+#define WIN2030_CLK_CLK_G2D_ST2 603
+#define WIN2030_CLK_G2D_CLK 604
+#define WIN2030_CLK_G2D_ACLK 605
+#define WIN2030_CLK_CLK_RESERVED 606
+#define WIN2030_CLK_PVT_CLK_0 607
+#define WIN2030_CLK_PVT_CLK_1 608
+#define WIN2030_CLK_HSP_RMII_REF_0 609
+#define WIN2030_CLK_HSP_RMII_REF_1 610
+#define WIN2030_CLK_HSP_SATA_PHY_REF 611
+#define WIN2030_CLK_AONDMA_CFG 612
+#define WIN2030_CLK_CLK_AONDMA_AXI_ST3 613
+#define WIN2030_CLK_AONDMA_ACLK 614
+#define WIN2030_CLK_AON_ACLK 615
+#define WIN2030_CLK_TIMER_CLK_0 616 //AON timer
+#define WIN2030_CLK_TIMER_CLK_1 617
+#define WIN2030_CLK_TIMER_CLK_2 618
+#define WIN2030_CLK_TIMER_CLK_3 619
+#define WIN2030_CLK_TIMER_PCLK_0 620
+#define WIN2030_CLK_TIMER_PCLK_1 621
+#define WIN2030_CLK_TIMER_PCLK_2 622
+#define WIN2030_CLK_TIMER_PCLK_3 623
+#define WIN2030_CLK_TIMER3_CLK8 624
+#define WIN2030_CLK_CLK_RTC_CFG 625 // AON rtc
+#define WIN2030_CLK_CLK_RTC 626 // AON rtc
+#define WIN2030_CLK_CLK_U84_RTC_TOGGLE 627
+#define WIN2030_CLK_UNUSED_1 628
+#define WIN2030_CLK_CLK_PKA_CFG 629
+#define WIN2030_CLK_CLK_SPACC_CFG 630
+#define WIN2030_CLK_CLK_CRYPTO 631
+#define WIN2030_CLK_CLK_TRNG_CFG 632
+#define WIN2030_CLK_CLK_OTP_CFG 633
+#define WIN2030_CLK_CLMM_CFG_CLK 634
+#define WIN2030_CLK_CLMM_DEB_CLK 635
+#define WIN2030_CLK_DDR_PLL_BYP_CLK 636
+#define WIN2030_CLK_DDR_PLL_REF_AND_DFI_CLK 637
+#define WIN2030_CLK_DDR_RX_TEST_CLK 638
+#define WIN2030_CLK_MAILBOX_0 638
+#define WIN2030_CLK_MAILBOX_1 639
+#define WIN2030_CLK_MAILBOX_2 640
+#define WIN2030_CLK_MAILBOX_3 641
+#define WIN2030_CLK_MAILBOX_4 642
+#define WIN2030_CLK_MAILBOX_5 643
+#define WIN2030_CLK_MAILBOX_6 644
+#define WIN2030_CLK_MAILBOX_7 645
+#define WIN2030_CLK_MAILBOX_8 646
+#define WIN2030_CLK_MAILBOX_9 647
+#define WIN2030_CLK_MAILBOX_10 648
+#define WIN2030_CLK_MAILBOX_11 649
+#define WIN2030_CLK_MAILBOX_12 650
+#define WIN2030_CLK_MAILBOX_13 651
+#define WIN2030_CLK_MAILBOX_14 652
+#define WIN2030_CLK_MAILBOX_15 653
+#define WIN2030_CLK_LSP_I2C0_PCLK 654
+#define WIN2030_CLK_LSP_I2C1_PCLK 655
+#define WIN2030_CLK_LSP_I2C2_PCLK 656
+#define WIN2030_CLK_LSP_I2C3_PCLK 657
+#define WIN2030_CLK_LSP_I2C4_PCLK 658
+#define WIN2030_CLK_LSP_I2C5_PCLK 659
+#define WIN2030_CLK_LSP_I2C6_PCLK 660
+#define WIN2030_CLK_LSP_I2C7_PCLK 661
+#define WIN2030_CLK_LSP_I2C8_PCLK 662
+#define WIN2030_CLK_LSP_I2C9_PCLK 663
+#define WIN2030_CLK_LSP_WDT0_PCLK 664
+#define WIN2030_CLK_LSP_WDT1_PCLK 665
+#define WIN2030_CLK_LSP_WDT2_PCLK 666
+#define WIN2030_CLK_LSP_WDT3_PCLK 667
+#define WIN2030_CLK_LSP_SSI0_PCLK 668
+#define WIN2030_CLK_LSP_SSI1_PCLK 669
+#define WIN2030_CLK_LSP_PVT_PCLK 670
+#define WIN2030_CLK_AON_I2C0_PCLK 671
+#define WIN2030_CLK_AON_I2C1_PCLK 672
+#define WIN2030_CLK_LSP_UART0_PCLK 673
+#define WIN2030_CLK_LSP_UART1_PCLK 674
+#define WIN2030_CLK_LSP_UART2_PCLK 675
+#define WIN2030_CLK_LSP_UART3_PCLK 676
+#define WIN2030_CLK_LSP_UART4_PCLK 677
+#define WIN2030_CLK_LSP_TIMER_PCLK 678 //LSP timer
+#define WIN2030_CLK_LSP_FAN_PCLK 679
+#define WIN2030_CLK_DSP_ACLK_0 680
+#define WIN2030_CLK_DSP_ACLK_1 681
+#define WIN2030_CLK_DSP_ACLK_2 682
+#define WIN2030_CLK_DSP_ACLK_3 683
+
+#define WIN2030_CLK_VC_JE_PCLK 685
+#define WIN2030_CLK_VC_JD_PCLK 686
+#define WIN2030_CLK_VC_VE_PCLK 687
+#define WIN2030_CLK_VC_VD_PCLK 688
+#define WIN2030_CLK_VC_MON_PCLK 689
+
+#define WIN2030_CLK_HSP_DMA0_CLK 690
+
+#define WIN2030_NR_CLKS 700
+
+/* run frquency */
+#define CLK_FREQ_1800M 1800000000
+#define CLK_FREQ_1700M 1700000000
+#define CLK_FREQ_1600M 1600000000
+#define CLK_FREQ_1500M 1500000000
+#define CLK_FREQ_1400M 1400000000
+#define CLK_FREQ_1300M 1300000000
+#define CLK_FREQ_1200M 1200000000
+#define CLK_FREQ_1000M 1000000000
+#define CLK_FREQ_900M 900000000
+#define CLK_FREQ_800M 800000000
+#define CLK_FREQ_700M 700000000
+#define CLK_FREQ_600M 600000000
+#define CLK_FREQ_500M 500000000
+#define CLK_FREQ_400M 400000000
+#define CLK_FREQ_200M 200000000
+#define CLK_FREQ_100M 100000000
+#define CLK_FREQ_24M 24000000
+
+#define APLL_HIGH_FREQ 983040000
+#define APLL_LOW_FREQ 225792000
+
+#endif /*endif __DTS_WIN2030_CLOCK_H*/
diff --git a/include/dt-bindings/interconnect/eswin,win2030.h b/include/dt-bindings/interconnect/eswin,win2030.h
new file mode 100644
index 000000000000..9e44657848c9
--- /dev/null
+++ b/include/dt-bindings/interconnect/eswin,win2030.h
@@ -0,0 +1,160 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Interconnect driver for Eswin Win2030 SoC
+ *
+ * Copyright (C) 2022 Beiing Eswin Co. Ltd
+ * Author: Huangyifeng <huangyifeng@eswincomputing.com>
+ */
+
+#ifndef _DT_BINDINGS_INTERCONNECT_ESWIN_WIN2030_H_
+#define _DT_BINDINGS_INTERCONNECT_ESWIN_WIN2030_H_
+
+#define OFFSET0 (0)
+#define OFFSET1 (1)
+#define OFFSET2 (2)
+#define OFFSET3 (3)
+#define OFFSET4 (4)
+#define OFFSET5 (5)
+#define OFFSET6 (6)
+#define OFFSET7 (7)
+#define OFFSET8 (8)
+#define OFFSET9 (9)
+#define OFFSET10 (10)
+#define OFFSET11 (11)
+#define OFFSET12 (12)
+#define OFFSET13 (13)
+#define OFFSET14 (14)
+#define OFFSET15 (15)
+#define OFFSET16 (16)
+#define OFFSET17 (17)
+#define OFFSET18 (18)
+#define OFFSET19 (19)
+#define OFFSET20 (20)
+#define OFFSET21 (21)
+#define OFFSET22 (22)
+#define OFFSET23 (23)
+
+#define OFFSET31 (31)
+
+/*sideband manager module id defination*/
+/*sys noc*/
+#define SBM_AON_SNOC_SP0 0
+#define SBM_DSPT_SNOC 1
+#define SBM_JTAG_SNOC 2
+#define SBM_MCPUT_SNOC_D2D 3
+#define SBM_MCPUT_SNOC_MP 4
+#define SBM_MCPUT_SNOC_SP0 5
+#define SBM_MCPUT_SNOC_SP1 6
+#define SBM_NPU_SNOC_SP0 7
+#define SBM_NPU_SNOC_SP1 8
+#define SBM_PCIET_SNOC_P 9
+#define SBM_SPISLV_PCIET_SNOC 10
+#define SBM_TBU4_SNOC 11
+#define SBM_TCU_SNOC 12
+#define SBM_SNOC_AON 13
+#define SBM_SNOC_DDR0_P1 14
+#define SBM_SNOC_DDR0_P2 15
+#define SBM_SNOC_DDR1_P1 16
+#define SBM_SNOC_DDR1_P2 17
+#define SBM_SNOC_DSPT 18
+#define SBM_SNOC_MCPUT_D2D 19
+#define SBM_SNOC_NPU 20
+#define SBM_SNOC_PCIET 21
+
+/*cfg noc*/
+#define SBM_CLMM 30
+#define SBM_CNOC_AON 31
+#define SBM_CNOC_DDRT0_CTRL 32
+#define SBM_CNOC_DDRT0_PHY 33
+#define SBM_CNOC_DDRT1_CTRL 34
+#define SBM_CNOC_DDRT1_PHY 35
+#define SBM_CNOC_DSPT 36
+#define SBM_CNOC_GPU 37
+#define SBM_CNOC_HSP 38
+#define SBM_CNOC_LSP_APB2 39
+#define SBM_CNOC_LSP_APB3 40
+#define SBM_CNOC_LSP_APB4 41
+#define SBM_CNOC_LSP_APB6 42
+#define SBM_CNOC_MCPUT_D2D 43
+#define SBM_CNOC_NPU 44
+#define SBM_CNOC_PCIET_P 45
+#define SBM_CNOC_PCIET_X 46
+#define SBM_CNOC_TCU 47
+#define SBM_CNOC_VC 48
+#define SBM_CNOC_VI 49
+#define SBM_CNOC_VO 50
+
+/*llc noc*/
+#define SBM_LNOC_NPU_LLC0 60
+#define SBM_LNOC_NPU_LLC1 61
+#define SBM_LNOC_DDRT0_P0 62
+#define SBM_LNOC_DDRT1_P0 63
+
+/*media noc*/
+#define SBM_MNOC_GPU 70
+#define SBM_MNOC_TBU2 71
+#define SBM_MNOC_VC 72
+#define SBM_MNOC_DDRT0_P3 73
+#define SBM_MNOC_DDRT1_P3 74
+
+/*realtime noc*/
+#define SBM_RNOC_TBU0 80
+#define SBM_RNOC_VO 81
+#define SBM_RNOC_DDRT0_P4 82
+#define SBM_RNOC_DDRT1_P4 83
+
+/*RouteID defination*/
+#ifdef PLATFORM_HAPS
+#define aon_snoc_sp0_I_O 0x0
+#define dspt_snoc_I_O 0x1
+#define fpga_snoc_I_O 0x2
+#define jtag_snoc_I_O 0x3
+#define mcput_snoc_d2d_I_O 0x4
+#define mcput_snoc_mp_I_O 0x5
+#define mcput_snoc_sp0_I_O 0x6
+#define mcput_snoc_sp1_I_O 0x7
+#define mnoc_snoc_I_O 0x8
+#define npu_snoc_sp0_I_O 0x9
+#define npu_snoc_sp1_I_O 0xA
+#define pciet_snoc_p_I_O 0xB
+#define rnoc_snoc_I_O 0xC
+#define spislv_tbu3_snoc_I_O 0xD
+#define tbu4_snoc_I_O 0xE
+#define tcu_snoc_I_O 0xF
+#else
+#define aon_snoc_sp0_I_O 0x0
+#define dspt_snoc_I_O 0x1
+#define jtag_snoc_I_O 0x2
+#define mcput_snoc_d2d_I_O 0x3
+#define mcput_snoc_mp_I_O 0x4
+#define mcput_snoc_sp0_I_O 0x5
+#define mcput_snoc_sp1_I_O 0x6
+#define mnoc_snoc_I_O 0x7
+#define npu_snoc_sp0_I_O 0x8
+#define npu_snoc_sp1_I_O 0x9
+#define pciet_snoc_p_I_O 0xA
+#define rnoc_snoc_I_O 0xB
+#define spislv_tbu3_snoc_I_O 0xC
+#define tbu4_snoc_I_O 0xD
+#define tcu_snoc_I_O 0xE
+#define RESERVED0 0xF
+#endif
+
+#define snoc_aon_T_O 0x0
+#define snoc_cnoc_T_O 0x1
+#define snoc_ddrt0_p1_T_O 0x2
+#define snoc_ddrt0_p2_T_O 0x3
+#define snoc_ddrt1_p1_T_O 0x4
+#define snoc_ddrt1_p2_T_O 0x5
+#define snoc_dspt_T_O 0x6
+#define snoc_lnoc_T_O 0x7
+#define snoc_mcput_d2d_T_O 0x8
+#define snoc_mnoc_T_O 0x9
+#define snoc_npu_T_O 0xA
+#define snoc_pciet_T_O 0xB
+#define snoc_rnoc_T_O 0xC
+#define snoc_service_T_O 0xD
+#define RESERVED1 0xE
+#define RESERVED2 0xF
+
+#endif /* _DT_BINDINGS_INTERCONNECT_ESWIN_WIN2030_H_ */
diff --git a/include/dt-bindings/mailbox/eswin-mailbox.h b/include/dt-bindings/mailbox/eswin-mailbox.h
new file mode 100755
index 000000000000..1c82418dbadc
--- /dev/null
+++ b/include/dt-bindings/mailbox/eswin-mailbox.h
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ESWIN Mailbox Driver
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Authors: HuangYiFeng<huangyifeng@eswincomputing.com>
+ */
+
+#ifndef _DTS_ESWIN_MAILBOX_H_
+#define _DTS_ESWIN_MAILBOX_H_
+
+#define ESWIN_MAILBOX_U84_TO_SCPU_REG_BASE 0x50a00000 /*maibox 0*/
+#define ESWIN_MAILBOX_SCPU_TO_U84_REG_BASE 0x50a10000 /*maibox 1*/
+
+#define ESWIN_MAILBOX_U84_TO_LPCPU_REG_BASE 0x50a20000 /*maibox 2*/
+#define ESWIN_MAILBOX_LPCPU_TO_U84_REG_BASE 0x50a30000 /*maibox 3*/
+
+#define ESWIN_MAILBOX_U84_TO_NPU_0_REG_BASE 0x50a40000 /*maibox 4*/
+#define ESWIN_MAILBOX_NPU_0_TO_U84_REG_BASE 0x50a50000 /*maibox 5*/
+
+#define ESWIN_MAILBOX_U84_TO_NPU_1_REG_BASE 0x50a60000 /*maibox 6*/
+#define ESWIN_MAILBOX_NP1_0_TO_U84_REG_BASE 0x50a70000 /*maibox 7*/
+
+#define ESWIN_MAILBOX_U84_TO_DSP_0_REG_BASE 0x50a80000 /*maibox 8*/
+#define ESWIN_MAILBOX_DSP_0_TO_U84_REG_BASE 0x50a90000 /*maibox 9*/
+
+#define ESWIN_MAILBOX_U84_TO_DSP_1_REG_BASE 0x50aa0000 /*maibox 10*/
+#define ESWIN_MAILBOX_DSP_1_TO_U84_REG_BASE 0x50ab0000 /*maibox 11*/
+
+#define ESWIN_MAILBOX_U84_TO_DSP_2_REG_BASE 0x50ac0000 /*maibox 12*/
+#define ESWIN_MAILBOX_DSP_2_TO_U84_REG_BASE 0x50ad0000 /*maibox 13*/
+
+#define ESWIN_MAILBOX_U84_TO_DSP_3_REG_BASE 0x50ae0000 /*maibox 14*/
+#define ESWIN_MAILBOX_DSP_3_TO_U84_REG_BASE 0x50af0000 /*maibox 15*/
+
+#define BIT0 (1 << 0)
+#define BIT1 (1 << 1)
+#define BIT2 (1 << 2)
+#define BIT3 (1 << 3)
+#define BIT4 (1 << 4)
+#define BIT5 (1 << 5)
+#define BIT6 (1 << 6)
+#define BIT7 (1 << 7)
+#define BIT8 (1 << 8)
+#define BIT9 (1 << 9)
+#define BIT10 (1 << 10)
+#define BIT11 (1 << 11)
+#define BIT12 (1 << 12)
+#define BIT13 (1 << 13)
+#define BIT14 (1 << 14)
+#define BIT31 (1 << 31)
+
+#define ESWIN_MAILBOX_WR_LOCK_BIT_U84 BIT0
+#define ESWIN_MAILBOX_WR_LOCK_BIT_SCPU BIT1
+#define ESWIN_MAILBOX_WR_LOCK_BIT_LPCPU BIT2
+#define ESWIN_MAILBOX_WR_LOCK_BIT_NPU_0 BIT3
+#define ESWIN_MAILBOX_WR_LOCK_BIT_NPU_1 BIT4
+#define ESWIN_MAILBOX_WR_LOCK_BIT_DSP_0 BIT5
+#define ESWIN_MAILBOX_WR_LOCK_BIT_DSP_1 BIT6
+#define ESWIN_MAILBOX_WR_LOCK_BIT_DSP_2 BIT7
+#define ESWIN_MAILBOX_WR_LOCK_BIT_DSP_3 BIT8
+
+
+#define ESWIN_MAIBOX_U84_IRQ_BIT BIT0
+#define ESWIN_MAIBOX_SCPU_IRQ_BIT BIT1
+#define ESWIN_MAIBOX_LPCPU_IRQ_BIT BIT2
+#define ESWIN_MAIBOX_NPU_0_IRQ_BIT BIT3
+#define ESWIN_MAIBOX_NPU_1_IRQ_BIT BIT4
+#define ESWIN_MAIBOX_DSP_0_IRQ_BIT BIT5
+#define ESWIN_MAIBOX_DSP_1_IRQ_BIT BIT6
+#define ESWIN_MAIBOX_DSP_2_IRQ_BIT BIT7
+#define ESWIN_MAIBOX_DSP_3_IRQ_BIT BIT8
+
+#endif /* _DTS_ESWIN_MAILBOX_H_ */
diff --git a/include/dt-bindings/memory/eswin-win2030-sid.h b/include/dt-bindings/memory/eswin-win2030-sid.h
new file mode 100644
index 000000000000..df2e20cdfb01
--- /dev/null
+++ b/include/dt-bindings/memory/eswin-win2030-sid.h
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * For Eswin EIC7700 SoC, define Stream ID of the devices to identify devices by SMMU, and TBU ID of the devices.
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#ifndef DT_BINDINGS_MEMORY_WIN2030_SID_H
+#define DT_BINDINGS_MEMORY_WIN2030_SID_H
+
+#define WIN2030_SID_DMA0 1
+
+#define WIN2030_SID_JDEC 2
+
+#define WIN2030_SID_JENC 3
+
+/* NPU DMA*/
+#define WIN2030_SID_NPU_DMA 4
+
+/* NPU-E31 */
+#define WIN2030_SID_NPU_E31 5
+
+/* Video In */
+#define WIN2030_SID_ISP0 6
+
+#define WIN2030_SID_ISP1 WIN2030_SID_ISP0
+
+#define WIN2030_SID_DW 8
+
+#define WIN2030_SID_DVP 9
+
+/* High Speed */
+#define WIN2030_SID_USB0 10
+
+#define WIN2030_SID_USB1 11
+
+#define WIN2030_SID_ETH0 12
+
+#define WIN2030_SID_ETH1 13
+
+#define WIN2030_SID_SATA 14
+
+#define WIN2030_SID_EMMC0 15
+
+#define WIN2030_SID_SD0 16
+
+#define WIN2030_SID_SD1 17
+
+
+/* DSP */
+#define WIN2030_SID_DSP_0 18
+#define WIN2030_SID_DSP_1 19
+#define WIN2030_SID_DSP_2 20
+#define WIN2030_SID_DSP_3 21
+
+/* CODEC */
+#define WIN2030_SID_VDEC WIN2030_SID_JDEC
+
+#define WIN2030_SID_VENC WIN2030_SID_JENC
+
+/*** AON subsystem ***/
+/* Secure CPU */
+#define WIN2030_SID_SCPU 24
+#define SCPU_SID_REG_OFFSET 0x1004
+
+/* Low power CPU */
+#define WIN2030_SID_LCPU 25
+#define LCPU_SID_REG_OFFSET 0x2004
+
+/* Always on, DMA1 */
+#define WIN2030_SID_DMA1 26
+#define DMA1_SID_REG_OFFSET 0x3004
+
+/* crypt */
+#define WIN2030_SID_CRYPT WIN2030_SID_SCPU
+#define CRYPT_SID_REG_OFFSET 0x4004
+
+/*** for iova mapping test ***/
+#define WIN2030_SID_DEV_FOO_A 28
+#define WIN2030_SID_DEV_FOO_B 29
+#define WIN2030_SID_DEV_FOO_FOR_DIE1 30
+
+
+/*** tbu id ***/
+/* tbu_id: bit[3:0] is for major, bit[7:4] is for minor;
+ For example, tbu of dsp3 is tbu7_3, the bu 0x73. It measn tbu7_3
+*/
+#define WIN2030_TBUID_0x0 0x0
+
+#define WIN2030_TBUID_0x10 0x10
+#define WIN2030_TBUID_0x11 0x11
+#define WIN2030_TBUID_0x12 0x12
+#define WIN2030_TBUID_0x13 0x13
+
+#define WIN2030_TBUID_0x2 0x2
+
+#define WIN2030_TBUID_0x3 0x3
+
+#define WIN2030_TBUID_0x4 0x4
+
+#define WIN2030_TBUID_0x5 0x5
+
+#define WIN2030_TBUID_0x70 0x70
+#define WIN2030_TBUID_0x71 0x71
+#define WIN2030_TBUID_0x72 0x72
+#define WIN2030_TBUID_0x73 0x73
+
+#define WIN2030_TBUID_0xF00 0xF00 // simulation for WIN2030_SID_DEV_FOO_A/B, No real tbu attached infact
+
+
+/* For better use by devices in dts, create tbu alias for devices*/
+#define WIN2030_TBUID_ISP WIN2030_TBUID_0x0
+#define WIN2030_TBUID_DW WIN2030_TBUID_ISP
+
+#define WIN2030_TBUID_VDEC WIN2030_TBUID_0x10
+#define WIN2030_TBUID_VENC WIN2030_TBUID_0x11
+#define WIN2030_TBUID_JENC WIN2030_TBUID_0x12
+#define WIN2030_TBUID_JDEC WIN2030_TBUID_0x13
+
+//high speed modules share the same tbu2
+#define WIN2030_TBUID_DMA0 WIN2030_TBUID_0x2
+#define WIN2030_TBUID_USB WIN2030_TBUID_DMA0
+#define WIN2030_TBUID_ETH WIN2030_TBUID_DMA0
+#define WIN2030_TBUID_SATA WIN2030_TBUID_DMA0
+#define WIN2030_TBUID_EMMC WIN2030_TBUID_DMA0
+#define WIN2030_TBUID_SD WIN2030_TBUID_DMA0
+
+#define WIN2030_TBUID_PCIE WIN2030_TBUID_0x3
+
+//scpu, crypto, lpcpu, dma1 share the same tbu4
+#define WIN2030_TBUID_SCPU WIN2030_TBUID_0x4
+#define WIN2030_TBUID_CRYPT WIN2030_TBUID_SCPU
+#define WIN2030_TBUID_DMA1 WIN2030_TBUID_SCPU
+#define WIN2030_TBUID_LPCPU WIN2030_TBUID_SCPU
+
+//npu
+#define WIN2030_TBUID_NPU WIN2030_TBUID_0x5
+
+//dsp
+#define WIN2030_TBUID_DSP0 WIN2030_TBUID_0x70
+#define WIN2030_TBUID_DSP1 WIN2030_TBUID_0x71
+#define WIN2030_TBUID_DSP2 WIN2030_TBUID_0x72
+#define WIN2030_TBUID_DSP3 WIN2030_TBUID_0x73
+
+
+
+
+
+
+
+#endif
diff --git a/include/dt-bindings/reset/eswin,win2030-syscrg.h b/include/dt-bindings/reset/eswin,win2030-syscrg.h
new file mode 100755
index 000000000000..3c27a51c18ae
--- /dev/null
+++ b/include/dt-bindings/reset/eswin,win2030-syscrg.h
@@ -0,0 +1,693 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ESWIN SysCrg Definition
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Authors: HuangYiFeng<huangyifeng@eswincomputing.com>
+ */
+
+#ifndef __DT_ESWIN_WIN2030_SYSCRG_H__
+#define __DT_ESWIN_WIN2030_SYSCRG_H__
+
+/*REG OFFSET OF SYS-CRG*/
+
+#define WIN2030_REG_OFFSET_SPLL0_CFG_0 0X0000
+#define WIN2030_REG_OFFSET_SPLL0_CFG_1 0X0004
+#define WIN2030_REG_OFFSET_SPLL0_CFG_2 0X0008
+#define WIN2030_REG_OFFSET_SPLL0_DSKEWCAL 0X000C
+#define WIN2030_REG_OFFSET_SPLL0_SSC 0X0010
+#define WIN2030_REG_OFFSET_SPLL1_CFG_0 0X0014
+#define WIN2030_REG_OFFSET_SPLL1_CFG_1 0X0018
+#define WIN2030_REG_OFFSET_SPLL1_CFG_2 0X001C
+#define WIN2030_REG_OFFSET_SPLL1_DSKEWCAL 0X0020
+#define WIN2030_REG_OFFSET_SPLL1_SSC 0X0024
+#define WIN2030_REG_OFFSET_SPLL2_CFG_0 0X0028
+#define WIN2030_REG_OFFSET_SPLL2_CFG_1 0X002C
+#define WIN2030_REG_OFFSET_SPLL2_CFG_2 0X0030
+#define WIN2030_REG_OFFSET_SPLL2_DSKEWCAL 0X0034
+#define WIN2030_REG_OFFSET_SPLL2_SSC 0X0038
+#define WIN2030_REG_OFFSET_VPLL_CFG_0 0X003C
+#define WIN2030_REG_OFFSET_VPLL_CFG_1 0X0040
+#define WIN2030_REG_OFFSET_VPLL_CFG_2 0X0044
+#define WIN2030_REG_OFFSET_VPLL_DSKEWCAL 0X0048
+#define WIN2030_REG_OFFSET_VPLL_SSC 0X004C
+#define WIN2030_REG_OFFSET_APLL_CFG_0 0X0050
+#define WIN2030_REG_OFFSET_APLL_CFG_1 0X0054
+#define WIN2030_REG_OFFSET_APLL_CFG_2 0X0058
+#define WIN2030_REG_OFFSET_APLL_DSKEWCAL 0X005C
+#define WIN2030_REG_OFFSET_APLL_SSC 0X0060
+#define WIN2030_REG_OFFSET_MCPUT_PLL_CFG_0 0X0064
+#define WIN2030_REG_OFFSET_MCPUT_PLL_CFG_1 0X0068
+#define WIN2030_REG_OFFSET_MCPUT_PLL_CFG_2 0X006C
+#define WIN2030_REG_OFFSET_MCPUT_PLL_DSKEWCAL 0X0070
+#define WIN2030_REG_OFFSET_MCPUT_PLL_SSC 0X0074
+#define WIN2030_REG_OFFSET_DDRT_PLL_CFG_0 0X0078
+#define WIN2030_REG_OFFSET_DDRT_PLL_CFG_1 0X007C
+#define WIN2030_REG_OFFSET_DDRT_PLL_CFG_2 0X0080
+#define WIN2030_REG_OFFSET_DDRT_PLL_DSKEWCAL 0X0084
+#define WIN2030_REG_OFFSET_DDRT_PLL_SSC 0X0088
+#define WIN2030_REG_OFFSET_PLL_STATUS 0X00A4
+#define WIN2030_REG_OFFSET_NOC_CLK_CTRL 0X100
+#define WIN2030_REG_OFFSET_BOOTSPI_CLK_CTRL 0X104
+#define WIN2030_REG_OFFSET_BOOTSPI_CFGCLK_CTRL 0X108
+#define WIN2030_REG_OFFSET_SCPU_CORECLK_CTRL 0X10C
+#define WIN2030_REG_OFFSET_SCPU_BUSCLK_CTRL 0X110
+#define WIN2030_REG_OFFSET_LPCPU_CORECLK_CTRL 0X114
+#define WIN2030_REG_OFFSET_LPCPU_BUSCLK_CTRL 0X118
+#define WIN2030_REG_OFFSET_TCU_ACLK_CTRL 0X11C
+#define WIN2030_REG_OFFSET_TCU_CFG_CTRL 0X120
+#define WIN2030_REG_OFFSET_DDR_CLK_CTRL 0X124
+#define WIN2030_REG_OFFSET_DDR1_CLK_CTRL 0X128
+#define WIN2030_REG_OFFSET_GPU_ACLK_CTRL 0X12C
+#define WIN2030_REG_OFFSET_GPU_CFG_CTRL 0X130
+#define WIN2030_REG_OFFSET_GPU_GRAY_CTRL 0X134
+#define WIN2030_REG_OFFSET_DSP_ACLK_CTRL 0X138
+#define WIN2030_REG_OFFSET_DSP_CFG_CTRL 0X13C
+#define WIN2030_REG_OFFSET_D2D_ACLK_CTRL 0X140
+#define WIN2030_REG_OFFSET_D2D_CFG_CTRL 0X144
+#define WIN2030_REG_OFFSET_HSP_ACLK_CTRL 0X148
+#define WIN2030_REG_OFFSET_HSP_CFG_CTRL 0X14C
+#define WIN2030_REG_OFFSET_SATA_RBC_CTRL 0X150
+#define WIN2030_REG_OFFSET_SATA_OOB_CTRL 0X154
+#define WIN2030_REG_OFFSET_ETH0_CTRL 0X158
+#define WIN2030_REG_OFFSET_ETH1_CTRL 0X15C
+#define WIN2030_REG_OFFSET_MSHC0_CORECLK_CTRL 0X160
+#define WIN2030_REG_OFFSET_MSHC1_CORECLK_CTRL 0X164
+#define WIN2030_REG_OFFSET_MSHC2_CORECLK_CTRL 0X168
+#define WIN2030_REG_OFFSET_MSHC_USB_SLWCLK 0X16C
+#define WIN2030_REG_OFFSET_PCIE_ACLK_CTRL 0X170
+#define WIN2030_REG_OFFSET_PCIE_CFG_CTRL 0X174
+#define WIN2030_REG_OFFSET_NPU_ACLK_CTRL 0X178
+#define WIN2030_REG_OFFSET_NPU_LLC_CTRL 0X17C
+#define WIN2030_REG_OFFSET_NPU_CORE_CTRL 0X180
+#define WIN2030_REG_OFFSET_VI_DWCLK_CTRL 0X184
+#define WIN2030_REG_OFFSET_VI_ACLK_CTRL 0X188
+#define WIN2030_REG_OFFSET_VI_DIG_ISP_CLK_CTRL 0X18C
+#define WIN2030_REG_OFFSET_VI_DVP_CLK_CTRL 0X190
+#define WIN2030_REG_OFFSET_VI_SHUTTER0 0X194
+#define WIN2030_REG_OFFSET_VI_SHUTTER1 0X198
+#define WIN2030_REG_OFFSET_VI_SHUTTER2 0X19C
+#define WIN2030_REG_OFFSET_VI_SHUTTER3 0X1A0
+#define WIN2030_REG_OFFSET_VI_SHUTTER4 0X1A4
+#define WIN2030_REG_OFFSET_VI_SHUTTER5 0X1A8
+#define WIN2030_REG_OFFSET_VI_PHY_CLKCTRL 0X1AC
+#define WIN2030_REG_OFFSET_VO_ACLK_CTRL 0X1B0
+#define WIN2030_REG_OFFSET_VO_IESMCLK_CTRL 0X1B4
+#define WIN2030_REG_OFFSET_VO_PIXEL_CTRL 0X1B8
+#define WIN2030_REG_OFFSET_VO_MCLK_CTRL 0X1BC
+#define WIN2030_REG_OFFSET_VO_PHY_CLKCTRL 0X1C0
+#define WIN2030_REG_OFFSET_VC_ACLK_CTRL 0X1C4
+#define WIN2030_REG_OFFSET_VCDEC_ROOTCLK_CTRL 0X1C8
+#define WIN2030_REG_OFFSET_G2D_CTRL 0X1CC
+#define WIN2030_REG_OFFSET_VC_CLKEN_CTRL 0X1D0
+#define WIN2030_REG_OFFSET_JE_CLK_CTRL 0X1D4
+#define WIN2030_REG_OFFSET_JD_CLK_CTRL 0X1D8
+#define WIN2030_REG_OFFSET_VD_CLK_CTRL 0X1DC
+#define WIN2030_REG_OFFSET_VE_CLK_CTRL 0X1E0
+#define WIN2030_REG_OFFSET_AON_DMA_CLK_CTRL 0X1E4
+#define WIN2030_REG_OFFSET_TIMER_CLK_CTRL 0X1E8
+#define WIN2030_REG_OFFSET_RTC_CLK_CTRL 0X1EC
+#define WIN2030_REG_OFFSET_PKA_CLK_CTRL 0X1F0
+#define WIN2030_REG_OFFSET_SPACC_CLK_CTRL 0X1F4
+#define WIN2030_REG_OFFSET_TRNG_CLK_CTRL 0X1F8
+#define WIN2030_REG_OFFSET_OTP_CLK_CTRL 0X1FC
+#define WIN2030_REG_OFFSET_LSP_CLK_EN0 0X200
+#define WIN2030_REG_OFFSET_LSP_CLK_EN1 0X204
+#define WIN2030_REG_OFFSET_U84_CLK_CTRL 0X208
+#define WIN2030_REG_OFFSET_SYSCFG_CLK_CTRL 0X20C
+#define WIN2030_REG_OFFSET_I2C0_CLK_CTRL 0X210
+#define WIN2030_REG_OFFSET_I2C1_CLK_CTRL 0X214
+#define WIN2030_REG_OFFSET_DFT_CLK_CTRL 0X280
+#define WIN2030_REG_OFFSET_SYS_SWRST_VALUE 0X300
+#define WIN2030_REG_OFFSET_CLR_RST_STATUS 0X304
+#define WIN2030_REG_OFFSET_DIE_STATUS 0X308
+#define WIN2030_REG_OFFSET_CLR_BOOT_INFO 0X30C
+#define WIN2030_REG_OFFSET_SCPU_BOOT_ADDRESS 0X310
+#define WIN2030_REG_OFFSET_LPCPU_BOOT_ADDRESS 0X314
+#define WIN2030_REG_OFFSET_NPUE31_BOOT_ADDRESS 0X318
+#define WIN2030_REG_OFFSET_U84_BOOT_ADDRESS0_HI 0X31C
+#define WIN2030_REG_OFFSET_U84_BOOT_ADDRESS0_LOW 0X320
+#define WIN2030_REG_OFFSET_U84_BOOT_ADDRESS1_HI 0X324
+#define WIN2030_REG_OFFSET_U84_BOOT_ADDRESS1_LOW 0X328
+#define WIN2030_REG_OFFSET_U84_BOOT_ADDRESS2_HI 0X32C
+#define WIN2030_REG_OFFSET_U84_BOOT_ADDRESS2_LOW 0X330
+#define WIN2030_REG_OFFSET_U84_BOOT_ADDRESS3_HI 0X334
+#define WIN2030_REG_OFFSET_U84_BOOT_ADDRESS3_LOW 0X338
+#define WIN2030_REG_OFFSET_BOOT_SEL_STAT 0X33C
+#define WIN2030_REG_OFFSET_BOOT_SPI_CFG 0X340
+#define WIN2030_REG_OFFSET_SNOC_RST_CTRL 0X400
+#define WIN2030_REG_OFFSET_GPU_RST_CTRL 0X404
+#define WIN2030_REG_OFFSET_DSP_RST_CTRL 0X408
+#define WIN2030_REG_OFFSET_D2D_RST_CTRL 0X40C
+#define WIN2030_REG_OFFSET_DDR_RST_CTRL 0X410
+#define WIN2030_REG_OFFSET_TCU_RST_CTRL 0X414
+#define WIN2030_REG_OFFSET_NPU_RST_CTRL 0X418
+#define WIN2030_REG_OFFSET_HSPDMA_RST_CTRL 0X41C
+#define WIN2030_REG_OFFSET_PCIE_RST_CTRL 0X420
+#define WIN2030_REG_OFFSET_I2C_RST_CTRL 0X424
+#define WIN2030_REG_OFFSET_FAN_RST_CTRL 0X428
+#define WIN2030_REG_OFFSET_PVT_RST_CTRL 0X42C
+#define WIN2030_REG_OFFSET_MBOX_RST_CTRL 0X430
+#define WIN2030_REG_OFFSET_UART_RST_CTRL 0X434
+#define WIN2030_REG_OFFSET_GPIO_RST_CTRL 0X438
+#define WIN2030_REG_OFFSET_TIMER_RST_CTRL 0X43C
+#define WIN2030_REG_OFFSET_SSI_RST_CTRL 0X440
+#define WIN2030_REG_OFFSET_WDT_RST_CTRL 0X444
+#define WIN2030_REG_OFFSET_LSP_CFGRST_CTRL 0X448
+#define WIN2030_REG_OFFSET_U84_RST_CTRL 0X44C
+#define WIN2030_REG_OFFSET_SCPU_RST_CTRL 0X450
+#define WIN2030_REG_OFFSET_LPCPU_RST_CTRL 0X454
+#define WIN2030_REG_OFFSET_VC_RST_CTRL 0X458
+#define WIN2030_REG_OFFSET_JD_RST_CTRL 0X45C
+#define WIN2030_REG_OFFSET_JE_RST_CTRL 0X460
+#define WIN2030_REG_OFFSET_VD_RST_CTRL 0X464
+#define WIN2030_REG_OFFSET_VE_RST_CTRL 0X468
+#define WIN2030_REG_OFFSET_G2D_RST_CTRL 0X46C
+#define WIN2030_REG_OFFSET_VI_RST_CTRL 0X470
+#define WIN2030_REG_OFFSET_DVP_RST_CTRL 0X474
+#define WIN2030_REG_OFFSET_ISP0_RST_CTRL 0X478
+#define WIN2030_REG_OFFSET_ISP1_RST_CTRL 0X47C
+#define WIN2030_REG_OFFSET_SHUTTER_RST_CTRL 0X480
+#define WIN2030_REG_OFFSET_VO_PHYRST_CTRL 0X484
+#define WIN2030_REG_OFFSET_VO_I2SRST_CTRL 0X488
+#define WIN2030_REG_OFFSET_VO_RST_CTRL 0X48C
+#define WIN2030_REG_OFFSET_BOOTSPI_RST_CTRL 0X490
+#define WIN2030_REG_OFFSET_I2C1_RST_CTRL 0X494
+#define WIN2030_REG_OFFSET_I2C0_RST_CTRL 0X498
+#define WIN2030_REG_OFFSET_DMA1_RST_CTRL 0X49C
+#define WIN2030_REG_OFFSET_FPRT_RST_CTRL 0X4A0
+#define WIN2030_REG_OFFSET_HBLOCK_RST_CTRL 0X4A4
+#define WIN2030_REG_OFFSET_SECSR_RST_CTRL 0X4A8
+#define WIN2030_REG_OFFSET_OTP_RST_CTRL 0X4AC
+#define WIN2030_REG_OFFSET_PKA_RST_CTRL 0X4B0
+#define WIN2030_REG_OFFSET_SPACC_RST_CTRL 0X4B4
+#define WIN2030_REG_OFFSET_TRNG_RST_CTRL 0X4B8
+#define WIN2030_REG_OFFSET_TIMER0_RST_CTRL 0X4C0
+#define WIN2030_REG_OFFSET_TIMER1_RST_CTRL 0X4C4
+#define WIN2030_REG_OFFSET_TIMER2_RST_CTRL 0X4C8
+#define WIN2030_REG_OFFSET_TIMER3_RST_CTRL 0X4CC
+#define WIN2030_REG_OFFSET_RTC_RST_CTRL 0X4D0
+#define WIN2030_REG_OFFSET_MNOC_RST_CTRL 0X4D4
+#define WIN2030_REG_OFFSET_RNOC_RST_CTRL 0X4D8
+#define WIN2030_REG_OFFSET_CNOC_RST_CTRL 0X4DC
+#define WIN2030_REG_OFFSET_LNOC_RST_CTRL 0X4E0
+
+/*
+ * RESET DEV ID FOR EACH RESET CONSUMER
+ *
+ */
+#define SNOC_RST_CTRL 0X00
+#define GPU_RST_CTRL 0X01
+#define DSP_RST_CTRL 0X02
+#define D2D_RST_CTRL 0X03
+#define DDR_RST_CTRL 0X04
+#define TCU_RST_CTRL 0X05
+#define NPU_RST_CTRL 0X06
+#define HSPDMA_RST_CTRL 0X07
+#define PCIE_RST_CTRL 0X08
+#define I2C_RST_CTRL 0X09
+#define FAN_RST_CTRL 0X0A
+#define PVT_RST_CTRL 0X0B
+#define MBOX_RST_CTRL 0X0C
+#define UART_RST_CTRL 0X0D
+#define GPIO_RST_CTRL 0X0E
+#define TIMER_RST_CTRL 0X0F
+#define SSI_RST_CTRL 0X10
+#define WDT_RST_CTRL 0X11
+#define LSP_CFGRST_CTRL 0X12
+#define U84_RST_CTRL 0X13
+#define SCPU_RST_CTRL 0X14
+#define LPCPU_RST_CTRL 0X15
+#define VC_RST_CTRL 0X16
+#define JD_RST_CTRL 0X17
+#define JE_RST_CTRL 0X18
+#define VD_RST_CTRL 0X19
+#define VE_RST_CTRL 0X1A
+#define G2D_RST_CTRL 0X1B
+#define VI_RST_CTRL 0X1C
+#define DVP_RST_CTRL 0X1D
+#define ISP0_RST_CTRL 0X1E
+#define ISP1_RST_CTRL 0X1F
+#define SHUTTER_RST_CTRL 0X20
+#define VO_PHYRST_CTRL 0X21
+#define VO_I2SRST_CTRL 0X22
+#define VO_RST_CTRL 0X23
+#define BOOTSPI_RST_CTRL 0X24
+#define I2C1_RST_CTRL 0X25
+#define I2C0_RST_CTRL 0X26
+#define DMA1_RST_CTRL 0X27
+#define FPRT_RST_CTRL 0X28
+#define HBLOCK_RST_CTRL 0X29
+#define SECSR_RST_CTRL 0X2A
+#define OTP_RST_CTRL 0X2B
+#define PKA_RST_CTRL 0X2C
+#define SPACC_RST_CTRL 0X2D
+#define TRNG_RST_CTRL 0X2E
+#define RESERVED 0X2F
+#define TIMER0_RST_CTRL 0X30
+#define TIMER1_RST_CTRL 0X31
+#define TIMER2_RST_CTRL 0X32
+#define TIMER3_RST_CTRL 0X33
+#define RTC_RST_CTRL 0X34
+#define MNOC_RST_CTRL 0X35
+#define RNOC_RST_CTRL 0X36
+#define CNOC_RST_CTRL 0X37
+#define LNOC_RST_CTRL 0X38
+
+#define BIT0 (1 << 0)
+#define BIT1 (1 << 1)
+#define BIT2 (1 << 2)
+#define BIT3 (1 << 3)
+#define BIT4 (1 << 4)
+#define BIT5 (1 << 5)
+#define BIT6 (1 << 6)
+#define BIT7 (1 << 7)
+#define BIT8 (1 << 8)
+#define BIT9 (1 << 9)
+#define BIT10 (1 << 10)
+#define BIT11 (1 << 11)
+#define BIT12 (1 << 12)
+#define BIT13 (1 << 13)
+#define BIT14 (1 << 14)
+#define BIT15 (1 << 15)
+#define BIT16 (1 << 16)
+#define BIT17 (1 << 17)
+#define BIT18 (1 << 18)
+#define BIT19 (1 << 19)
+#define BIT20 (1 << 20)
+#define BIT21 (1 << 21)
+#define BIT22 (1 << 22)
+#define BIT23 (1 << 23)
+#define BIT24 (1 << 24)
+#define BIT25 (1 << 25)
+#define BIT26 (1 << 26)
+#define BIT27 (1 << 27)
+#define BIT28 (1 << 28)
+#define BIT29 (1 << 29)
+#define BIT30 (1 << 30)
+#define BIT31 (1 << 31)
+
+/*
+ CONSUMER RESET CONTROL BIT
+*/
+/*SNOC*/
+#define SW_NOC_NSP_RSTN BIT0
+#define SW_NOC_CFG_RSTN BIT1
+#define SW_RNOC_NSP_RSTN BIT2
+#define SW_SNOC_TCU_ARSTN BIT3
+#define SW_SNOC_U84_ARSTN BIT4
+#define SW_SNOC_PCIET_XSRSTN BIT5
+#define SW_SNOC_PCIET_XMRSTN BIT6
+#define SW_SNOC_PCIET_PRSTN BIT7
+#define SW_SNOC_NPU_ARSTN BIT8
+#define SW_SNOC_JTAG_ARSTN BIT9
+#define SW_SNOC_DSPT_ARSTN BIT10
+#define SW_SNOC_DDRC1_P2_ARSTN BIT11
+#define SW_SNOC_DDRC1_P1_ARSTN BIT12
+#define SW_SNOC_DDRC0_P2_ARSTN BIT13
+#define SW_SNOC_DDRC0_P1_ARSTN BIT14
+#define SW_SNOC_D2D_ARSTN BIT15
+#define SW_SNOC_AON_ARSTN BIT16
+
+/*GPU*/
+#define SW_GPU_AXI_RSTN BIT0
+#define SW_GPU_CFG_RSTN BIT1
+#define SW_GPU_GRAY_RSTN BIT2
+#define SW_GPU_JONES_RSTN BIT3
+#define SW_GPU_SPU_RSTN BIT4
+
+/*DSP*/
+#define SW_DSP_AXI_RSTN BIT0
+#define SW_DSP_CFG_RSTN BIT1
+#define SW_DSP_DIV4_RSTN BIT2
+#define SW_DSP_DIV_RSTN_0 BIT4
+#define SW_DSP_DIV_RSTN_1 BIT5
+#define SW_DSP_DIV_RSTN_2 BIT6
+#define SW_DSP_DIV_RSTN_3 BIT7
+
+/*D2D*/
+#define SW_D2D_AXI_RSTN BIT0
+#define SW_D2D_CFG_RSTN BIT1
+#define SW_D2D_PRST_N BIT2
+#define SW_D2D_RAW_PCS_RST_N BIT4
+#define SW_D2D_RX_RST_N BIT5
+#define SW_D2D_TX_RST_N BIT6
+#define SW_D2D_CORE_RST_N BIT7
+
+/*TCU*/
+#define SW_TCU_AXI_RSTN BIT0
+#define SW_TCU_CFG_RSTN BIT1
+#define TBU_RSTN_0 BIT4
+#define TBU_RSTN_1 BIT5
+#define TBU_RSTN_2 BIT6
+#define TBU_RSTN_3 BIT7
+#define TBU_RSTN_4 BIT8
+#define TBU_RSTN_5 BIT9
+#define TBU_RSTN_6 BIT10
+#define TBU_RSTN_7 BIT11
+#define TBU_RSTN_8 BIT12
+#define TBU_RSTN_9 BIT13
+#define TBU_RSTN_10 BIT14
+#define TBU_RSTN_11 BIT15
+#define TBU_RSTN_12 BIT16
+#define TBU_RSTN_13 BIT17
+#define TBU_RSTN_14 BIT18
+#define TBU_RSTN_15 BIT19
+#define TBU_RSTN_16 BIT20
+
+/*NPU*/
+#define SW_NPU_AXI_RSTN BIT0
+#define SW_NPU_CFG_RSTN BIT1
+#define SW_NPU_CORE_RSTN BIT2
+#define SW_NPU_E31CORE_RSTN BIT3
+#define SW_NPU_E31BUS_RSTN BIT4
+#define SW_NPU_E31DBG_RSTN BIT5
+#define SW_NPU_LLC_RSTN BIT6
+
+/*HSP DMA*/
+#define SW_HSP_AXI_RSTN BIT0
+#define SW_HSP_CFG_RSTN BIT1
+#define SW_HSP_POR_RSTN BIT2
+#define SW_MSHC0_PHY_RSTN BIT3
+#define SW_MSHC1_PHY_RSTN BIT4
+#define SW_MSHC2_PHY_RSTN BIT5
+#define SW_MSHC0_TXRX_RSTN BIT6
+#define SW_MSHC1_TXRX_RSTN BIT7
+#define SW_MSHC2_TXRX_RSTN BIT8
+#define SW_SATA_ASIC0_RSTN BIT9
+#define SW_SATA_OOB_RSTN BIT10
+#define SW_SATA_PMALIVE_RSTN BIT11
+#define SW_SATA_RBC_RSTN BIT12
+#define SW_DMA0_RST_N BIT13
+#define SW_HSP_DMA0_RSTN BIT14
+#define SW_USB0_VAUX_RSTN BIT15
+#define SW_USB1_VAUX_RSTN BIT16
+#define SW_HSP_SD1_PRSTN BIT17
+#define SW_HSP_SD0_PRSTN BIT18
+#define SW_HSP_EMMC_PRSTN BIT19
+#define SW_HSP_DMA_PRSTN BIT20
+#define SW_HSP_SD1_ARSTN BIT21
+#define SW_HSP_SD0_ARSTN BIT22
+#define SW_HSP_EMMC_ARSTN BIT23
+#define SW_HSP_DMA_ARSTN BIT24
+#define SW_HSP_ETH1_ARSTN BIT25
+#define SW_HSP_ETH0_ARSTN BIT26
+#define SW_HSP_SATA_ARSTN BIT27
+
+/*PCIE*/
+#define SW_PCIE_CFG_RSTN BIT0
+#define SW_PCIE_POWERUP_RSTN BIT1
+#define SW_PCIE_PERST_N BIT2
+
+/*I2C*/
+#define SW_I2C_RST_N_0 BIT0
+#define SW_I2C_RST_N_1 BIT1
+#define SW_I2C_RST_N_2 BIT2
+#define SW_I2C_RST_N_3 BIT3
+#define SW_I2C_RST_N_4 BIT4
+#define SW_I2C_RST_N_5 BIT5
+#define SW_I2C_RST_N_6 BIT6
+#define SW_I2C_RST_N_7 BIT7
+#define SW_I2C_RST_N_8 BIT8
+#define SW_I2C_RST_N_9 BIT9
+
+/*FAN*/
+#define SW_FAN_RST_N BIT0
+
+/*PVT*/
+#define SW_PVT_RST_N_0 BIT0
+#define SW_PVT_RST_N_1 BIT1
+
+/*MBOX*/
+#define SW_MBOX_RST_N_0 BIT0
+#define SW_MBOX_RST_N_1 BIT1
+#define SW_MBOX_RST_N_2 BIT2
+#define SW_MBOX_RST_N_3 BIT3
+#define SW_MBOX_RST_N_4 BIT4
+#define SW_MBOX_RST_N_5 BIT5
+#define SW_MBOX_RST_N_6 BIT6
+#define SW_MBOX_RST_N_7 BIT7
+#define SW_MBOX_RST_N_8 BIT8
+#define SW_MBOX_RST_N_9 BIT9
+#define SW_MBOX_RST_N_10 BIT10
+#define SW_MBOX_RST_N_11 BIT11
+#define SW_MBOX_RST_N_12 BIT12
+#define SW_MBOX_RST_N_13 BIT13
+#define SW_MBOX_RST_N_14 BIT14
+#define SW_MBOX_RST_N_15 BIT15
+
+/*UART*/
+#define SW_UART_RST_N_0 BIT0
+#define SW_UART_RST_N_1 BIT1
+#define SW_UART_RST_N_2 BIT2
+#define SW_UART_RST_N_3 BIT3
+#define SW_UART_RST_N_4 BIT4
+
+/*GPIO*/
+/*
+#define SW_GPIO_RST_N_0 BIT0
+#define SW_GPIO_RST_N_1 BIT1
+*/
+
+/*TIMER*/
+#define SW_TIMER_RST_N BIT0
+
+/*SSI*/
+#define SW_SSI_RST_N_0 BIT0
+#define SW_SSI_RST_N_1 BIT1
+
+/*WDT*/
+#define SW_WDT_RST_N_0 BIT0
+#define SW_WDT_RST_N_1 BIT1
+#define SW_WDT_RST_N_2 BIT2
+#define SW_WDT_RST_N_3 BIT3
+
+/*LSP CFG*/
+#define SW_LSP_CFG_RSTN BIT0
+
+/*U84 CFG*/
+#define SW_U84_CORE_RSTN_0 BIT0
+#define SW_U84_CORE_RSTN_1 BIT1
+#define SW_U84_CORE_RSTN_2 BIT2
+#define SW_U84_CORE_RSTN_3 BIT3
+#define SW_U84_BUS_RSTN BIT4
+#define SW_U84_DBG_RSTN BIT5
+#define SW_U84_TRACECOM_RSTN BIT6
+#define SW_U84_TRACE_RSTN_0 BIT8
+#define SW_U84_TRACE_RSTN_1 BIT9
+#define SW_U84_TRACE_RSTN_2 BIT10
+#define SW_U84_TRACE_RSTN_3 BIT11
+
+/*SCPU*/
+#define SW_SCPU_CORE_RSTN BIT0
+#define SW_SCPU_BUS_RSTN BIT1
+#define SW_SCPU_DBG_RSTN BIT2
+
+/*LPCPU*/
+#define SW_LPCPU_CORE_RSTN BIT0
+#define SW_LPCPU_BUS_RSTN BIT1
+#define SW_LPCPU_DBG_RSTN BIT2
+
+/*VC*/
+#define SW_VC_CFG_RSTN BIT0
+#define SW_VC_AXI_RSTN BIT1
+#define SW_VC_MONCFG_RSTN BIT2
+
+/*JD*/
+#define SW_JD_CFG_RSTN BIT0
+#define SW_JD_AXI_RSTN BIT1
+
+/*JE*/
+#define SW_JE_CFG_RSTN BIT0
+#define SW_JE_AXI_RSTN BIT1
+
+/*VD*/
+#define SW_VD_CFG_RSTN BIT0
+#define SW_VD_AXI_RSTN BIT1
+
+/*VE*/
+#define SW_VE_AXI_RSTN BIT0
+#define SW_VE_CFG_RSTN BIT1
+
+/*G2D*/
+#define SW_G2D_CORE_RSTN BIT0
+#define SW_G2D_CFG_RSTN BIT1
+#define SW_G2D_AXI_RSTN BIT2
+
+/*VI*/
+#define SW_VI_AXI_RSTN BIT0
+#define SW_VI_CFG_RSTN BIT1
+#define SW_VI_DWE_RSTN BIT2
+
+/*DVP*/
+#define SW_VI_DVP_RSTN BIT0
+
+/*ISP0*/
+#define SW_VI_ISP0_RSTN BIT0
+
+/*ISP1*/
+#define SW_VI_ISP1_RSTN BIT0
+
+/*SHUTTR*/
+#define SW_VI_SHUTTER_RSTN_0 BIT0
+#define SW_VI_SHUTTER_RSTN_1 BIT1
+#define SW_VI_SHUTTER_RSTN_2 BIT2
+#define SW_VI_SHUTTER_RSTN_3 BIT3
+#define SW_VI_SHUTTER_RSTN_4 BIT4
+#define SW_VI_SHUTTER_RSTN_5 BIT5
+
+/*VO PHY*/
+#define SW_VO_MIPI_PRSTN BIT0
+#define SW_VO_PRSTN BIT1
+#define SW_VO_HDMI_PRSTN BIT3
+#define SW_HDMI_PHYCTRL_RSTN BIT4
+#define SW_VO_HDMI_RSTN BIT5
+
+/*VO I2S*/
+#define SW_VO_I2S_RSTN BIT0
+#define SW_VO_I2S_PRSTN BIT1
+
+/*VO*/
+#define SW_VO_AXI_RSTN BIT0
+#define SW_VO_CFG_RSTN BIT1
+#define SW_VO_DC_RSTN BIT2
+#define SW_VO_DC_PRSTN BIT3
+
+/*BOOTSPI*/
+#define SW_BOOTSPI_HRSTN BIT0
+#define SW_BOOTSPI_RSTN BIT1
+
+/*I2C1*/
+#define SW_I2C1_PRSTN BIT0
+
+/*I2C0*/
+#define SW_I2C0_PRSTN BIT0
+
+/*DMA1*/
+#define SW_DMA1_ARSTN BIT0
+#define SW_DMA1_HRSTN BIT1
+
+/*FPRT*/
+#define SW_FP_PRT_HRSTN BIT0
+
+/*HBLOCK*/
+#define SW_HBLOCK_HRSTN BIT0
+
+/*SECSR*/
+#define SW_SECSR_HRSTN BIT0
+
+/*OTP*/
+#define SW_OTP_PRSTN BIT0
+
+/*PKA*/
+#define SW_PKA_HRSTN BIT0
+
+/*SPACC*/
+#define SW_SPACC_RSTN BIT0
+
+/*TRNG*/
+#define SW_TRNG_HRSTN BIT0
+
+/*TIMER0*/
+#define SW_TIMER0_RSTN_0 BIT0
+#define SW_TIMER0_RSTN_1 BIT1
+#define SW_TIMER0_RSTN_2 BIT2
+#define SW_TIMER0_RSTN_3 BIT3
+#define SW_TIMER0_RSTN_4 BIT4
+#define SW_TIMER0_RSTN_5 BIT5
+#define SW_TIMER0_RSTN_6 BIT6
+#define SW_TIMER0_RSTN_7 BIT7
+#define SW_TIMER0_PRSTN BIT8
+
+/*TIMER1*/
+#define SW_TIMER1_RSTN_0 BIT0
+#define SW_TIMER1_RSTN_1 BIT1
+#define SW_TIMER1_RSTN_2 BIT2
+#define SW_TIMER1_RSTN_3 BIT3
+#define SW_TIMER1_RSTN_4 BIT4
+#define SW_TIMER1_RSTN_5 BIT5
+#define SW_TIMER1_RSTN_6 BIT6
+#define SW_TIMER1_RSTN_7 BIT7
+#define SW_TIMER1_PRSTN BIT8
+
+/*TIMER2*/
+#define SW_TIMER2_RSTN_0 BIT0
+#define SW_TIMER2_RSTN_1 BIT1
+#define SW_TIMER2_RSTN_2 BIT2
+#define SW_TIMER2_RSTN_3 BIT3
+#define SW_TIMER2_RSTN_4 BIT4
+#define SW_TIMER2_RSTN_5 BIT5
+#define SW_TIMER2_RSTN_6 BIT6
+#define SW_TIMER2_RSTN_7 BIT7
+#define SW_TIMER2_PRSTN BIT8
+
+/*TIMER3*/
+#define SW_TIMER3_RSTN_0 BIT0
+#define SW_TIMER3_RSTN_1 BIT1
+#define SW_TIMER3_RSTN_2 BIT2
+#define SW_TIMER3_RSTN_3 BIT3
+#define SW_TIMER3_RSTN_4 BIT4
+#define SW_TIMER3_RSTN_5 BIT5
+#define SW_TIMER3_RSTN_6 BIT6
+#define SW_TIMER3_RSTN_7 BIT7
+#define SW_TIMER3_PRSTN BIT8
+
+/*RTC*/
+#define SW_RTC_RSTN BIT0
+
+/*MNOC*/
+#define SW_MNOC_SNOC_NSP_RSTN BIT0
+#define SW_MNOC_VC_ARSTN BIT1
+#define SW_MNOC_CFG_RSTN BIT2
+#define SW_MNOC_HSP_ARSTN BIT3
+#define SW_MNOC_GPU_ARSTN BIT4
+#define SW_MNOC_DDRC1_P3_ARSTN BIT5
+#define SW_MNOC_DDRC0_P3_ARSTN BIT6
+
+/*RNOC*/
+#define SW_RNOC_VO_ARSTN BIT0
+#define SW_RNOC_VI_ARSTN BIT1
+#define SW_RNOC_SNOC_NSP_RSTN BIT2
+#define SW_RNOC_CFG_RSTN BIT3
+#define SW_MNOC_DDRC1_P4_ARSTN BIT4
+#define SW_MNOC_DDRC0_P4_ARSTN BIT5
+
+/*CNOC*/
+#define SW_CNOC_VO_CFG_RSTN BIT0
+#define SW_CNOC_VI_CFG_RSTN BIT1
+#define SW_CNOC_VC_CFG_RSTN BIT2
+#define SW_CNOC_TCU_CFG_RSTN BIT3
+#define SW_CNOC_PCIET_CFG_RSTN BIT4
+#define SW_CNOC_NPU_CFG_RSTN BIT5
+#define SW_CNOC_LSP_CFG_RSTN BIT6
+#define SW_CNOC_HSP_CFG_RSTN BIT7
+#define SW_CNOC_GPU_CFG_RSTN BIT8
+#define SW_CNOC_DSPT_CFG_RSTN BIT9
+#define SW_CNOC_DDRT1_CFG_RSTN BIT10
+#define SW_CNOC_DDRT0_CFG_RSTN BIT11
+#define SW_CNOC_D2D_CFG_RSTN BIT12
+#define SW_CNOC_CFG_RSTN BIT13
+#define SW_CNOC_CLMM_CFG_RSTN BIT14
+#define SW_CNOC_AON_CFG_RSTN BIT15
+
+/*LNOC*/
+#define SW_LNOC_CFG_RSTN BIT0
+#define SW_LNOC_NPU_LLC_ARSTN BIT1
+#define SW_LNOC_DDRC1_P0_ARSTN BIT2
+#define SW_LNOC_DDRC0_P0_ARSTN BIT3
+
+#endif /*endif __DT_ESWIN_WIN2030_SYSCRG_H__*/
--
2.47.0
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