185 lines
7.1 KiB
Diff
185 lines
7.1 KiB
Diff
From patchwork Fri May 11 02:27:50 2018
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 8bit
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Subject: [1/2] arm64: arch_timer: Workaround for Allwinner A64 timer
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instability
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From: Samuel Holland <samuel@sholland.org>
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X-Patchwork-Id: 10392891
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Message-Id: <20180511022751.9096-2-samuel@sholland.org>
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To: Maxime Ripard <maxime.ripard@bootlin.com>, Chen-Yu Tsai <wens@csie.org>,
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Catalin Marinas <catalin.marinas@arm.com>,
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Will Deacon <will.deacon@arm.com>,
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Daniel Lezcano <daniel.lezcano@linaro.org>,
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Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <marc.zyngier@arm.com>
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Cc: linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,
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linux-arm-kernel@lists.infradead.org, Samuel Holland <samuel@sholland.org>
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Date: Thu, 10 May 2018 21:27:50 -0500
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The Allwinner A64 SoC is known [1] to have an unstable architectural
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timer, which manifests itself most obviously in the time jumping forward
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a multiple of 95 years [2][3]. This coincides with 2^56 cycles at a
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timer frequency of 24 MHz, implying that the time went slightly backward
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(and this was interpreted by the kernel as it jumping forward and
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wrapping around past the epoch).
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Further investigation revealed instability in the low bits of CNTVCT at
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the point a high bit rolls over. This leads to power-of-two cycle
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forward and backward jumps. (Testing shows that forward jumps are about
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twice as likely as backward jumps.)
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Without trapping reads to CNTVCT, a userspace program is able to read it
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in a loop faster than it changes. A test program running on all 4 CPU
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cores that reported jumps larger than 100 ms was run for 13.6 hours and
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reported the following:
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Count | Event
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-------+---------------------------
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9940 | jumped backward 699ms
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268 | jumped backward 1398ms
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1 | jumped backward 2097ms
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16020 | jumped forward 175ms
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6443 | jumped forward 699ms
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2976 | jumped forward 1398ms
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9 | jumped forward 356516ms
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9 | jumped forward 357215ms
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4 | jumped forward 714430ms
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1 | jumped forward 3578440ms
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This works out to a jump larger than 100 ms about every 5.5 seconds on
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each CPU core.
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The largest jump (almost an hour!) was the following sequence of reads:
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0x0000007fffffffff → 0x00000093feffffff → 0x0000008000000000
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Note that the middle bits don't necessarily all read as all zeroes or
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all ones during the anomalous behavior; however the low 11 bits checked
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by the function in this patch have never been observed with any other
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value.
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Also note that smaller jumps are much more common, with the smallest
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backward jumps of 2048 cycles observed over 400 times per second on each
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core. (Of course, this is partially due to lower bits rolling over more
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frequently.) Any one of these could have caused the 95 year time skip.
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Similar anomalies were observed while reading CNTPCT (after patching the
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kernel to allow reads from userspace). However, the jumps are much less
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frequent, and only small jumps were observed. The same program as before
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(except now reading CNTPCT) observed after 72 hours:
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Count | Event
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-------+---------------------------
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17 | jumped backward 699ms
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52 | jumped forward 175ms
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2831 | jumped forward 699ms
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5 | jumped forward 1398ms
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Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
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Tested-by: Andre Przywara <andre.przywara@arm.com>
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========================================================================
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Because the CPU can read the CNTPCT/CNTVCT registers faster than they
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change, performing two reads of the register and comparing the high bits
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(like other workarounds) is not a workable solution. And because the
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timer can jump both forward and backward, no pair of reads can
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distinguish a good value from a bad one. The only way to guarantee a
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good value from consecutive reads would be to read _three_ times, and
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take the middle value iff the three values are 1) individually unique
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and 2) increasing. This takes at minimum 3 cycles (125 ns), or more if
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an anomaly is detected.
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However, since there is a distinct pattern to the bad values, we can
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optimize the common case (2046/2048 of the time) to a single read by
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simply ignoring values that match the pattern. This still takes no more
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than 3 cycles in the worst case, and requires much less code.
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[1]: https://github.com/armbian/build/commit/a08cd6fe7ae9
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[2]: https://forum.armbian.com/topic/3458-a64-datetime-clock-issue/
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[3]: https://irclog.whitequark.org/linux-sunxi/2018-01-26
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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drivers/clocksource/Kconfig | 11 ++++++++++
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drivers/clocksource/arm_arch_timer.c | 39 ++++++++++++++++++++++++++++++++++++
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2 files changed, 50 insertions(+)
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diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
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index 8e8a09755d10..7a5d434dd30b 100644
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--- a/drivers/clocksource/Kconfig
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+++ b/drivers/clocksource/Kconfig
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@@ -364,6 +364,17 @@ config ARM64_ERRATUM_858921
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The workaround will be dynamically enabled when an affected
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core is detected.
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+config SUN50I_A64_UNSTABLE_TIMER
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+ bool "Workaround for Allwinner A64 timer instability"
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+ default y
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+ depends on ARM_ARCH_TIMER && ARM64 && ARCH_SUNXI
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+ select ARM_ARCH_TIMER_OOL_WORKAROUND
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+ help
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+ This option enables a workaround for instability in the timer on
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+ the Allwinner A64 SoC. The workaround will only be active if the
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+ allwinner,sun50i-a64-unstable-timer property is found in the
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+ timer node.
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+
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config ARM_GLOBAL_TIMER
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bool "Support for the ARM global timer" if COMPILE_TEST
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select TIMER_OF if OF
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diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
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index 57cb2f00fc07..66ce13578c52 100644
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--- a/drivers/clocksource/arm_arch_timer.c
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+++ b/drivers/clocksource/arm_arch_timer.c
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@@ -319,6 +319,36 @@ static u64 notrace arm64_858921_read_cntvct_el0(void)
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}
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#endif
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+#ifdef CONFIG_SUN50I_A64_UNSTABLE_TIMER
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+/*
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+ * The low bits of each register can transiently read as all ones or all zeroes
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+ * when bit 11 or greater rolls over. Since the value can jump both backward
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+ * (7ff -> 000 -> 800) and forward (7ff -> fff -> 800), it is simplest to just
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+ * ignore register values with all ones or zeros in the low bits.
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+ */
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+static u64 notrace sun50i_a64_read_cntpct_el0(void)
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+{
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+ u64 val;
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+
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+ do {
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+ val = read_sysreg(cntpct_el0);
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+ } while (((val + 1) & GENMASK(10, 0)) <= 1);
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+
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+ return val;
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+}
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+
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+static u64 notrace sun50i_a64_read_cntvct_el0(void)
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+{
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+ u64 val;
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+
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+ do {
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+ val = read_sysreg(cntvct_el0);
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+ } while (((val + 1) & GENMASK(10, 0)) <= 1);
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+
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+ return val;
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+}
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+#endif
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+
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#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
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DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround);
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EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
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@@ -408,6 +438,15 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = {
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.read_cntvct_el0 = arm64_858921_read_cntvct_el0,
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},
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#endif
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+#ifdef CONFIG_SUN50I_A64_UNSTABLE_TIMER
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+ {
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+ .match_type = ate_match_dt,
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+ .id = "allwinner,sun50i-a64-unstable-timer",
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+ .desc = "Allwinner A64 timer instability",
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+ .read_cntpct_el0 = sun50i_a64_read_cntpct_el0,
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+ .read_cntvct_el0 = sun50i_a64_read_cntvct_el0,
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+ },
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+#endif
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};
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typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *,
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