62 lines
2.4 KiB
Diff
62 lines
2.4 KiB
Diff
From 69682c252ebd9924b2602d50a5a608aae3602232 Mon Sep 17 00:00:00 2001
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From: Pritesh Patel <pritesh.patel@einfochips.com>
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Date: Tue, 3 Sep 2024 11:52:32 +0000
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Subject: [PATCH 041/128] riscv: dts: hifive-premier-p550: Update ISA extension
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in dtsi
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Removed "riscv,isa" property since its deprecated and replace them
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with "riscv,isa-base" and "riscv,isa-extensions" properties.
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Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
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---
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arch/riscv/boot/dts/eswin/eic7700-arch.dtsi | 12 ++++++++----
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1 file changed, 8 insertions(+), 4 deletions(-)
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diff --git a/arch/riscv/boot/dts/eswin/eic7700-arch.dtsi b/arch/riscv/boot/dts/eswin/eic7700-arch.dtsi
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index 0ffbfd21e8ec..c0d9f396a50c 100644
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--- a/arch/riscv/boot/dts/eswin/eic7700-arch.dtsi
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+++ b/arch/riscv/boot/dts/eswin/eic7700-arch.dtsi
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@@ -62,7 +62,8 @@ L17: cpu@0 {
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mmu-type = "riscv,sv48";
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next-level-cache = <&L15>;
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reg = <0x0>;
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- riscv,isa = "rv64imafdc_h_zicsr_zifencei_zba_zbb_sscofpmf";
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+ riscv,isa-base = "rv64i";
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+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicsr", "zifencei", "zba", "zbb", "sscofpmf";
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riscv,pmpgranularity = <4096>;
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riscv,pmpregions = <8>;
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sifive,buserror = <&L16>;
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@@ -126,7 +127,8 @@ L22: cpu@1 {
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mmu-type = "riscv,sv48";
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next-level-cache = <&L20>;
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reg = <0x1>;
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- riscv,isa = "rv64imafdc_h_zicsr_zifencei_zba_zbb_sscofpmf";
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+ riscv,isa-base = "rv64i";
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+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicsr", "zifencei", "zba", "zbb", "sscofpmf";
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riscv,pmpgranularity = <4096>;
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riscv,pmpregions = <8>;
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sifive,buserror = <&L21>;
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@@ -190,7 +192,8 @@ L27: cpu@2 {
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mmu-type = "riscv,sv48";
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next-level-cache = <&L25>;
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reg = <0x2>;
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- riscv,isa = "rv64imafdc_h_zicsr_zifencei_zba_zbb_sscofpmf";
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+ riscv,isa-base = "rv64i";
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+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicsr", "zifencei", "zba", "zbb", "sscofpmf";
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riscv,pmpgranularity = <4096>;
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riscv,pmpregions = <8>;
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sifive,buserror = <&L26>;
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@@ -254,7 +257,8 @@ L32: cpu@3 {
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mmu-type = "riscv,sv48";
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next-level-cache = <&L30>;
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reg = <0x3>;
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- riscv,isa = "rv64imafdc_h_zicsr_zifencei_zba_zbb_sscofpmf";
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+ riscv,isa-base = "rv64i";
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+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicsr", "zifencei", "zba", "zbb", "sscofpmf";
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riscv,pmpgranularity = <4096>;
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riscv,pmpregions = <8>;
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sifive,buserror = <&L31>;
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--
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2.47.0
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