33 lines
1.2 KiB
Diff
33 lines
1.2 KiB
Diff
From 30f69f3fb20bd719b5e1bf879339914063d38f47 Mon Sep 17 00:00:00 2001
|
|
From: Jerome Glisse <jglisse@redhat.com>
|
|
Date: Fri, 16 Apr 2010 18:46:35 +0200
|
|
Subject: [PATCH] drm/radeon/kms: fix rs600 tlb flush
|
|
|
|
Typo in in flush leaded to no flush of the RS600 tlb which
|
|
ultimately leaded to massive system ram corruption, with
|
|
this patch everythings seems to work properly.
|
|
|
|
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
|
|
Cc: stable <stable@kernel.org>
|
|
Signed-off-by: Dave Airlie <airlied@redhat.com>
|
|
---
|
|
drivers/gpu/drm/radeon/rs600.c | 2 +-
|
|
1 files changed, 1 insertions(+), 1 deletions(-)
|
|
|
|
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
|
|
index abf824c..a81bc7a 100644
|
|
--- a/drivers/gpu/drm/radeon/rs600.c
|
|
+++ b/drivers/gpu/drm/radeon/rs600.c
|
|
@@ -159,7 +159,7 @@ void rs600_gart_tlb_flush(struct radeon_device *rdev)
|
|
WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
|
|
|
|
tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
|
|
- tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1);
|
|
+ tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
|
|
WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
|
|
|
|
tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
|
|
--
|
|
1.6.6.1
|
|
|