575 lines
19 KiB
Diff
575 lines
19 KiB
Diff
From 39bb622a9804de9fa51cae31f07104a19067483a Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
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Date: Mon, 21 Oct 2013 10:52:06 +0300
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Subject: [PATCH 1/5] drm/i915: Add support for pipe_bpp readout
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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On CTG+ read out the pipe bpp setting from hardware and fill it into
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pipe config. Also check it appropriately.
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v2: Don't do the pipe_bpp extraction inside the PCH only code block on
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ILK+.
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Avoid the PIPECONF read as we already have read it for the
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PIPECONF_EANBLE check.
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Note: This is already in drm-intel-next-queued as
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commit 42571aefafb1d330ef84eb29418832f72e7dfb4c
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Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
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Date: Fri Sep 6 23:29:00 2013 +0300
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drm/i915: Add support for pipe_bpp readout
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but is needed for the following bugfix.
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Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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Reviewed-by: Jani Nikula <jani.nikula@intel.com>
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Cc: stable@vger.kernel.org
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Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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---
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drivers/gpu/drm/i915/intel_ddi.c | 17 +++++++++++++++++
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drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++++++++++++++++++
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2 files changed, 53 insertions(+)
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diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
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index b042ee5..83e413b 100644
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--- a/drivers/gpu/drm/i915/intel_ddi.c
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+++ b/drivers/gpu/drm/i915/intel_ddi.c
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@@ -1280,6 +1280,23 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
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flags |= DRM_MODE_FLAG_NVSYNC;
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pipe_config->adjusted_mode.flags |= flags;
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+
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+ switch (temp & TRANS_DDI_BPC_MASK) {
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+ case TRANS_DDI_BPC_6:
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+ pipe_config->pipe_bpp = 18;
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+ break;
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+ case TRANS_DDI_BPC_8:
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+ pipe_config->pipe_bpp = 24;
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+ break;
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+ case TRANS_DDI_BPC_10:
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+ pipe_config->pipe_bpp = 30;
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+ break;
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+ case TRANS_DDI_BPC_12:
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+ pipe_config->pipe_bpp = 36;
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+ break;
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+ default:
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+ break;
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+ }
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}
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static void intel_ddi_destroy(struct drm_encoder *encoder)
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diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
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index 90a7c17..4aaccd3 100644
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--- a/drivers/gpu/drm/i915/intel_display.c
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+++ b/drivers/gpu/drm/i915/intel_display.c
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@@ -4943,6 +4943,22 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
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if (!(tmp & PIPECONF_ENABLE))
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return false;
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+ if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
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+ switch (tmp & PIPECONF_BPC_MASK) {
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+ case PIPECONF_6BPC:
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+ pipe_config->pipe_bpp = 18;
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+ break;
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+ case PIPECONF_8BPC:
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+ pipe_config->pipe_bpp = 24;
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+ break;
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+ case PIPECONF_10BPC:
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+ pipe_config->pipe_bpp = 30;
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+ break;
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+ default:
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+ break;
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+ }
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+ }
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+
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intel_get_pipe_timings(crtc, pipe_config);
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i9xx_get_pfit_config(crtc, pipe_config);
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@@ -5821,6 +5837,23 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
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if (!(tmp & PIPECONF_ENABLE))
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return false;
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+ switch (tmp & PIPECONF_BPC_MASK) {
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+ case PIPECONF_6BPC:
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+ pipe_config->pipe_bpp = 18;
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+ break;
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+ case PIPECONF_8BPC:
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+ pipe_config->pipe_bpp = 24;
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+ break;
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+ case PIPECONF_10BPC:
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+ pipe_config->pipe_bpp = 30;
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+ break;
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+ case PIPECONF_12BPC:
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+ pipe_config->pipe_bpp = 36;
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+ break;
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+ default:
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+ break;
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+ }
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+
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if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
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struct intel_shared_dpll *pll;
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@@ -8147,6 +8180,9 @@ intel_pipe_config_compare(struct drm_device *dev,
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PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
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PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
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+ if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
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+ PIPE_CONF_CHECK_I(pipe_bpp);
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+
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#undef PIPE_CONF_CHECK_X
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#undef PIPE_CONF_CHECK_I
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#undef PIPE_CONF_CHECK_FLAGS
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--
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1.8.3.1
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From b59da942a708f7cf1c421a7cb666f98fd8172208 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
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Date: Tue, 24 Sep 2013 14:24:05 +0300
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Subject: [PATCH 2/5] drm/i915: Add HSW CRT output readout support
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Call intel_ddi_get_config() to get the pipe_bpp settings from
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DDI.
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The sync polarity settings from DDI are irrelevant for CRT
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output, so override them with data from the ADPA register.
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Note: This is already merged in drm-intel-next-queued as
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commit 6801c18c0a43386bb44712cbc028a7e05adb9f0d
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Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
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Date: Tue Sep 24 14:24:05 2013 +0300
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drm/i915: Add HSW CRT output readout support
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but is required for the following edp bpp bugfix.
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v2: Extract intel_crt_get_flags()
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Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=69691
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Tested-by: Qingshuai Tian <qingshuai.tian@intel.com>
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Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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Cc: stable@vger.kernel.org
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Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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---
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drivers/gpu/drm/i915/intel_crt.c | 30 ++++++++++++++++++++++++++----
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drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
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drivers/gpu/drm/i915/intel_drv.h | 2 ++
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3 files changed, 30 insertions(+), 6 deletions(-)
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diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
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index 3acec8c..6aa6ebd 100644
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--- a/drivers/gpu/drm/i915/intel_crt.c
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+++ b/drivers/gpu/drm/i915/intel_crt.c
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@@ -84,8 +84,7 @@ static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
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return true;
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}
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-static void intel_crt_get_config(struct intel_encoder *encoder,
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- struct intel_crtc_config *pipe_config)
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+static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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struct intel_crt *crt = intel_encoder_to_crt(encoder);
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@@ -103,7 +102,27 @@ static void intel_crt_get_config(struct intel_encoder *encoder,
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else
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flags |= DRM_MODE_FLAG_NVSYNC;
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- pipe_config->adjusted_mode.flags |= flags;
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+ return flags;
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+}
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+
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+static void intel_crt_get_config(struct intel_encoder *encoder,
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+ struct intel_crtc_config *pipe_config)
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+{
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+ struct drm_device *dev = encoder->base.dev;
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+
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+ pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder);
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+}
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+
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+static void hsw_crt_get_config(struct intel_encoder *encoder,
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+ struct intel_crtc_config *pipe_config)
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+{
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+ intel_ddi_get_config(encoder, pipe_config);
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+
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+ pipe_config->adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
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+ DRM_MODE_FLAG_NHSYNC |
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+ DRM_MODE_FLAG_PVSYNC |
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+ DRM_MODE_FLAG_NVSYNC);
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+ pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder);
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}
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/* Note: The caller is required to filter out dpms modes not supported by the
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@@ -802,7 +821,10 @@ void intel_crt_init(struct drm_device *dev)
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crt->base.compute_config = intel_crt_compute_config;
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crt->base.disable = intel_disable_crt;
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crt->base.enable = intel_enable_crt;
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- crt->base.get_config = intel_crt_get_config;
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+ if (IS_HASWELL(dev))
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+ crt->base.get_config = hsw_crt_get_config;
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+ else
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+ crt->base.get_config = intel_crt_get_config;
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if (I915_HAS_HOTPLUG(dev))
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crt->base.hpd_pin = HPD_CRT;
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if (HAS_DDI(dev))
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diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
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index 83e413b..5a6368d 100644
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--- a/drivers/gpu/drm/i915/intel_ddi.c
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+++ b/drivers/gpu/drm/i915/intel_ddi.c
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@@ -1261,8 +1261,8 @@ static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
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intel_dp_check_link_status(intel_dp);
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}
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-static void intel_ddi_get_config(struct intel_encoder *encoder,
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- struct intel_crtc_config *pipe_config)
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+void intel_ddi_get_config(struct intel_encoder *encoder,
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+ struct intel_crtc_config *pipe_config)
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{
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
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diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
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index b7d6e09..ddf7e2f 100644
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--- a/drivers/gpu/drm/i915/intel_drv.h
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+++ b/drivers/gpu/drm/i915/intel_drv.h
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@@ -816,6 +816,8 @@ extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
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extern bool
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intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
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extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
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+extern void intel_ddi_get_config(struct intel_encoder *encoder,
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+ struct intel_crtc_config *pipe_config);
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extern void intel_display_handle_reset(struct drm_device *dev);
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extern bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
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--
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1.8.3.1
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From 92c64493f41092185230c552c277b42bf6113140 Mon Sep 17 00:00:00 2001
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From: Jani Nikula <jani.nikula@intel.com>
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Date: Mon, 21 Oct 2013 10:52:07 +0300
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Subject: [PATCH 3/5] drm/i915/dp: workaround BIOS eDP bpp clamping issue
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This isn't a real fix to the problem, but rather a stopgap measure while
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trying to find a proper solution.
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There are several laptops out there that fail to light up the eDP panel
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in UEFI boot mode. They seem to be mostly IVB machines, including but
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apparently not limited to Dell XPS 13, Asus TX300, Asus UX31A, Asus
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UX32VD, Acer Aspire S7. They seem to work in CSM or legacy boot.
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The difference between UEFI and CSM is that the BIOS provides a
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different VBT to the kernel. The UEFI VBT typically specifies 18 bpp and
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1.62 GHz link for eDP, while CSM VBT has 24 bpp and 2.7 GHz link. We end
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up clamping to 18 bpp in UEFI mode, which we can fit in the 1.62 Ghz
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link, and for reasons yet unknown fail to light up the panel.
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Dithering from 24 to 18 bpp itself seems to work; if we use 18 bpp with
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2.7 GHz link, the eDP panel lights up. So essentially this is a link
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speed issue, and *not* a bpp clamping issue.
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The bug raised its head since
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commit 657445fe8660100ad174600ebfa61536392b7624
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Author: Daniel Vetter <daniel.vetter@ffwll.ch>
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Date: Sat May 4 10:09:18 2013 +0200
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Revert "drm/i915: revert eDP bpp clamping code changes"
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which started clamping bpp *before* computing the link requirements, and
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thus affecting the required bandwidth. Clamping after the computations
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kept the link at 2.7 GHz.
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Even though the BIOS tells us to use 18 bpp through the VBT, it happily
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boots up at 24 bpp and 2.7 GHz itself! Use this information to
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selectively ignore the VBT provided value.
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We can't ignore the VBT eDP bpp altogether, as there are other laptops
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that do require the clamping to be used due to EDID reporting higher bpp
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than the panel can support.
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Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=59841
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Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67950
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Tested-by: Ulf Winkelvos <ulf@winkelvos.de>
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Tested-by: jkp <jkp@iki.fi>
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CC: stable@vger.kernel.org
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Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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---
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drivers/gpu/drm/i915/intel_dp.c | 20 ++++++++++++++++++++
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1 file changed, 20 insertions(+)
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diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
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index 3aed1fe..07eb447 100644
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--- a/drivers/gpu/drm/i915/intel_dp.c
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+++ b/drivers/gpu/drm/i915/intel_dp.c
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@@ -1371,6 +1371,26 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
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}
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pipe_config->adjusted_mode.flags |= flags;
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+
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+ if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
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+ pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
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+ /*
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+ * This is a big fat ugly hack.
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+ *
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+ * Some machines in UEFI boot mode provide us a VBT that has 18
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+ * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
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+ * unknown we fail to light up. Yet the same BIOS boots up with
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+ * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
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+ * max, not what it tells us to use.
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+ *
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+ * Note: This will still be broken if the eDP panel is not lit
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+ * up by the BIOS, and thus we can't get the mode at module
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+ * load.
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+ */
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+ DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
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+ pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
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+ dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
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+ }
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}
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static void intel_disable_dp(struct intel_encoder *encoder)
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--
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1.8.3.1
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From 1e5ec9a5628cfd23443a91f80dea2118efb21afd Mon Sep 17 00:00:00 2001
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From: Rob Pearce <rob@flitspace.org.uk>
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Date: Sun, 27 Oct 2013 16:13:42 +0000
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Subject: [PATCH 4/5] drm/i915: No LVDS hardware on Intel D410PT and D425KT
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The Intel D410PT(LW) and D425KT Mini-ITX desktop boards both show up as
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having LVDS but the hardware is not populated. This patch adds them to
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the list of such systems. Patch is against 3.11.4
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v2: Patch revised to match the D425KT exactly as the D425KTW does have
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LVDS. According to Intel's documentation, the D410PTL and D410PLTW
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don't.
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Signed-off-by: Rob Pearce <rob@flitspace.org.uk>
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Cc: stable@vger.kernel.org
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[danvet: Pimp commit message to my liking and add cc: stable.]
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Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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---
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drivers/gpu/drm/i915/intel_lvds.c | 16 ++++++++++++++++
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1 file changed, 16 insertions(+)
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diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
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index 61348ea..44533dd 100644
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--- a/drivers/gpu/drm/i915/intel_lvds.c
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+++ b/drivers/gpu/drm/i915/intel_lvds.c
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@@ -696,6 +696,22 @@ static const struct dmi_system_id intel_no_lvds[] = {
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},
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{
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.callback = intel_no_lvds_dmi_callback,
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+ .ident = "Intel D410PT",
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+ .matches = {
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+ DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
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+ DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
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+ },
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+ },
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+ {
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+ .callback = intel_no_lvds_dmi_callback,
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+ .ident = "Intel D425KT",
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+ .matches = {
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+ DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
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+ DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
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+ },
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+ },
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+ {
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+ .callback = intel_no_lvds_dmi_callback,
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.ident = "Intel D510MO",
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
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--
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1.8.3.1
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From 239319357b4a2d085e5f5c27b46aab5f612c5036 Mon Sep 17 00:00:00 2001
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From: Daniel Vetter <daniel.vetter@ffwll.ch>
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Date: Tue, 29 Oct 2013 12:04:08 +0100
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Subject: [PATCH 5/5] drm/i915: Fix the PPT fdi lane bifurcate state handling
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on ivb
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Originally I've thought that this is leftover hw state dirt from the
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BIOS. But after way too much helpless flailing around on my part I've
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noticed that the actual bug is when we change the state of an already
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active pipe.
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For example when we change the fdi lines from 2 to 3 without switching
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off outputs in-between we'll never see the crucial on->off transition
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in the ->modeset_global_resources hook the current logic relies on.
|
|
|
|
Patch version 2 got this right by instead also checking whether the
|
|
pipe is indeed active. But that in turn broke things when pipes have
|
|
been turned off through dpms since the bifurcate enabling is done in
|
|
the ->crtc_mode_set callback.
|
|
|
|
To address this issues discussed with Ville in the patch review move
|
|
the setting of the bifurcate bit into the ->crtc_enable hook. That way
|
|
we won't wreak havoc with this state when userspace puts all other
|
|
outputs into dpms off state. This also moves us forward with our
|
|
overall goal to unify the modeset and dpms on paths (which we need to
|
|
have to allow runtime pm in the dpms off state).
|
|
|
|
Unfortunately this requires us to move the bifurcate helpers around a
|
|
bit.
|
|
|
|
Also update the commit message, I've misanalyzed the bug rather badly.
|
|
|
|
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70507
|
|
Tested-by: Jan-Michael Brummer <jan.brummer@tabos.org>
|
|
Cc: stable@vger.kernel.org
|
|
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
|
|
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
|
|
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
|
|
---
|
|
drivers/gpu/drm/i915/intel_display.c | 95 ++++++++++++++++++------------------
|
|
1 file changed, 48 insertions(+), 47 deletions(-)
|
|
|
|
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
|
|
index 4aaccd3..ad2a258 100644
|
|
--- a/drivers/gpu/drm/i915/intel_display.c
|
|
+++ b/drivers/gpu/drm/i915/intel_display.c
|
|
@@ -2251,9 +2251,10 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
|
|
FDI_FE_ERRC_ENABLE);
|
|
}
|
|
|
|
-static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
|
|
+static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
|
|
{
|
|
- return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
|
|
+ return crtc->base.enabled && crtc->active &&
|
|
+ crtc->config.has_pch_encoder;
|
|
}
|
|
|
|
static void ivb_modeset_global_resources(struct drm_device *dev)
|
|
@@ -2901,6 +2902,48 @@ static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
|
|
I915_READ(VSYNCSHIFT(cpu_transcoder)));
|
|
}
|
|
|
|
+static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
|
|
+{
|
|
+ struct drm_i915_private *dev_priv = dev->dev_private;
|
|
+ uint32_t temp;
|
|
+
|
|
+ temp = I915_READ(SOUTH_CHICKEN1);
|
|
+ if (temp & FDI_BC_BIFURCATION_SELECT)
|
|
+ return;
|
|
+
|
|
+ WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
|
|
+ WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
|
|
+
|
|
+ temp |= FDI_BC_BIFURCATION_SELECT;
|
|
+ DRM_DEBUG_KMS("enabling fdi C rx\n");
|
|
+ I915_WRITE(SOUTH_CHICKEN1, temp);
|
|
+ POSTING_READ(SOUTH_CHICKEN1);
|
|
+}
|
|
+
|
|
+static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
|
|
+{
|
|
+ struct drm_device *dev = intel_crtc->base.dev;
|
|
+ struct drm_i915_private *dev_priv = dev->dev_private;
|
|
+
|
|
+ switch (intel_crtc->pipe) {
|
|
+ case PIPE_A:
|
|
+ break;
|
|
+ case PIPE_B:
|
|
+ if (intel_crtc->config.fdi_lanes > 2)
|
|
+ WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
|
|
+ else
|
|
+ cpt_enable_fdi_bc_bifurcation(dev);
|
|
+
|
|
+ break;
|
|
+ case PIPE_C:
|
|
+ cpt_enable_fdi_bc_bifurcation(dev);
|
|
+
|
|
+ break;
|
|
+ default:
|
|
+ BUG();
|
|
+ }
|
|
+}
|
|
+
|
|
/*
|
|
* Enable PCH resources required for PCH ports:
|
|
* - PCH PLLs
|
|
@@ -2919,6 +2962,9 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
|
|
|
|
assert_pch_transcoder_disabled(dev_priv, pipe);
|
|
|
|
+ if (IS_IVYBRIDGE(dev))
|
|
+ ivybridge_update_fdi_bc_bifurcation(intel_crtc);
|
|
+
|
|
/* Write the TU size bits before fdi link training, so that error
|
|
* detection works. */
|
|
I915_WRITE(FDI_RX_TUSIZE1(pipe),
|
|
@@ -5512,48 +5558,6 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc,
|
|
return true;
|
|
}
|
|
|
|
-static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
|
|
-{
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
- uint32_t temp;
|
|
-
|
|
- temp = I915_READ(SOUTH_CHICKEN1);
|
|
- if (temp & FDI_BC_BIFURCATION_SELECT)
|
|
- return;
|
|
-
|
|
- WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
|
|
- WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
|
|
-
|
|
- temp |= FDI_BC_BIFURCATION_SELECT;
|
|
- DRM_DEBUG_KMS("enabling fdi C rx\n");
|
|
- I915_WRITE(SOUTH_CHICKEN1, temp);
|
|
- POSTING_READ(SOUTH_CHICKEN1);
|
|
-}
|
|
-
|
|
-static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
|
|
-{
|
|
- struct drm_device *dev = intel_crtc->base.dev;
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
-
|
|
- switch (intel_crtc->pipe) {
|
|
- case PIPE_A:
|
|
- break;
|
|
- case PIPE_B:
|
|
- if (intel_crtc->config.fdi_lanes > 2)
|
|
- WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
|
|
- else
|
|
- cpt_enable_fdi_bc_bifurcation(dev);
|
|
-
|
|
- break;
|
|
- case PIPE_C:
|
|
- cpt_enable_fdi_bc_bifurcation(dev);
|
|
-
|
|
- break;
|
|
- default:
|
|
- BUG();
|
|
- }
|
|
-}
|
|
-
|
|
int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
|
|
{
|
|
/*
|
|
@@ -5768,9 +5772,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
|
|
&intel_crtc->config.fdi_m_n);
|
|
}
|
|
|
|
- if (IS_IVYBRIDGE(dev))
|
|
- ivybridge_update_fdi_bc_bifurcation(intel_crtc);
|
|
-
|
|
ironlake_set_pipeconf(crtc);
|
|
|
|
/* Set up the display plane register */
|
|
--
|
|
1.8.3.1
|
|
|