95 lines
3.2 KiB
Diff
95 lines
3.2 KiB
Diff
From c8ff7a795bf883c61b7d7f506b0bb7796db6cb01 Mon Sep 17 00:00:00 2001
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From: Matt Porter <mporter@ti.com>
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Date: Wed, 6 Mar 2013 19:56:05 +0000
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Subject: [PATCH 03/13] dmaengine: add dma_get_slave_sg_limits()
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Add a dmaengine API to retrieve slave SG transfer limits.
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The API is optionally implemented by dmaengine drivers and when
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unimplemented will return a NULL pointer. A client driver using
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this API provides the required dma channel, address width, and
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burst size of the transfer. dma_get_slave_sg_limits() returns an
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SG limits structure with the maximum number and size of SG segments
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that the given channel can handle.
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Signed-off-by: Matt Porter <mporter@ti.com>
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Signed-off-by: Joel A Fernandes <joelagnel@ti.com>
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---
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include/linux/dmaengine.h | 39 +++++++++++++++++++++++++++++++++++++++
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1 file changed, 39 insertions(+)
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diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
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index cb286b1..d71fe5d 100644
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--- a/include/linux/dmaengine.h
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+++ b/include/linux/dmaengine.h
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@@ -370,6 +370,18 @@ struct dma_slave_config {
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unsigned int slave_id;
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};
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+/* struct dma_slave_sg_limits - expose SG transfer limits of a channel
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+ *
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+ * @max_seg_nr: maximum number of SG segments supported on a SG/SLAVE
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+ * channel (0 for no maximum or not a SG/SLAVE channel)
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+ * @max_seg_len: maximum length of SG segments supported on a SG/SLAVE
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+ * channel (0 for no maximum or not a SG/SLAVE channel)
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+ */
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+struct dma_slave_sg_limits {
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+ u32 max_seg_nr;
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+ u32 max_seg_len;
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+};
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+
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static inline const char *dma_chan_name(struct dma_chan *chan)
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{
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return dev_name(&chan->dev->device);
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@@ -532,6 +544,7 @@ struct dma_tx_state {
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* struct with auxiliary transfer status information, otherwise the call
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* will just return a simple status code
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* @device_issue_pending: push pending transactions to hardware
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+ * @device_slave_sg_limits: return the slave SG capabilities
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*/
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struct dma_device {
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@@ -597,6 +610,9 @@ struct dma_device {
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dma_cookie_t cookie,
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struct dma_tx_state *txstate);
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void (*device_issue_pending)(struct dma_chan *chan);
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+ struct dma_slave_sg_limits *(*device_slave_sg_limits)(
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+ struct dma_chan *chan, enum dma_slave_buswidth addr_width,
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+ u32 maxburst);
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};
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static inline int dmaengine_device_control(struct dma_chan *chan,
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@@ -958,6 +974,29 @@ dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used,
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}
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}
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+/**
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+ * dma_get_slave_sg_limits - get DMAC SG transfer capabilities
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+ * @chan: target DMA channel
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+ * @addr_width: address width of the DMA transfer
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+ * @maxburst: maximum DMA transfer burst size
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+ *
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+ * Get SG transfer capabilities for a specified channel. If the dmaengine
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+ * driver does not implement SG transfer capabilities then NULL is
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+ * returned.
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+ */
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+static inline struct dma_slave_sg_limits
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+*dma_get_slave_sg_limits(struct dma_chan *chan,
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+ enum dma_slave_buswidth addr_width,
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+ u32 maxburst)
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+{
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+ if (chan->device->device_slave_sg_limits)
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+ return chan->device->device_slave_sg_limits(chan,
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+ addr_width,
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+ maxburst);
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+
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+ return NULL;
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+}
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+
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enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
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#ifdef CONFIG_DMA_ENGINE
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enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
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--
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1.8.2.1
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