224 lines
7.1 KiB
Diff
224 lines
7.1 KiB
Diff
From 785e1b03850b298955416c69df6f02e23a686e8b Mon Sep 17 00:00:00 2001
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From: huangyifeng <huangyifeng@eswincomputing.com>
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Date: Thu, 29 Aug 2024 16:17:29 +0800
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Subject: [PATCH 171/219] feat:add cpu volatge adjust
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Changelogs:
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add cpu volatge adjust.When the CPU frequency is scaled above
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1.6GHz, the voltage is adjusted to 0.9V; otherwise, it remains at 0.8V.
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Signed-off-by: huangyifeng <huangyifeng@eswincomputing.com>
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---
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.../dts/eswin/eic7700-hifive-premier-p550.dts | 23 +++++-
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drivers/clk/eswin/clk.c | 71 ++++++++++++++++++-
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drivers/clk/eswin/clk.h | 7 ++
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3 files changed, 97 insertions(+), 4 deletions(-)
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diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
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index f20c86264c3e..9cacb373b3bc 100644
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--- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
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+++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
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@@ -772,7 +772,8 @@ &pinctrl_gpio37_default &pinctrl_gpio38_default &pinctrl_gpio39_default &pinctrl
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&pinctrl_gpio41_default &pinctrl_gpio46_default &pinctrl_gpio52_default
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&pinctrl_gpio53_default &pinctrl_gpio64_default &pinctrl_gpio65_default &pinctrl_gpio66_default
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&pinctrl_gpio67_default &pinctrl_gpio70_default &pinctrl_gpio73_default &pinctrl_gpio83_default
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- &pinctrl_gpio86_default &pinctrl_gpio87_default &pinctrl_gpio92_default &pinctrl_gpio93_default>;
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+ &pinctrl_gpio86_default &pinctrl_gpio87_default &pinctrl_gpio92_default &pinctrl_gpio93_default
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+ &pinctrl_gpio94_default>;
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/* pin header default function for GPIO
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SPI1 (CS0,SCLK,MOSI,MISO,D2,D3): GPIO 35,36,37,38,39,40
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@@ -817,6 +818,24 @@ &gpio0 {
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status = "okay";
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};
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-&dev_llc_d0{
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+&dev_llc_d0 {
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apply_npu_high_freq;
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+};
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+
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+&d0_clock {
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+ status = "okay";
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+ cpu-voltage-gpios = <&portc 30 GPIO_ACTIVE_HIGH>;
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+};
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+
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+&d0_cpu_opp_table {
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+ opp-1600000000 {
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+ opp-hz = /bits/ 64 <CLK_FREQ_1600M>;
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+ opp-microvolt = <900000>;
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+ clock-latency-ns = <70000>;
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+ };
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+ opp-1800000000 {
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+ opp-hz = /bits/ 64 <CLK_FREQ_1800M>;
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+ opp-microvolt = <900000>;
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+ clock-latency-ns = <70000>;
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+ };
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};
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\ No newline at end of file
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diff --git a/drivers/clk/eswin/clk.c b/drivers/clk/eswin/clk.c
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index 06569c72ba37..b944a5e6ec44 100755
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--- a/drivers/clk/eswin/clk.c
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+++ b/drivers/clk/eswin/clk.c
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@@ -30,8 +30,8 @@
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/util_macros.h>
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+#include <linux/gpio/consumer.h>
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#include <dt-bindings/clock/win2030-clock.h>
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-
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#include "clk.h"
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struct clk_hw *eswin_clk_find_parent(struct eswin_clock_data *data, char *parent_name)
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@@ -128,6 +128,26 @@ int eswin_clk_register_fixed_rate(const struct eswin_fixed_rate_clock *clks,
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}
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EXPORT_SYMBOL_GPL(eswin_clk_register_fixed_rate);
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+static int eswin_clk_set_cpu_volatge(struct gpio_desc *cpu_voltage_gpio,
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+ enum voltage_level target_volatge)
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+{
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+ if (!cpu_voltage_gpio) {
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+ return -EINVAL;
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+ }
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+ switch (target_volatge) {
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+ case VOLTAGE_0_9V:
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+ gpiod_set_value(cpu_voltage_gpio, 1);
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+ break;
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+ case VOLTAGE_0_8V:
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+ gpiod_set_value(cpu_voltage_gpio, 0);
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+ break;
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+ default:
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+ pr_err("%s %d: unsupport volatge %d\n", __func__,__LINE__, target_volatge);
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+ return -EINVAL;
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+ }
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+ return 0;
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+}
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+
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static int eswin_calc_pll(u32 *frac_val, u32 *postdiv1_val,
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u32 *fbdiv_val, u32 *refdiv_val, u64 rate,
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const struct eswin_clk_pll *clk)
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@@ -328,6 +348,40 @@ static int clk_pll_set_rate(struct clk_hw *hw,
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clk_disable_unprepare(clk_cpu_lp_pll);
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return -EPERM;
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}
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+ /*
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+ The CPU clock has now switched to the LP_PLL, so we can adjust the CPU's supply voltage
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+ If the board cpu voltage does not support boosting to 0.9V, then the frequency cannot exceed 1.6GHz.
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+ */
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+ switch (rate) {
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+ case CLK_FREQ_1800M:
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+ case CLK_FREQ_1700M:
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+ case CLK_FREQ_1600M:
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+ ret = eswin_clk_set_cpu_volatge(clk->cpu_voltage_gpio, VOLTAGE_0_9V);
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+ if (ret) {
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+ pr_warn("Failed to change cpu volatge to 0.9V, not support rate %ld\n", rate);
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+ goto switch_back;
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+ } else {
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+ if (clk->cpu_current_volatge != VOLTAGE_0_9V) {
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+ pr_info("Cpu volatge change to 0.9V, target rate %ld\n", rate);
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+ clk->cpu_current_volatge = VOLTAGE_0_9V;
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+ }
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+ }
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+ break;
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+ default:
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+ ret = eswin_clk_set_cpu_volatge(clk->cpu_voltage_gpio, VOLTAGE_0_8V);
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+ if (!ret) {
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+ if (clk->cpu_current_volatge != VOLTAGE_0_8V) {
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+ pr_info("cpu volatge change to 0.8V, target rate %ld\n", rate);
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+ clk->cpu_current_volatge = VOLTAGE_0_8V;
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+ }
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+ }
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+ /*
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+ For boards that do not support voltage switching, the voltage is maintained at 0.8V.
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+ Therefore, this is also considered successful.
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+ */
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+ ret = 0;
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+ break;
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+ }
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}
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/*first disable pll */
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@@ -375,6 +429,8 @@ static int clk_pll_set_rate(struct clk_hw *hw,
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pr_err("%s %d, faild to lock the cpu pll, cpu will work on low power pll\n",__func__,__LINE__);
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return -EBUSY;
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}
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+
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+switch_back:
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if (WIN2030_PLL_CPU == clk->id) {
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ret = clk_set_parent(clk_cpu_mux, clk_cpu_pll);
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if (ret) {
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@@ -384,7 +440,7 @@ static int clk_pll_set_rate(struct clk_hw *hw,
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}
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clk_disable_unprepare(clk_cpu_lp_pll);
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}
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- return 0;
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+ return ret;
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}
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static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
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@@ -539,12 +595,21 @@ void eswin_clk_register_pll(struct eswin_pll_clock *clks,
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struct clk *clk = NULL;
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struct clk_init_data init;
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int i;
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+ struct gpio_desc *cpu_voltage_gpio;
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p_clk = devm_kzalloc(dev, sizeof(*p_clk) * nums, GFP_KERNEL);
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if (!p_clk)
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return;
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+ cpu_voltage_gpio = devm_gpiod_get(dev, "cpu-voltage", GPIOD_OUT_HIGH);
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+ if (IS_ERR_OR_NULL(cpu_voltage_gpio)) {
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+ dev_warn(dev, "failed to get cpu volatge gpio\n");
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+ cpu_voltage_gpio = NULL;
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+ } else {
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+ /*cpu default freq is 1400M, the volatge should be VOLTAGE_0_8V*/
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+ eswin_clk_set_cpu_volatge(cpu_voltage_gpio, VOLTAGE_0_8V);
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+ }
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for (i = 0; i < nums; i++) {
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char *name = kzalloc(strlen(clks[i].name)
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+ 2 * sizeof(char) + sizeof(int), GFP_KERNEL);
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@@ -593,6 +658,7 @@ void eswin_clk_register_pll(struct eswin_pll_clock *clks,
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p_clk->lock_width = clks[i].lock_width;
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p_clk->hw.init = &init;
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+ p_clk->cpu_voltage_gpio = cpu_voltage_gpio;
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clk = clk_register(dev, &p_clk->hw);
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if (IS_ERR(clk)) {
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@@ -603,6 +669,7 @@ void eswin_clk_register_pll(struct eswin_pll_clock *clks,
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data->clk_data.clks[clks[i].id] = clk;
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p_clk++;
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+
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kfree(name);
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if (parent_name) {
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kfree(parent_name);
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diff --git a/drivers/clk/eswin/clk.h b/drivers/clk/eswin/clk.h
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index c5906c420769..95e222d5194c 100755
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--- a/drivers/clk/eswin/clk.h
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+++ b/drivers/clk/eswin/clk.h
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@@ -128,6 +128,11 @@ struct eswin_pll_clock {
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const u8 lock_width;
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};
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+enum voltage_level {
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+ VOLTAGE_0_9V = 900, // Represents 0.9V in millivolts
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+ VOLTAGE_0_8V = 800 // Represents 0.8V in millivolts
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+};
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+
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struct eswin_clk_pll {
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struct clk_hw hw;
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u32 id;
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@@ -153,6 +158,8 @@ struct eswin_clk_pll {
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void __iomem *status_reg;
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u8 lock_shift;
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u8 lock_width;
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+ struct gpio_desc *cpu_voltage_gpio;
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+ enum voltage_level cpu_current_volatge;
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};
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struct eswin_clock_data *eswin_clk_init(struct platform_device *, int);
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--
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2.47.0
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