232 lines
8.0 KiB
Diff
232 lines
8.0 KiB
Diff
From e7e3837f6395e44b5b5fb7cdbcccaba5baf76803 Mon Sep 17 00:00:00 2001
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From: Ben Skeggs <bskeggs@redhat.com>
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Date: Fri, 22 Oct 2010 10:26:24 +1000
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Subject: [PATCH] drm-nouveau-nv86-bug
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drm/nv50: implement possible workaround for NV86 PGRAPH TLB flush hang
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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---
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drivers/gpu/drm/nouveau/nouveau_drv.h | 5 +++
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drivers/gpu/drm/nouveau/nouveau_mem.c | 14 +++-----
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drivers/gpu/drm/nouveau/nouveau_sgdma.c | 8 ++--
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drivers/gpu/drm/nouveau/nouveau_state.c | 10 ++++++
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drivers/gpu/drm/nouveau/nv50_fifo.c | 5 +++
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drivers/gpu/drm/nouveau/nv50_graph.c | 52 +++++++++++++++++++++++++++++++
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drivers/gpu/drm/nouveau/nv50_instmem.c | 1 -
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7 files changed, 82 insertions(+), 13 deletions(-)
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diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
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index be53e92..4273390 100644
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--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
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+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
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@@ -304,6 +304,7 @@ struct nouveau_fifo_engine {
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void (*destroy_context)(struct nouveau_channel *);
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int (*load_context)(struct nouveau_channel *);
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int (*unload_context)(struct drm_device *);
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+ void (*tlb_flush)(struct drm_device *dev);
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};
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struct nouveau_pgraph_object_method {
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@@ -336,6 +337,7 @@ struct nouveau_pgraph_engine {
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void (*destroy_context)(struct nouveau_channel *);
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int (*load_context)(struct nouveau_channel *);
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int (*unload_context)(struct drm_device *);
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+ void (*tlb_flush)(struct drm_device *dev);
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void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
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uint32_t size, uint32_t pitch);
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@@ -944,6 +946,7 @@ extern int nv50_fifo_create_context(struct nouveau_channel *);
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extern void nv50_fifo_destroy_context(struct nouveau_channel *);
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extern int nv50_fifo_load_context(struct nouveau_channel *);
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extern int nv50_fifo_unload_context(struct drm_device *);
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+extern void nv50_fifo_tlb_flush(struct drm_device *dev);
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/* nvc0_fifo.c */
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extern int nvc0_fifo_init(struct drm_device *);
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@@ -1021,6 +1024,8 @@ extern int nv50_graph_load_context(struct nouveau_channel *);
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extern int nv50_graph_unload_context(struct drm_device *);
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extern void nv50_graph_context_switch(struct drm_device *);
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extern int nv50_grctx_init(struct nouveau_grctx *);
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+extern void nv50_graph_tlb_flush(struct drm_device *dev);
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+extern void nv86_graph_tlb_flush(struct drm_device *dev);
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/* nvc0_graph.c */
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extern int nvc0_graph_init(struct drm_device *);
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diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
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index 4f0ae39..514ad9f 100644
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--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
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+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
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@@ -173,11 +173,10 @@ nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
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}
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}
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}
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- dev_priv->engine.instmem.flush(dev);
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- nv50_vm_flush(dev, 5);
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- nv50_vm_flush(dev, 0);
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- nv50_vm_flush(dev, 4);
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+ dev_priv->engine.instmem.flush(dev);
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+ dev_priv->engine.fifo.tlb_flush(dev);
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+ dev_priv->engine.graph.tlb_flush(dev);
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nv50_vm_flush(dev, 6);
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return 0;
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}
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@@ -207,11 +206,10 @@ nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size)
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pte++;
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}
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}
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- dev_priv->engine.instmem.flush(dev);
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- nv50_vm_flush(dev, 5);
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- nv50_vm_flush(dev, 0);
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- nv50_vm_flush(dev, 4);
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+ dev_priv->engine.instmem.flush(dev);
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+ dev_priv->engine.fifo.tlb_flush(dev);
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+ dev_priv->engine.graph.tlb_flush(dev);
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nv50_vm_flush(dev, 6);
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}
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diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
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index 7f028fe..d55a583 100644
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--- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c
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+++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
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@@ -120,8 +120,8 @@ nouveau_sgdma_bind(struct ttm_backend *be, struct ttm_mem_reg *mem)
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dev_priv->engine.instmem.flush(nvbe->dev);
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if (dev_priv->card_type == NV_50) {
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- nv50_vm_flush(dev, 5); /* PGRAPH */
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- nv50_vm_flush(dev, 0); /* PFIFO */
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+ dev_priv->engine.fifo.tlb_flush(dev);
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+ dev_priv->engine.graph.tlb_flush(dev);
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}
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nvbe->bound = true;
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@@ -162,8 +162,8 @@ nouveau_sgdma_unbind(struct ttm_backend *be)
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dev_priv->engine.instmem.flush(nvbe->dev);
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if (dev_priv->card_type == NV_50) {
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- nv50_vm_flush(dev, 5);
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- nv50_vm_flush(dev, 0);
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+ dev_priv->engine.fifo.tlb_flush(dev);
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+ dev_priv->engine.graph.tlb_flush(dev);
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}
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nvbe->bound = false;
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diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
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index be85960..47c353c 100644
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--- a/drivers/gpu/drm/nouveau/nouveau_state.c
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+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
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@@ -333,6 +333,15 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
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engine->graph.destroy_context = nv50_graph_destroy_context;
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engine->graph.load_context = nv50_graph_load_context;
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engine->graph.unload_context = nv50_graph_unload_context;
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+ if (dev_priv->chipset != 0x86)
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+ engine->graph.tlb_flush = nv50_graph_tlb_flush;
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+ else {
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+ /* from what i can see nvidia do this on every
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+ * pre-NVA3 board except NVAC, but, we've only
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+ * ever seen problems on NV86
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+ */
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+ engine->graph.tlb_flush = nv86_graph_tlb_flush;
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+ }
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engine->fifo.channels = 128;
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engine->fifo.init = nv50_fifo_init;
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engine->fifo.takedown = nv50_fifo_takedown;
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@@ -344,6 +353,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
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engine->fifo.destroy_context = nv50_fifo_destroy_context;
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engine->fifo.load_context = nv50_fifo_load_context;
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engine->fifo.unload_context = nv50_fifo_unload_context;
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+ engine->fifo.tlb_flush = nv50_fifo_tlb_flush;
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engine->display.early_init = nv50_display_early_init;
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engine->display.late_takedown = nv50_display_late_takedown;
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engine->display.create = nv50_display_create;
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diff --git a/drivers/gpu/drm/nouveau/nv50_fifo.c b/drivers/gpu/drm/nouveau/nv50_fifo.c
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index a46a961..1da65bd 100644
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--- a/drivers/gpu/drm/nouveau/nv50_fifo.c
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+++ b/drivers/gpu/drm/nouveau/nv50_fifo.c
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@@ -464,3 +464,8 @@ nv50_fifo_unload_context(struct drm_device *dev)
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return 0;
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}
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+void
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+nv50_fifo_tlb_flush(struct drm_device *dev)
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+{
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+ nv50_vm_flush(dev, 5);
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+}
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diff --git a/drivers/gpu/drm/nouveau/nv50_graph.c b/drivers/gpu/drm/nouveau/nv50_graph.c
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index cbf5ae2..8b669d0 100644
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--- a/drivers/gpu/drm/nouveau/nv50_graph.c
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+++ b/drivers/gpu/drm/nouveau/nv50_graph.c
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@@ -402,3 +402,55 @@ struct nouveau_pgraph_object_class nv50_graph_grclass[] = {
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{ 0x8597, false, NULL }, /* tesla (nva3, nva5, nva8) */
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{}
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};
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+
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+void
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+nv50_graph_tlb_flush(struct drm_device *dev)
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+{
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+ nv50_vm_flush(dev, 0);
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+}
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+
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+void
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+nv86_graph_tlb_flush(struct drm_device *dev)
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+{
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+ struct drm_nouveau_private *dev_priv = dev->dev_private;
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+ struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
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+ bool idle, timeout = false;
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+ unsigned long flags;
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+ u64 start;
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+ u32 tmp;
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+
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+ spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
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+ nv_mask(dev, 0x400500, 0x00000001, 0x00000000);
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+
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+ start = ptimer->read(dev);
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+ do {
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+ idle = true;
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+
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+ for (tmp = nv_rd32(dev, 0x400380); tmp && idle; tmp >>= 3) {
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+ if ((tmp & 7) == 1)
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+ idle = false;
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+ }
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+
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+ for (tmp = nv_rd32(dev, 0x400384); tmp && idle; tmp >>= 3) {
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+ if ((tmp & 7) == 1)
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+ idle = false;
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+ }
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+
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+ for (tmp = nv_rd32(dev, 0x400388); tmp && idle; tmp >>= 3) {
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+ if ((tmp & 7) == 1)
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+ idle = false;
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+ }
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+ } while (!idle && !(timeout = ptimer->read(dev) - start > 2000000000));
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+
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+ if (timeout) {
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+ NV_ERROR(dev, "PGRAPH TLB flush idle timeout fail: "
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+ "0x%08x 0x%08x 0x%08x 0x%08x\n",
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+ nv_rd32(dev, 0x400700), nv_rd32(dev, 0x400380),
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+ nv_rd32(dev, 0x400384), nv_rd32(dev, 0x400388));
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+ }
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+
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+ nv50_vm_flush(dev, 0);
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+
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+ nv_mask(dev, 0x400500, 0x00000001, 0x00000001);
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+ spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
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+}
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diff --git a/drivers/gpu/drm/nouveau/nv50_instmem.c b/drivers/gpu/drm/nouveau/nv50_instmem.c
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index ac3de05..c836ddc 100644
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--- a/drivers/gpu/drm/nouveau/nv50_instmem.c
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+++ b/drivers/gpu/drm/nouveau/nv50_instmem.c
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@@ -402,7 +402,6 @@ nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
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}
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dev_priv->engine.instmem.flush(dev);
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- nv50_vm_flush(dev, 4);
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nv50_vm_flush(dev, 6);
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gpuobj->im_bound = 1;
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--
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1.7.3.1
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