116 lines
3.6 KiB
Diff
116 lines
3.6 KiB
Diff
From cd7240c0b900eb6d690ccee088a6c9b46dae815a Mon Sep 17 00:00:00 2001
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From: Suresh Siddha <suresh.b.siddha@intel.com>
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Date: Thu, 19 Aug 2010 17:03:38 -0700
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Subject: x86, tsc, sched: Recompute cyc2ns_offset's during resume from sleep states
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From: Suresh Siddha <suresh.b.siddha@intel.com>
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commit cd7240c0b900eb6d690ccee088a6c9b46dae815a upstream.
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TSC's get reset after suspend/resume (even on cpu's with invariant TSC
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which runs at a constant rate across ACPI P-, C- and T-states). And in
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some systems BIOS seem to reinit TSC to arbitrary large value (still
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sync'd across cpu's) during resume.
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This leads to a scenario of scheduler rq->clock (sched_clock_cpu()) less
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than rq->age_stamp (introduced in 2.6.32). This leads to a big value
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returned by scale_rt_power() and the resulting big group power set by the
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update_group_power() is causing improper load balancing between busy and
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idle cpu's after suspend/resume.
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This resulted in multi-threaded workloads (like kernel-compilation) go
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slower after suspend/resume cycle on core i5 laptops.
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Fix this by recomputing cyc2ns_offset's during resume, so that
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sched_clock() continues from the point where it was left off during
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suspend.
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Reported-by: Florian Pritz <flo@xssn.at>
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Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
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Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
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LKML-Reference: <1282262618.2675.24.camel@sbsiddha-MOBL3.sc.intel.com>
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Signed-off-by: Ingo Molnar <mingo@elte.hu>
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Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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---
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arch/x86/include/asm/tsc.h | 2 ++
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arch/x86/kernel/tsc.c | 38 ++++++++++++++++++++++++++++++++++++++
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arch/x86/power/cpu.c | 2 ++
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3 files changed, 42 insertions(+)
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--- a/arch/x86/include/asm/tsc.h
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+++ b/arch/x86/include/asm/tsc.h
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@@ -59,5 +59,7 @@ extern void check_tsc_sync_source(int cp
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extern void check_tsc_sync_target(void);
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extern int notsc_setup(char *);
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+extern void save_sched_clock_state(void);
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+extern void restore_sched_clock_state(void);
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#endif /* _ASM_X86_TSC_H */
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--- a/arch/x86/kernel/tsc.c
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+++ b/arch/x86/kernel/tsc.c
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@@ -626,6 +626,44 @@ static void set_cyc2ns_scale(unsigned lo
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local_irq_restore(flags);
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}
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+static unsigned long long cyc2ns_suspend;
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+
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+void save_sched_clock_state(void)
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+{
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+ if (!sched_clock_stable)
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+ return;
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+
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+ cyc2ns_suspend = sched_clock();
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+}
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+
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+/*
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+ * Even on processors with invariant TSC, TSC gets reset in some the
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+ * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
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+ * arbitrary value (still sync'd across cpu's) during resume from such sleep
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+ * states. To cope up with this, recompute the cyc2ns_offset for each cpu so
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+ * that sched_clock() continues from the point where it was left off during
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+ * suspend.
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+ */
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+void restore_sched_clock_state(void)
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+{
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+ unsigned long long offset;
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+ unsigned long flags;
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+ int cpu;
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+
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+ if (!sched_clock_stable)
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+ return;
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+
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+ local_irq_save(flags);
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+
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+ get_cpu_var(cyc2ns_offset) = 0;
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+ offset = cyc2ns_suspend - sched_clock();
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+
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+ for_each_possible_cpu(cpu)
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+ per_cpu(cyc2ns_offset, cpu) = offset;
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+
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+ local_irq_restore(flags);
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+}
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+
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#ifdef CONFIG_CPU_FREQ
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/* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
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--- a/arch/x86/power/cpu.c
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+++ b/arch/x86/power/cpu.c
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@@ -112,6 +112,7 @@ static void __save_processor_state(struc
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void save_processor_state(void)
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{
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__save_processor_state(&saved_context);
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+ save_sched_clock_state();
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}
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#ifdef CONFIG_X86_32
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EXPORT_SYMBOL(save_processor_state);
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@@ -253,6 +254,7 @@ static void __restore_processor_state(st
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void restore_processor_state(void)
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{
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__restore_processor_state(&saved_context);
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+ restore_sched_clock_state();
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}
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#ifdef CONFIG_X86_32
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EXPORT_SYMBOL(restore_processor_state);
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