158 lines
4.9 KiB
Diff
158 lines
4.9 KiB
Diff
From: Stephen Hemminger <shemminger@vyatta.com>
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Date: Thu, 29 Oct 2009 06:37:09 +0000 (+0000)
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Subject: sky2: 88E8059 support
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X-Git-Tag: v2.6.33-rc1~388^2~588
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X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Ftorvalds%2Flinux-2.6.git;a=commitdiff_plain;h=0f5aac7070a01ec757ed243febe4fff7c944c4d2
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sky2: 88E8059 support
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Tentative support for newer Marvell hardware including
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the Yukon-2 Optima chip. Do not have hatdware to test this yet,
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code is based on vendor driver.
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Signed-off-by: Stephen Hemminger <shemminger@vyatta.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
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index 3387a2f..53cce74 100644
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--- a/drivers/net/sky2.c
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+++ b/drivers/net/sky2.c
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@@ -140,6 +140,7 @@ static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
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+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
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{ 0 }
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};
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@@ -603,6 +604,16 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
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/* apply workaround for integrated resistors calibration */
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gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
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gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
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+ } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
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+ /* apply fixes in PHY AFE */
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+ gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
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+
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+ /* apply RDAC termination workaround */
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+ gm_phy_write(hw, port, 24, 0x2800);
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+ gm_phy_write(hw, port, 23, 0x2001);
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+
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+ /* set page register back to 0 */
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+ gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
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} else if (hw->chip_id != CHIP_ID_YUKON_EX &&
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hw->chip_id < CHIP_ID_YUKON_SUPR) {
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/* no effect on Yukon-XL */
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@@ -2127,6 +2138,25 @@ out:
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spin_unlock(&sky2->phy_lock);
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}
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+/* Special quick link interrupt (Yukon-2 Optima only) */
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+static void sky2_qlink_intr(struct sky2_hw *hw)
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+{
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+ struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
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+ u32 imask;
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+ u16 phy;
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+
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+ /* disable irq */
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+ imask = sky2_read32(hw, B0_IMSK);
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+ imask &= ~Y2_IS_PHY_QLNK;
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+ sky2_write32(hw, B0_IMSK, imask);
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+
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+ /* reset PHY Link Detect */
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+ phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
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+ sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
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+
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+ sky2_link_up(sky2);
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+}
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+
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/* Transmit timeout is only called if we are running, carrier is up
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* and tx queue is full (stopped).
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*/
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@@ -2796,6 +2826,9 @@ static int sky2_poll(struct napi_struct *napi, int work_limit)
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if (status & Y2_IS_IRQ_PHY2)
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sky2_phy_intr(hw, 1);
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+ if (status & Y2_IS_PHY_QLNK)
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+ sky2_qlink_intr(hw);
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+
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while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
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work_done += sky2_status_intr(hw, work_limit - work_done, idx);
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@@ -2845,6 +2878,7 @@ static u32 sky2_mhz(const struct sky2_hw *hw)
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case CHIP_ID_YUKON_EX:
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case CHIP_ID_YUKON_SUPR:
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case CHIP_ID_YUKON_UL_2:
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+ case CHIP_ID_YUKON_OPT:
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return 125;
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case CHIP_ID_YUKON_FE:
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@@ -2934,6 +2968,7 @@ static int __devinit sky2_init(struct sky2_hw *hw)
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break;
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case CHIP_ID_YUKON_UL_2:
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+ case CHIP_ID_YUKON_OPT:
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hw->flags = SKY2_HW_GIGABIT
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| SKY2_HW_ADV_POWER_CTL;
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break;
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@@ -3024,6 +3059,46 @@ static void sky2_reset(struct sky2_hw *hw)
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sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
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}
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+ if (hw->chip_id == CHIP_ID_YUKON_OPT) {
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+ u16 reg;
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+ u32 msk;
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+
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+ if (hw->chip_rev == 0) {
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+ /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
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+ sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
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+
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+ /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
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+ reg = 10;
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+ } else {
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+ /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
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+ reg = 3;
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+ }
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+
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+ reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
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+
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+ /* reset PHY Link Detect */
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+ sky2_pci_write16(hw, PSM_CONFIG_REG4,
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+ reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
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+ sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
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+
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+
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+ /* enable PHY Quick Link */
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+ msk = sky2_read32(hw, B0_IMSK);
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+ msk |= Y2_IS_PHY_QLNK;
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+ sky2_write32(hw, B0_IMSK, msk);
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+
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+ /* check if PSMv2 was running before */
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+ reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
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+ if (reg & PCI_EXP_LNKCTL_ASPMC) {
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+ int cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
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+ /* restore the PCIe Link Control register */
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+ sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
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+ }
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+
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+ /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
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+ sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
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+ }
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+
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/* Clear I2C IRQ noise */
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sky2_write32(hw, B2_I2C_IRQ, 1);
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@@ -4442,9 +4517,11 @@ static const char *sky2_name(u8 chipid, char *buf, int sz)
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"FE+", /* 0xb8 */
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"Supreme", /* 0xb9 */
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"UL 2", /* 0xba */
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+ "Unknown", /* 0xbb */
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+ "Optima", /* 0xbc */
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};
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- if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
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+ if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_OPT)
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strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
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else
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snprintf(buf, sz, "(chip %#x)", chipid);
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