From b40b54dd65c93525f008c0ad0a02ee50cf8bc429 Mon Sep 17 00:00:00 2001 From: huangyifeng Date: Wed, 25 Sep 2024 16:04:43 +0800 Subject: [PATCH 178/219] feat:fix clock&pmic&noc init initialization order Changelogs: 1. when the device tree node of the clock controller references a GPIO property, the clock controller driver will be initialized after the GPIO controller driver. However, the GPIO controller is defined in the device_initcall stage. Therefore, the clock controller driver cannot be defined in the arch_initcall stage. 2.Add a reference to the regulator node in the LLC node in the device tree to determine the initialization order of the two drivers 3.Noc driver init in device_initcall stage Signed-off-by: huangyifeng Signed-off-by: yangwei1 --- arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts | 4 +++- arch/riscv/boot/dts/eswin/eic7700-evb.dts | 4 +++- .../boot/dts/eswin/eic7700-hifive-premier-p550.dts | 6 ++++-- arch/riscv/boot/dts/eswin/eic7702-evb-a1-d0.dts | 4 +++- arch/riscv/boot/dts/eswin/eic7702-evb-a1-d1.dts | 4 +++- drivers/clk/eswin/clk-win2030.c | 9 ++++----- drivers/interconnect/eswin/noc.c | 11 +++-------- drivers/memory/eswin/codacache/llc_spram.c | 11 ++++++----- 8 files changed, 29 insertions(+), 24 deletions(-) diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts index 5a979e84d2c9..83b656f6c481 100644 --- a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts +++ b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts @@ -895,5 +895,7 @@ &gpio0 { status = "okay"; }; &dev_llc_d0{ - apply_npu_high_freq; + /* apply_npu_1G_freq; */ + npu-supply=<&npu_vcc1>; + status = "okay"; }; diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb.dts b/arch/riscv/boot/dts/eswin/eic7700-evb.dts index 20fe88d55119..d99fe95e2a31 100644 --- a/arch/riscv/boot/dts/eswin/eic7700-evb.dts +++ b/arch/riscv/boot/dts/eswin/eic7700-evb.dts @@ -875,5 +875,7 @@ &gpio0 { status = "okay"; }; &dev_llc_d0{ - apply_npu_high_freq; + /* apply_npu_1G_freq; */ + npu-supply=<&npu_vcc1>; + status = "okay"; }; diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts index 9cacb373b3bc..573b1e7d148d 100644 --- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts @@ -818,8 +818,10 @@ &gpio0 { status = "okay"; }; -&dev_llc_d0 { - apply_npu_high_freq; +&dev_llc_d0{ + /* apply_npu_1G_freq; */ + npu-supply=<&npu_vcc1>; + status = "okay"; }; &d0_clock { diff --git a/arch/riscv/boot/dts/eswin/eic7702-evb-a1-d0.dts b/arch/riscv/boot/dts/eswin/eic7702-evb-a1-d0.dts index 52cec742b771..8c558119a286 100644 --- a/arch/riscv/boot/dts/eswin/eic7702-evb-a1-d0.dts +++ b/arch/riscv/boot/dts/eswin/eic7702-evb-a1-d0.dts @@ -808,6 +808,8 @@ &gpio0 { status = "okay"; }; &dev_llc_d0{ - apply_npu_high_freq; + /* apply_npu_1G_freq; */ + npu-supply=<&npu_vcc1>; + status = "okay"; }; diff --git a/arch/riscv/boot/dts/eswin/eic7702-evb-a1-d1.dts b/arch/riscv/boot/dts/eswin/eic7702-evb-a1-d1.dts index d065b67d3dda..2733649b4c3f 100644 --- a/arch/riscv/boot/dts/eswin/eic7702-evb-a1-d1.dts +++ b/arch/riscv/boot/dts/eswin/eic7702-evb-a1-d1.dts @@ -823,6 +823,8 @@ &gpio0 { status = "okay"; }; &dev_llc_d0{ - apply_npu_high_freq; + /* apply_npu_1G_freq; */ + npu-supply=<&npu_vcc1>; + status = "okay"; }; diff --git a/drivers/clk/eswin/clk-win2030.c b/drivers/clk/eswin/clk-win2030.c index b7c382133ccc..ccb7dade5475 100755 --- a/drivers/clk/eswin/clk-win2030.c +++ b/drivers/clk/eswin/clk-win2030.c @@ -1222,8 +1222,7 @@ static struct platform_driver eswin_clock_driver = { .of_match_table = eswin_clock_dt_ids, }, }; -static int __init win2030_clk_init(void) -{ - return platform_driver_register(&eswin_clock_driver); -} -arch_initcall(win2030_clk_init); +module_platform_driver(eswin_clock_driver); +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("huangyifeng"); +MODULE_DESCRIPTION("Eswin EIC770X clock controller driver"); diff --git a/drivers/interconnect/eswin/noc.c b/drivers/interconnect/eswin/noc.c index cd577ec7c116..2bcbe3f48f59 100644 --- a/drivers/interconnect/eswin/noc.c +++ b/drivers/interconnect/eswin/noc.c @@ -2323,19 +2323,14 @@ static struct platform_driver win2030_noc_driver = { .of_match_table = of_match_ptr(win2030_noc_of_match),}, }; -static int __init win2030_noc_init(void) -{ - return platform_driver_register(&win2030_noc_driver); -} - static void __exit win2030_noc_exit(void) { platform_driver_unregister(&win2030_noc_driver); } -subsys_initcall(win2030_noc_init); +module_platform_driver(win2030_noc_driver); module_exit(win2030_noc_exit); -MODULE_AUTHOR("huangyifeng@eswincomputing.com"); +MODULE_AUTHOR("huangyifeng"); MODULE_VERSION("1.0.0"); -MODULE_LICENSE("GPL"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/memory/eswin/codacache/llc_spram.c b/drivers/memory/eswin/codacache/llc_spram.c index c26567e5aa80..ed71d83c3060 100644 --- a/drivers/memory/eswin/codacache/llc_spram.c +++ b/drivers/memory/eswin/codacache/llc_spram.c @@ -751,13 +751,13 @@ static int llc_clk_set_parent(struct platform_device *pdev, u8 *is_low_freq) if (spram == NULL) return -EINVAL; np = of_node_get(dev->of_node); - npu_regulator = devm_regulator_get_exclusive(dev, "NPU_SVCC"); + npu_regulator = devm_regulator_get_exclusive(dev, "npu"); if ((NULL == npu_regulator) || (IS_ERR(npu_regulator))) { - dev_warn(dev, "failed to get npu regulator\n"); - *is_low_freq = 0; - return -ENODEV; + dev_warn(dev, "failed to get npu regulator,the npu freq will set to 1G\n"); + *is_low_freq = 1; + //return -ENODEV; } else { @@ -769,6 +769,7 @@ static int llc_clk_set_parent(struct platform_device *pdev, u8 *is_low_freq) if (0 == *is_low_freq) { ret = regulator_set_voltage(npu_regulator, NPU_1P5G_VOLTAGE, NPU_1P5G_VOLTAGE); + dev_dbg(dev,"name:%s,volt:%d,ret:%d\n",pdev->name,NPU_1P5G_VOLTAGE,ret); if(0 != ret) { dev_err(dev, "set volt:%duV ret:%d\n", NPU_1P5G_VOLTAGE,ret); @@ -784,7 +785,7 @@ static int llc_clk_set_parent(struct platform_device *pdev, u8 *is_low_freq) if (((NULL != npu_regulator)) && (!IS_ERR(npu_regulator))) { regulator_set_voltage(npu_regulator, NPU_DEFAULT_VOLTAGE, NPU_DEFAULT_VOLTAGE); - dev_dbg(dev, "set volt:%duV ret:%d\n", NPU_1P5G_VOLTAGE,ret); + dev_dbg(dev,"name:%s,volt:%d,ret:%d\n", pdev->name,NPU_DEFAULT_VOLTAGE,ret); /* devm_regulator_put(npu_regulator); */ mdelay(10); } -- 2.47.0