From cf27cca5f287108e0c91643289fb431a77c1ece8 Mon Sep 17 00:00:00 2001 From: ningyu Date: Thu, 1 Aug 2024 17:32:12 +0800 Subject: [PATCH 134/219] refactor:modify evb1 dts Changelogs: 1. Modify evb1 dts, adjust mmz size to 6GB, in order to consistent with other board. Signed-off-by: ningyu --- arch/riscv/boot/dts/eswin/eic7700-evb.dts | 48 +++++------------------ 1 file changed, 10 insertions(+), 38 deletions(-) diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb.dts b/arch/riscv/boot/dts/eswin/eic7700-evb.dts index fc7dd40a4bc4..854bd4a80e1d 100644 --- a/arch/riscv/boot/dts/eswin/eic7700-evb.dts +++ b/arch/riscv/boot/dts/eswin/eic7700-evb.dts @@ -23,9 +23,9 @@ #define RTCCLK_FREQ 1000000 #define LSPCLK_FREQ 200000000 -/* reserve 2GB space for ddr ecc */ -#define MEMORY_SIZE_H 0x3 -#define MEMORY_SIZE_L 0x80000000 +/* If wanna enable ECC capability of DDR, should reserve highest zone of 1/8 all space for it */ +#define MEMORY_SIZE_H 0x4 +#define MEMORY_SIZE_L 0x0 #define CMA_SIZE 0x20000000 #include "eswin-win2030-die0-soc.dtsi" @@ -89,54 +89,26 @@ npu0_reserved: sprammemory@59000000 { reg = <0x0 0x59000000 0x0 0x400000>; }; - smpmemtest_rsv0@91200000 { - reg = <0 0x91200000 0 0x2000000>; - no-map; - }; - - lpcpu0_reserved: lpcpu@a0000000 { + g2d_4GB_boundary_reserved_4k { no-map; - reg = <0x0 0xa0000000 0x0 0x100000>; + reg = <0x0 0xfffff000 0x0 0x1000>; }; - secure_memory_nid_0_part_0 { - compatible = "eswin-reserve-memory"; - reg = <0x0 0xb0000000 0x0 0x8000000>; + g2d_8GB_boundary_reserved_4k { no-map; + reg = <0x1 0xfffff000 0x0 0x1000>; }; - secure_memory_nid_0_part_1 { - compatible = "eswin-reserve-memory"; - reg = <0x0 (0xb0000000 + 0x8000000) 0x0 0x8000000>; + g2d_12GB_boundary_reserved_4k { no-map; - }; - - g2d_4GB_boundary_reserved_4k { - no-map; - reg = <0x0 0xfffff000 0x0 0x1000>; + reg = <0x2 0xfffff000 0x0 0x1000>; }; mmz_nid_0_part_0 { compatible = "eswin-reserve-memory"; - reg = <0x1 0x40000000 0x2 0x80000000>; + reg = <0x3 0x0 0x1 0x80000000>; no-map; }; - - mmz_nid_0_part_1 { - compatible = "eswin-reserve-memory"; - reg = <0x3 0xc0000000 0x0 0x40000000>; - no-map; - }; - }; - - soc { - reset_test@1e00e000 { - compatible = "reset_test"; - resets = <&d0_reset SCPU_RST_CTRL SW_SCPU_BUS_RSTN>, - <&d0_reset SCPU_RST_CTRL SW_SCPU_CORE_RSTN>, - <&d0_reset SCPU_RST_CTRL SW_SCPU_DBG_RSTN>; - reset-names = "bus", "core", "dbg"; - }; }; }; -- 2.47.0