From 4d737c2b7b626fce3b004a7cea774c90c3224f32 Mon Sep 17 00:00:00 2001 From: luyulin Date: Fri, 24 May 2024 10:47:11 +0800 Subject: [PATCH 024/219] feat:sata driver to linux 6.6. Changelogs: sata driver to linux 6.6. --- arch/riscv/configs/win2030_defconfig | 1 + drivers/ata/Kconfig | 9 + drivers/ata/Makefile | 1 + drivers/ata/ahci_eswin.c | 341 +++++++++++++++++++++++++++ 4 files changed, 352 insertions(+) create mode 100644 drivers/ata/ahci_eswin.c diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig index 0c9b6e662ed4..f57a7581943b 100644 --- a/arch/riscv/configs/win2030_defconfig +++ b/arch/riscv/configs/win2030_defconfig @@ -73,6 +73,7 @@ CONFIG_BLK_DEV_SD=y # CONFIG_SCSI_LOWLEVEL is not set CONFIG_ATA=y CONFIG_SATA_AHCI=y +CONFIG_AHCI_ESWIN=y CONFIG_NETDEVICES=y # CONFIG_NET_VENDOR_ALACRITECH is not set # CONFIG_NET_VENDOR_AMAZON is not set diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 42b51c9812a0..fcc935629d93 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -136,6 +136,15 @@ config SATA_MOBILE_LPM_POLICY Note "Minimum power" is known to cause issues, including disk corruption, with some disks and should not be used. +config AHCI_ESWIN + tristate "Eswin AHCI SATA support" + select SATA_HOST + help + This option enables support for Eswin AHCI Serial ATA + controllers. + + If unsure, say N. + config SATA_AHCI_PLATFORM tristate "Platform AHCI SATA support" select SATA_HOST diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index 20e6645ab737..a596e5ea5134 100644 --- a/drivers/ata/Makefile +++ b/drivers/ata/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_SATA_INIC162X) += sata_inic162x.o obj-$(CONFIG_SATA_SIL24) += sata_sil24.o obj-$(CONFIG_SATA_DWC) += sata_dwc_460ex.o obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o +obj-$(CONFIG_AHCI_ESWIN) += ahci_eswin.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_BRCM) += ahci_brcm.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_CEVA) += ahci_ceva.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_DA850) += ahci_da850.o libahci.o libahci_platform.o diff --git a/drivers/ata/ahci_eswin.c b/drivers/ata/ahci_eswin.c new file mode 100644 index 000000000000..d9495dfe9887 --- /dev/null +++ b/drivers/ata/ahci_eswin.c @@ -0,0 +1,341 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ESWIN AHCI SATA Driver + * + * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved. + * SPDX-License-Identifier: GPL-2.0 + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 2. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * Authors: Yulin Lu + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ahci.h" + +#define DRV_NAME "ahci" + +#define AWSMMUSID GENMASK(31, 24) // The sid of write operation +#define AWSMMUSSID GENMASK(23, 16) // The ssid of write operation +#define ARSMMUSID GENMASK(15, 8) // The sid of read operation +#define ARSMMUSSID GENMASK(7, 0) // The ssid of read operation +#define SATA_REF_CTRL1 0x338 +#define SATA_PHY_CTRL0 0x328 +#define SATA_PHY_CTRL1 0x32c +#define SATA_LOS_IDEN 0x33c +#define SATA_AXI_LP_CTRL 0x308 +#define SATA_REG_CTRL 0x334 +#define SATA_MPLL_CTRL 0x320 +#define SATA_RESET_CTRL 0x340 +#define SATA_RESET_CTRL_ASSERT 0x3 +#define SATA_RESET_CTRL_DEASSERT 0x0 +#define SATA_PHY_RESET BIT(0) +#define SATA_P0_RESET BIT(1) +#define SATA_LOS_LEVEL 0x9 +#define SATA_LOS_BIAS (0x02 << 16) +#define SATA_REF_REPEATCLK_EN BIT(0) +#define SATA_REF_USE_PAD BIT(20) +#define SATA_P0_AMPLITUDE_GEN1 0x42 +#define SATA_P0_AMPLITUDE_GEN2 (0x46 << 8) +#define SATA_P0_AMPLITUDE_GEN3 (0x73 << 16) +#define SATA_P0_PHY_TX_PREEMPH_GEN1 0x05 +#define SATA_P0_PHY_TX_PREEMPH_GEN2 (0x05 << 8) +#define SATA_P0_PHY_TX_PREEMPH_GEN3 (0x23 << 16) +#define SATA_MPLL_MULTIPLIER (0x3c << 16) +#define SATA_M_CSYSREQ BIT(0) +#define SATA_S_CSYSREQ BIT(16) +#define HSPDME_RST_CTRL 0x41C +#define SW_HSP_SATA_ARSTN BIT(27) +#define SW_SATA_RSTN (0xf << 9) + +static const struct ata_port_info ahci_port_info = { + .flags = AHCI_FLAG_COMMON, + .pio_mask = ATA_PIO4, + .udma_mask = ATA_UDMA6, + .port_ops = &ahci_platform_ops, +}; + +static const struct ata_port_info ahci_port_info_nolpm = { + .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_LPM, + .pio_mask = ATA_PIO4, + .udma_mask = ATA_UDMA6, + .port_ops = &ahci_platform_ops, +}; + +static struct scsi_host_template ahci_platform_sht = { + AHCI_SHT(DRV_NAME), +}; + +static int eswin_sata_sid_cfg(struct device *dev) +{ + int ret; + struct regmap *regmap; + int hsp_mmu_sata_reg; + u32 rdwr_sid_ssid; + u32 sid; + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + + /* not behind smmu, use the default reset value(0x0) of the reg as streamID*/ + if (fwspec == NULL) { + dev_dbg(dev, "dev is not behind smmu, skip configuration of sid\n"); + return 0; + } + sid = fwspec->ids[0]; + regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "eswin,hsp_sp_csr"); + if (IS_ERR(regmap)) { + dev_dbg(dev, "No hsp_sp_csr phandle specified\n"); + return 0; + } + ret = of_property_read_u32_index(dev->of_node, "eswin,hsp_sp_csr", 1, + &hsp_mmu_sata_reg); + if (ret) { + dev_err(dev, "can't get sata sid cfg reg offset (%d)\n", ret); + return ret; + } + + /* make the reading sid the same as writing sid, ssid is fixed to zero */ + rdwr_sid_ssid = FIELD_PREP(AWSMMUSID, sid); + rdwr_sid_ssid |= FIELD_PREP(ARSMMUSID, sid); + rdwr_sid_ssid |= FIELD_PREP(AWSMMUSSID, 0); + rdwr_sid_ssid |= FIELD_PREP(ARSMMUSSID, 0); + regmap_write(regmap, hsp_mmu_sata_reg, rdwr_sid_ssid); + + ret = win2030_dynm_sid_enable(dev_to_node(dev)); + if (ret < 0) + dev_err(dev, "failed to config sata streamID(%d)!\n", sid); + else + dev_dbg(dev, "success to config sata streamID(%d)!\n", sid); + pr_err("eswin_sata_sid_cfg success\n"); + return ret; +} + +static int eswin_sata_init(struct device *dev) +{ + struct regmap *regmap; + regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "eswin,hsp_sp_csr"); + if (IS_ERR(regmap)) { + dev_dbg(dev, "No hsp_sp_csr phandle specified\n"); + return -1; + } + regmap_write(regmap, SATA_REF_CTRL1, 0x1); + regmap_write(regmap, SATA_PHY_CTRL0, (SATA_P0_AMPLITUDE_GEN1|SATA_P0_AMPLITUDE_GEN2|SATA_P0_AMPLITUDE_GEN3)); + regmap_write(regmap, SATA_PHY_CTRL1, (SATA_P0_PHY_TX_PREEMPH_GEN1|SATA_P0_PHY_TX_PREEMPH_GEN2|SATA_P0_PHY_TX_PREEMPH_GEN3)); + regmap_write(regmap, SATA_LOS_IDEN, SATA_LOS_LEVEL|SATA_LOS_BIAS); + regmap_write(regmap, SATA_AXI_LP_CTRL, (SATA_M_CSYSREQ|SATA_S_CSYSREQ)); + regmap_write(regmap, SATA_REG_CTRL, (SATA_REF_REPEATCLK_EN|SATA_REF_USE_PAD)); + regmap_write(regmap, SATA_MPLL_CTRL, SATA_MPLL_MULTIPLIER); + regmap_write(regmap, SATA_RESET_CTRL, 0x0); + return 0; +} + +static int __init eswin_reset(struct device *dev) +{ + struct reset_control *asic0_rst; + struct reset_control *oob_rst; + struct reset_control *pmalive_rst; + struct reset_control *rbc_rst; + struct reset_control *apb_rst; + int rc; + asic0_rst = devm_reset_control_get_shared(dev, "asic0"); + if (IS_ERR_OR_NULL(asic0_rst)) { + dev_err(dev, "Failed to asic0_rst handle\n"); + return -EFAULT; + } + oob_rst = devm_reset_control_get_shared(dev, "oob"); + if (IS_ERR_OR_NULL(oob_rst)) { + dev_err(dev, "Failed to oob_rst handle\n"); + return -EFAULT; + } + pmalive_rst = devm_reset_control_get_shared(dev, "pmalive"); + if (IS_ERR_OR_NULL(pmalive_rst)) { + dev_err(dev, "Failed to pmalive_rst handle\n"); + return -EFAULT; + } + rbc_rst = devm_reset_control_get_shared(dev, "rbc"); + if (IS_ERR_OR_NULL(rbc_rst)) { + dev_err(dev, "Failed to rbc_rst handle\n"); + return -EFAULT; + } + apb_rst = devm_reset_control_get_shared(dev, "apb"); + if (IS_ERR_OR_NULL(apb_rst)) { + dev_err(dev, "Failed to apb_rst handle\n"); + return -EFAULT; + } + printk("eswin sata before reset control deasser\n"); + if (asic0_rst) { + rc = reset_control_deassert(asic0_rst); + WARN_ON(0 != rc); + } + if (oob_rst) { + rc = reset_control_deassert(oob_rst); + WARN_ON(0 != rc); + } + if (pmalive_rst) { + rc = reset_control_deassert(pmalive_rst); + WARN_ON(0 != rc); + } + if (rbc_rst) { + rc = reset_control_deassert(rbc_rst); + WARN_ON(0 != rc); + } + if (apb_rst) { + rc = reset_control_deassert(apb_rst); + WARN_ON(0 != rc); + } + printk("eswin sata after reset control deasser\n"); + return 0; +} + + +static int eswin_unreset(struct device *dev) +{ + struct reset_control *asic0_rst; + struct reset_control *oob_rst; + struct reset_control *pmalive_rst; + struct reset_control *rbc_rst; + int rc; + + asic0_rst = devm_reset_control_get_shared(dev, "asic0"); + if (IS_ERR_OR_NULL(asic0_rst)) { + dev_err(dev, "Failed to asic0_rst handle\n"); + return -EFAULT; + } + oob_rst = devm_reset_control_get_shared(dev, "oob"); + if (IS_ERR_OR_NULL(oob_rst)) { + dev_err(dev, "Failed to oob_rst handle\n"); + return -EFAULT; + } + pmalive_rst = devm_reset_control_get_shared(dev, "pmalive"); + if (IS_ERR_OR_NULL(pmalive_rst)) { + dev_err(dev, "Failed to pmalive_rst handle\n"); + return -EFAULT; + } + rbc_rst = devm_reset_control_get_shared(dev, "rbc"); + if (IS_ERR_OR_NULL(rbc_rst)) { + dev_err(dev, "Failed to rbc_rst handle\n"); + return -EFAULT; + } + if (asic0_rst) { + rc = reset_control_assert(asic0_rst); + WARN_ON(0 != rc); + } + if (oob_rst) { + rc = reset_control_assert(oob_rst); + WARN_ON(0 != rc); + } + if (pmalive_rst) { + rc = reset_control_assert(pmalive_rst); + WARN_ON(0 != rc); + } + if (rbc_rst) { + rc = reset_control_assert(rbc_rst); + WARN_ON(0 != rc); + } + return 0; +} + +static int ahci_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct ahci_host_priv *hpriv; + const struct ata_port_info *port; + int rc; + hpriv = ahci_platform_get_resources(pdev, + 0); + if (IS_ERR(hpriv)) + return PTR_ERR(hpriv); + + rc = eswin_reset(dev); + if (rc) + return rc; + eswin_sata_init(dev); + eswin_sata_sid_cfg(dev); + win2030_tbu_power(&pdev->dev, true); + rc = dma_set_mask_and_coherent(dev,DMA_BIT_MASK(41)); + of_property_read_u32(dev->of_node, + "ports-implemented", &hpriv->saved_port_map); + + if (of_device_is_compatible(dev->of_node, "hisilicon,hisi-ahci")) + hpriv->flags |= AHCI_HFLAG_NO_FBS | AHCI_HFLAG_NO_NCQ; + + port = acpi_device_get_match_data(dev); + if (!port){ + port = &ahci_port_info; + } + rc = ahci_platform_init_host(pdev, hpriv, port, + &ahci_platform_sht); + if (rc) + goto disable_resources; + + return 0; +disable_resources: + ahci_platform_disable_resources(hpriv); + return rc; +} + +static int ahci_remove(struct platform_device *pdev) +{ + win2030_tbu_power(&pdev->dev, false); + eswin_unreset(&pdev->dev); + ata_platform_remove_one(pdev); + return 0; +} + +static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspend, + ahci_platform_resume); + +static const struct of_device_id ahci_of_match[] = { + { .compatible = "snps,eswin-ahci", }, + {}, +}; +MODULE_DEVICE_TABLE(of, ahci_of_match); + +static const struct acpi_device_id ahci_acpi_match[] = { + { "APMC0D33", (unsigned long)&ahci_port_info_nolpm }, + { ACPI_DEVICE_CLASS(PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff) }, + {}, +}; +MODULE_DEVICE_TABLE(acpi, ahci_acpi_match); + +static struct platform_driver ahci_driver = { + .probe = ahci_probe, + .remove = ahci_remove, + .shutdown = ahci_platform_shutdown, + .driver = { + .name = DRV_NAME, + .of_match_table = ahci_of_match, + .acpi_match_table = ahci_acpi_match, + .pm = &ahci_pm_ops, + }, +}; +module_platform_driver(ahci_driver); + +MODULE_DESCRIPTION("ESWIN AHCI SATA driver"); +MODULE_AUTHOR("Lu Yulin "); +MODULE_LICENSE("GPL"); \ No newline at end of file -- 2.47.0