From db67a0946ee163692da7dc12e26f0307593b23ce Mon Sep 17 00:00:00 2001 From: yangwei1 Date: Tue, 28 May 2024 10:37:37 +0800 Subject: [PATCH 036/222] feat(llc_spram):set npu default freq to 1.5G Changelogs: 1.Added apply_npu_high_freq attribute in the dev_llc_d0 dts node to set npu default freq to 1.5G and voltage to 1.05V. If apply_npu_high_freq is not configured, then set npu freq to 1.04G and voltage to 0.8V --- arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts | 3 + arch/riscv/boot/dts/eswin/eic7700-evb.dts | 3 + .../dts/eswin/eswin-win2030-die0-soc.dtsi | 6 +- .../dts/eswin/eswin-win2030-die1-soc.dtsi | 6 +- drivers/memory/eswin/codacache/llc_spram.c | 111 +++++++++++++++--- include/linux/eswin_npu.h | 4 + 6 files changed, 110 insertions(+), 23 deletions(-) diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts index 922db5ee1d4c..584338c8ad4c 100644 --- a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts +++ b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts @@ -902,3 +902,6 @@ gpio111 : mipi dsi resetn(O) &gpio0 { status = "okay"; }; +&dev_llc_d0{ + apply_npu_high_freq; +}; \ No newline at end of file diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb.dts b/arch/riscv/boot/dts/eswin/eic7700-evb.dts index 642a62246b54..4ed625ef7bd3 100644 --- a/arch/riscv/boot/dts/eswin/eic7700-evb.dts +++ b/arch/riscv/boot/dts/eswin/eic7700-evb.dts @@ -879,3 +879,6 @@ gpio111 : mipi dsi resetn(O) &gpio0 { status = "okay"; }; +&dev_llc_d0{ + apply_npu_high_freq; +}; \ No newline at end of file diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi index 0371d532d2ec..7c742eb16669 100644 --- a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi +++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi @@ -533,9 +533,11 @@ dev_llc_d0: llc@51c00000 { <&d0_clock WIN2030_CLK_NPU_LLC_ACLK>, <&d0_clock WIN2030_CLK_NPU_CLK>, <&d0_clock WIN2030_MUX_U_NPU_CORE_3MUX1_GFREE>, - <&d0_clock WIN2030_SPLL2_FOUT2>; + <&d0_clock WIN2030_SPLL2_FOUT2>, + <&d0_clock WIN2030_SPLL1_FOUT1>; clock-names = "aclk", "cfg_clk", "llc_clk", "core_clk", - "mux_u_npu_core_3mux1_gfree", "fixed_rate_clk_spll2_fout2"; + "mux_u_npu_core_3mux1_gfree", "fixed_rate_clk_spll2_fout2", + "fixed_rate_clk_spll1_fout1"; resets = <&d0_reset NPU_RST_CTRL SW_NPU_AXI_RSTN>, <&d0_reset NPU_RST_CTRL SW_NPU_CFG_RSTN>, <&d0_reset NPU_RST_CTRL SW_NPU_CORE_RSTN>, diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi index 9e12379cc7d3..971b506eaf0b 100644 --- a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi +++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi @@ -940,9 +940,11 @@ dev_llc_d1: llc@71c00000 { <&d1_clock WIN2030_CLK_NPU_LLC_ACLK>, <&d1_clock WIN2030_CLK_NPU_CLK>, <&d1_clock WIN2030_MUX_U_NPU_CORE_3MUX1_GFREE>, - <&d1_clock WIN2030_SPLL2_FOUT2>; + <&d1_clock WIN2030_SPLL2_FOUT2>, + <&d0_clock WIN2030_SPLL1_FOUT1>; clock-names = "aclk", "cfg_clk", "llc_clk", "core_clk", - "mux_u_npu_core_3mux1_gfree", "fixed_rate_clk_spll2_fout2"; + "mux_u_npu_core_3mux1_gfree", "fixed_rate_clk_spll2_fout2", + "fixed_rate_clk_spll1_fout1"; resets = <&d1_reset NPU_RST_CTRL SW_NPU_AXI_RSTN>, <&d1_reset NPU_RST_CTRL SW_NPU_CFG_RSTN>, <&d1_reset NPU_RST_CTRL SW_NPU_CORE_RSTN>, diff --git a/drivers/memory/eswin/codacache/llc_spram.c b/drivers/memory/eswin/codacache/llc_spram.c index 2e343f1da43f..01744360937c 100644 --- a/drivers/memory/eswin/codacache/llc_spram.c +++ b/drivers/memory/eswin/codacache/llc_spram.c @@ -40,7 +40,7 @@ #include #include - +#include #include "llc_spram.h" #define HAVE_LLC_HARDWARE 1 @@ -96,6 +96,7 @@ struct spram_dev { struct clk *core_clk; struct clk *mux_u_npu_core_3mux1_gfree; struct clk *fixed_rate_clk_spll2_fout2; + struct clk *fixed_rate_clk_spll1_fout1; struct reset_control *rstc_axi; struct reset_control *rstc_cfg; struct reset_control *rstc_core; @@ -603,6 +604,14 @@ static int llc_clk_init(struct platform_device *pdev) dev_err(&pdev->dev, "failed to get fixed_rate_clk_spll2_fout2: %d\n", ret); return ret; } + spram->fixed_rate_clk_spll1_fout1 = + devm_clk_get(&pdev->dev, "fixed_rate_clk_spll1_fout1"); + if (IS_ERR(spram->fixed_rate_clk_spll1_fout1)) + { + ret = PTR_ERR(spram->fixed_rate_clk_spll1_fout1); + dev_err(&pdev->dev, "failed to get fixed_rate_clk_spll1_fout1: %d\n", ret); + return ret; + } return 0; } @@ -675,23 +684,62 @@ static int llc_rst_init(struct platform_device *pdev) return 0; } -static int llc_clk_set_parent(struct platform_device *pdev) +static int llc_clk_set_parent(struct platform_device *pdev, u8 *is_high_freq) { int ret; struct spram_dev *spram = platform_get_drvdata(pdev); + struct device_node *np; + struct regulator *npu_regulator; + struct device *dev = &pdev->dev; + if (spram == NULL) return -EINVAL; + np = of_node_get(dev->of_node); + npu_regulator = devm_regulator_get_exclusive(dev, "NPU_SVCC"); - ret = clk_set_parent(spram->mux_u_npu_core_3mux1_gfree, spram->fixed_rate_clk_spll2_fout2); - if (ret){ - dev_err(&pdev->dev, "failed to set mux_u_npu_core_3mux1_gfree parent: %d\n", ret); + if ((NULL == npu_regulator) || (IS_ERR(npu_regulator))) + { + dev_warn(dev, "failed to get npu regulator\n"); + *is_high_freq = 0; + } + else + { + *is_high_freq = of_property_read_bool(np, "apply_npu_high_freq"); + dev_dbg(dev, "success to get npu regulator,apply_npu_high_freq:%d\n", + *is_high_freq); + } + if (1 == *is_high_freq) + { + regulator_set_voltage(npu_regulator, NPU_1P5G_VOLTAGE, NPU_1P5G_VOLTAGE); + dev_dbg(dev, "set volt:%duV ret:%d\n", NPU_1P5G_VOLTAGE,ret); + /* devm_regulator_put(npu_regulator); */ + mdelay(10); + ret = clk_set_parent(spram->mux_u_npu_core_3mux1_gfree, + spram->fixed_rate_clk_spll1_fout1); + } + else + { + if (((NULL != npu_regulator)) && (!IS_ERR(npu_regulator))) + { + regulator_set_voltage(npu_regulator, NPU_DEFAULT_VOLTAGE, NPU_DEFAULT_VOLTAGE); + dev_dbg(dev, "set volt:%duV ret:%d\n", NPU_1P5G_VOLTAGE,ret); + /* devm_regulator_put(npu_regulator); */ + mdelay(10); + } + ret = clk_set_parent(spram->mux_u_npu_core_3mux1_gfree, + spram->fixed_rate_clk_spll2_fout2); + } + if (ret) + { + dev_err(&pdev->dev, "failed to set mux_u_npu_core_3mux1_gfree parent: %d\n", + ret); return ret; } return 0; } -static int llc_clk_set_frq(struct platform_device *pdev) +static int llc_clk_set_frq(struct platform_device *pdev, u8 is_high_freq) { int ret; unsigned long rate = 0; @@ -702,23 +750,47 @@ static int llc_clk_set_frq(struct platform_device *pdev) rate = clk_round_rate(spram->aclk, NPU_ACLK_RATE); ret = clk_set_rate(spram->aclk, rate); - if(ret != 0){ + if (ret != 0) + { dev_err(&pdev->dev, "failed to set aclk: %d\n", ret); return ret; } - rate = clk_round_rate(spram->llc_clk, NPU_LLC_CLK_RATE); - ret = clk_set_rate(spram->llc_clk, rate); - if(ret != 0){ - dev_err(&pdev->dev, "failed to set llc_clk: %d\n", ret); - return ret; + if (1 == is_high_freq) + { + rate = clk_round_rate(spram->llc_clk, NPU_LLC_CLK_1P5G_RATE); + ret = clk_set_rate(spram->llc_clk, rate); + + if (ret != 0) + { + dev_err(&pdev->dev, "failed to set llc_clk: %d\n", ret); + return ret; + } + rate = clk_round_rate(spram->core_clk, NPU_CORE_CLK_1P5G_RATE); + ret = clk_set_rate(spram->core_clk, rate); + if (ret != 0) + { + dev_err(&pdev->dev, "failed to set core_clk: %d\n", ret); + return ret; + } } + else + { + rate = clk_round_rate(spram->llc_clk, NPU_LLC_CLK_RATE); - rate = clk_round_rate(spram->core_clk, NPU_CORE_CLK_RATE); - ret = clk_set_rate(spram->core_clk, rate); - if(ret != 0){ - dev_err(&pdev->dev, "failed to set core_clk: %d\n", ret); - return ret; + ret = clk_set_rate(spram->llc_clk, rate); + if (ret != 0) + { + dev_err(&pdev->dev, "failed to set llc_clk: %d\n", ret); + return ret; + } + rate = clk_round_rate(spram->core_clk, NPU_CORE_CLK_RATE); + ret = clk_set_rate(spram->core_clk, rate); + if (ret != 0) + { + dev_err(&pdev->dev, "failed to set core_clk: %d\n", ret); + return ret; + } } return 0; @@ -810,6 +882,7 @@ static int llc_clk_rst_print(struct platform_device *pdev) static int llc_clk_rst_init(struct platform_device *pdev) { int ret = 0; + u8 is_high_freq = 0; dev_dbg(&pdev->dev, "---%s\n", __func__); @@ -819,7 +892,7 @@ static int llc_clk_rst_init(struct platform_device *pdev) return ret; } - ret = llc_clk_set_parent(pdev); + ret = llc_clk_set_parent(pdev, &is_high_freq); if(ret != 0){ dev_err(&pdev->dev, "llc_clk_set_parent error: %d\n", ret); return ret; @@ -831,7 +904,7 @@ static int llc_clk_rst_init(struct platform_device *pdev) return ret; } - ret = llc_clk_set_frq(pdev); + ret = llc_clk_set_frq(pdev, is_high_freq); if(ret != 0){ dev_err(&pdev->dev, "llc_clk_set_frq error: %d\n", ret); return ret; diff --git a/include/linux/eswin_npu.h b/include/linux/eswin_npu.h index d7f3c91491f1..44784eeefba3 100644 --- a/include/linux/eswin_npu.h +++ b/include/linux/eswin_npu.h @@ -14,8 +14,12 @@ #define __LINUX_ESWIN_NPU_H #define NPU_ACLK_RATE 800000000 +#define NPU_DEFAULT_VOLTAGE 800000 //uV #define NPU_LLC_CLK_RATE 800000000 //nvdla #define NPU_CORE_CLK_RATE 1040000000 //npu and e31 +#define NPU_1P5G_VOLTAGE 1050000 //uV +#define NPU_LLC_CLK_1P5G_RATE 1188000000 //nvdla +#define NPU_CORE_CLK_1P5G_RATE 1500000000 //npu and e31 #define NPU_E31_CLK_RATE 1040000000 //llc #endif /* __LINUX_ESWIN_NPU_H */ -- 2.47.0