Merge remote-tracking branch 'up/f31' into private-davidlt-try1

Error: Mismatches found in configuration files
Found CONFIG_SND_SOC_ES8328_SPI=is not set after generation, had CONFIG_SND_SOC_ES8328_SPI=n in Source tree

Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>

0001-riscv-add-SECCOMP-support.patch

@@ -0,0 +1,184 @@
+From 0cb0b507d7eaff090b2607799de3acad464fa446 Mon Sep 17 00:00:00 2001
+From: David Abdurachmanov <david.abdurachmanov@sifive.com>
+Date: Mon, 24 Jun 2019 18:58:45 +0300
+Subject: [PATCH] riscv: add SECCOMP support
+
+Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
+
+diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
+index 0c4b12205632..6f89a83c1e9c 100644
+--- a/arch/riscv/Kconfig
++++ b/arch/riscv/Kconfig
+@@ -30,6 +30,7 @@ config RISCV
+ 	select GENERIC_SMP_IDLE_THREAD
+ 	select GENERIC_ATOMIC64 if !64BIT
+ 	select HAVE_ARCH_AUDITSYSCALL
++	select HAVE_ARCH_SECCOMP_FILTER
+ 	select HAVE_MEMBLOCK_NODE_MAP
+ 	select HAVE_DMA_CONTIGUOUS
+ 	select HAVE_FUTEX_CMPXCHG if FUTEX
+@@ -223,6 +224,19 @@ menu "Kernel features"
+ 
+ source "kernel/Kconfig.hz"
+ 
++config SECCOMP
++	bool "Enable seccomp to safely compute untrusted bytecode"
++	help
++	  This kernel feature is useful for number crunching applications
++	  that may need to compute untrusted bytecode during their
++	  execution. By using pipes or other transports made available to
++	  the process as file descriptors supporting the read/write
++	  syscalls, it's possible to isolate those applications in
++	  their own address space using seccomp. Once seccomp is
++	  enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
++	  and the task is only allowed to execute a few safe syscalls
++	  defined by each seccomp mode.
++
+ endmenu
+ 
+ menu "Boot options"
+diff --git a/arch/riscv/include/asm/seccomp.h b/arch/riscv/include/asm/seccomp.h
+new file mode 100644
+index 000000000000..bf7744ee3b3d
+--- /dev/null
++++ b/arch/riscv/include/asm/seccomp.h
+@@ -0,0 +1,10 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++
++#ifndef _ASM_SECCOMP_H
++#define _ASM_SECCOMP_H
++
++#include <asm/unistd.h>
++
++#include <asm-generic/seccomp.h>
++
++#endif /* _ASM_SECCOMP_H */
+diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/thread_info.h
+index 905372d7eeb8..a0b2a29a0da1 100644
+--- a/arch/riscv/include/asm/thread_info.h
++++ b/arch/riscv/include/asm/thread_info.h
+@@ -75,6 +75,7 @@ struct thread_info {
+ #define TIF_MEMDIE		5	/* is terminating due to OOM killer */
+ #define TIF_SYSCALL_TRACEPOINT  6       /* syscall tracepoint instrumentation */
+ #define TIF_SYSCALL_AUDIT	7	/* syscall auditing */
++#define TIF_SECCOMP		8	/* syscall secure computing */
+ 
+ #define _TIF_SYSCALL_TRACE	(1 << TIF_SYSCALL_TRACE)
+ #define _TIF_NOTIFY_RESUME	(1 << TIF_NOTIFY_RESUME)
+@@ -82,11 +83,13 @@ struct thread_info {
+ #define _TIF_NEED_RESCHED	(1 << TIF_NEED_RESCHED)
+ #define _TIF_SYSCALL_TRACEPOINT	(1 << TIF_SYSCALL_TRACEPOINT)
+ #define _TIF_SYSCALL_AUDIT	(1 << TIF_SYSCALL_AUDIT)
++#define _TIF_SECCOMP		(1 << TIF_SECCOMP)
+ 
+ #define _TIF_WORK_MASK \
+ 	(_TIF_NOTIFY_RESUME | _TIF_SIGPENDING | _TIF_NEED_RESCHED)
+ 
+ #define _TIF_SYSCALL_WORK \
+-	(_TIF_SYSCALL_TRACE | _TIF_SYSCALL_TRACEPOINT | _TIF_SYSCALL_AUDIT)
++	(_TIF_SYSCALL_TRACE | _TIF_SYSCALL_TRACEPOINT | _TIF_SYSCALL_AUDIT | \
++	 _TIF_SECCOMP )
+ 
+ #endif /* _ASM_RISCV_THREAD_INFO_H */
+diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
+index bc7a56e1ca6f..0bbedfa3e47d 100644
+--- a/arch/riscv/kernel/entry.S
++++ b/arch/riscv/kernel/entry.S
+@@ -203,8 +203,25 @@ check_syscall_nr:
+ 	/* Check to make sure we don't jump to a bogus syscall number. */
+ 	li t0, __NR_syscalls
+ 	la s0, sys_ni_syscall
+-	/* Syscall number held in a7 */
+-	bgeu a7, t0, 1f
++	/*
++	 * The tracer can change syscall number to valid/invalid value.
++	 * We use syscall_set_nr helper in syscall_trace_enter thus we
++	 * cannot trust the current value in a7 and have to reload from
++	 * the current task pt_regs.
++	 */
++	REG_L a7, PT_A7(sp)
++	/*
++	 * Syscall number held in a7.
++	 * If syscall number is above allowed value, redirect to ni_syscall.
++	 */
++	bge a7, t0, 1f
++	/*
++	 * Check if syscall is rejected by tracer or seccomp, i.e., a7 == -1.
++	 * If yes, we pretend it was executed.
++	 */
++	li t1, -1
++	beq a7, t1, ret_from_syscall_rejected
++	/* Call syscall */
+ 	la s0, sys_call_table
+ 	slli t0, a7, RISCV_LGPTR
+ 	add s0, s0, t0
+@@ -215,6 +232,12 @@ check_syscall_nr:
+ ret_from_syscall:
+ 	/* Set user a0 to kernel a0 */
+ 	REG_S a0, PT_A0(sp)
++	/*
++	 * We didn't execute the actual syscall.
++	 * Seccomp already set return value for the current task pt_regs.
++	 * (If it was configured with SECCOMP_RET_ERRNO/TRACE)
++	 */
++ret_from_syscall_rejected:
+ 	/* Trace syscalls, but only if requested by the user. */
+ 	REG_L t0, TASK_TI_FLAGS(tp)
+ 	andi t0, t0, _TIF_SYSCALL_WORK
+diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c
+index 368751438366..63e47c9f85f0 100644
+--- a/arch/riscv/kernel/ptrace.c
++++ b/arch/riscv/kernel/ptrace.c
+@@ -154,6 +154,16 @@ void do_syscall_trace_enter(struct pt_regs *regs)
+ 		if (tracehook_report_syscall_entry(regs))
+ 			syscall_set_nr(current, regs, -1);
+ 
++	/*
++	 * Do the secure computing after ptrace; failures should be fast.
++	 * If this fails we might have return value in a0 from seccomp
++	 * (via SECCOMP_RET_ERRNO/TRACE).
++	 */
++	if (secure_computing(NULL) == -1) {
++		syscall_set_nr(current, regs, -1);
++		return;
++	}
++
+ #ifdef CONFIG_HAVE_SYSCALL_TRACEPOINTS
+ 	if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
+ 		trace_sys_enter(regs, syscall_get_nr(current, regs));
+diff --git a/tools/testing/selftests/seccomp/seccomp_bpf.c b/tools/testing/selftests/seccomp/seccomp_bpf.c
+index dc66fe852768..e30864b25fb5 100644
+--- a/tools/testing/selftests/seccomp/seccomp_bpf.c
++++ b/tools/testing/selftests/seccomp/seccomp_bpf.c
+@@ -112,6 +112,8 @@ struct seccomp_data {
+ #  define __NR_seccomp 383
+ # elif defined(__aarch64__)
+ #  define __NR_seccomp 277
++# elif defined(__riscv)
++#  define __NR_seccomp 277
+ # elif defined(__hppa__)
+ #  define __NR_seccomp 338
+ # elif defined(__powerpc__)
+@@ -1582,6 +1584,10 @@ TEST_F(TRACE_poke, getpid_runs_normally)
+ # define ARCH_REGS	struct user_pt_regs
+ # define SYSCALL_NUM	regs[8]
+ # define SYSCALL_RET	regs[0]
++#elif defined(__riscv) && __riscv_xlen == 64
++# define ARCH_REGS	struct user_regs_struct
++# define SYSCALL_NUM	a7
++# define SYSCALL_RET	a0
+ #elif defined(__hppa__)
+ # define ARCH_REGS	struct user_regs_struct
+ # define SYSCALL_NUM	gr[20]
+@@ -1671,7 +1677,7 @@ void change_syscall(struct __test_metadata *_metadata,
+ 	EXPECT_EQ(0, ret) {}
+ 
+ #if defined(__x86_64__) || defined(__i386__) || defined(__powerpc__) || \
+-    defined(__s390__) || defined(__hppa__)
++    defined(__s390__) || defined(__hppa__) || defined(__riscv)
+ 	{
+ 		regs.SYSCALL_NUM = syscall;
+ 	}
+-- 
+2.21.0
+

0001-x86-amd_nb-Add-PCI-device-IDs-for-family-17h-model-7.patch

@@ -0,0 +1,92 @@
+From af4e1c5eca95bed1192d8dc45c8ed63aea2209e8 Mon Sep 17 00:00:00 2001
+From: Marcel Bocu <marcel.p.bocu@gmail.com>
+Date: Mon, 22 Jul 2019 20:45:10 +0300
+Subject: [PATCH] x86/amd_nb: Add PCI device IDs for family 17h, model 70h
+
+The AMD Ryzen gen 3 processors came with a different PCI IDs for the
+function 3 & 4 which are used to access the SMN interface. The root
+PCI address however remained at the same address as the model 30h.
+
+Adding the F3/F4 PCI IDs respectively to the misc and link ids appear
+to be sufficient for k10temp, so let's add them and follow up on the
+patch if other functions need more tweaking.
+
+Vicki Pfau sent an identical patch after I checked that no-one had
+written this patch. I would have been happy about dropping my patch but
+unlike for his patch series, I had already Cc:ed the x86 people and
+they already reviewed the changes. Since Vicki has not answered to
+any email after his initial series, let's assume she is on vacation
+and let's avoid duplication of reviews from the maintainers and merge
+my series. To acknowledge Vicki's anteriority, I added her S-o-b to
+the patch.
+
+v2, suggested by Guenter Roeck and Brian Woods:
+ - rename from 71h to 70h
+
+Signed-off-by: Vicki Pfau <vi@endrift.com>
+Signed-off-by: Marcel Bocu <marcel.p.bocu@gmail.com>
+Tested-by: Marcel Bocu <marcel.p.bocu@gmail.com>
+Acked-by: Thomas Gleixner <tglx@linutronix.de>
+Acked-by: Brian Woods <brian.woods@amd.com>
+Acked-by: Bjorn Helgaas <bhelgaas@google.com>	# pci_ids.h
+
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: Ingo Molnar <mingo@redhat.com>
+Cc: Borislav Petkov <bp@alien8.de>
+Cc: "H. Peter Anvin" <hpa@zytor.com>
+Cc: x86@kernel.org
+Cc: "Woods, Brian" <Brian.Woods@amd.com>
+Cc: Clemens Ladisch <clemens@ladisch.de>
+Cc: Jean Delvare <jdelvare@suse.com>
+Cc: Guenter Roeck <linux@roeck-us.net>
+Cc: linux-hwmon@vger.kernel.org
+Link: https://lore.kernel.org/r/20190722174510.2179-1-marcel.p.bocu@gmail.com
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+---
+ arch/x86/kernel/amd_nb.c | 3 +++
+ include/linux/pci_ids.h  | 1 +
+ 2 files changed, 4 insertions(+)
+
+diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
+index d63e63b7d1d9..251c795b4eb3 100644
+--- a/arch/x86/kernel/amd_nb.c
++++ b/arch/x86/kernel/amd_nb.c
+@@ -21,6 +21,7 @@
+ #define PCI_DEVICE_ID_AMD_17H_DF_F4	0x1464
+ #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
+ #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 0x1494
++#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444
+ 
+ /* Protect the PCI config register pairs used for SMN and DF indirect access. */
+ static DEFINE_MUTEX(smn_mutex);
+@@ -50,6 +51,7 @@ const struct pci_device_id amd_nb_misc_ids[] = {
+ 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
+ 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
+ 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
++	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
+ 	{}
+ };
+ EXPORT_SYMBOL_GPL(amd_nb_misc_ids);
+@@ -63,6 +65,7 @@ static const struct pci_device_id amd_nb_link_ids[] = {
+ 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },
+ 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F4) },
+ 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F4) },
++	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F4) },
+ 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
+ 	{}
+ };
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index c842735a4f45..4b97f427cc92 100644
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -548,6 +548,7 @@
+ #define PCI_DEVICE_ID_AMD_17H_DF_F3	0x1463
+ #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb
+ #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F3 0x1493
++#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F3 0x1443
+ #define PCI_DEVICE_ID_AMD_CNB17H_F3	0x1703
+ #define PCI_DEVICE_ID_AMD_LANCE		0x2000
+ #define PCI_DEVICE_ID_AMD_LANCE_HOME	0x2001
+-- 
+2.21.0
+

0002-SiFive-Unleashed-CPUFreq.patch

@@ -0,0 +1,140 @@
+From 8d741d97eeb3a0c1b9aa09da15fbb1c5c7214fcd Mon Sep 17 00:00:00 2001
+From: Fedora Kernel Team <kernel-team@fedoraproject.org>
+Date: Sun, 25 Aug 2019 06:58:34 +0000
+Subject: [PATCH 2/2] SiFive Unleashed CPUFreq
+
+Signed-off-by: Fedora Kernel Team <kernel-team@fedoraproject.org>
+---
+ arch/riscv/Kconfig                            |  8 +++++
+ arch/riscv/boot/dts/sifive/fu540-c000.dtsi    |  5 +++
+ .../boot/dts/sifive/hifive-unleashed-a00.dts  | 34 +++++++++++++++++++
+ arch/riscv/configs/defconfig                  |  5 +++
+ 4 files changed, 52 insertions(+)
+
+diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
+index 441e63f..ccd590c 100644
+--- a/arch/riscv/Kconfig
++++ b/arch/riscv/Kconfig
+@@ -298,6 +298,14 @@ endchoice
+ 
+ endmenu
+ 
++menu "CPU Power Management"
++
++source "drivers/cpuidle/Kconfig"
++
++source "drivers/cpufreq/Kconfig"
++
++endmenu
++
+ menu "Power management options"
+ 
+ source "kernel/power/Kconfig"
+diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+index 42b5ec2..b07079f 100644
+--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
++++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+@@ -29,6 +29,7 @@
+ 			i-cache-size = <16384>;
+ 			reg = <0>;
+ 			riscv,isa = "rv64imac";
++			clocks = <&prci PRCI_CLK_COREPLL>;
+ 			status = "disabled";
+ 			cpu0_intc: interrupt-controller {
+ 				#interrupt-cells = <1>;
+@@ -53,6 +54,7 @@
+ 			reg = <1>;
+ 			riscv,isa = "rv64imafdc";
+ 			tlb-split;
++			clocks = <&prci PRCI_CLK_COREPLL>;
+ 			cpu1_intc: interrupt-controller {
+ 				#interrupt-cells = <1>;
+ 				compatible = "riscv,cpu-intc";
+@@ -77,6 +79,7 @@
+ 			reg = <2>;
+ 			riscv,isa = "rv64imafdc";
+ 			tlb-split;
++			clocks = <&prci PRCI_CLK_COREPLL>;
+ 			cpu2_intc: interrupt-controller {
+ 				#interrupt-cells = <1>;
+ 				compatible = "riscv,cpu-intc";
+@@ -101,6 +104,7 @@
+ 			reg = <3>;
+ 			riscv,isa = "rv64imafdc";
+ 			tlb-split;
++			clocks = <&prci PRCI_CLK_COREPLL>;
+ 			cpu3_intc: interrupt-controller {
+ 				#interrupt-cells = <1>;
+ 				compatible = "riscv,cpu-intc";
+@@ -125,6 +129,7 @@
+ 			reg = <4>;
+ 			riscv,isa = "rv64imafdc";
+ 			tlb-split;
++			clocks = <&prci PRCI_CLK_COREPLL>;
+ 			cpu4_intc: interrupt-controller {
+ 				#interrupt-cells = <1>;
+ 				compatible = "riscv,cpu-intc";
+diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
+index 54fc701..5b43bdf 100644
+--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
++++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
+@@ -40,6 +40,40 @@
+ 		clock-frequency = <RTCCLK_FREQ>;
+ 		clock-output-names = "rtcclk";
+ 	};
++
++	fu540_c000_opp_table: opp-table {
++		compatible = "operating-points-v2";
++		opp-shared;
++
++		opp-350000000 {
++			opp-hz = /bits/ 64 <350000000>;
++		};
++		opp-700000000 {
++			opp-hz = /bits/ 64 <700000000>;
++		};
++		opp-999999999 {
++			opp-hz = /bits/ 64 <999999999>;
++		};
++		opp-1400000000 {
++			opp-hz = /bits/ 64 <1400000000>;
++		};
++	};
++};
++
++&cpu0 {
++	operating-points-v2 = <&fu540_c000_opp_table>;
++};
++&cpu1 {
++	operating-points-v2 = <&fu540_c000_opp_table>;
++};
++&cpu2 {
++	operating-points-v2 = <&fu540_c000_opp_table>;
++};
++&cpu3 {
++	operating-points-v2 = <&fu540_c000_opp_table>;
++};
++&cpu4 {
++	operating-points-v2 = <&fu540_c000_opp_table>;
+ };
+ 
+ &uart0 {
+diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
+index 3efff55..c9542a9 100644
+--- a/arch/riscv/configs/defconfig
++++ b/arch/riscv/configs/defconfig
+@@ -16,6 +16,11 @@ CONFIG_EXPERT=y
+ CONFIG_BPF_SYSCALL=y
+ CONFIG_SOC_SIFIVE=y
+ CONFIG_SMP=y
++CONFIG_CPU_IDLE=y
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
++CONFIG_CPUFREQ_DT=y
+ CONFIG_MODULES=y
+ CONFIG_MODULE_UNLOAD=y
+ CONFIG_NET=y
+-- 
+2.23.0
+

configs/build_configs.sh

@@ -81,6 +81,8 @@ function merge_configs()
 		echo "# arm64" > $name
 	elif [ "x$arch" == "xppc64le" ]; then
 		echo "# powerpc" > $name
+	elif [ "x$arch" == "xriscv64" ]; then
+		echo "# riscv" > $name
 	elif [ "x$arch" == "xs390x" ]; then
 		echo "# s390" > $name
 	elif [ "x$arch" == "xarmv7hl" ]; then

configs/config_generation

@@ -28,6 +28,10 @@ s390x-debug=generic:generic-s390x:debug
 aarch64=generic:generic-arm:generic-arm-aarch64
 aarch64-debug=generic:generic-arm:generic-arm-aarch64:debug:debug-arm
 
+# riscv64
+riscv64=generic:generic-riscv:generic-riscv-riscv64
+riscv64-debug=generic:generic-riscv:generic-riscv-riscv64:debug
+
 # arm
 armv7hl=generic:generic-arm:generic-arm-armv7:generic-arm-armv7-armv7
 armv7hl-debug=generic:generic-arm:generic-arm-armv7:generic-arm-armv7-armv7:debug:debug-arm

configs/fedora/generic/CONFIG_ARM_TIMER_SP804

@@ -0,0 +1 @@
+# CONFIG_ARM_TIMER_SP804 is not set

configs/fedora/generic/CONFIG_NETFILTER_XT_TARGET_MASQUERADE

@@ -0,0 +1 @@
+CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m

configs/fedora/generic/riscv/CONFIG_ARCH_RV32I

@@ -0,0 +1 @@
+# CONFIG_ARCH_RV32I is not set

configs/fedora/generic/riscv/CONFIG_AUTOFS4_FS

@@ -0,0 +1 @@
+CONFIG_AUTOFS4_FS=y

configs/fedora/generic/riscv/CONFIG_BLK_DEV

@@ -0,0 +1 @@
+CONFIG_BLK_DEV=y

configs/fedora/generic/riscv/CONFIG_BLK_DEV_BSG

@@ -0,0 +1 @@
+CONFIG_BLK_DEV_BSG=y

configs/fedora/generic/riscv/CONFIG_BLK_DEV_DM

@@ -0,0 +1 @@
+CONFIG_BLK_DEV_DM=y

configs/fedora/generic/riscv/CONFIG_BLK_DEV_DM_BUILTIN

@@ -0,0 +1 @@
+CONFIG_BLK_DEV_DM_BUILTIN=y

configs/fedora/generic/riscv/CONFIG_BLK_DEV_LOOP

@@ -0,0 +1 @@
+CONFIG_BLK_DEV_LOOP=y

configs/fedora/generic/riscv/CONFIG_BLK_DEV_NBD

@@ -0,0 +1 @@
+CONFIG_BLK_DEV_NBD=y

configs/fedora/generic/riscv/CONFIG_BRIDGE

@@ -0,0 +1 @@
+CONFIG_BRIDGE=y

configs/fedora/generic/riscv/CONFIG_BTRFS_FS_POSIX_ACL

@@ -0,0 +1 @@
+CONFIG_BTRFS_FS_POSIX_ACL=y

configs/fedora/generic/riscv/CONFIG_CFS_BANDWIDTH

@@ -0,0 +1 @@
+CONFIG_CFS_BANDWIDTH=y

configs/fedora/generic/riscv/CONFIG_CGROUPS

@@ -0,0 +1 @@
+CONFIG_CGROUPS=y

configs/fedora/generic/riscv/CONFIG_CGROUP_SCHED

@@ -0,0 +1 @@
+CONFIG_CGROUP_SCHED=y

configs/fedora/generic/riscv/CONFIG_CHECKPOINT_RESTORE

@@ -0,0 +1 @@
+CONFIG_CHECKPOINT_RESTORE=y

configs/fedora/generic/riscv/CONFIG_CLK_SIFIVE

@@ -0,0 +1 @@
+CONFIG_CLK_SIFIVE=y

configs/fedora/generic/riscv/CONFIG_CLK_SIFIVE_FU540_PRCI

@@ -0,0 +1 @@
+CONFIG_CLK_SIFIVE_FU540_PRCI=y

configs/fedora/generic/riscv/CONFIG_CMDLINE

@@ -0,0 +1 @@
+CONFIG_CMDLINE=""

configs/fedora/generic/riscv/CONFIG_CMDLINE_BOOL

@@ -0,0 +1 @@
+# CONFIG_CMDLINE_BOOL is not set

configs/fedora/generic/riscv/CONFIG_CMODEL_MEDANY

@@ -0,0 +1 @@
+CONFIG_CMODEL_MEDANY=y

configs/fedora/generic/riscv/CONFIG_CMODEL_MEDLOW

@@ -0,0 +1 @@
+# CONFIG_CMODEL_MEDLOW is not set

configs/fedora/generic/riscv/CONFIG_CPUFREQ_DT

@@ -0,0 +1 @@
+CONFIG_CPUFREQ_DT=y

configs/fedora/generic/riscv/CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND

@@ -0,0 +1 @@
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set

configs/fedora/generic/riscv/CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE

@@ -0,0 +1 @@
+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y

configs/fedora/generic/riscv/CONFIG_CRYPTO_USER

@@ -0,0 +1 @@
+CONFIG_CRYPTO_USER=y

configs/fedora/generic/riscv/CONFIG_CRYPTO_USER_API

@@ -0,0 +1 @@
+CONFIG_CRYPTO_USER_API=y

configs/fedora/generic/riscv/CONFIG_CRYPTO_USER_API_AEAD

@@ -0,0 +1 @@
+CONFIG_CRYPTO_USER_API_AEAD=y

configs/fedora/generic/riscv/CONFIG_CRYPTO_USER_API_HASH

@@ -0,0 +1 @@
+CONFIG_CRYPTO_USER_API_HASH=y

configs/fedora/generic/riscv/CONFIG_CRYPTO_USER_API_RNG

@@ -0,0 +1 @@
+CONFIG_CRYPTO_USER_API_RNG=y

configs/fedora/generic/riscv/CONFIG_CRYPTO_USER_API_SKCIPHER

@@ -0,0 +1 @@
+CONFIG_CRYPTO_USER_API_SKCIPHER=y

configs/fedora/generic/riscv/CONFIG_DEVPTS_MULTIPLE_INSTANCES

@@ -0,0 +1 @@
+CONFIG_DEVPTS_MULTIPLE_INSTANCES=y

configs/fedora/generic/riscv/CONFIG_DEVTMPFS

@@ -0,0 +1 @@
+CONFIG_DEVTMPFS=y

configs/fedora/generic/riscv/CONFIG_DMIID

@@ -0,0 +1 @@
+CONFIG_DMIID=y

configs/fedora/generic/riscv/CONFIG_DM_BIO_PRISON

@@ -0,0 +1 @@
+CONFIG_DM_BIO_PRISON=y

configs/fedora/generic/riscv/CONFIG_DM_BUFIO

@@ -0,0 +1 @@
+CONFIG_DM_BUFIO=y

configs/fedora/generic/riscv/CONFIG_DM_CACHE

@@ -0,0 +1 @@
+CONFIG_DM_CACHE=y

configs/fedora/generic/riscv/CONFIG_DM_CACHE_SMQ

@@ -0,0 +1 @@
+CONFIG_DM_CACHE_SMQ=y

configs/fedora/generic/riscv/CONFIG_DM_CRYPT

@@ -0,0 +1 @@
+CONFIG_DM_CRYPT=y

configs/fedora/generic/riscv/CONFIG_DM_DEBUG

@@ -0,0 +1 @@
+CONFIG_DM_DEBUG=y

configs/fedora/generic/riscv/CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING

@@ -0,0 +1 @@
+CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING=y

configs/fedora/generic/riscv/CONFIG_DM_DELAY

@@ -0,0 +1 @@
+CONFIG_DM_DELAY=y

configs/fedora/generic/riscv/CONFIG_DM_FLAKEY

@@ -0,0 +1 @@
+CONFIG_DM_FLAKEY=y

configs/fedora/generic/riscv/CONFIG_DM_INTEGRITY

@@ -0,0 +1 @@
+CONFIG_DM_INTEGRITY=y

configs/fedora/generic/riscv/CONFIG_DM_LOG_USERSPACE

@@ -0,0 +1 @@
+CONFIG_DM_LOG_USERSPACE=y

configs/fedora/generic/riscv/CONFIG_DM_LOG_WRITES

@@ -0,0 +1 @@
+CONFIG_DM_LOG_WRITES=y

configs/fedora/generic/riscv/CONFIG_DM_MIRROR

@@ -0,0 +1 @@
+CONFIG_DM_MIRROR=y

configs/fedora/generic/riscv/CONFIG_DM_MULTIPATH

@@ -0,0 +1 @@
+CONFIG_DM_MULTIPATH=y

configs/fedora/generic/riscv/CONFIG_DM_MULTIPATH_QL

@@ -0,0 +1 @@
+CONFIG_DM_MULTIPATH_QL=y

configs/fedora/generic/riscv/CONFIG_DM_MULTIPATH_ST

@@ -0,0 +1 @@
+CONFIG_DM_MULTIPATH_ST=y

configs/fedora/generic/riscv/CONFIG_DM_PERSISTENT_DATA

@@ -0,0 +1 @@
+CONFIG_DM_PERSISTENT_DATA=y

configs/fedora/generic/riscv/CONFIG_DM_RAID

@@ -0,0 +1 @@
+CONFIG_DM_RAID=y

configs/fedora/generic/riscv/CONFIG_DM_SNAPSHOT

@@ -0,0 +1 @@
+CONFIG_DM_SNAPSHOT=y

configs/fedora/generic/riscv/CONFIG_DM_SWITCH

@@ -0,0 +1 @@
+CONFIG_DM_SWITCH=y

configs/fedora/generic/riscv/CONFIG_DM_THIN_PROVISIONING

@@ -0,0 +1 @@
+CONFIG_DM_THIN_PROVISIONING=y

configs/fedora/generic/riscv/CONFIG_DM_UEVENT

@@ -0,0 +1 @@
+CONFIG_DM_UEVENT=y

configs/fedora/generic/riscv/CONFIG_DM_UNSTRIPED

@@ -0,0 +1 @@
+CONFIG_DM_UNSTRIPED=y

configs/fedora/generic/riscv/CONFIG_DM_VERITY

@@ -0,0 +1 @@
+CONFIG_DM_VERITY=y

configs/fedora/generic/riscv/CONFIG_DM_VERITY_FEC

@@ -0,0 +1 @@
+CONFIG_DM_VERITY_FEC=y

configs/fedora/generic/riscv/CONFIG_DM_ZERO

@@ -0,0 +1 @@
+CONFIG_DM_ZERO=y

configs/fedora/generic/riscv/CONFIG_DM_ZONED

@@ -0,0 +1 @@
+CONFIG_DM_ZONED=y

configs/fedora/generic/riscv/CONFIG_DNS_RESOLVER

@@ -0,0 +1 @@
+CONFIG_DNS_RESOLVER=y

configs/fedora/generic/riscv/CONFIG_DRM_PANEL

@@ -0,0 +1 @@
+CONFIG_DRM_PANEL=y

configs/fedora/generic/riscv/CONFIG_DRM_VIRTIO_GPU

@@ -0,0 +1 @@
+CONFIG_DRM_VIRTIO_GPU=m

configs/fedora/generic/riscv/CONFIG_EDAC_SIFIVE

@@ -0,0 +1 @@
+CONFIG_EDAC_SIFIVE=y

configs/fedora/generic/riscv/CONFIG_EFIVAR_FS

@@ -0,0 +1 @@
+CONFIG_EFIVAR_FS=y

configs/fedora/generic/riscv/CONFIG_EFI_PARTITION

@@ -0,0 +1 @@
+CONFIG_EFI_PARTITION=y

configs/fedora/generic/riscv/CONFIG_EPOLL

@@ -0,0 +1 @@
+CONFIG_EPOLL=y

configs/fedora/generic/riscv/CONFIG_EXT4_FS

@@ -0,0 +1 @@
+CONFIG_EXT4_FS=y

configs/fedora/generic/riscv/CONFIG_EXT4_FS_SECURITY

@@ -0,0 +1 @@
+CONFIG_EXT4_FS_SECURITY=y

configs/fedora/generic/riscv/CONFIG_EXT4_POSIX_ACL

@@ -0,0 +1 @@
+CONFIG_EXT4_POSIX_ACL=y

configs/fedora/generic/riscv/CONFIG_FAILOVER

@@ -0,0 +1 @@
+CONFIG_FAILOVER=y

configs/fedora/generic/riscv/CONFIG_FAIR_GROUP_SCHED

@@ -0,0 +1 @@
+CONFIG_FAIR_GROUP_SCHED=y

configs/fedora/generic/riscv/CONFIG_FB_SSD1307

@@ -0,0 +1 @@
+# CONFIG_FB_SSD1307 is not set

configs/fedora/generic/riscv/CONFIG_FHANDLE

@@ -0,0 +1 @@
+CONFIG_FHANDLE=y

configs/fedora/generic/riscv/CONFIG_FILE_LOCKING

@@ -0,0 +1 @@
+CONFIG_FILE_LOCKING=y

configs/fedora/generic/riscv/CONFIG_FPU

@@ -0,0 +1 @@
+CONFIG_FPU=y

configs/fedora/generic/riscv/CONFIG_FRAME_WARN

@@ -0,0 +1 @@
+CONFIG_FRAME_WARN=2048

configs/fedora/generic/riscv/CONFIG_FW_LOADER_USER_HELPER

@@ -0,0 +1 @@
+# CONFIG_FW_LOADER_USER_HELPER is not set

configs/fedora/generic/riscv/CONFIG_GENERIC_PHY

@@ -0,0 +1 @@
+CONFIG_GENERIC_PHY=y

configs/fedora/generic/riscv/CONFIG_GPIO_74XX_MMIO

@@ -0,0 +1 @@
+# CONFIG_GPIO_74XX_MMIO is not set

configs/fedora/generic/riscv/CONFIG_HOTPLUG_PCI

@@ -0,0 +1 @@
+CONFIG_HOTPLUG_PCI=y

configs/fedora/generic/riscv/CONFIG_HOTPLUG_PCI_PCIE

@@ -0,0 +1 @@
+CONFIG_HOTPLUG_PCI_PCIE=y

configs/fedora/generic/riscv/CONFIG_HVC_RISCV_SBI

@@ -0,0 +1 @@
+CONFIG_HVC_RISCV_SBI=y

configs/fedora/generic/riscv/CONFIG_I2C_MUX

@@ -0,0 +1 @@
+CONFIG_I2C_MUX=m

configs/fedora/generic/riscv/CONFIG_INET

@@ -0,0 +1 @@
+CONFIG_INET=y

configs/fedora/generic/riscv/CONFIG_INOTIFY_USER

@@ -0,0 +1 @@
+CONFIG_INOTIFY_USER=y

configs/fedora/generic/riscv/CONFIG_INPUT_MATRIXKMAP

@@ -0,0 +1 @@
+CONFIG_INPUT_MATRIXKMAP=m

configs/fedora/generic/riscv/CONFIG_IP6_NF_FILTER

@@ -0,0 +1 @@
+CONFIG_IP6_NF_FILTER=y

configs/fedora/generic/riscv/CONFIG_IP6_NF_IPTABLES

@@ -0,0 +1 @@
+CONFIG_IP6_NF_IPTABLES=y

configs/fedora/generic/riscv/CONFIG_IP6_NF_MANGLE

@@ -0,0 +1 @@
+CONFIG_IP6_NF_MANGLE=y

configs/fedora/generic/riscv/CONFIG_IP6_NF_NAT

@@ -0,0 +1 @@
+CONFIG_IP6_NF_NAT=y

configs/fedora/generic/riscv/CONFIG_IP6_NF_RAW

@@ -0,0 +1 @@
+CONFIG_IP6_NF_RAW=y

configs/fedora/generic/riscv/CONFIG_IP6_NF_TARGET_REJECT

@@ -0,0 +1 @@
+CONFIG_IP6_NF_TARGET_REJECT=y

configs/fedora/generic/riscv/CONFIG_IPV6

@@ -0,0 +1 @@
+CONFIG_IPV6=y