Add i915 eDP fixes

kernel.org switched how they generate GPG signatures. This
doesn't work with the existing scripts so disable this for now.

0001-random-add-a-config-option-to-trust-the-CPU-s-hwrng.patch

@@ -0,0 +1,78 @@
+From 39a8883a2b989d1d21bd8dd99f5557f0c5e89694 Mon Sep 17 00:00:00 2001
+From: Theodore Ts'o <tytso@mit.edu>
+Date: Tue, 17 Jul 2018 18:24:27 -0400
+Subject: [PATCH] random: add a config option to trust the CPU's hwrng
+
+This gives the user building their own kernel (or a Linux
+distribution) the option of deciding whether or not to trust the CPU's
+hardware random number generator (e.g., RDRAND for x86 CPU's) as being
+correctly implemented and not having a back door introduced (perhaps
+courtesy of a Nation State's law enforcement or intelligence
+agencies).
+
+This will prevent getrandom(2) from blocking, if there is a
+willingness to trust the CPU manufacturer.
+
+Signed-off-by: Theodore Ts'o <tytso@mit.edu>
+---
+ drivers/char/Kconfig  | 14 ++++++++++++++
+ drivers/char/random.c | 11 ++++++++++-
+ 2 files changed, 24 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
+index 212f447938ae..ce277ee0a28a 100644
+--- a/drivers/char/Kconfig
++++ b/drivers/char/Kconfig
+@@ -554,3 +554,17 @@ config ADI
+ 
+ endmenu
+ 
++config RANDOM_TRUST_CPU
++	bool "Trust the CPU manufacturer to initialize Linux's CRNG"
++	depends on X86 || S390 || PPC
++	default n
++	help
++	Assume that CPU manufacturer (e.g., Intel or AMD for RDSEED or
++	RDRAND, IBM for the S390 and Power PC architectures) is trustworthy
++	for the purposes of initializing Linux's CRNG.  Since this is not
++	something that can be independently audited, this amounts to trusting
++	that CPU manufacturer (perhaps with the insistence or mandate
++	of a Nation State's intelligence or law enforcement agencies)
++	has not installed a hidden back door to compromise the CPU's
++	random number generation facilities.
++
+diff --git a/drivers/char/random.c b/drivers/char/random.c
+index 34ddfd57419b..f4013b8a711b 100644
+--- a/drivers/char/random.c
++++ b/drivers/char/random.c
+@@ -782,6 +782,7 @@ static void invalidate_batched_entropy(void);
+ static void crng_initialize(struct crng_state *crng)
+ {
+ 	int		i;
++	int		arch_init = 1;
+ 	unsigned long	rv;
+ 
+ 	memcpy(&crng->state[0], "expand 32-byte k", 16);
+@@ -792,10 +793,18 @@ static void crng_initialize(struct crng_state *crng)
+ 		_get_random_bytes(&crng->state[4], sizeof(__u32) * 12);
+ 	for (i = 4; i < 16; i++) {
+ 		if (!arch_get_random_seed_long(&rv) &&
+-		    !arch_get_random_long(&rv))
++		    !arch_get_random_long(&rv)) {
+ 			rv = random_get_entropy();
++			arch_init = 0;
++		}
+ 		crng->state[i] ^= rv;
+ 	}
++#ifdef CONFIG_RANDOM_TRUST_CPU
++	if (arch_init) {
++		crng_init = 2;
++		pr_notice("random: crng done (trusting CPU's manufacturer)\n");
++	}
++#endif
+ 	crng->init_time = jiffies - CRNG_RESEED_INTERVAL - 1;
+ }
+ 
+-- 
+2.17.1
+

0001-random-make-CPU-trust-a-boot-parameter.patch

@@ -0,0 +1,82 @@
+From 9b25436662d5fb4c66eb527ead53cab15f596ee0 Mon Sep 17 00:00:00 2001
+From: Kees Cook <keescook@chromium.org>
+Date: Mon, 27 Aug 2018 14:51:54 -0700
+Subject: [PATCH] random: make CPU trust a boot parameter
+
+Instead of forcing a distro or other system builder to choose
+at build time whether the CPU is trusted for CRNG seeding via
+CONFIG_RANDOM_TRUST_CPU, provide a boot-time parameter for end users to
+control the choice. The CONFIG will set the default state instead.
+
+Signed-off-by: Kees Cook <keescook@chromium.org>
+Signed-off-by: Theodore Ts'o <tytso@mit.edu>
+---
+ Documentation/admin-guide/kernel-parameters.txt |  6 ++++++
+ drivers/char/Kconfig                            |  4 ++--
+ drivers/char/random.c                           | 11 ++++++++---
+ 3 files changed, 16 insertions(+), 5 deletions(-)
+
+diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
+index 0c8f7889efa1..227c5c6fa4c1 100644
+--- a/Documentation/admin-guide/kernel-parameters.txt
++++ b/Documentation/admin-guide/kernel-parameters.txt
+@@ -3390,6 +3390,12 @@
+ 	ramdisk_size=	[RAM] Sizes of RAM disks in kilobytes
+ 			See Documentation/blockdev/ramdisk.txt.
+ 
++	random.trust_cpu={on,off}
++			[KNL] Enable or disable trusting the use of the
++			CPU's random number generator (if available) to
++			fully seed the kernel's CRNG. Default is controlled
++			by CONFIG_RANDOM_TRUST_CPU.
++
+ 	ras=option[,option,...]	[KNL] RAS-specific options
+ 
+ 		cec_disable	[X86]
+diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
+index ce277ee0a28a..40728491f37b 100644
+--- a/drivers/char/Kconfig
++++ b/drivers/char/Kconfig
+@@ -566,5 +566,5 @@ config RANDOM_TRUST_CPU
+ 	that CPU manufacturer (perhaps with the insistence or mandate
+ 	of a Nation State's intelligence or law enforcement agencies)
+ 	has not installed a hidden back door to compromise the CPU's
+-	random number generation facilities.
+-
++	random number generation facilities. This can also be configured
++	at boot with "random.trust_cpu=on/off".
+diff --git a/drivers/char/random.c b/drivers/char/random.c
+index bf5f99fc36f1..c75b6cdf0053 100644
+--- a/drivers/char/random.c
++++ b/drivers/char/random.c
+@@ -779,6 +779,13 @@ static struct crng_state **crng_node_pool __read_mostly;
+ 
+ static void invalidate_batched_entropy(void);
+ 
++static bool trust_cpu __ro_after_init = IS_ENABLED(CONFIG_RANDOM_TRUST_CPU);
++static int __init parse_trust_cpu(char *arg)
++{
++	return kstrtobool(arg, &trust_cpu);
++}
++early_param("random.trust_cpu", parse_trust_cpu);
++
+ static void crng_initialize(struct crng_state *crng)
+ {
+ 	int		i;
+@@ -799,12 +806,10 @@ static void crng_initialize(struct crng_state *crng)
+ 		}
+ 		crng->state[i] ^= rv;
+ 	}
+-#ifdef CONFIG_RANDOM_TRUST_CPU
+-	if (arch_init) {
++	if (trust_cpu && arch_init) {
+ 		crng_init = 2;
+ 		pr_notice("random: crng done (trusting CPU's manufacturer)\n");
+ 	}
+-#endif
+ 	crng->init_time = jiffies - CRNG_RESEED_INTERVAL - 1;
+ }
+ 
+-- 
+2.17.1
+

0006-efifb-Copy-the-ACPI-BGRT-boot-graphics-to-the-frameb.patch

@@ -22,7 +22,7 @@ Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
  1 file changed, 140 insertions(+)
 
 diff --git a/drivers/video/fbdev/efifb.c b/drivers/video/fbdev/efifb.c
-index c6f78d27947b..67684412ba8a 100644
+index 46a4484e3da7..fa01eecc0a55 100644
 --- a/drivers/video/fbdev/efifb.c
 +++ b/drivers/video/fbdev/efifb.c
 @@ -9,16 +9,39 @@
@@ -63,7 +63,7 @@ index c6f78d27947b..67684412ba8a 100644
 +} __packed;
 +
  static bool request_mem_succeeded = false;
- static u64 mem_flags = EFI_MEMORY_WC | EFI_MEMORY_UC;
+ static bool nowc = false;
  
 @@ -66,6 +89,121 @@ static int efifb_setcolreg(unsigned regno, unsigned red, unsigned green,
  	return 0;
@@ -186,8 +186,8 @@ index c6f78d27947b..67684412ba8a 100644
 +
  static void efifb_destroy(struct fb_info *info)
  {
- 	if (info->screen_base) {
-@@ -311,6 +449,8 @@ static int efifb_probe(struct platform_device *dev)
+ 	if (info->screen_base)
+@@ -283,6 +421,8 @@ static int efifb_probe(struct platform_device *dev)
  		goto err_release_fb;
  	}
  

ALSA-hda-Add-mic-quirk-for-the-Lenovo-G50-30-17aa-39.patch

@@ -0,0 +1,32 @@
+From 44002a8818bc64f53d855bc8e3ee4c6bb2d3db99 Mon Sep 17 00:00:00 2001
+From: Jeremy Cline <jcline@redhat.com>
+Date: Mon, 8 Oct 2018 14:37:52 -0400
+Subject: [PATCH] ALSA: hda - Add mic quirk for the Lenovo G50-30 (17aa:3905)
+
+The Lenovo G50-30, like other G50 models, has a Conexant codec that
+requires a quirk for its inverted stereo dmic.
+
+Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1249364
+Reported-by: Alexander Ploumistos <alex.ploumistos@gmail.com>
+Tested-by: Alexander Ploumistos <alex.ploumistos@gmail.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Jeremy Cline <jcline@redhat.com>
+---
+ sound/pci/hda/patch_conexant.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/sound/pci/hda/patch_conexant.c b/sound/pci/hda/patch_conexant.c
+index 5592557fe50e..950e02e71766 100644
+--- a/sound/pci/hda/patch_conexant.c
++++ b/sound/pci/hda/patch_conexant.c
+@@ -943,6 +943,7 @@ static const struct snd_pci_quirk cxt5066_fixups[] = {
+ 	SND_PCI_QUIRK(0x17aa, 0x21da, "Lenovo X220", CXT_PINCFG_LENOVO_TP410),
+ 	SND_PCI_QUIRK(0x17aa, 0x21db, "Lenovo X220-tablet", CXT_PINCFG_LENOVO_TP410),
+ 	SND_PCI_QUIRK(0x17aa, 0x38af, "Lenovo IdeaPad Z560", CXT_FIXUP_MUTE_LED_EAPD),
++	SND_PCI_QUIRK(0x17aa, 0x3905, "Lenovo G50-30", CXT_FIXUP_STEREO_DMIC),
+ 	SND_PCI_QUIRK(0x17aa, 0x390b, "Lenovo G50-80", CXT_FIXUP_STEREO_DMIC),
+ 	SND_PCI_QUIRK(0x17aa, 0x3975, "Lenovo U300s", CXT_FIXUP_STEREO_DMIC),
+ 	SND_PCI_QUIRK(0x17aa, 0x3977, "Lenovo IdeaPad U310", CXT_FIXUP_STEREO_DMIC),
+-- 
+2.19.1
+

CI-1-6-drm-i915-dp-Fix-link-retraining-comment-in-intel_dp_long_pulse.patch

@@ -0,0 +1,60 @@
+From patchwork Thu Sep 27 20:57:30 2018
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 8bit
+Subject: [CI, 1/6] drm/i915/dp: Fix link retraining comment in
+ intel_dp_long_pulse()
+From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
+X-Patchwork-Id: 253516
+Message-Id: <20180927205735.16651-1-dhinakaran.pandiyan@intel.com>
+To: intel-gfx@lists.freedesktop.org
+Date: Thu, 27 Sep 2018 13:57:30 -0700
+
+Comment claims link needs to be retrained because the connected sink raised
+a long pulse to indicate link loss. If the sink did so,
+intel_dp_hotplug() would have handled link retraining. Looking at the
+logs in Bugzilla referenced in commit '3cf71bc9904d ("drm/i915: Re-apply
+Perform link quality check, unconditionally during long pulse"")', the
+issue is that the sink does not trigger an interrupt. What we want is
+->detect() from user space to check link status and retrain. Ville's
+review for the original patch also indicates the same root cause. So,
+rewrite the comment.
+
+v2: Patch split and rewrote comment.
+
+Cc: Lyude Paul <lyude@redhat.com>
+Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Cc: Jani Nikula <jani.nikula@linux.intel.com>
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Cc: Jan-Marek Glogowski <glogow@fbihome.de>
+References: 3cf71bc9904d ("drm/i915: Re-apply "Perform link quality check, unconditionally during long pulse"")
+Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
+Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+---
+ drivers/gpu/drm/i915/intel_dp.c | 13 +++----------
+ 1 file changed, 3 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
+index 256a71c8c093..207b3ea2ed1a 100644
+--- a/drivers/gpu/drm/i915/intel_dp.c
++++ b/drivers/gpu/drm/i915/intel_dp.c
+@@ -5074,16 +5074,9 @@ intel_dp_long_pulse(struct intel_connector *connector,
+ 		goto out;
+ 	} else {
+ 		/*
+-		 * If display is now connected check links status,
+-		 * there has been known issues of link loss triggering
+-		 * long pulse.
+-		 *
+-		 * Some sinks (eg. ASUS PB287Q) seem to perform some
+-		 * weird HPD ping pong during modesets. So we can apparently
+-		 * end up with HPD going low during a modeset, and then
+-		 * going back up soon after. And once that happens we must
+-		 * retrain the link to get a picture. That's in case no
+-		 * userspace component reacted to intermittent HPD dip.
++		 * Some external monitors do not signal loss of link
++		 * synchronization with an IRQ_HPD, so force a link status
++		 * check.
+ 		 */
+ 		struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+ 

CI-2-6-drm-i915-dp-Restrict-link-retrain-workaround-to-external-monitors.patch

@@ -0,0 +1,55 @@
+From patchwork Thu Sep 27 20:57:31 2018
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 8bit
+Subject: [CI, 2/6] drm/i915/dp: Restrict link retrain workaround to external
+ monitors
+From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
+X-Patchwork-Id: 253514
+Message-Id: <20180927205735.16651-2-dhinakaran.pandiyan@intel.com>
+To: intel-gfx@lists.freedesktop.org
+Date: Thu, 27 Sep 2018 13:57:31 -0700
+
+Commit '3cf71bc9904d ("drm/i915: Re-apply "Perform link quality check,
+unconditionally during long pulse"")' applies a work around for sinks
+that don't signal link loss. The work around does not need to have to be
+that broad as the issue was seen with only one particular monitor; limit
+this only for external displays as eDP features like PSR turn off the link
+and the driver ends up retraining the link seeeing that link is not
+synchronized.
+
+Cc: Lyude Paul <lyude@redhat.com>
+Cc: Jan-Marek Glogowski <glogow@fbihome.de>
+Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
+References: 3cf71bc9904d ("drm/i915: Re-apply "Perform link quality check, unconditionally during long pulse"")
+Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
+Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+---
+ drivers/gpu/drm/i915/intel_dp.c | 13 +++++++------
+ 1 file changed, 7 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
+index 207b3ea2ed1a..4e0870f3a4a5 100644
+--- a/drivers/gpu/drm/i915/intel_dp.c
++++ b/drivers/gpu/drm/i915/intel_dp.c
+@@ -5072,12 +5072,13 @@ intel_dp_long_pulse(struct intel_connector *connector,
+ 		 */
+ 		status = connector_status_disconnected;
+ 		goto out;
+-	} else {
+-		/*
+-		 * Some external monitors do not signal loss of link
+-		 * synchronization with an IRQ_HPD, so force a link status
+-		 * check.
+-		 */
++	}
++
++	/*
++	 * Some external monitors do not signal loss of link synchronization
++	 * with an IRQ_HPD, so force a link status check.
++	 */
++	if (!intel_dp_is_edp(intel_dp)) {
+ 		struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+ 
+ 		intel_dp_retrain_link(encoder, ctx);

CVE-2018-5391-additional.patch

@@ -0,0 +1,110 @@
+From 5d407b071dc369c26a38398326ee2be53651cfe4 Mon Sep 17 00:00:00 2001
+From: Taehee Yoo <ap420073@gmail.com>
+Date: Mon, 10 Sep 2018 02:47:05 +0900
+Subject: [PATCH] ip: frags: fix crash in ip_do_fragment()
+
+A kernel crash occurrs when defragmented packet is fragmented
+in ip_do_fragment().
+In defragment routine, skb_orphan() is called and
+skb->ip_defrag_offset is set. but skb->sk and
+skb->ip_defrag_offset are same union member. so that
+frag->sk is not NULL.
+Hence crash occurrs in skb->sk check routine in ip_do_fragment() when
+defragmented packet is fragmented.
+
+test commands:
+   %iptables -t nat -I POSTROUTING -j MASQUERADE
+   %hping3 192.168.4.2 -s 1000 -p 2000 -d 60000
+
+splat looks like:
+[  261.069429] kernel BUG at net/ipv4/ip_output.c:636!
+[  261.075753] invalid opcode: 0000 [#1] SMP DEBUG_PAGEALLOC KASAN PTI
+[  261.083854] CPU: 1 PID: 1349 Comm: hping3 Not tainted 4.19.0-rc2+ #3
+[  261.100977] RIP: 0010:ip_do_fragment+0x1613/0x2600
+[  261.106945] Code: e8 e2 38 e3 fe 4c 8b 44 24 18 48 8b 74 24 08 e9 92 f6 ff ff 80 3c 02 00 0f 85 da 07 00 00 48 8b b5 d0 00 00 00 e9 25 f6 ff ff <0f> 0b 0f 0b 44 8b 54 24 58 4c 8b 4c 24 18 4c 8b 5c 24 60 4c 8b 6c
+[  261.127015] RSP: 0018:ffff8801031cf2c0 EFLAGS: 00010202
+[  261.134156] RAX: 1ffff1002297537b RBX: ffffed0020639e6e RCX: 0000000000000004
+[  261.142156] RDX: 0000000000000000 RSI: 0000000000000000 RDI: ffff880114ba9bd8
+[  261.150157] RBP: ffff880114ba8a40 R08: ffffed0022975395 R09: ffffed0022975395
+[  261.158157] R10: 0000000000000001 R11: ffffed0022975394 R12: ffff880114ba9ca4
+[  261.166159] R13: 0000000000000010 R14: ffff880114ba9bc0 R15: dffffc0000000000
+[  261.174169] FS:  00007fbae2199700(0000) GS:ffff88011b400000(0000) knlGS:0000000000000000
+[  261.183012] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
+[  261.189013] CR2: 00005579244fe000 CR3: 0000000119bf4000 CR4: 00000000001006e0
+[  261.198158] Call Trace:
+[  261.199018]  ? dst_output+0x180/0x180
+[  261.205011]  ? save_trace+0x300/0x300
+[  261.209018]  ? ip_copy_metadata+0xb00/0xb00
+[  261.213034]  ? sched_clock_local+0xd4/0x140
+[  261.218158]  ? kill_l4proto+0x120/0x120 [nf_conntrack]
+[  261.223014]  ? rt_cpu_seq_stop+0x10/0x10
+[  261.227014]  ? find_held_lock+0x39/0x1c0
+[  261.233008]  ip_finish_output+0x51d/0xb50
+[  261.237006]  ? ip_fragment.constprop.56+0x220/0x220
+[  261.243011]  ? nf_ct_l4proto_register_one+0x5b0/0x5b0 [nf_conntrack]
+[  261.250152]  ? rcu_is_watching+0x77/0x120
+[  261.255010]  ? nf_nat_ipv4_out+0x1e/0x2b0 [nf_nat_ipv4]
+[  261.261033]  ? nf_hook_slow+0xb1/0x160
+[  261.265007]  ip_output+0x1c7/0x710
+[  261.269005]  ? ip_mc_output+0x13f0/0x13f0
+[  261.273002]  ? __local_bh_enable_ip+0xe9/0x1b0
+[  261.278152]  ? ip_fragment.constprop.56+0x220/0x220
+[  261.282996]  ? nf_hook_slow+0xb1/0x160
+[  261.287007]  raw_sendmsg+0x21f9/0x4420
+[  261.291008]  ? dst_output+0x180/0x180
+[  261.297003]  ? sched_clock_cpu+0x126/0x170
+[  261.301003]  ? find_held_lock+0x39/0x1c0
+[  261.306155]  ? stop_critical_timings+0x420/0x420
+[  261.311004]  ? check_flags.part.36+0x450/0x450
+[  261.315005]  ? _raw_spin_unlock_irq+0x29/0x40
+[  261.320995]  ? _raw_spin_unlock_irq+0x29/0x40
+[  261.326142]  ? cyc2ns_read_end+0x10/0x10
+[  261.330139]  ? raw_bind+0x280/0x280
+[  261.334138]  ? sched_clock_cpu+0x126/0x170
+[  261.338995]  ? check_flags.part.36+0x450/0x450
+[  261.342991]  ? __lock_acquire+0x4500/0x4500
+[  261.348994]  ? inet_sendmsg+0x11c/0x500
+[  261.352989]  ? dst_output+0x180/0x180
+[  261.357012]  inet_sendmsg+0x11c/0x500
+[ ... ]
+
+v2:
+ - clear skb->sk at reassembly routine.(Eric Dumarzet)
+
+Fixes: fa0f527358bd ("ip: use rb trees for IP frag queue.")
+Suggested-by: Eric Dumazet <edumazet@google.com>
+Signed-off-by: Taehee Yoo <ap420073@gmail.com>
+Reviewed-by: Eric Dumazet <edumazet@google.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ net/ipv4/ip_fragment.c                  | 1 +
+ net/ipv6/netfilter/nf_conntrack_reasm.c | 1 +
+ 2 files changed, 2 insertions(+)
+
+diff --git a/net/ipv4/ip_fragment.c b/net/ipv4/ip_fragment.c
+index 88281fbce88c..e7227128df2c 100644
+--- a/net/ipv4/ip_fragment.c
++++ b/net/ipv4/ip_fragment.c
+@@ -599,6 +599,7 @@ static int ip_frag_reasm(struct ipq *qp, struct sk_buff *skb,
+ 			nextp = &fp->next;
+ 			fp->prev = NULL;
+ 			memset(&fp->rbnode, 0, sizeof(fp->rbnode));
++			fp->sk = NULL;
+ 			head->data_len += fp->len;
+ 			head->len += fp->len;
+ 			if (head->ip_summed != fp->ip_summed)
+diff --git a/net/ipv6/netfilter/nf_conntrack_reasm.c b/net/ipv6/netfilter/nf_conntrack_reasm.c
+index 2a14d8b65924..8f68a518d9db 100644
+--- a/net/ipv6/netfilter/nf_conntrack_reasm.c
++++ b/net/ipv6/netfilter/nf_conntrack_reasm.c
+@@ -445,6 +445,7 @@ nf_ct_frag6_reasm(struct frag_queue *fq, struct sk_buff *prev,  struct net_devic
+ 		else if (head->ip_summed == CHECKSUM_COMPLETE)
+ 			head->csum = csum_add(head->csum, fp->csum);
+ 		head->truesize += fp->truesize;
++		fp->sk = NULL;
+ 	}
+ 	sub_frag_mem_limit(fq->q.net, head->truesize);
+
+-- 
+2.17.1
+

arm-tegra-fix-nouveau-crash.patch

@@ -1,64 +0,0 @@
-From 369971aa0101c4cfb84dacaaaa1b5cc5790c14ff Mon Sep 17 00:00:00 2001
-From: Thierry Reding <treding@nvidia.com>
-Date: Wed, 11 Apr 2018 10:34:17 +0200
-Subject: [PATCH] drm/nouveau: tegra: Detach from ARM DMA/IOMMU mapping
-
-Depending on the kernel configuration, early ARM architecture setup code
-may have attached the GPU to a DMA/IOMMU mapping that transparently uses
-the IOMMU to back the DMA API. Tegra requires special handling for IOMMU
-backed buffers (a special bit in the GPU's MMU page tables indicates the
-memory path to take: via the SMMU or directly to the memory controller).
-Transparently backing DMA memory with an IOMMU prevents Nouveau from
-properly handling such memory accesses and causes memory access faults.
-
-As a side-note: buffers other than those allocated in instance memory
-don't need to be physically contiguous from the GPU's perspective since
-the GPU can map them into contiguous buffers using its own MMU. Mapping
-these buffers through the IOMMU is unnecessary and will even lead to
-performance degradation because of the additional translation.
-
-Signed-off-by: Thierry Reding <treding@nvidia.com>
----
- drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 19 +++++++++++++++++++
- 1 file changed, 19 insertions(+)
-
-diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
-index 1f07999aea1d..ac7706f56f6f 100644
---- a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
-+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
-@@ -19,6 +19,11 @@
-  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-  * DEALINGS IN THE SOFTWARE.
-  */
-+
-+#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
-+#include <asm/dma-iommu.h>
-+#endif
-+
- #include <core/tegra.h>
- #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
- #include "priv.h"
-@@ -105,6 +110,20 @@ nvkm_device_tegra_probe_iommu(struct nvkm_device_tegra *tdev)
- 	unsigned long pgsize_bitmap;
- 	int ret;
- 
-+#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
-+	if (dev->archdata.mapping) {
-+		struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
-+
-+		arm_iommu_release_mapping(mapping);
-+		arm_iommu_detach_device(dev);
-+
-+		if (dev->archdata.dma_coherent)
-+			set_dma_ops(dev, &arm_coherent_dma_ops);
-+		else
-+			set_dma_ops(dev, &arm_dma_ops);
-+	}
-+#endif
-+
- 	if (!tdev->func->iommu_bit)
- 		return;
- 
--- 
-2.16.3
-

arm64-96boards-RK3399-Ficus-board.patch

@@ -0,0 +1,947 @@
+From b41023282d07b61a53e2c9b9508912b1e7ce7b4f Mon Sep 17 00:00:00 2001
+From: Randy Li <ayaka@soulik.info>
+Date: Thu, 21 Jun 2018 21:32:10 +0800
+Subject: arm64: dts: rockchip: add some common pin-settings to rk3399
+
+Those pins would be used by many boards.
+
+Signed-off-by: Randy Li <ayaka@soulik.info>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3399.dtsi | 86 ++++++++++++++++++++++++++------
+ 1 file changed, 72 insertions(+), 14 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+index adb037cd80fe..87350c694b38 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+@@ -1923,19 +1923,49 @@
+ 			drive-strength = <12>;
+ 		};
+ 
++		pcfg_pull_none_13ma: pcfg-pull-none-13ma {
++			bias-disable;
++			drive-strength = <13>;
++		};
++
++		pcfg_pull_none_18ma: pcfg-pull-none-18ma {
++			bias-disable;
++			drive-strength = <18>;
++		};
++
++		pcfg_pull_none_20ma: pcfg-pull-none-20ma {
++			bias-disable;
++			drive-strength = <20>;
++		};
++
++		pcfg_pull_up_2ma: pcfg-pull-up-2ma {
++			bias-pull-up;
++			drive-strength = <2>;
++		};
++
+ 		pcfg_pull_up_8ma: pcfg-pull-up-8ma {
+ 			bias-pull-up;
+ 			drive-strength = <8>;
+ 		};
+ 
++		pcfg_pull_up_18ma: pcfg-pull-up-18ma {
++			bias-pull-up;
++			drive-strength = <18>;
++		};
++
++		pcfg_pull_up_20ma: pcfg-pull-up-20ma {
++			bias-pull-up;
++			drive-strength = <20>;
++		};
++
+ 		pcfg_pull_down_4ma: pcfg-pull-down-4ma {
+ 			bias-pull-down;
+ 			drive-strength = <4>;
+ 		};
+ 
+-		pcfg_pull_up_2ma: pcfg-pull-up-2ma {
+-			bias-pull-up;
+-			drive-strength = <2>;
++		pcfg_pull_down_8ma: pcfg-pull-down-8ma {
++			bias-pull-down;
++			drive-strength = <8>;
+ 		};
+ 
+ 		pcfg_pull_down_12ma: pcfg-pull-down-12ma {
+@@ -1943,9 +1973,22 @@
+ 			drive-strength = <12>;
+ 		};
+ 
+-		pcfg_pull_none_13ma: pcfg-pull-none-13ma {
+-			bias-disable;
+-			drive-strength = <13>;
++		pcfg_pull_down_18ma: pcfg-pull-down-18ma {
++			bias-pull-down;
++			drive-strength = <18>;
++		};
++
++		pcfg_pull_down_20ma: pcfg-pull-down-20ma {
++			bias-pull-down;
++			drive-strength = <20>;
++		};
++
++		pcfg_output_high: pcfg-output-high {
++			output-high;
++		};
++
++		pcfg_output_low: pcfg-output-low {
++			output-low;
+ 		};
+ 
+ 		clock {
+@@ -2468,45 +2511,60 @@
+ 		pwm0 {
+ 			pwm0_pin: pwm0-pin {
+ 				rockchip,pins =
+-					<4 18 RK_FUNC_1 &pcfg_pull_none>;
++					<4 RK_PC2 RK_FUNC_1 &pcfg_pull_none>;
++			};
++
++			pwm0_pin_pull_down: pwm0-pin-pull-down {
++				rockchip,pins =
++					<4 RK_PC2 RK_FUNC_1 &pcfg_pull_down>;
+ 			};
+ 
+ 			vop0_pwm_pin: vop0-pwm-pin {
+ 				rockchip,pins =
+-					<4 18 RK_FUNC_2 &pcfg_pull_none>;
++					<4 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
++			};
++
++			vop1_pwm_pin: vop1-pwm-pin {
++				rockchip,pins =
++					<4 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
+ 			};
+ 		};
+ 
+ 		pwm1 {
+ 			pwm1_pin: pwm1-pin {
+ 				rockchip,pins =
+-					<4 22 RK_FUNC_1 &pcfg_pull_none>;
++					<4 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
+ 			};
+ 
+-			vop1_pwm_pin: vop1-pwm-pin {
++			pwm1_pin_pull_down: pwm1-pin-pull-down {
+ 				rockchip,pins =
+-					<4 18 RK_FUNC_3 &pcfg_pull_none>;
++					<4 RK_PC6 RK_FUNC_1 &pcfg_pull_down>;
+ 			};
+ 		};
+ 
+ 		pwm2 {
+ 			pwm2_pin: pwm2-pin {
+ 				rockchip,pins =
+-					<1 19 RK_FUNC_1 &pcfg_pull_none>;
++					<1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
++			};
++
++			pwm2_pin_pull_down: pwm2-pin-pull-down {
++				rockchip,pins =
++					<1 RK_PC3 RK_FUNC_1 &pcfg_pull_down>;
+ 			};
+ 		};
+ 
+ 		pwm3a {
+ 			pwm3a_pin: pwm3a-pin {
+ 				rockchip,pins =
+-					<0 6 RK_FUNC_1 &pcfg_pull_none>;
++					<0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
+ 			};
+ 		};
+ 
+ 		pwm3b {
+ 			pwm3b_pin: pwm3b-pin {
+ 				rockchip,pins =
+-					<1 14 RK_FUNC_1 &pcfg_pull_none>;
++					<1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;
+ 			};
+ 		};
+ 
+-- 
+cgit 1.2-0.3.lf.el7
+From 7c41a3f42a51d88e271c989c16be178bd6d38dfe Mon Sep 17 00:00:00 2001
+From: Peter Robinson <pbrobinson@gmail.com>
+Date: Mon, 10 Sep 2018 18:17:36 +0100
+Subject: [PATCH 1/4] arm64: dts: rockchip: add 96boards RK3399 Ficus board
+
+The RK3399 Ficus board is an Enterprise Edition board
+manufactured by Vamrs Ltd., based on the Rockchip RK3399 SoC.
+
+The board exposes a bunch of nice peripherals, including
+SATA, HDMI, MIPI CSI, Ethernet, WiFi, and PCIe.
+
+Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
+---
+ .../devicetree/bindings/arm/rockchip.txt      |   5 +
+ arch/arm64/boot/dts/rockchip/Makefile         |   1 +
+ arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 514 ++++++++++++++++++
+ 3 files changed, 520 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
+
+diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt
+index 1c1d62d03c4f..d46c5d43e27f 100644
+--- a/Documentation/devicetree/bindings/arm/rockchip.txt
++++ b/Documentation/devicetree/bindings/arm/rockchip.txt
+@@ -1,5 +1,10 @@
+ Rockchip platforms device tree bindings
+ ---------------------------------------
++
++- 96boards RK3399 Ficus (ROCK960 Enterprise Edition)
++    Required root node properties:
++      - compatible = "vamrs,ficus", "rockchip,rk3399";
++
+ - Amarula Vyasa RK3288 board
+     Required root node properties:
+       - compatible = "amarula,vyasa-rk3288", "rockchip,rk3288";
+diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
+index 48a83f882947..2811fb701f12 100644
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
+new file mode 100644
+index 000000000000..0d14183dd4a9
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
+@@ -0,0 +1,514 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2018 Collabora Ltd.
++ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
++ *
++ * Schematics available at https://dl.vamrs.com/products/ficus/docs/hw
++ */
++
++/dts-v1/;
++#include "rk3399.dtsi"
++#include "rk3399-opp.dtsi"
++
++/ {
++	model = "96boards RK3399 Ficus";
++	compatible = "vamrs,ficus", "rockchip,rk3399";
++
++	chosen {
++		stdout-path = "serial2:1500000n8";
++	};
++
++	clkin_gmac: external-gmac-clock {
++		compatible = "fixed-clock";
++		clock-frequency = <125000000>;
++		clock-output-names = "clkin_gmac";
++		#clock-cells = <0>;
++	};
++
++	vcc1v8_s0: vcc1v8-s0 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc1v8_s0";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-always-on;
++	};
++
++	vcc_sys: vcc-sys {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_sys";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-always-on;
++	};
++
++	vcc3v3_sys: vcc3v3-sys {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3_sys";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-always-on;
++		vin-supply = <&vcc_sys>;
++	};
++
++	vcc3v3_pcie: vcc3v3-pcie-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pcie_drv>;
++		regulator-boot-on;
++		regulator-name = "vcc3v3_pcie";
++		vin-supply = <&vcc3v3_sys>;
++	};
++
++	vdd_log: vdd-log {
++		compatible = "pwm-regulator";
++		pwms = <&pwm2 0 25000 0>;
++		regulator-name = "vdd_log";
++		regulator-min-microvolt = <800000>;
++		regulator-max-microvolt = <1400000>;
++		regulator-always-on;
++		regulator-boot-on;
++
++		/* for rockchip boot on */
++		rockchip,pwm_id= <2>;
++		rockchip,pwm_voltage = <900000>;
++
++		vin-supply = <&vcc_sys>;
++	};
++
++};
++
++&cpu_l0 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_l1 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_l2 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_l3 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_b0 {
++	cpu-supply = <&vdd_cpu_b>;
++};
++
++&cpu_b1 {
++	cpu-supply = <&vdd_cpu_b>;
++};
++
++&emmc_phy {
++	status = "okay";
++};
++
++&gmac {
++	assigned-clocks = <&cru SCLK_RMII_SRC>;
++	assigned-clock-parents = <&clkin_gmac>;
++	clock_in_out = "input";
++	phy-supply = <&vcc3v3_sys>;
++	phy-mode = "rgmii";
++	pinctrl-names = "default";
++	pinctrl-0 = <&rgmii_pins>;
++	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
++	snps,reset-active-low;
++	snps,reset-delays-us = <0 10000 50000>;
++	tx_delay = <0x28>;
++	rx_delay = <0x11>;
++	status = "okay";
++};
++
++&hdmi {
++	ddc-i2c-bus = <&i2c3>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&hdmi_cec>;
++	status = "okay";
++};
++
++&i2c0 {
++	clock-frequency = <400000>;
++	i2c-scl-rising-time-ns = <168>;
++	i2c-scl-falling-time-ns = <4>;
++	status = "okay";
++
++	vdd_cpu_b: regulator@40 {
++		compatible = "silergy,syr827";
++		reg = <0x40>;
++		fcs,suspend-voltage-selector = <1>;
++		regulator-name = "vdd_cpu_b";
++		regulator-min-microvolt = <712500>;
++		regulator-max-microvolt = <1500000>;
++		regulator-ramp-delay = <1000>;
++		regulator-always-on;
++		regulator-boot-on;
++		vin-supply = <&vcc_sys>;
++		status = "okay";
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++
++	vdd_gpu: regulator@41 {
++		compatible = "silergy,syr828";
++		reg = <0x41>;
++		fcs,suspend-voltage-selector = <1>;
++		regulator-name = "vdd_gpu";
++		regulator-min-microvolt = <712500>;
++		regulator-max-microvolt = <1500000>;
++		regulator-ramp-delay = <1000>;
++		regulator-always-on;
++		regulator-boot-on;
++		vin-supply = <&vcc_sys>;
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++
++	rk808: pmic@1b {
++		compatible = "rockchip,rk808";
++		reg = <0x1b>;
++		interrupt-parent = <&gpio1>;
++		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pmic_int_l>;
++		rockchip,system-power-controller;
++		wakeup-source;
++		#clock-cells = <1>;
++		clock-output-names = "xin32k", "rk808-clkout2";
++
++		vcc1-supply = <&vcc_sys>;
++		vcc2-supply = <&vcc_sys>;
++		vcc3-supply = <&vcc_sys>;
++		vcc4-supply = <&vcc_sys>;
++		vcc6-supply = <&vcc_sys>;
++		vcc7-supply = <&vcc_sys>;
++		vcc8-supply = <&vcc3v3_sys>;
++		vcc9-supply = <&vcc_sys>;
++		vcc10-supply = <&vcc_sys>;
++		vcc11-supply = <&vcc_sys>;
++		vcc12-supply = <&vcc3v3_sys>;
++		vddio-supply = <&vcc_1v8>;
++
++		regulators {
++			vdd_center: DCDC_REG1 {
++				regulator-name = "vdd_center";
++				regulator-min-microvolt = <750000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_cpu_l: DCDC_REG2 {
++				regulator-name = "vdd_cpu_l";
++				regulator-min-microvolt = <750000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_ddr: DCDC_REG3 {
++				regulator-name = "vcc_ddr";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++
++			vcc_1v8: DCDC_REG4 {
++				regulator-name = "vcc_1v8";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcc1v8_dvp: LDO_REG1 {
++				regulator-name = "vcc1v8_dvp";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcca1v8_hdmi: LDO_REG2 {
++				regulator-name = "vcca1v8_hdmi";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcca_1v8: LDO_REG3 {
++				regulator-name = "vcca_1v8";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcc_sd: LDO_REG4 {
++				regulator-name = "vcc_sd";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vcc3v0_sd: LDO_REG5 {
++				regulator-name = "vcc3v0_sd";
++				regulator-min-microvolt = <3000000>;
++				regulator-max-microvolt = <3000000>;
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3000000>;
++				};
++			};
++
++			vcc_1v5: LDO_REG6 {
++				regulator-name = "vcc_1v5";
++				regulator-min-microvolt = <1500000>;
++				regulator-max-microvolt = <1500000>;
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1500000>;
++				};
++			};
++
++			vcca0v9_hdmi: LDO_REG7 {
++				regulator-name = "vcca0v9_hdmi";
++				regulator-min-microvolt = <900000>;
++				regulator-max-microvolt = <900000>;
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <900000>;
++				};
++			};
++
++			vcc_3v0: LDO_REG8 {
++				regulator-name = "vcc_3v0";
++				regulator-min-microvolt = <3000000>;
++				regulator-max-microvolt = <3000000>;
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3000000>;
++				};
++			};
++
++			vcc3v3_s3: SWITCH_REG1 {
++				regulator-name = "vcc3v3_s3";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++
++			vcc3v3_s0: SWITCH_REG2 {
++				regulator-name = "vcc3v3_s0";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++		};
++	};
++};
++
++&i2c1 {
++	status = "okay";
++};
++
++&i2c2 {
++	status = "okay";
++};
++
++&i2c3 {
++	status = "okay";
++};
++
++&i2c4 {
++	status = "okay";
++};
++
++&io_domains {
++	bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */
++	audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */
++	sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */
++	gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */
++	status = "okay";
++};
++
++&pcie_phy {
++	status = "okay";
++};
++
++&pcie0 {
++	ep-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
++	num-lanes = <4>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&pcie_clkreqn_cpm>;
++	vpcie3v3-supply = <&vcc3v3_pcie>;
++	status = "okay";
++};
++
++&pmu_io_domains {
++	pmu1830-supply = <&vcc_1v8>;
++	status = "okay";
++};
++
++&pinctrl {
++	gmac {
++		rgmii_sleep_pins: rgmii-sleep-pins {
++			rockchip,pins =
++				<3 15 RK_FUNC_GPIO &pcfg_output_low>;
++		};
++	};
++
++	sdmmc {
++		sdmmc_bus1: sdmmc-bus1 {
++			rockchip,pins =
++				<4 8 RK_FUNC_1 &pcfg_pull_up_8ma>;
++		};
++
++		sdmmc_bus4: sdmmc-bus4 {
++			rockchip,pins =
++				<4 8 RK_FUNC_1 &pcfg_pull_up_8ma>,
++				<4 9 RK_FUNC_1 &pcfg_pull_up_8ma>,
++				<4 10 RK_FUNC_1 &pcfg_pull_up_8ma>,
++				<4 11 RK_FUNC_1 &pcfg_pull_up_8ma>;
++		};
++
++		sdmmc_clk: sdmmc-clk {
++			rockchip,pins =
++				<4 12 RK_FUNC_1 &pcfg_pull_none_18ma>;
++		};
++
++		sdmmc_cmd: sdmmc-cmd {
++			rockchip,pins =
++				<4 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
++		};
++	};
++
++	pcie {
++		pcie_drv: pcie-drv {
++			rockchip,pins =
++				<1 24 RK_FUNC_GPIO &pcfg_pull_none>;
++			};
++	};
++
++	pmic {
++		pmic_int_l: pmic-int-l {
++			rockchip,pins =
++				<1 21 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++
++		vsel1_gpio: vsel1-gpio {
++			rockchip,pins =
++				<1 17 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++
++		vsel2_gpio: vsel2-gpio {
++			rockchip,pins =
++				<1 14 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++	};
++};
++
++&pwm2 {
++	status = "okay";
++};
++
++&pwm3 {
++	status = "okay";
++};
++
++&sdhci {
++	bus-width = <8>;
++	mmc-hs400-1_8v;
++	mmc-hs400-enhanced-strobe;
++	non-removable;
++	status = "okay";
++};
++
++&sdmmc {
++	bus-width = <4>;
++	cap-mmc-highspeed;
++	cap-sd-highspeed;
++	clock-frequency = <100000000>;
++	clock-freq-min-max = <100000 100000000>;
++	disable-wp;
++	sd-uhs-sdr104;
++	vqmmc-supply = <&vcc_sd>;
++	card-detect-delay = <800>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
++	status = "okay";
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_xfer &uart0_cts>;
++	status = "okay";
++};
++
++&uart2 {
++	status = "okay";
++};
++
++&vopb {
++	status = "okay";
++};
++
++&vopb_mmu {
++	status = "okay";
++};
++
++&vopl {
++	status = "okay";
++};
++
++&vopl_mmu {
++	status = "okay";
++};
+-- 
+2.19.0.rc1
+
+From 2e3f4fb6f0a94b6cf56407536414b93bd3c45471 Mon Sep 17 00:00:00 2001
+From: Enric Balletbo i Serra <enric.balletbo@collabora.com>
+Date: Sat, 14 Jul 2018 14:09:22 -0300
+Subject: [PATCH 2/4] arm64: dts: rockchip: add USB 2.0 and 3.0 support on
+ Ficus board
+
+The board exposes two types A ports, one is USB 3.0, up to 5.0Gbps and
+another one is USB 2.0 up to 480Mbps. Enable the USB PHYs and the USB
+controllers to enable theses devices.
+
+Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
+Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 88 +++++++++++++++++++
+ 1 file changed, 88 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
+index 0d14183dd4a9..890b9e13cfe8 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
+@@ -61,6 +61,19 @@
+ 		vin-supply = <&vcc3v3_sys>;
+ 	};
+ 
++	vcc5v0_host: vcc5v0-host-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&host_vbus_drv>;
++		regulator-name = "vcc5v0_host";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-always-on;
++		vin-supply = <&vcc_sys>;
++	};
++
+ 	vdd_log: vdd-log {
+ 		compatible = "pwm-regulator";
+ 		pwms = <&pwm2 0 25000 0>;
+@@ -454,6 +467,13 @@
+ 				<1 14 RK_FUNC_GPIO &pcfg_pull_down>;
+ 		};
+ 	};
++
++	usb2 {
++		host_vbus_drv: host-vbus-drv {
++			rockchip,pins =
++				<4 27 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
+ };
+ 
+ &pwm2 {
+@@ -487,6 +507,40 @@
+ 	status = "okay";
+ };
+ 
++&tcphy0 {
++	status = "okay";
++};
++
++&tcphy1 {
++	status = "okay";
++};
++
++&u2phy0 {
++	status = "okay";
++};
++
++&u2phy1 {
++	status = "okay";
++};
++
++&u2phy0_host {
++	phy-supply = <&vcc5v0_host>;
++	status = "okay";
++};
++
++&u2phy1_host {
++	phy-supply = <&vcc5v0_host>;
++	status = "okay";
++};
++
++&u2phy0_otg {
++	status = "okay";
++};
++
++&u2phy1_otg {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_xfer &uart0_cts>;
+@@ -497,6 +551,40 @@
+ 	status = "okay";
+ };
+ 
++&usb_host0_ehci {
++	status = "okay";
++};
++
++&usb_host0_ohci {
++	status = "okay";
++};
++
++&usb_host1_ehci {
++	status = "okay";
++};
++
++&usb_host1_ohci {
++	status = "okay";
++};
++
++&usbdrd3_0 {
++	status = "okay";
++};
++
++&usbdrd_dwc3_0 {
++	status = "okay";
++	dr_mode = "host";
++};
++
++&usbdrd3_1 {
++	status = "okay";
++};
++
++&usbdrd_dwc3_1 {
++	status = "okay";
++	dr_mode = "host";
++};
++
+ &vopb {
+ 	status = "okay";
+ };
+-- 
+2.19.0.rc1
+
+From d875193399378e17911829b9df9d27fd4a1ba195 Mon Sep 17 00:00:00 2001
+From: Enric Balletbo i Serra <enric.balletbo@collabora.com>
+Date: Sat, 14 Jul 2018 14:09:22 -0300
+Subject: [PATCH 3/4] arm64: dts: rockchip: add voltage properties for
+ vcc3v3_pcie on rk3399 ficus
+
+The vcc3v3_pcie regulator supplies 3.3V so add voltage properties
+for it.
+
+Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
+Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
+[split off from original patch]
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
+index 890b9e13cfe8..6295483b701f 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
+@@ -58,6 +58,8 @@
+ 		pinctrl-0 = <&pcie_drv>;
+ 		regulator-boot-on;
+ 		regulator-name = "vcc3v3_pcie";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
+ 		vin-supply = <&vcc3v3_sys>;
+ 	};
+ 
+-- 
+2.19.0.rc1
+
+From 416756dbf32ff2394b320fa88c09e9461496fc4c Mon Sep 17 00:00:00 2001
+From: Heiko Stuebner <heiko@sntech.de>
+Date: Mon, 16 Jul 2018 18:52:44 +0200
+Subject: [PATCH 4/4] arm64: dts: rockchip: drop out-of-tree properties from
+ rk3399-ficus regulator
+
+The pwm-regulator for vdd_log uses additional unreviewed properties in the
+vendor kernel, which slipped in with the devicetree.
+As written, they are unreviewed and unused in all mainline implementations
+so drop them again.
+
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 5 -----
+ 1 file changed, 5 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
+index 6295483b701f..8978d924eb83 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
+@@ -84,11 +84,6 @@
+ 		regulator-max-microvolt = <1400000>;
+ 		regulator-always-on;
+ 		regulator-boot-on;
+-
+-		/* for rockchip boot on */
+-		rockchip,pwm_id= <2>;
+-		rockchip,pwm_voltage = <900000>;
+-
+ 		vin-supply = <&vcc_sys>;
+ 	};
+ 
+-- 
+2.19.0.rc1
+

arm64-drm-msm-fix-missing-CTL-flush.patch

@@ -0,0 +1,42 @@
+From 6e8bed6a3e2fd6f1e82ea9b1f705bbc82060a2b7 Mon Sep 17 00:00:00 2001
+From: Rob Clark <robdclark@gmail.com>
+Date: Tue, 3 Jul 2018 08:14:32 -0400
+Subject: [PATCH] drm/msm/mdp5: fix missing CTL flush
+
+f9cb8d8d836e fixed various race conditions with CTL flush, in particular
+flushing and sending the START signal before encoder state was updated.
+But it did this a little too well in some cases that don't trigger
+encoder->enable(), and CTL[n].FLUSH would never be set.  When page flips
+happen it would paper over the bug, since the first plag flip would
+flush out the state to the hardware.
+
+The issue could be reproduced with, for example, modetest (without the
+'-v' argument).
+
+Fixes: f9cb8d8d836e drm/msm/mdp5: rework CTL START signal handling
+Signed-off-by: Rob Clark <robdclark@gmail.com>
+Reviewed-by: Sean Paul <seanpaul@chromium.org>
+
+diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c
+index 9af94e35f678..fcd44d1d1068 100644
+--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c
++++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c
+@@ -319,7 +319,17 @@ static int mdp5_encoder_atomic_check(struct drm_encoder *encoder,
+ 
+ 	mdp5_cstate->ctl = ctl;
+ 	mdp5_cstate->pipeline.intf = intf;
+-	mdp5_cstate->defer_start = true;
++
++	/*
++	 * This is a bit awkward, but we want to flush the CTL and hit the
++	 * START bit at most once for an atomic update.  In the non-full-
++	 * modeset case, this is done from crtc->atomic_flush(), but that
++	 * is too early in the case of full modeset, in which case we
++	 * defer to encoder->enable().  But we need to *know* whether
++	 * encoder->enable() will be called to do this:
++	 */
++	if (drm_atomic_crtc_needs_modeset(crtc_state))
++		mdp5_cstate->defer_start = true;
+ 
+ 	return 0;
+ }

arm64-dts-marvell-a3700-reserve-ATF-memory.patch

@@ -0,0 +1,45 @@
+From e1912a821a992f04c258e844d717733de03daeb7 Mon Sep 17 00:00:00 2001
+From: Peter Robinson <pbrobinson@gmail.com>
+Date: Wed, 15 Aug 2018 14:06:45 +0100
+Subject: [PATCH] arm64: dts: marvell: a3700: reserve ATF memory
+
+On Marvell Armada 3700, the ARM Trusted Firmware is loaded in RAM at address
+0x04000000, and can use up to 16MiB (0x01000000).
+
+As the ATF is responsible for handling PSCI calls (including, but not limited
+to, system reset management), its memory area should never be overwritten
+during runtime.
+
+Declaring a range of reserved memory solves this problem.
+
+Signed-off-by: Arnaud Ferraris <arnaud.ferraris.external@xxxxxxxxxx>
+Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
+---
+ arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+index 3353252d78a0a..2110e7dbc9818 100644
+--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+@@ -34,6 +34,17 @@
+ 		};
+ 	};
+ 
++	reserved-memory {
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++
++		arm-trusted-firmware@4000000 {
++			no-map;
++			reg = <0x0 0x04000000 0x0 0x01000000>;
++		};
++	};
++
+ 	psci {
+ 		compatible = "arm,psci-0.2";
+ 		method = "smc";
+-- 
+2.17.1
+

arm64-rockchip-add-initial-Rockpro64.patch

@@ -0,0 +1,862 @@
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+X-Patchwork-Id: 10615319
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+From: Akash Gajjar <Akash_Gajjar@mentor.com>
+To: <heiko@sntech.de>
+Subject: [PATCH v3] arm64: dts: rockchip: add initial dts support for
+ Rockpro64
+Date: Wed, 26 Sep 2018 11:54:57 +0530
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+
+Rockpro64 is a rockchip RK3399 based board from pine64.org.
+This patch adds basic device node support for Rockpro64 board and make it able
+to bring up.
+
+Peripheral Works
+- Sdcard
+- USB 2.0, 3.0
+- Leds
+- Ethernet
+- Debug console
+
+Not working:
+- USB Type-C
+
+Signed-off-by: Akash Gajjar <Akash_Gajjar@mentor.com>
+Acked-by: Deepak Das <Deepak_Das@mentor.com>
+---
+changes for v2
+- Added support for usb 2.0, 3.0
+- Added fusb302 node and its regulator support
+- Cleanup pinctrl node
+- Remove backlight, pcie, sound codec node inherited from firefly-rk3399 dts
+changes for v3
+- Added copyright properly
+- Typo correction in commit message
+
+ Documentation/devicetree/bindings/arm/rockchip.txt |   4 +
+ arch/arm64/boot/dts/rockchip/Makefile              |   1 +
+ arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts  | 692 +++++++++++++++++++++
+ 3 files changed, 697 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts
+
+diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt
+index acfd3c7..ac95183 100644
+--- a/Documentation/devicetree/bindings/arm/rockchip.txt
++++ b/Documentation/devicetree/bindings/arm/rockchip.txt
+@@ -160,6 +160,10 @@ Rockchip platforms device tree bindings
+     Required root node properties:
+     - compatible = "pine64,rock64", "rockchip,rk3328";
+ 
++- Pine64 RockPro64 board:
++    Required root node properties:
++    - compatible = "pine64,rockpro64", "rockchip,rk3399";
++
+ - Rockchip PX3 Evaluation board:
+     Required root node properties:
+       - compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188";
+diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
+index b0092d9..03d523a 100644
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -15,5 +15,6 @@
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts
+new file mode 100644
+index 0000000..1d35f54
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts
+@@ -0,0 +1,692 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
++ * Copyright (c) 2018 Akash Gajjar <Akash_Gajjar@mentor.com>
++ */
++
++/dts-v1/;
++#include <dt-bindings/input/linux-event-codes.h>
++#include <dt-bindings/pwm/pwm.h>
++#include "rk3399.dtsi"
++#include "rk3399-opp.dtsi"
++
++/ {
++	model = "Pine64 RockPro64";
++	compatible = "pine64,rockpro64", "rockchip,rk3399";
++
++	chosen {
++		stdout-path = "serial2:1500000n8";
++	};
++
++	clkin_gmac: external-gmac-clock {
++		compatible = "fixed-clock";
++		clock-frequency = <125000000>;
++		clock-output-names = "clkin_gmac";
++		#clock-cells = <0>;
++	};
++
++	dc_12v: dc-12v {
++		compatible = "regulator-fixed";
++		regulator-name = "dc_12v";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <12000000>;
++		regulator-max-microvolt = <12000000>;
++	};
++
++	gpio-keys {
++		compatible = "gpio-keys";
++		autorepeat;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pwrbtn>;
++
++		power {
++			debounce-interval = <100>;
++			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
++			label = "GPIO Key Power";
++			linux,code = <KEY_POWER>;
++			wakeup-source;
++		};
++	};
++
++	leds {
++		compatible = "gpio-leds";
++		pinctrl-names = "default";
++		pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>;
++
++		work-led {
++			label = "work";
++			default-state = "on";
++			gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
++		};
++
++		diy-led {
++			label = "diy";
++			default-state = "off";
++			gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
++		};
++	};
++
++	sdio_pwrseq: sdio-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rk808 1>;
++		clock-names = "ext_clock";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_enable_h>;
++
++		/*
++		 * On the module itself this is one of these (depending
++		 * on the actual card populated):
++		 * - SDIO_RESET_L_WL_REG_ON
++		 * - PDN (power down when low)
++		 */
++		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
++	};
++
++	/* switched by pmic_sleep */
++	vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc1v8_s3";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		vin-supply = <&vcc_1v8>;
++	};
++
++	vcc3v3_pcie: vcc3v3-pcie-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pcie_pwr_en>;
++		regulator-name = "vcc3v3_pcie";
++		regulator-always-on;
++		regulator-boot-on;
++		vin-supply = <&dc_12v>;
++	};
++
++	vcc3v3_sys: vcc3v3-sys {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc_sys>;
++	};
++
++	/* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
++	vcc5v0_host: vcc5v0-host-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc5v0_host_en>;
++		regulator-name = "vcc5v0_host";
++		regulator-always-on;
++		vin-supply = <&vcc_sys>;
++	};
++
++	vcc5v0_typec: vcc5v0-typec-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc5v0_typec_en>;
++		regulator-name = "vcc5v0_typec";
++		regulator-always-on;
++		vin-supply = <&vcc_sys>;
++	};
++
++	vcc_sys: vcc-sys {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&dc_12v>;
++	};
++
++	vdd_log: vdd-log {
++		compatible = "pwm-regulator";
++		pwms = <&pwm2 0 25000 1>;
++		regulator-name = "vdd_log";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <800000>;
++		regulator-max-microvolt = <1400000>;
++		vin-supply = <&vcc_sys>;
++	};
++};
++
++&cpu_l0 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_l1 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_l2 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_l3 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_b0 {
++	cpu-supply = <&vdd_cpu_b>;
++};
++
++&cpu_b1 {
++	cpu-supply = <&vdd_cpu_b>;
++};
++
++&emmc_phy {
++	status = "okay";
++};
++
++&gmac {
++	assigned-clocks = <&cru SCLK_RMII_SRC>;
++	assigned-clock-parents = <&clkin_gmac>;
++	clock_in_out = "input";
++	phy-supply = <&vcc_lan>;
++	phy-mode = "rgmii";
++	pinctrl-names = "default";
++	pinctrl-0 = <&rgmii_pins>;
++	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
++	snps,reset-active-low;
++	snps,reset-delays-us = <0 10000 50000>;
++	tx_delay = <0x28>;
++	rx_delay = <0x11>;
++	status = "okay";
++};
++
++&i2c0 {
++	clock-frequency = <400000>;
++	i2c-scl-rising-time-ns = <168>;
++	i2c-scl-falling-time-ns = <4>;
++	status = "okay";
++
++	rk808: pmic@1b {
++		compatible = "rockchip,rk808";
++		reg = <0x1b>;
++		interrupt-parent = <&gpio1>;
++		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
++		#clock-cells = <1>;
++		clock-output-names = "xin32k", "rk808-clkout2";
++		pinctrl-names = "default";
++		pinctrl-0 = <&pmic_int_l>;
++		rockchip,system-power-controller;
++		wakeup-source;
++
++		vcc1-supply = <&vcc_sys>;
++		vcc2-supply = <&vcc_sys>;
++		vcc3-supply = <&vcc_sys>;
++		vcc4-supply = <&vcc_sys>;
++		vcc6-supply = <&vcc_sys>;
++		vcc7-supply = <&vcc_sys>;
++		vcc8-supply = <&vcc3v3_sys>;
++		vcc9-supply = <&vcc_sys>;
++		vcc10-supply = <&vcc_sys>;
++		vcc11-supply = <&vcc_sys>;
++		vcc12-supply = <&vcc3v3_sys>;
++		vddio-supply = <&vcc1v8_pmu>;
++
++		regulators {
++			vdd_center: DCDC_REG1 {
++				regulator-name = "vdd_center";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <750000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_cpu_l: DCDC_REG2 {
++				regulator-name = "vdd_cpu_l";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <750000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_ddr: DCDC_REG3 {
++				regulator-name = "vcc_ddr";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++
++			vcc_1v8: DCDC_REG4 {
++				regulator-name = "vcc_1v8";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcc1v8_dvp: LDO_REG1 {
++				regulator-name = "vcc1v8_dvp";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc2v8_dvp: LDO_REG2 {
++				regulator-name = "vcc2v8_dvp";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <2800000>;
++				regulator-max-microvolt = <2800000>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc1v8_pmu: LDO_REG3 {
++				regulator-name = "vcc1v8_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcc_sdio: LDO_REG4 {
++				regulator-name = "vcc_sdio";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3000000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3000000>;
++				};
++			};
++
++			vcca3v0_codec: LDO_REG5 {
++				regulator-name = "vcca3v0_codec";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3000000>;
++				regulator-max-microvolt = <3000000>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_1v5: LDO_REG6 {
++				regulator-name = "vcc_1v5";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1500000>;
++				regulator-max-microvolt = <1500000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1500000>;
++				};
++			};
++
++			vcca1v8_codec: LDO_REG7 {
++				regulator-name = "vcca1v8_codec";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_3v0: LDO_REG8 {
++				regulator-name = "vcc_3v0";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3000000>;
++				regulator-max-microvolt = <3000000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3000000>;
++				};
++			};
++
++			vcc3v3_s3: vcc_lan: SWITCH_REG1 {
++				regulator-name = "vcc3v3_s3";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc3v3_s0: SWITCH_REG2 {
++				regulator-name = "vcc3v3_s0";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++		};
++	};
++
++	vdd_cpu_b: regulator@40 {
++		compatible = "silergy,syr827";
++		reg = <0x40>;
++		fcs,suspend-voltage-selector = <0>;
++		regulator-name = "vdd_cpu_b";
++		regulator-min-microvolt = <712500>;
++		regulator-max-microvolt = <1500000>;
++		regulator-ramp-delay = <1000>;
++		regulator-always-on;
++		regulator-boot-on;
++		vin-supply = <&vcc_sys>;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++
++	vdd_gpu: regulator@41 {
++		compatible = "silergy,syr828";
++		reg = <0x41>;
++		fcs,suspend-voltage-selector = <1>;
++		regulator-name = "vdd_gpu";
++		regulator-min-microvolt = <712500>;
++		regulator-max-microvolt = <1500000>;
++		regulator-ramp-delay = <1000>;
++		regulator-always-on;
++		regulator-boot-on;
++		vin-supply = <&vcc_sys>;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++};
++
++&i2c1 {
++	i2c-scl-rising-time-ns = <300>;
++	i2c-scl-falling-time-ns = <15>;
++	status = "okay";
++};
++
++&i2c3 {
++	i2c-scl-rising-time-ns = <450>;
++	i2c-scl-falling-time-ns = <15>;
++	status = "okay";
++};
++
++&i2c4 {
++	i2c-scl-rising-time-ns = <600>;
++	i2c-scl-falling-time-ns = <20>;
++	status = "okay";
++
++	fusb0: typec-portc@22 {
++		compatible = "fcs,fusb302";
++		reg = <0x22>;
++		interrupt-parent = <&gpio1>;
++		interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&fusb0_int>;
++		vbus-supply = <&vcc5v0_typec>;
++		status = "okay";
++	};
++};
++
++&i2s0 {
++	rockchip,playback-channels = <8>;
++	rockchip,capture-channels = <8>;
++	status = "okay";
++};
++
++&i2s1 {
++	rockchip,playback-channels = <2>;
++	rockchip,capture-channels = <2>;
++	status = "okay";
++};
++
++&i2s2 {
++	status = "okay";
++};
++
++&io_domains {
++	status = "okay";
++
++	bt656-supply = <&vcc1v8_dvp>;
++	audio-supply = <&vcca1v8_codec>;
++	sdmmc-supply = <&vcc_sdio>;
++	gpio1830-supply = <&vcc_3v0>;
++};
++
++&pmu_io_domains {
++	pmu1830-supply = <&vcc_3v0>;
++	status = "okay";
++};
++
++&pinctrl {
++	buttons {
++		pwrbtn: pwrbtn {
++			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	fusb302x {
++		fusb0_int: fusb0-int {
++			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	leds {
++		work_led_gpio: work_led-gpio {
++			rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		diy_led_gpio: diy_led-gpio {
++			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	lcd-panel {
++		lcd_panel_reset: lcd-panel-reset {
++			rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	pcie {
++		pcie_pwr_en: pcie-pwr-en {
++			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	pmic {
++		pmic_int_l: pmic-int-l {
++			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++
++		vsel1_gpio: vsel1-gpio {
++			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++
++		vsel2_gpio: vsel2-gpio {
++			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++	};
++
++	sdio-pwrseq {
++		wifi_enable_h: wifi-enable-h {
++			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	usb-typec {
++		vcc5v0_typec_en: vcc5v0_typec_en {
++			rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	usb2 {
++		vcc5v0_host_en: vcc5v0-host-en {
++			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++};
++
++&pwm0 {
++	status = "okay";
++};
++
++&pwm2 {
++	status = "okay";
++};
++
++&saradc {
++	vref-supply = <&vcca1v8_s3>;
++	status = "okay";
++};
++
++&sdmmc {
++	bus-width = <4>;
++	cap-mmc-highspeed;
++	cap-sd-highspeed;
++	cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
++	disable-wp;
++	max-frequency = <150000000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
++	status = "okay";
++};
++
++&sdhci {
++	bus-width = <8>;
++	mmc-hs400-1_8v;
++	mmc-hs400-enhanced-strobe;
++	non-removable;
++	status = "okay";
++};
++
++&tcphy0 {
++	status = "okay";
++};
++
++&tcphy1 {
++	status = "okay";
++};
++
++&tsadc {
++	/* tshut mode 0:CRU 1:GPIO */
++	rockchip,hw-tshut-mode = <1>;
++	/* tshut polarity 0:LOW 1:HIGH */
++	rockchip,hw-tshut-polarity = <1>;
++	status = "okay";
++};
++
++&u2phy0 {
++	status = "okay";
++
++	u2phy0_otg: otg-port {
++		status = "okay";
++	};
++
++	u2phy0_host: host-port {
++		phy-supply = <&vcc5v0_host>;
++		status = "okay";
++	};
++};
++
++&u2phy1 {
++	status = "okay";
++
++	u2phy1_otg: otg-port {
++		status = "okay";
++	};
++
++	u2phy1_host: host-port {
++		phy-supply = <&vcc5v0_host>;
++		status = "okay";
++	};
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_xfer &uart0_cts>;
++	status = "okay";
++};
++
++&uart2 {
++	status = "okay";
++};
++
++&usb_host0_ehci {
++	status = "okay";
++};
++
++&usb_host0_ohci {
++	status = "okay";
++};
++
++&usb_host1_ehci {
++	status = "okay";
++};
++
++&usb_host1_ohci {
++	status = "okay";
++};
++
++&usbdrd3_0 {
++	status = "okay";
++};
++
++&usbdrd_dwc3_0 {
++	status = "okay";
++	dr_mode = "otg";
++};
++
++&usbdrd3_1 {
++	status = "okay";
++};
++
++&usbdrd_dwc3_1 {
++	status = "okay";
++	dr_mode = "host";
++};
++
++&vopb {
++	status = "okay";
++};
++
++&vopb_mmu {
++	status = "okay";
++};
++
++&vopl {
++	status = "okay";
++};
++
++&vopl_mmu {
++	status = "okay";
++};

bcm2835-cpufreq-add-CPU-frequency-control-driver.patch

@@ -299,3 +299,98 @@ index 4adb85e66be3..aaefb078f391 100644
 -- 
 2.17.1
 
+From d00bd46b40001d3500b8a7207dcfe1d66600e47e Mon Sep 17 00:00:00 2001
+From: Stefan Wahren <stefan.wahren@i2se.com>
+Date: Wed, 26 Sep 2018 21:13:22 +0200
+Subject: [PATCH] ARM: bcm2837: Use CPU0 as cooling device
+
+Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
+---
+ arch/arm/boot/dts/bcm2837.dtsi | 25 +++++++++++++++++++++++++
+ arch/arm/boot/dts/bcm283x.dtsi |  2 +-
+ 2 files changed, 26 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi
+index 9cfc553..1590d94 100644
+--- a/arch/arm/boot/dts/bcm2837.dtsi
++++ b/arch/arm/boot/dts/bcm2837.dtsi
+@@ -1,4 +1,5 @@
+ #include "bcm283x.dtsi"
++#include <dt-bindings/thermal/thermal.h>
+ 
+ / {
+ 	compatible = "brcm,bcm2837";
+@@ -47,6 +48,7 @@
+ 			clocks = <&arm_clk>;
+ 			clock-names = "cpu";
+ 			operating-points-v2 = <&cpu0_opp_table>;
++			#cooling-cells = <2>;
+ 		};
+ 
+ 		cpu1: cpu@1 {
+@@ -58,6 +60,7 @@
+ 			clocks = <&arm_clk>;
+ 			clock-names = "cpu";
+ 			operating-points-v2 = <&cpu0_opp_table>;
++			#cooling-cells = <2>;
+ 		};
+ 
+ 		cpu2: cpu@2 {
+@@ -69,6 +72,7 @@
+ 			clocks = <&arm_clk>;
+ 			clock-names = "cpu";
+ 			operating-points-v2 = <&cpu0_opp_table>;
++			#cooling-cells = <2>;
+ 		};
+ 
+ 		cpu3: cpu@3 {
+@@ -80,6 +84,7 @@
+ 			clocks = <&arm_clk>;
+ 			clock-names = "cpu";
+ 			operating-points-v2 = <&cpu0_opp_table>;
++			#cooling-cells = <2>;
+ 		};
+ 	};
+ 
+@@ -117,6 +122,26 @@
+ 
+ &cpu_thermal {
+ 	coefficients = <(-538)	412000>;
++
++	trips {
++		cpu_alert0: cpu-alert0 {
++			temperature	= <70000>;
++			hysteresis	= <0>;
++			type		= "passive";
++		};
++	};
++
++	cooling-maps {
++		map0 {
++			trip = <&cpu_alert0>;
++			cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++		};
++
++		map1 {
++			trip = <&cpu_crit>;
++			cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++		};
++	};
+ };
+ 
+ /* enable thermal sensor with the correct compatible property set */
+diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
+index 31b2964..2def068 100644
+--- a/arch/arm/boot/dts/bcm283x.dtsi
++++ b/arch/arm/boot/dts/bcm283x.dtsi
+@@ -38,7 +38,7 @@
+ 			thermal-sensors = <&thermal>;
+ 
+ 			trips {
+-				cpu-crit {
++				cpu_crit: cpu-crit {
+ 					temperature	= <80000>;
+ 					hysteresis	= <0>;
+ 					type		= "critical";
+-- 
+2.7.4

bcm283x-drm-vc4-set-is_yuv-to-false-when-num_planes-1.patch

@@ -0,0 +1,40 @@
+From patchwork Tue Oct  9 13:24:46 2018
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+Subject: drm/vc4: Set ->is_yuv to false when num_planes == 1
+From: Boris Brezillon <boris.brezillon@bootlin.com>
+X-Patchwork-Id: 255528
+Message-Id: <20181009132446.21960-1-boris.brezillon@bootlin.com>
+To: David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
+ dri-devel@lists.freedesktop.org, Eric Anholt <eric@anholt.net>
+Cc: Boris Brezillon <boris.brezillon@bootlin.com>, stable@vger.kernel.org
+Date: Tue,  9 Oct 2018 15:24:46 +0200
+
+When vc4_plane_state is duplicated ->is_yuv is left assigned to its
+previous value, and we never set it back to false when switching to
+a non-YUV format.
+
+Fix that by setting ->is_yuv to false in the 'num_planes == 1' branch
+of the vc4_plane_setup_clipping_and_scaling() function.
+
+Fixes: fc04023fafecf ("drm/vc4: Add support for YUV planes.")
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
+Reviewed-by: Eric Anholt <eric@anholt.net>
+---
+ drivers/gpu/drm/vc4/vc4_plane.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
+index d04b3c3246ba..60d5ad19cedd 100644
+--- a/drivers/gpu/drm/vc4/vc4_plane.c
++++ b/drivers/gpu/drm/vc4/vc4_plane.c
+@@ -321,6 +321,7 @@ static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state)
+ 		if (vc4_state->is_unity)
+ 			vc4_state->x_scaling[0] = VC4_SCALING_PPF;
+ 	} else {
++		vc4_state->is_yuv = false;
+ 		vc4_state->x_scaling[1] = VC4_SCALING_NONE;
+ 		vc4_state->y_scaling[1] = VC4_SCALING_NONE;
+ 	}

configs/build_configs.sh

@@ -79,8 +79,6 @@ function merge_configs()
 	done
 	if [ "x$arch" == "xaarch64" ]; then
 		echo "# arm64" > $name
-	elif [ "x$arch" == "xppc64" ]; then
-		echo "# powerpc" > $name
 	elif [ "x$arch" == "xppc64le" ]; then
 		echo "# powerpc" > $name
 	elif [ "x$arch" == "xs390x" ]; then

configs/config_generation

@@ -18,10 +18,6 @@ i686-debug=generic:generic-x86:generic-x86-i686:debug:debug-x86
 i686-PAE=generic:generic-x86:generic-x86-i686PAE
 i686-PAEdebug=generic:generic-x86:generic-x86-i686PAE:debug:debug-x86
 
-# ppc64
-ppc64=generic:generic-powerpc:generic-powerpc-powerpc64
-ppc64-debug=generic:generic-powerpc:generic-powerpc-powerpc64:debug
-
 # ppc64le
 ppc64le=generic:generic-powerpc:generic-powerpc-powerpc64le
 ppc64le-debug=generic:generic-powerpc:generic-powerpc-powerpc64le:debug

configs/fedora/generic/CONFIG_BACKLIGHT_PWM

@@ -1 +1 @@
-# CONFIG_BACKLIGHT_PWM is not set
+CONFIG_BACKLIGHT_PWM=m

configs/fedora/generic/CONFIG_CIFS_ALLOW_INSECURE_LEGACY

@@ -1 +0,0 @@
-CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y

configs/fedora/generic/CONFIG_CRYPTO_AEGIS128

@@ -1 +1 @@
-# CONFIG_CRYPTO_AEGIS128 is not set
+CONFIG_CRYPTO_AEGIS128=m

configs/fedora/generic/CONFIG_CRYPTO_AEGIS128L

@@ -1 +1 @@
-# CONFIG_CRYPTO_AEGIS128L is not set
+CONFIG_CRYPTO_AEGIS128L=m

configs/fedora/generic/CONFIG_CRYPTO_AEGIS256

@@ -1 +1 @@
-# CONFIG_CRYPTO_AEGIS256 is not set
+CONFIG_CRYPTO_AEGIS256=m

configs/fedora/generic/CONFIG_CRYPTO_MORUS1280

@@ -1 +1 @@
-# CONFIG_CRYPTO_MORUS1280 is not set
+CONFIG_CRYPTO_MORUS1280=m

configs/fedora/generic/CONFIG_CRYPTO_MORUS640

@@ -1 +1 @@
-# CONFIG_CRYPTO_MORUS640 is not set
+CONFIG_CRYPTO_MORUS640=m

configs/fedora/generic/CONFIG_DRM_HISI_HIBMC

@@ -1 +1 @@
-CONFIG_DRM_HISI_HIBMC=m
+# CONFIG_DRM_HISI_HIBMC is not set

configs/fedora/generic/CONFIG_DRM_MGA

@@ -1 +0,0 @@
-# CONFIG_DRM_MGA is not set

configs/fedora/generic/CONFIG_DRM_R128

@@ -1 +0,0 @@
-# CONFIG_DRM_R128 is not set

configs/fedora/generic/CONFIG_DRM_SAVAGE

@@ -1 +0,0 @@
-# CONFIG_DRM_SAVAGE is not set

configs/fedora/generic/CONFIG_DRM_SIS

@@ -1 +0,0 @@
-# CONFIG_DRM_SIS is not set

configs/fedora/generic/CONFIG_DRM_TDFX

@@ -1 +0,0 @@
-# CONFIG_DRM_TDFX is not set

configs/fedora/generic/CONFIG_DRM_VIA

@@ -1 +0,0 @@
-CONFIG_DRM_VIA=m

configs/fedora/generic/CONFIG_FIRMWARE_IN_KERNEL

@@ -1 +0,0 @@
-# CONFIG_FIRMWARE_IN_KERNEL is not set

configs/fedora/generic/CONFIG_FIXED_PHY

@@ -1 +1 @@
-CONFIG_FIXED_PHY=m
+CONFIG_FIXED_PHY=y

configs/fedora/generic/CONFIG_KERNEL_UNCOMPRESSED

@@ -1 +0,0 @@
-# CONFIG_KERNEL_UNCOMPRESSED is not set

configs/fedora/generic/CONFIG_MAXIM_THERMOCOUPLE

@@ -1 +1 @@
-# CONFIG_MAXIM_THERMOCOUPLE is not set
+CONFIG_MAXIM_THERMOCOUPLE=m

configs/fedora/generic/CONFIG_MDIO_DEVICE

@@ -1 +1 @@
-CONFIG_MDIO_DEVICE=m
+CONFIG_MDIO_DEVICE=y

configs/fedora/generic/CONFIG_MLX90614

@@ -1 +1 @@
-# CONFIG_MLX90614 is not set
+CONFIG_MLX90614=m

configs/fedora/generic/CONFIG_PHYLIB

@@ -1 +1 @@
-CONFIG_PHYLIB=m
+CONFIG_PHYLIB=y

configs/fedora/generic/CONFIG_RANDOM_TRUST_CPU

@@ -0,0 +1 @@
+CONFIG_RANDOM_TRUST_CPU=y

configs/fedora/generic/CONFIG_SENSORS_MLXREG_FAN

@@ -1 +0,0 @@
-CONFIG_SENSORS_MLXREG_FAN=m

configs/fedora/generic/CONFIG_SENSORS_NPCM7XX

@@ -1 +0,0 @@
-CONFIG_SENSORS_NPCM7XX=m

configs/fedora/generic/CONFIG_SSB

@@ -1 +1 @@
-CONFIG_SSB=y
+CONFIG_SSB=m

configs/fedora/generic/CONFIG_TEST_ASYNC_DRIVER_PROBE

@@ -1 +1 @@
-CONFIG_TEST_ASYNC_DRIVER_PROBE=m
+# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set

configs/fedora/generic/arm/CONFIG_BACKLIGHT_PWM

@@ -1 +0,0 @@
-CONFIG_BACKLIGHT_PWM=m

configs/fedora/generic/arm/CONFIG_COMMON_CLK_RK808

@@ -1 +1 @@
-CONFIG_COMMON_CLK_RK808=m
+CONFIG_COMMON_CLK_RK808=y

configs/fedora/generic/arm/CONFIG_EFI_ARMSTUB_DTB_LOADER

@@ -1 +0,0 @@
-# CONFIG_EFI_ARMSTUB_DTB_LOADER is not set

configs/fedora/generic/arm/CONFIG_INV_MPU6050_I2C

@@ -0,0 +1 @@
+CONFIG_INV_MPU6050_I2C=m

configs/fedora/generic/arm/CONFIG_INV_MPU6050_IIO

@@ -0,0 +1 @@
+CONFIG_INV_MPU6050_IIO=m

configs/fedora/generic/arm/CONFIG_MFD_RK808

@@ -1 +1 @@
-CONFIG_MFD_RK808=m
+CONFIG_MFD_RK808=y

configs/fedora/generic/arm/CONFIG_OF_MDIO

@@ -1 +1 @@
-CONFIG_OF_MDIO=m
+CONFIG_OF_MDIO=y

configs/fedora/generic/arm/CONFIG_PCIE_ROCKCHIP_HOST

@@ -1 +1 @@
-CONFIG_PCIE_ROCKCHIP_HOST=m
+# CONFIG_PCIE_ROCKCHIP_HOST is not set

configs/fedora/generic/arm/CONFIG_PWM

@@ -1 +0,0 @@
-CONFIG_PWM=y

configs/fedora/generic/arm/CONFIG_QRTR

@@ -1 +1 @@
-# CONFIG_QRTR is not set
+CONFIG_QRTR=m

configs/fedora/generic/arm/CONFIG_QRTR_SMD

@@ -0,0 +1 @@
+CONFIG_QRTR_SMD=m

configs/fedora/generic/arm/CONFIG_QRTR_TUN

@@ -0,0 +1 @@
+CONFIG_QRTR_TUN=m

configs/fedora/generic/arm/CONFIG_REGULATOR_RK808

@@ -1 +1 @@
-CONFIG_REGULATOR_RK808=m
+CONFIG_REGULATOR_RK808=y

configs/fedora/generic/arm/CONFIG_RTC_DRV_AS3722

@@ -0,0 +1 @@
+CONFIG_RTC_DRV_AS3722=m

configs/fedora/generic/arm/CONFIG_SCSI_MPT3SAS

@@ -1 +0,0 @@
-# CONFIG_SCSI_MPT3SAS is not set

configs/fedora/generic/arm/aarch64/CONFIG_CRYPTO_CRC32_ARM64

@@ -1 +1 @@
-CONFIG_CRYPTO_CRC32_ARM64=m
+CONFIG_CRYPTO_CRC32_ARM64=y

configs/fedora/generic/arm/armv7/CONFIG_AD525X_DPOT

@@ -1 +0,0 @@
-CONFIG_AD525X_DPOT=m

configs/fedora/generic/arm/armv7/CONFIG_AD525X_DPOT_I2C

@@ -1 +0,0 @@
-CONFIG_AD525X_DPOT_I2C=m

configs/fedora/generic/arm/armv7/CONFIG_AD525X_DPOT_SPI

@@ -1 +0,0 @@
-CONFIG_AD525X_DPOT_SPI=m

configs/fedora/generic/arm/armv7/CONFIG_BPF_JIT

@@ -1 +0,0 @@
-# CONFIG_BPF_JIT is not set

configs/fedora/generic/arm/armv7/CONFIG_BPF_JIT_ALWAYS_ON

@@ -1 +0,0 @@
-# CONFIG_BPF_JIT_ALWAYS_ON is not set

configs/fedora/generic/arm/armv7/CONFIG_RTC_DRV_AS3722

@@ -1 +0,0 @@
-CONFIG_RTC_DRV_AS3722=y

configs/fedora/generic/arm/armv7/armv7/CONFIG_MACH_OMAP_LDP

@@ -1 +0,0 @@
-# CONFIG_MACH_OMAP_LDP is not set

configs/fedora/generic/powerpc/CONFIG_BACKLIGHT_PWM

@@ -1 +0,0 @@
-CONFIG_BACKLIGHT_PWM=m

configs/fedora/generic/powerpc/CONFIG_PPC_PS3

@@ -1 +0,0 @@
-# CONFIG_PPC_PS3 is not set

configs/fedora/generic/powerpc/CONFIG_PS3_VRAM

@@ -1 +0,0 @@
-# CONFIG_PS3_VRAM is not set

configs/fedora/generic/powerpc/powerpc64/CONFIG_ADB

@@ -1 +0,0 @@
-CONFIG_ADB=y

configs/fedora/generic/powerpc/powerpc64/CONFIG_ADB_PMU

@@ -1 +0,0 @@
-CONFIG_ADB_PMU=y

configs/fedora/generic/powerpc/powerpc64/CONFIG_ADB_PMU_LED

@@ -1 +0,0 @@
-CONFIG_ADB_PMU_LED=y

configs/fedora/generic/powerpc/powerpc64/CONFIG_ADB_PMU_LED_DISK

@@ -1 +0,0 @@
-CONFIG_ADB_PMU_LED_DISK=y

configs/fedora/generic/powerpc/powerpc64/CONFIG_AGP

@@ -1 +0,0 @@
-CONFIG_AGP=y

configs/fedora/generic/powerpc/powerpc64/CONFIG_AGP_UNINORTH

@@ -1 +0,0 @@
-CONFIG_AGP_UNINORTH=y

configs/fedora/generic/powerpc/powerpc64/CONFIG_APM_EMULATION

@@ -1 +0,0 @@
-CONFIG_APM_EMULATION=m

configs/fedora/generic/powerpc/powerpc64/CONFIG_APPLE_AIRPORT

@@ -1 +0,0 @@
-CONFIG_APPLE_AIRPORT=m

configs/fedora/generic/powerpc/powerpc64/CONFIG_BLK_DEV_AEC62XX

@@ -1 +0,0 @@
-# CONFIG_BLK_DEV_AEC62XX is not set

configs/fedora/generic/powerpc/powerpc64/CONFIG_BLK_DEV_ALI15X3

@@ -1 +0,0 @@
-# CONFIG_BLK_DEV_ALI15X3 is not set

configs/fedora/generic/powerpc/powerpc64/CONFIG_BLK_DEV_AMD74XX

@@ -1 +0,0 @@
-# CONFIG_BLK_DEV_AMD74XX is not set

configs/fedora/generic/powerpc/powerpc64/CONFIG_BLK_DEV_CMD64X

@@ -1 +0,0 @@
-# CONFIG_BLK_DEV_CMD64X is not set

configs/fedora/generic/powerpc/powerpc64/CONFIG_BLK_DEV_CS5520

@@ -1 +0,0 @@
-# CONFIG_BLK_DEV_CS5520 is not set

configs/fedora/generic/powerpc/powerpc64/CONFIG_BLK_DEV_CS5530

@@ -1 +0,0 @@
-# CONFIG_BLK_DEV_CS5530 is not set

configs/fedora/generic/powerpc/powerpc64/CONFIG_BLK_DEV_CY82C693

@@ -1 +0,0 @@
-# CONFIG_BLK_DEV_CY82C693 is not set

configs/fedora/generic/powerpc/powerpc64/CONFIG_BLK_DEV_DELKIN

@@ -1 +0,0 @@
-CONFIG_BLK_DEV_DELKIN=m

configs/fedora/generic/powerpc/powerpc64/CONFIG_BLK_DEV_GENERIC

@@ -1 +0,0 @@
-CONFIG_BLK_DEV_GENERIC=y

configs/fedora/generic/powerpc/powerpc64/CONFIG_BLK_DEV_HPT366

@@ -1 +0,0 @@
-# CONFIG_BLK_DEV_HPT366 is not set

configs/fedora/generic/powerpc/powerpc64/CONFIG_BLK_DEV_IDE

@@ -1 +0,0 @@
-CONFIG_BLK_DEV_IDE=y

configs/fedora/generic/powerpc/powerpc64/CONFIG_BLK_DEV_IDECD

@@ -1 +0,0 @@
-CONFIG_BLK_DEV_IDECD=m

configs/fedora/generic/powerpc/powerpc64/CONFIG_BLK_DEV_IDECS

@@ -1 +0,0 @@
-# CONFIG_BLK_DEV_IDECS is not set

configs/fedora/generic/powerpc/powerpc64/CONFIG_BLK_DEV_IDEDMA

@@ -1 +0,0 @@
-CONFIG_BLK_DEV_IDEDMA=y