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6 Commits

Author SHA1 Message Date
David Abdurachmanov e0288866a8
Update configs for riscv64 
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
 2020-03-21 21:47:55 +02:00
David Abdurachmanov 3765d834be
Update RISCV configs 
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
 2019-12-16 22:52:13 +02:00
David Abdurachmanov 032d42a245
Update riscv64 configs 
Found CONFIG_REGMAP_I2C=m after generation, had CONFIG_REGMAP_I2C=y in Source tree
Found CONFIG_REGMAP_SPI=m after generation, had CONFIG_REGMAP_SPI=y in Source tree

Cannot make then built-in, something forces them to be modules.

Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
 2019-09-29 07:47:26 +02:00
David Abdurachmanov bebf3adce1
Attempt again to get MMC built-in for RISC-V 
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
 2019-09-28 08:47:43 +02:00
David Abdurachmanov e185868e77
Fix riscv64 SPI config 
Found CONFIG_MMC_SPI=m after generation, had CONFIG_MMC_SPI=y in Source tree
Found CONFIG_REGMAP_SPI=m after generation, had CONFIG_REGMAP_SPI=y in Source tree

Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
 2019-09-28 08:24:37 +02:00
David Abdurachmanov 7ff284a90a
Tweak riscv64 SPI config 
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
 2019-09-28 07:35:32 +02:00