Commit Graph

21 Commits

Author SHA1 Message Date
4874335a34
Update riscv64 configs
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
2019-09-20 11:26:01 +03:00
576b1ae843
Update RISCV (riscv64) configs
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
2019-09-18 22:11:26 +03:00
43dcced80c
Update out-of-tree patches for RISC-V (riscv64)
- SECCOMP v2 was posted for review (one failing kernel selftest)
- SiFive Ethernet driver is approved upstream and might land in 5.3
- SiFive CPUFreq support is WIP, but people reported it working

Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
2019-08-25 00:03:31 -07:00
c12dd026dd
Update RISC-V (riscv64) configs
New options added:

CONFIG_SOC_SIFIVE=y
CONFIG_EDAC_SIFIVE=y
CONFIG_PWM_SIFIVE=y

Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
2019-08-24 23:10:49 -07:00
601e6a0b25
Add support for SECCOMP (v2)
The patch is added for testing before publishing on linux-riscv.

Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
2019-06-24 17:15:53 +03:00
394552ce0a
Update configs
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
2019-06-20 20:03:51 +03:00
8a92f6bb9e
Update RISC-V configs (incl. new SiFive drivers)
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
2019-06-20 18:45:40 +03:00
6a92c8e473
Update RISC-V (riscv64) configs
Solves:

  Found CONFIG_NF_REJECT_IPV4=y after generation, had CONFIG_NF_REJECT_IPV4=m in Source tree

Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
2019-04-03 23:31:11 +02:00
a0a6f7a375
riscv: update config
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
2019-01-15 03:33:20 +01:00
fc9138ad11
riscv: update config
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
2019-01-15 02:11:24 +01:00
ff3e5b658b
riscv: regenerate configs (enable CONFIG_AUDIT)
Audit support for Linux was merged in 5.0-rc2.

Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
2019-01-15 01:23:20 +01:00
f72820cd8f
Move CONFIG_ARCH_RV64I to generic/riscv/riscv64
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
2018-11-26 21:03:11 +01:00
bf6565ba91
riscv64: update configs
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
2018-11-20 10:14:20 +01:00
1838232458
riscv: rebuild configs
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
2018-11-08 08:31:25 +01:00
8d4ff40415
riscv: modify CONFIG_* options
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
2018-11-08 07:02:28 +01:00
f47d31c65b
riscv: update CONFIG_* options
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
2018-11-08 00:02:51 +01:00
80112e26ae
riscv: set CONFIG_FRAME_WARN to 2048 (lower is unrealistic)
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
2018-11-07 22:15:53 +01:00
fd01e1b407
riscv: change CONFIG_* options
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
2018-11-03 19:20:06 +01:00
e93b45642b
riscv: adjust CONFIG_* options again
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
2018-11-03 17:19:04 +01:00
681c2dab76
riscv: add missing CONFIG_* options
Found unset config items, please set them to an appropriate value
CONFIG_ARCH_RV32I=n
CONFIG_ARCH_RV64I=y
CONFIG_CMODEL_MEDLOW=n
CONFIG_CMODEL_MEDANY=y
CONFIG_MAXPHYSMEM_2GB=n
CONFIG_MAXPHYSMEM_128GB=y
CONFIG_NR_CPUS=8
CONFIG_TUNE_GENERIC=y
CONFIG_RISCV_ISA_C=y
CONFIG_RISCV_BASE_PMU=y
CONFIG_FPU=y
CONFIG_CMDLINE_BOOL=n
CONFIG_PCIE_CADENCE_EP=n
CONFIG_PCI_ENDPOINT_CONFIGFS=n
CONFIG_PCI_EPF_TEST=n
CONFIG_NETWORK_SECMARK=n
CONFIG_NETFILTER_XT_TARGET_HL=m
CONFIG_MTD_OF_PARTS=m
CONFIG_OF_UNITTEST=n
CONFIG_OF_OVERLAY=n
CONFIG_KEYBOARD_BCM=n
CONFIG_GPIO_74XX_MMIO=n
CONFIG_POWER_RESET_GPIO=n
CONFIG_POWER_RESET_GPIO_RESTART=n
CONFIG_THERMAL=m
CONFIG_FB_SSD1307=n
CONFIG_SND_SOC_AC97_CODEC=n
CONFIG_SND_SOC_ES8328_I2C=n
CONFIG_SIFIVE_PLIC=n
CONFIG_PROFILE_ALL_BRANCHES=n

Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
2018-11-03 15:51:18 +01:00
b3c173bfe0
Add initial RISC-V 64-bit (riscv64) support
UNTESTED

Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
2018-11-03 14:36:46 +01:00