Add notifer for PLL0 clock patch refactored for v6.10
Signed-off-by: Jason Montleon <jmontleo@redhat.com>
This commit is contained in:
parent
100e001ba1
commit
f87d5e87e2
@ -7528,3 +7528,332 @@ index 9bb9f0e29565..5cfc30572b7f 100644
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/* mask doorbell event */
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plda->events_bitmap = GENMASK(PLDA_INT_EVENT_NUM - 1, 0)
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& ~BIT(PLDA_AXI_DOORBELL)
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From: Xingyu Wu <xingyu.wu@starfivetech.com>
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To: Michael Turquette <mturquette@baylibre.com>,
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Stephen Boyd <sboyd@kernel.org>,
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Cc: Paul Walmsley <paul.walmsley@sifive.com>,
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devicetree@vger.kernel.org
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Subject: [PATCH v5 1/2] clk: starfive: jh7110-sys: Add notifier for PLL0 clock
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Date: Tue, 7 May 2024 14:53:18 +0800
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Add notifier function for PLL0 clock. In the function, the cpu_root clock
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should be operated by saving its current parent and setting a new safe
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parent (osc clock) before setting the PLL0 clock rate. After setting PLL0
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rate, it should be switched back to the original parent clock.
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Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC")
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Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
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Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
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---
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.../clk/starfive/clk-starfive-jh7110-sys.c | 31 ++++++++++++++++++-
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drivers/clk/starfive/clk-starfive-jh71x0.h | 2 ++
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2 files changed, 32 insertions(+), 1 deletion(-)
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diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
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index 8f5e5abfa178..dafa3ae71751 100644
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--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
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+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
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@@ -385,6 +385,32 @@ int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
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}
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EXPORT_SYMBOL_GPL(jh7110_reset_controller_register);
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+/*
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+ * This clock notifier is called when the rate of PLL0 clock is to be changed.
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+ * The cpu_root clock should save the curent parent clock and swicth its parent
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+ * clock to osc before PLL0 rate will be changed. Then swicth its parent clock
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+ * back after the PLL0 rate is completed.
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+ */
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+static int jh7110_pll0_clk_notifier_cb(struct notifier_block *nb,
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+ unsigned long action, void *data)
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+{
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+ struct jh71x0_clk_priv *priv = container_of(nb, struct jh71x0_clk_priv, pll_clk_nb);
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+ struct clk *cpu_root = priv->reg[JH7110_SYSCLK_CPU_ROOT].hw.clk;
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+ int ret = 0;
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+
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+ if (action == PRE_RATE_CHANGE) {
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+ struct clk *osc = clk_get(priv->dev, "osc");
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+
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+ priv->original_clk = clk_get_parent(cpu_root);
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+ ret = clk_set_parent(cpu_root, osc);
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+ clk_put(osc);
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+ } else if (action == POST_RATE_CHANGE) {
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+ ret = clk_set_parent(cpu_root, priv->original_clk);
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+ }
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+
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+ return notifier_from_errno(ret);
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+}
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+
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static int __init jh7110_syscrg_probe(struct platform_device *pdev)
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{
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struct jh71x0_clk_priv *priv;
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@@ -413,7 +439,10 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev)
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if (IS_ERR(priv->pll[0]))
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return PTR_ERR(priv->pll[0]);
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} else {
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- clk_put(pllclk);
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+ priv->pll_clk_nb.notifier_call = jh7110_pll0_clk_notifier_cb;
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+ ret = clk_notifier_register(pllclk, &priv->pll_clk_nb);
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+ if (ret)
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+ return ret;
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priv->pll[0] = NULL;
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}
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diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.h b/drivers/clk/starfive/clk-starfive-jh71x0.h
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index 23e052fc1549..e3f441393e48 100644
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--- a/drivers/clk/starfive/clk-starfive-jh71x0.h
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+++ b/drivers/clk/starfive/clk-starfive-jh71x0.h
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@@ -114,6 +114,8 @@ struct jh71x0_clk_priv {
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spinlock_t rmw_lock;
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struct device *dev;
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void __iomem *base;
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+ struct clk *original_clk;
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+ struct notifier_block pll_clk_nb;
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struct clk_hw *pll[3];
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struct jh71x0_clk reg[];
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};
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From patchwork Tue May 7 06:53:19 2024
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Subject: [PATCH v5 2/2] riscv: dts: starfive: visionfive-2: Fix lower rate of
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CPUfreq by setting PLL0 rate to 1.5GHz
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Date: Tue, 7 May 2024 14:53:19 +0800
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CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz.
|
||||
But now PLL0 rate is 1GHz and the cpu frequency loads become
|
||||
333/500/500/1000MHz in fact.
|
||||
|
||||
The PLL0 rate should be default set to 1.5GHz and set the
|
||||
cpu_core rate to 500MHz in safe.
|
||||
|
||||
Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC")
|
||||
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
|
||||
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
|
||||
---
|
||||
.../boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 6 ++++++
|
||||
1 file changed, 6 insertions(+)
|
||||
|
||||
diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
|
||||
index 45b58b6f3df8..28981b267de4 100644
|
||||
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
|
||||
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
|
||||
@@ -368,6 +368,12 @@ spi_dev0: spi@0 {
|
||||
};
|
||||
};
|
||||
|
||||
+&syscrg {
|
||||
+ assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>,
|
||||
+ <&pllclk JH7110_PLLCLK_PLL0_OUT>;
|
||||
+ assigned-clock-rates = <500000000>, <1500000000>;
|
||||
+};
|
||||
+
|
||||
&sysgpio {
|
||||
i2c0_pins: i2c0-0 {
|
||||
i2c-pins {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user