Linux v5.10.20
Signed-off-by: Justin M. Forbes <jforbes@fedoraproject.org>
This commit is contained in:
Justin M. Forbes
parent
3aecce4192
commit
f6cf69d6fa
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@ -1,38 +0,0 @@
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From 910f1601addae3e430fc7d3cd589d7622c5df693 Mon Sep 17 00:00:00 2001
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From: Alex Deucher <alexander.deucher@amd.com>
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Date: Wed, 3 Feb 2021 14:03:50 -0500
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Subject: [PATCH] Revert "drm/amd/display: Update NV1x SR latency values"
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This reverts commit 4a3dea8932d3b1199680d2056dd91d31d94d70b7.
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This causes blank screens for some users.
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Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1388
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Cc: Alvin Lee <alvin.lee2@amd.com>
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Cc: Jun Lei <Jun.Lei@amd.com>
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Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
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Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Cc: stable@vger.kernel.org
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---
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drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
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index a0a4ab47a1c0..a2cbafab663c 100644
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--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
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+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
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@@ -297,8 +297,8 @@ static struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
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},
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},
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.num_states = 5,
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- .sr_exit_time_us = 11.6,
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- .sr_enter_plus_exit_time_us = 13.9,
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+ .sr_exit_time_us = 8.6,
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+ .sr_enter_plus_exit_time_us = 10.9,
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.urgent_latency_us = 4.0,
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.urgent_latency_pixel_data_only_us = 4.0,
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.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
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--
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2.29.2
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@ -1,54 +0,0 @@
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From 54a080fdc2e65b38aea4dd59dde357d6c340fa25 Mon Sep 17 00:00:00 2001
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From: Karol Herbst <kherbst@redhat.com>
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Date: Thu, 26 Nov 2020 14:47:50 +0100
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Subject: [PATCH] drm/nouveau/kms: handle mDP connectors
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In some cases we have the handle those explicitly as the fallback
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connector type detection fails and marks those as eDP connectors.
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Attempting to use such a connector with mutter leads to a crash of mutter
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as it ends up with two eDP displays.
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Information is taken from the official DCB documentation.
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Upstream Nouveau commit: 95adf381b74e86a8a34b93c3fab73c15dd2f3f5c
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Cc: stable@vger.kernel.org
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Cc: dri-devel@lists.freedesktop.org
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Cc: Ben Skeggs <bskeggs@redhat.com>
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Reported-by: Mark Pearson <markpearson@lenovo.com>
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Tested-by: Mark Pearson <markpearson@lenovo.com>
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Signed-off-by: Karol Herbst <kherbst@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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---
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drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h | 1 +
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drivers/gpu/drm/nouveau/nouveau_connector.c | 1 +
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2 files changed, 2 insertions(+)
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diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h
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index f5f59261ea81..d1beaad0c82b 100644
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--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h
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+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h
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@@ -14,6 +14,7 @@ enum dcb_connector_type {
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DCB_CONNECTOR_LVDS_SPWG = 0x41,
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DCB_CONNECTOR_DP = 0x46,
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DCB_CONNECTOR_eDP = 0x47,
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+ DCB_CONNECTOR_mDP = 0x48,
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DCB_CONNECTOR_HDMI_0 = 0x60,
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DCB_CONNECTOR_HDMI_1 = 0x61,
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DCB_CONNECTOR_HDMI_C = 0x63,
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diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
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index 8b4b3688c7ae..4c992fd5bd68 100644
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--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
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+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
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@@ -1210,6 +1210,7 @@ drm_conntype_from_dcb(enum dcb_connector_type dcb)
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case DCB_CONNECTOR_DMS59_DP0:
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case DCB_CONNECTOR_DMS59_DP1:
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case DCB_CONNECTOR_DP :
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+ case DCB_CONNECTOR_mDP :
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case DCB_CONNECTOR_USB_C : return DRM_MODE_CONNECTOR_DisplayPort;
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case DCB_CONNECTOR_eDP : return DRM_MODE_CONNECTOR_eDP;
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case DCB_CONNECTOR_HDMI_0 :
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--
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2.29.2
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134
i915-fixes.patch
134
i915-fixes.patch
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@ -1,134 +0,0 @@
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From 660fd7a8af42f8715dc6784a2d1d2fe42dc5a72f Mon Sep 17 00:00:00 2001
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From: Chris Wilson <chris@chris-wilson.co.uk>
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Date: Tue, 19 Jan 2021 11:07:57 +0000
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Subject: [PATCH 1/3] drm/i915/gt: One more flush for Baytrail clear residuals
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CI reports that Baytail requires one more invalidate after CACHE_MODE
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for it to be happy.
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Fixes: ace44e13e577 ("drm/i915/gt: Clear CACHE_MODE prior to clearing residuals")
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
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Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Reviewed-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
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Link: https://patchwork.freedesktop.org/patch/msgid/20210119110802.22228-1-chris@chris-wilson.co.uk
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---
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drivers/gpu/drm/i915/gt/gen7_renderclear.c | 9 ++++++---
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1 file changed, 6 insertions(+), 3 deletions(-)
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diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
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index e961ad6a3129..c50b18dd67be 100644
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--- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
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+++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
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@@ -353,19 +353,21 @@ static void gen7_emit_pipeline_flush(struct batch_chunk *batch)
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static void gen7_emit_pipeline_invalidate(struct batch_chunk *batch)
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{
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- u32 *cs = batch_alloc_items(batch, 0, 8);
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+ u32 *cs = batch_alloc_items(batch, 0, 10);
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/* ivb: Stall before STATE_CACHE_INVALIDATE */
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- *cs++ = GFX_OP_PIPE_CONTROL(4);
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+ *cs++ = GFX_OP_PIPE_CONTROL(5);
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*cs++ = PIPE_CONTROL_STALL_AT_SCOREBOARD |
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PIPE_CONTROL_CS_STALL;
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*cs++ = 0;
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*cs++ = 0;
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+ *cs++ = 0;
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- *cs++ = GFX_OP_PIPE_CONTROL(4);
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+ *cs++ = GFX_OP_PIPE_CONTROL(5);
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*cs++ = PIPE_CONTROL_STATE_CACHE_INVALIDATE;
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*cs++ = 0;
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*cs++ = 0;
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+ *cs++ = 0;
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batch_advance(batch, cs);
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}
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@@ -397,6 +399,7 @@ static void emit_batch(struct i915_vma * const vma,
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batch_add(&cmds, 0xffff0000);
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batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1));
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batch_add(&cmds, 0xffff0000 | PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
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+ gen7_emit_pipeline_invalidate(&cmds);
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gen7_emit_pipeline_flush(&cmds);
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/* Switch to the media pipeline and our base address */
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--
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2.30.1
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From b3d131f8d2b9055052b6e072b57fa390b7275443 Mon Sep 17 00:00:00 2001
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From: Chris Wilson <chris@chris-wilson.co.uk>
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Date: Mon, 25 Jan 2021 22:02:47 +0000
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Subject: [PATCH 2/3] drm/i915/gt: Flush before changing register state
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Flush; invalidate; change registers; invalidate; flush.
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Will this finally work on every device? Or will Baytrail complain again?
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On the positive side, we immediately see the benefit of having hsw-gt1 in
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CI.
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Fixes: ace44e13e577 ("drm/i915/gt: Clear CACHE_MODE prior to clearing residuals")
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Testcase: igt/gem_render_tiled_blits # hsw-gt1
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
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Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Link: https://patchwork.freedesktop.org/patch/msgid/20210125220247.31701-1-chris@chris-wilson.co.uk
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---
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drivers/gpu/drm/i915/gt/gen7_renderclear.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
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index c50b18dd67be..e53b409012c0 100644
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--- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
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+++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
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@@ -393,6 +393,7 @@ static void emit_batch(struct i915_vma * const vma,
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desc_count);
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/* Reset inherited context registers */
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+ gen7_emit_pipeline_flush(&cmds);
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gen7_emit_pipeline_invalidate(&cmds);
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batch_add(&cmds, MI_LOAD_REGISTER_IMM(2));
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batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7));
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--
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2.30.1
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From 28f4f465f21f9dc267ce08833b8e79356cbc05f3 Mon Sep 17 00:00:00 2001
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From: Chris Wilson <chris@chris-wilson.co.uk>
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Date: Wed, 10 Feb 2021 12:27:28 +0000
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Subject: [PATCH 3/3] drm/i915/gt: Correct surface base address for renderclear
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The surface_state_base is an offset into the batch, so we need to pass
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the correct batch address for STATE_BASE_ADDRESS.
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Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
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Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
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Cc: Hans de Goede <hdegoede@redhat.com>
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Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Cc: <stable@vger.kernel.org> # v5.7+
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Link: https://patchwork.freedesktop.org/patch/msgid/20210210122728.20097-1-chris@chris-wilson.co.uk
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---
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drivers/gpu/drm/i915/gt/gen7_renderclear.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
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index e53b409012c0..4adbc2bba97f 100644
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--- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
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+++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
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@@ -240,7 +240,7 @@ gen7_emit_state_base_address(struct batch_chunk *batch,
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/* general */
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*cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY;
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/* surface */
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- *cs++ = batch_addr(batch) | surface_state_base | BASE_ADDRESS_MODIFY;
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+ *cs++ = (batch_addr(batch) + surface_state_base) | BASE_ADDRESS_MODIFY;
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/* dynamic */
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*cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY;
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/* indirect */
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--
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2.30.1
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13
kernel.spec
13
kernel.spec
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@ -94,7 +94,7 @@ Summary: The Linux kernel
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%if 0%{?released_kernel}
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# Do we have a -stable update to apply?
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%define stable_update 19
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%define stable_update 20
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# Set rpm version accordingly
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%if 0%{?stable_update}
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%define stablerev %{stable_update}
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@ -852,14 +852,6 @@ Patch104: 0001-brcm-rpi4-fix-usb-numeration.patch
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# RPi-4 and wifi issues
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Patch105: arm-dts-rpi-4-disable-wifi-frequencies.patch
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# Nouveau mDP detection fix
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Patch107: 0001-drm-nouveau-kms-handle-mDP-connectors.patch
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Patch109: 0001-Revert-drm-amd-display-Update-NV1x-SR-latency-values.patch
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# rhbz 1925346
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Patch111: i915-fixes.patch
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# END OF PATCH DEFINITIONS
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%endif
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@ -2973,6 +2965,9 @@ fi
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#
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#
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%changelog
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* Thu Mar 04 2021 Justin M. Forbes <jforbes@fedoraproject.org> - 5.10.20-200
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- Linux v5.10.20
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* Fri Feb 26 2021 Justin M. Forbes <jforbes@fedoraproject.org> - 5.10.19-200
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- Linux v5.10.19
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2
sources
2
sources
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@ -1,2 +1,2 @@
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SHA512 (linux-5.10.tar.xz) = c28d52bc0c1e2c99017ceeca0bf2e622427f3416e0692090b01f65e3b3a5bce0e3e52ce3cee15d71e84fcb965bd48bdfcccb818c0105035d712ebd07afde9452
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SHA512 (patch-5.10.19.xz) = 9637f8dac379ffa6d376afcce8da87250eb48a6a2ffac0e5732884cca2cc2f0a85811fc326f006d2d297680ff7dcf726665360d9c7d5d34307bc3e7169ce6a7a
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SHA512 (patch-5.10.20.xz) = 8cd7c81ae1f05ae749b92d46f32fe77eb9c44a0684c3c91457882c8388fc71b41a48a6691c1687a13c87c49f34695d3a7e0675f532471626274e6758b76d7b2e
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