From f49ba59706be3bca22ef53d0f0365d4a4a48e805 Mon Sep 17 00:00:00 2001
From: David Abdurachmanov <david.abdurachmanov@gmail.com>
Date: Thu, 6 Dec 2018 10:18:35 +0100
Subject: [PATCH] riscv: bring back syscalls.h and enable ARCH_HAS_SG_CHAIN

ARCH_HAS_SG_CHAIN change should land in upstream 4.21.
syscalls.h header is being used by glibc.

Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
---
 kernel.spec         |  4 ++
 riscv64-fixes.patch | 90 +++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 94 insertions(+)
 create mode 100644 riscv64-fixes.patch

diff --git a/kernel.spec b/kernel.spec
index 88eaa08d1..bdbc90268 100644
--- a/kernel.spec
+++ b/kernel.spec
@@ -625,6 +625,10 @@ Patch505: asus-fx503-keyb.patch
 # https://bugzilla.kernel.org/show_bug.cgi?id=201685
 Patch506: blk-mq-fix-corruption-with-direct-issue.patch
 
+# 600 - RISC-V
+
+Patch600: riscv64-fixes.patch
+
 # END OF PATCH DEFINITIONS
 
 %endif
diff --git a/riscv64-fixes.patch b/riscv64-fixes.patch
new file mode 100644
index 000000000..334e78c4a
--- /dev/null
+++ b/riscv64-fixes.patch
@@ -0,0 +1,90 @@
+From 17e45034166c22497ced74a71d0621c26a204b9f Mon Sep 17 00:00:00 2001
+From: Fedora Kernel Team <kernel-team@fedoraproject.org>
+Date: Thu, 6 Dec 2018 09:16:51 +0000
+Subject: [PATCH] riscv64 fixes
+
+---
+ arch/riscv/Kconfig                     |  1 +
+ arch/riscv/include/uapi/asm/syscalls.h | 29 ++++++++++++++++++++++++++
+ arch/riscv/include/uapi/asm/unistd.h   | 20 +-----------------
+ 3 files changed, 31 insertions(+), 19 deletions(-)
+ create mode 100644 arch/riscv/include/uapi/asm/syscalls.h
+
+diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
+index 55da93f..e4e8bcd 100644
+--- a/arch/riscv/Kconfig
++++ b/arch/riscv/Kconfig
+@@ -43,6 +43,7 @@ config RISCV
+ 	select RISCV_TIMER
+ 	select GENERIC_IRQ_MULTI_HANDLER
+ 	select ARCH_HAS_PTE_SPECIAL
++	select ARCH_HAS_SG_CHAIN
+ 
+ config MMU
+ 	def_bool y
+diff --git a/arch/riscv/include/uapi/asm/syscalls.h b/arch/riscv/include/uapi/asm/syscalls.h
+new file mode 100644
+index 0000000..206dc4b
+--- /dev/null
++++ b/arch/riscv/include/uapi/asm/syscalls.h
+@@ -0,0 +1,29 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Copyright (C) 2017-2018 SiFive
++ */
++
++/*
++ * There is explicitly no include guard here because this file is expected to
++ * be included multiple times in order to define the syscall macros via
++ * __SYSCALL.
++ */
++
++/*
++ * Allows the instruction cache to be flushed from userspace.  Despite RISC-V
++ * having a direct 'fence.i' instruction available to userspace (which we
++ * can't trap!), that's not actually viable when running on Linux because the
++ * kernel might schedule a process on another hart.  There is no way for
++ * userspace to handle this without invoking the kernel (as it doesn't know the
++ * thread->hart mappings), so we've defined a RISC-V specific system call to
++ * flush the instruction cache.
++ *
++ * __NR_riscv_flush_icache is defined to flush the instruction cache over an
++ * address range, with the flush applying to either all threads or just the
++ * caller.  We don't currently do anything with the address range, that's just
++ * in there for forwards compatibility.
++ */
++#ifndef __NR_riscv_flush_icache
++#define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15)
++#endif
++__SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache)
+diff --git a/arch/riscv/include/uapi/asm/unistd.h b/arch/riscv/include/uapi/asm/unistd.h
+index 1f3bd3e..0610313 100644
+--- a/arch/riscv/include/uapi/asm/unistd.h
++++ b/arch/riscv/include/uapi/asm/unistd.h
+@@ -20,22 +20,4 @@
+ #endif /* __LP64__ */
+ 
+ #include <asm-generic/unistd.h>
+-
+-/*
+- * Allows the instruction cache to be flushed from userspace.  Despite RISC-V
+- * having a direct 'fence.i' instruction available to userspace (which we
+- * can't trap!), that's not actually viable when running on Linux because the
+- * kernel might schedule a process on another hart.  There is no way for
+- * userspace to handle this without invoking the kernel (as it doesn't know the
+- * thread->hart mappings), so we've defined a RISC-V specific system call to
+- * flush the instruction cache.
+- *
+- * __NR_riscv_flush_icache is defined to flush the instruction cache over an
+- * address range, with the flush applying to either all threads or just the
+- * caller.  We don't currently do anything with the address range, that's just
+- * in there for forwards compatibility.
+- */
+-#ifndef __NR_riscv_flush_icache
+-#define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15)
+-#endif
+-__SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache)
++#include <asm/syscalls.h>
+-- 
+2.20.0.rc2
+