From f294283e438ab243fc28e45a5184d5ba9e53fd22 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Thu, 26 Mar 2020 10:51:42 +0000 Subject: [PATCH] add patch to fix display on some tegra devices (TK1, TX1, Nano) --- ...MMU-support-on-Tegra124-and-Tegra210.patch | 320 ++++++++++++++++++ kernel.spec | 2 + 2 files changed, 322 insertions(+) create mode 100644 arm64-drm-tegra-Fix-SMMU-support-on-Tegra124-and-Tegra210.patch diff --git a/arm64-drm-tegra-Fix-SMMU-support-on-Tegra124-and-Tegra210.patch b/arm64-drm-tegra-Fix-SMMU-support-on-Tegra124-and-Tegra210.patch new file mode 100644 index 000000000..3d43cd710 --- /dev/null +++ b/arm64-drm-tegra-Fix-SMMU-support-on-Tegra124-and-Tegra210.patch @@ -0,0 +1,320 @@ +From patchwork Wed Mar 25 20:16:03 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1261638 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; 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+ Wed, 25 Mar 2020 13:16:06 -0700 (PDT) +Received: from localhost + (p200300E41F4A9B0076D02BFFFE273F51.dip0.t-ipconnect.de. + [2003:e4:1f4a:9b00:76d0:2bff:fe27:3f51]) + by smtp.gmail.com with ESMTPSA id + i4sm132568wrm.32.2020.03.25.13.16.05 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 25 Mar 2020 13:16:05 -0700 (PDT) +From: Thierry Reding +To: Thierry Reding +Cc: dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org +Subject: [PATCH 1/2] drm/tegra: Fix SMMU support on Tegra124 and Tegra210 +Date: Wed, 25 Mar 2020 21:16:03 +0100 +Message-Id: <20200325201604.833898-1-thierry.reding@gmail.com> +X-Mailer: git-send-email 2.24.1 +MIME-Version: 1.0 +Sender: linux-tegra-owner@vger.kernel.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-tegra@vger.kernel.org + +From: Thierry Reding + +When testing whether or not to enable the use of the SMMU, consult the +supported DMA mask rather than the actually configured DMA mask, since +the latter might already have been restricted. + +Fixes: 2d9384ff9177 ("drm/tegra: Relax IOMMU usage criteria on old Tegra") +Signed-off-by: Thierry Reding +Tested-by: Jon Hunter +--- + drivers/gpu/drm/tegra/drm.c | 3 ++- + drivers/gpu/host1x/dev.c | 13 +++++++++++++ + include/linux/host1x.h | 3 +++ + 3 files changed, 18 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c +index bd268028fb3d..583cd6e0ae27 100644 +--- a/drivers/gpu/drm/tegra/drm.c ++++ b/drivers/gpu/drm/tegra/drm.c +@@ -1039,6 +1039,7 @@ void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt, + + static bool host1x_drm_wants_iommu(struct host1x_device *dev) + { ++ struct host1x *host1x = dev_get_drvdata(dev->dev.parent); + struct iommu_domain *domain; + + /* +@@ -1076,7 +1077,7 @@ static bool host1x_drm_wants_iommu(struct host1x_device *dev) + * sufficient and whether or not the host1x is attached to an IOMMU + * doesn't matter. + */ +- if (!domain && dma_get_mask(dev->dev.parent) <= DMA_BIT_MASK(32)) ++ if (!domain && host1x_get_dma_mask(host1x) <= DMA_BIT_MASK(32)) + return true; + + return domain != NULL; +diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c +index 388bcc2889aa..40a4b9f8b861 100644 +--- a/drivers/gpu/host1x/dev.c ++++ b/drivers/gpu/host1x/dev.c +@@ -502,6 +502,19 @@ static void __exit tegra_host1x_exit(void) + } + module_exit(tegra_host1x_exit); + ++/** ++ * host1x_get_dma_mask() - query the supported DMA mask for host1x ++ * @host1x: host1x instance ++ * ++ * Note that this returns the supported DMA mask for host1x, which can be ++ * different from the applicable DMA mask under certain circumstances. ++ */ ++u64 host1x_get_dma_mask(struct host1x *host1x) ++{ ++ return host1x->info->dma_mask; ++} ++EXPORT_SYMBOL(host1x_get_dma_mask); ++ + MODULE_AUTHOR("Thierry Reding "); + MODULE_AUTHOR("Terje Bergstrom "); + MODULE_DESCRIPTION("Host1x driver for Tegra products"); +diff --git a/include/linux/host1x.h b/include/linux/host1x.h +index 62d216ff1097..c230b4e70d75 100644 +--- a/include/linux/host1x.h ++++ b/include/linux/host1x.h +@@ -17,9 +17,12 @@ enum host1x_class { + HOST1X_CLASS_GR3D = 0x60, + }; + ++struct host1x; + struct host1x_client; + struct iommu_group; + ++u64 host1x_get_dma_mask(struct host1x *host1x); ++ + /** + * struct host1x_client_ops - host1x client operations + * @init: host1x client initialization code + +From patchwork Wed Mar 25 20:16:04 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1261639 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; spf=none (no SPF record) + smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; 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+ Wed, 25 Mar 2020 13:16:08 -0700 (PDT) +Received: from localhost + (p200300E41F4A9B0076D02BFFFE273F51.dip0.t-ipconnect.de. + [2003:e4:1f4a:9b00:76d0:2bff:fe27:3f51]) + by smtp.gmail.com with ESMTPSA id + e9sm151985wrw.30.2020.03.25.13.16.07 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 25 Mar 2020 13:16:07 -0700 (PDT) +From: Thierry Reding +To: Thierry Reding +Cc: dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org +Subject: [PATCH 2/2] gpu: host1x: Use SMMU on Tegra124 and Tegra210 +Date: Wed, 25 Mar 2020 21:16:04 +0100 +Message-Id: <20200325201604.833898-2-thierry.reding@gmail.com> +X-Mailer: git-send-email 2.24.1 +In-Reply-To: <20200325201604.833898-1-thierry.reding@gmail.com> +References: <20200325201604.833898-1-thierry.reding@gmail.com> +MIME-Version: 1.0 +Sender: linux-tegra-owner@vger.kernel.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-tegra@vger.kernel.org + +From: Thierry Reding + +Tegra124 and Tegra210 support addressing more than 32 bits of physical +memory. However, since their host1x does not support the wide GATHER +opcode, they should use the SMMU if at all possible to ensure that all +the system memory can be used for command buffers, irrespective of +whether or not the host1x firewall is enabled. + +Signed-off-by: Thierry Reding +Tested-by: Jon Hunter +--- + drivers/gpu/host1x/dev.c | 46 ++++++++++++++++++++++++++++++++++++---- + 1 file changed, 42 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c +index 40a4b9f8b861..d24344e91922 100644 +--- a/drivers/gpu/host1x/dev.c ++++ b/drivers/gpu/host1x/dev.c +@@ -192,17 +192,55 @@ static void host1x_setup_sid_table(struct host1x *host) + } + } + ++static bool host1x_wants_iommu(struct host1x *host1x) ++{ ++ /* ++ * If we support addressing a maximum of 32 bits of physical memory ++ * and if the host1x firewall is enabled, there's no need to enable ++ * IOMMU support. This can happen for example on Tegra20, Tegra30 ++ * and Tegra114. ++ * ++ * Tegra124 and later can address up to 34 bits of physical memory and ++ * many platforms come equipped with more than 2 GiB of system memory, ++ * which requires crossing the 4 GiB boundary. But there's a catch: on ++ * SoCs before Tegra186 (i.e. Tegra124 and Tegra210), the host1x can ++ * only address up to 32 bits of memory in GATHER opcodes, which means ++ * that command buffers need to either be in the first 2 GiB of system ++ * memory (which could quickly lead to memory exhaustion), or command ++ * buffers need to be treated differently from other buffers (which is ++ * not possible with the current ABI). ++ * ++ * A third option is to use the IOMMU in these cases to make sure all ++ * buffers will be mapped into a 32-bit IOVA space that host1x can ++ * address. This allows all of the system memory to be used and works ++ * within the limitations of the host1x on these SoCs. ++ * ++ * In summary, default to enable IOMMU on Tegra124 and later. For any ++ * of the earlier SoCs, only use the IOMMU for additional safety when ++ * the host1x firewall is disabled. ++ */ ++ if (host1x->info->dma_mask <= DMA_BIT_MASK(32)) { ++ if (IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL)) ++ return false; ++ } ++ ++ return true; ++} ++ + static struct iommu_domain *host1x_iommu_attach(struct host1x *host) + { + struct iommu_domain *domain = iommu_get_domain_for_dev(host->dev); + int err; + + /* +- * If the host1x firewall is enabled, there's no need to enable IOMMU +- * support. Similarly, if host1x is already attached to an IOMMU (via +- * the DMA API), don't try to attach again. ++ * We may not always want to enable IOMMU support (for example if the ++ * host1x firewall is already enabled and we don't support addressing ++ * more than 32 bits of physical memory), so check for that first. ++ * ++ * Similarly, if host1x is already attached to an IOMMU (via the DMA ++ * API), don't try to attach again. + */ +- if (IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL) || domain) ++ if (!host1x_wants_iommu(host) || domain) + return domain; + + host->group = iommu_group_get(host->dev); diff --git a/kernel.spec b/kernel.spec index 1177596ee..75ebfe247 100644 --- a/kernel.spec +++ b/kernel.spec @@ -840,6 +840,8 @@ Patch323: arm64-tegra-fix-pcie.patch Patch324: regulator-pwm-Don-t-warn-on-probe-deferral.patch # http://patchwork.ozlabs.org/patch/1243112/ Patch325: backlight-lp855x-Ensure-regulators-are-disabled-on-probe-failure.patch +# https://patchwork.ozlabs.org/patch/1261638/ +Patch326: arm64-drm-tegra-Fix-SMMU-support-on-Tegra124-and-Tegra210.patch # Coral Patch330: arm64-dts-imx8mq-phanbell-Add-support-for-ethernet.patch