Add vc4 T-Format support to improve performance on RPi
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kernel.spec
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kernel.spec
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@ -551,9 +551,6 @@ Patch430: bcm2837-initial-support.patch
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Patch431: arm-rk3288-tinker.patch
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# http://www.spinics.net/lists/dri-devel/msg132235.html
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Patch433: drm-vc4-Fix-OOPSes-from-trying-to-cache-a-partially-constructed-BO..patch
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# bcm283x mmc for wifi http://www.spinics.net/lists/arm-kernel/msg567077.html
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Patch434: bcm283x-mmc-bcm2835.patch
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@ -575,6 +572,11 @@ Patch440: arm64-Add-option-of-13-for-FORCE_MAX_ZONEORDER.patch
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Patch441: bcm2835-clk-audio-jitter-issues.patch
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# http://www.spinics.net/lists/dri-devel/msg132235.html
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Patch443: drm-vc4-Fix-OOPSes-from-trying-to-cache-a-partially-constructed-BO..patch
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# https://lists.freedesktop.org/archives/dri-devel/2017-June/143688.html
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Patch444: vc4-tformat-fixes.patch
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Patch460: lib-cpumask-Make-CPUMASK_OFFSTACK-usable-without-deb.patch
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Patch466: input-kill-stupid-messages.patch
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@ -2230,6 +2232,9 @@ fi
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#
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#
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%changelog
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* Mon Jun 19 2017 Peter Robinson <pbrobinson@fedoraproject.org>
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- Add vc4 T-Format support to improve performance
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* Fri Jun 16 2017 Laura Abbott <labbott@fedoraproject.org>
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- Fix an auditd race condition (rhbz 1459326)
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@ -0,0 +1,428 @@
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From ac4e55169649132123c4f2f39e0b02b5c849bae8 Mon Sep 17 00:00:00 2001
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From: Peter Robinson <pbrobinson@gmail.com>
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Date: Mon, 19 Jun 2017 13:20:48 +0100
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Subject: [PATCH] drm/vc4: Add T-format scanout support
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The T tiling format is what V3D uses for textures, with no raster
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support at all until later revisions of the hardware (and always at a
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large 3D performance penalty). If we can't scan out V3D's format,
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then we often need to do a relayout at some stage of the pipeline,
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either right before texturing from the scanout buffer (common in X11
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without a compositor) or between a tiled screen buffer right before
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scanout (an option I've considered in trying to resolve this
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inconsistency, but which means needing to use the dirty fb ioctl and
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having some update policy).
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T-format scanout lets us avoid either of those shadow copies, for a
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massive, obvious performance improvement to X11 window dragging
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without a compositor. Unfortunately, enabling a compositor to work
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around the discrepancy has turned out to be too costly in memory
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consumption for the Raspbian distribution.
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Because the HVS operates a scanline at a time, compositing from T does
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increase the memory bandwidth cost of scanout. On my 1920x1080@32bpp
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display on a RPi3, we go from about 15% of system memory bandwidth
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with linear to about 20% with tiled. However, for X11 this still ends
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up being a huge performance win in active usage.
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This patch doesn't yet handle src_x/src_y offsetting within the tiled
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buffer. However, we fail to do so for untiled buffers already.
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drm/vc4: Add get/set tiling ioctls.
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This allows mesa to set the tiling format for a BO and have that
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tiling format be respected by mesa on the other side of an
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import/export (and by vc4 scanout in the kernel), without defining a
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protocol to pass the tiling through userspace.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
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Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
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---
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drivers/gpu/drm/vc4/vc4_bo.c | 83 +++++++++++++++++++++++++++++++++++++++++
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drivers/gpu/drm/vc4/vc4_drv.c | 2 +
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drivers/gpu/drm/vc4/vc4_drv.h | 6 +++
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drivers/gpu/drm/vc4/vc4_kms.c | 41 +++++++++++++++++++-
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drivers/gpu/drm/vc4/vc4_plane.c | 31 +++++++++++++--
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drivers/gpu/drm/vc4/vc4_regs.h | 19 ++++++++++
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include/uapi/drm/drm_fourcc.h | 22 +++++++++++
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include/uapi/drm/vc4_drm.h | 16 ++++++++
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8 files changed, 215 insertions(+), 5 deletions(-)
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diff --git a/drivers/gpu/drm/vc4/vc4_bo.c b/drivers/gpu/drm/vc4/vc4_bo.c
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index 3f6704cf6608..0918346c248e 100644
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--- a/drivers/gpu/drm/vc4/vc4_bo.c
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+++ b/drivers/gpu/drm/vc4/vc4_bo.c
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@@ -325,6 +325,7 @@ void vc4_free_object(struct drm_gem_object *gem_bo)
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bo->validated_shader = NULL;
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}
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+ bo->t_format = false;
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bo->free_time = jiffies;
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list_add(&bo->size_head, cache_list);
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list_add(&bo->unref_head, &vc4->bo_cache.time_list);
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@@ -525,6 +526,88 @@ vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
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return ret;
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}
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+/**
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+ * vc4_set_tiling_ioctl() - Sets the tiling modifier for a BO.
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+ * @dev: DRM device
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+ * @data: ioctl argument
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+ * @file_priv: DRM file for this fd
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+ *
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+ * The tiling state of the BO decides the default modifier of an fb if
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+ * no specific modifier was set by userspace, and the return value of
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+ * vc4_get_tiling_ioctl() (so that userspace can treat a BO it
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+ * received from dmabuf as the same tiling format as the producer
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+ * used).
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+ */
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+int vc4_set_tiling_ioctl(struct drm_device *dev, void *data,
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+ struct drm_file *file_priv)
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+{
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+ struct drm_vc4_set_tiling *args = data;
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+ struct drm_gem_object *gem_obj;
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+ struct vc4_bo *bo;
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+ bool t_format;
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+
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+ if (args->flags != 0)
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+ return -EINVAL;
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+
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+ switch (args->modifier) {
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+ case DRM_FORMAT_MOD_NONE:
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+ t_format = false;
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+ break;
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+ case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED:
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+ t_format = true;
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+ break;
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+ default:
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+ return -EINVAL;
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+ }
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+
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+ gem_obj = drm_gem_object_lookup(file_priv, args->handle);
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+ if (!gem_obj) {
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+ DRM_ERROR("Failed to look up GEM BO %d\n", args->handle);
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+ return -ENOENT;
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+ }
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+ bo = to_vc4_bo(gem_obj);
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+ bo->t_format = t_format;
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+
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+ drm_gem_object_unreference_unlocked(gem_obj);
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+
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+ return 0;
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+}
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+
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+/**
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+ * vc4_get_tiling_ioctl() - Gets the tiling modifier for a BO.
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+ * @dev: DRM device
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+ * @data: ioctl argument
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+ * @file_priv: DRM file for this fd
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+ *
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+ * Returns the tiling modifier for a BO as set by vc4_set_tiling_ioctl().
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+ */
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+int vc4_get_tiling_ioctl(struct drm_device *dev, void *data,
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+ struct drm_file *file_priv)
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+{
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+ struct drm_vc4_get_tiling *args = data;
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+ struct drm_gem_object *gem_obj;
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+ struct vc4_bo *bo;
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+
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+ if (args->flags != 0 || args->modifier != 0)
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+ return -EINVAL;
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+
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+ gem_obj = drm_gem_object_lookup(file_priv, args->handle);
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+ if (!gem_obj) {
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+ DRM_ERROR("Failed to look up GEM BO %d\n", args->handle);
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+ return -ENOENT;
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+ }
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+ bo = to_vc4_bo(gem_obj);
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+
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+ if (bo->t_format)
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+ args->modifier = DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED;
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+ else
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+ args->modifier = DRM_FORMAT_MOD_NONE;
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+
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+ drm_gem_object_unreference_unlocked(gem_obj);
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+
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+ return 0;
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+}
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+
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void vc4_bo_cache_init(struct drm_device *dev)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c
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index a459745e96f7..2edf2d4c5156 100644
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--- a/drivers/gpu/drm/vc4/vc4_drv.c
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+++ b/drivers/gpu/drm/vc4/vc4_drv.c
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@@ -122,6 +122,8 @@ static const struct drm_ioctl_desc vc4_drm_ioctls[] = {
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DRM_IOCTL_DEF_DRV(VC4_GET_HANG_STATE, vc4_get_hang_state_ioctl,
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DRM_ROOT_ONLY),
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DRM_IOCTL_DEF_DRV(VC4_GET_PARAM, vc4_get_param_ioctl, DRM_RENDER_ALLOW),
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+ DRM_IOCTL_DEF_DRV(VC4_SET_TILING, vc4_set_tiling_ioctl, DRM_RENDER_ALLOW),
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+ DRM_IOCTL_DEF_DRV(VC4_GET_TILING, vc4_get_tiling_ioctl, DRM_RENDER_ALLOW),
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};
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static struct drm_driver vc4_drm_driver = {
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diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
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index 0e59f3ee1b83..64f0cb1f889e 100644
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--- a/drivers/gpu/drm/vc4/vc4_drv.h
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+++ b/drivers/gpu/drm/vc4/vc4_drv.h
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@@ -135,6 +135,8 @@ struct vc4_bo {
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*/
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uint64_t write_seqno;
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+ bool t_format;
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+
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/* List entry for the BO's position in either
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* vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list
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*/
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@@ -433,6 +435,10 @@ int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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+int vc4_set_tiling_ioctl(struct drm_device *dev, void *data,
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+ struct drm_file *file_priv);
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+int vc4_get_tiling_ioctl(struct drm_device *dev, void *data,
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+ struct drm_file *file_priv);
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int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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int vc4_mmap(struct file *filp, struct vm_area_struct *vma);
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diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
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index ad7925a9e0ea..25be60016527 100644
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--- a/drivers/gpu/drm/vc4/vc4_kms.c
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+++ b/drivers/gpu/drm/vc4/vc4_kms.c
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@@ -202,11 +202,50 @@ static int vc4_atomic_commit(struct drm_device *dev,
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return 0;
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}
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+static struct drm_framebuffer *vc4_fb_create(struct drm_device *dev,
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+ struct drm_file *file_priv,
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+ const struct drm_mode_fb_cmd2 *mode_cmd)
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+{
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+ struct drm_mode_fb_cmd2 mode_cmd_local;
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+
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+ /* If the user didn't specify a modifier, use the
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+ * vc4_set_tiling_ioctl() state for the BO.
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+ */
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+ if (!(mode_cmd->flags & DRM_MODE_FB_MODIFIERS)) {
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+ struct drm_gem_object *gem_obj;
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+ struct vc4_bo *bo;
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+
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+ gem_obj = drm_gem_object_lookup(file_priv,
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+ mode_cmd->handles[0]);
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+ if (!gem_obj) {
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+ DRM_ERROR("Failed to look up GEM BO %d\n",
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+ mode_cmd->handles[0]);
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+ return ERR_PTR(-ENOENT);
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+ }
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+ bo = to_vc4_bo(gem_obj);
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+
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+ mode_cmd_local = *mode_cmd;
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+
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+ if (bo->t_format) {
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+ mode_cmd_local.modifier[0] =
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+ DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED;
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+ } else {
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+ mode_cmd_local.modifier[0] = DRM_FORMAT_MOD_NONE;
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+ }
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+
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+ drm_gem_object_unreference_unlocked(gem_obj);
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+
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+ mode_cmd = &mode_cmd_local;
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+ }
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+
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+ return drm_fb_cma_create(dev, file_priv, mode_cmd);
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+}
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+
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static const struct drm_mode_config_funcs vc4_mode_funcs = {
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.output_poll_changed = vc4_output_poll_changed,
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.atomic_check = drm_atomic_helper_check,
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.atomic_commit = vc4_atomic_commit,
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- .fb_create = drm_fb_cma_create,
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+ .fb_create = vc4_fb_create,
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};
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int vc4_kms_load(struct drm_device *dev)
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diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
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index f7a229df572d..99f4d4b48015 100644
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--- a/drivers/gpu/drm/vc4/vc4_plane.c
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+++ b/drivers/gpu/drm/vc4/vc4_plane.c
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@@ -498,8 +498,8 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
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u32 ctl0_offset = vc4_state->dlist_count;
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const struct hvs_format *format = vc4_get_hvs_format(fb->format->format);
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int num_planes = drm_format_num_planes(format->drm);
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- u32 scl0, scl1;
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- u32 lbm_size;
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+ u32 scl0, scl1, pitch0;
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+ u32 lbm_size, tiling;
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unsigned long irqflags;
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int ret, i;
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@@ -540,11 +540,31 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
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scl1 = vc4_get_scl_field(state, 0);
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}
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+ switch (fb->modifier) {
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+ case DRM_FORMAT_MOD_LINEAR:
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+ tiling = SCALER_CTL0_TILING_LINEAR;
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+ pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH);
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+ break;
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+ case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED:
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+ tiling = SCALER_CTL0_TILING_256B_OR_T;
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+
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+ pitch0 = (VC4_SET_FIELD(0, SCALER_PITCH0_TILE_Y_OFFSET),
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+ VC4_SET_FIELD(0, SCALER_PITCH0_TILE_WIDTH_L),
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+ VC4_SET_FIELD((vc4_state->src_w[0] + 31) >> 5,
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+ SCALER_PITCH0_TILE_WIDTH_R));
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+ break;
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+ default:
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+ DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx",
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+ (long long)fb->modifier);
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+ return -EINVAL;
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+ }
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+
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/* Control word */
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vc4_dlist_write(vc4_state,
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SCALER_CTL0_VALID |
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(format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
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(format->hvs << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
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+ VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
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(vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
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VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
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VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
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@@ -598,8 +618,11 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
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for (i = 0; i < num_planes; i++)
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vc4_dlist_write(vc4_state, 0xc0c0c0c0);
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- /* Pitch word 0/1/2 */
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- for (i = 0; i < num_planes; i++) {
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+ /* Pitch word 0 */
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+ vc4_dlist_write(vc4_state, pitch0);
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+
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+ /* Pitch word 1/2 */
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+ for (i = 1; i < num_planes; i++) {
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vc4_dlist_write(vc4_state,
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VC4_SET_FIELD(fb->pitches[i], SCALER_SRC_PITCH));
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}
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diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
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index 385405a2df05..362d8b7f8a5f 100644
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--- a/drivers/gpu/drm/vc4/vc4_regs.h
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+++ b/drivers/gpu/drm/vc4/vc4_regs.h
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@@ -604,6 +604,13 @@ enum hvs_pixel_format {
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#define SCALER_CTL0_SIZE_MASK VC4_MASK(29, 24)
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#define SCALER_CTL0_SIZE_SHIFT 24
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+#define SCALER_CTL0_TILING_MASK VC4_MASK(21, 20)
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+#define SCALER_CTL0_TILING_SHIFT 20
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+#define SCALER_CTL0_TILING_LINEAR 0
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+#define SCALER_CTL0_TILING_64B 1
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+#define SCALER_CTL0_TILING_128B 2
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+#define SCALER_CTL0_TILING_256B_OR_T 3
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+
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#define SCALER_CTL0_HFLIP BIT(16)
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#define SCALER_CTL0_VFLIP BIT(15)
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@@ -733,7 +740,19 @@ enum hvs_pixel_format {
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#define SCALER_PPF_KERNEL_OFFSET_SHIFT 0
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#define SCALER_PPF_KERNEL_UNCACHED BIT(31)
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+/* PITCH0/1/2 fields for raster. */
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#define SCALER_SRC_PITCH_MASK VC4_MASK(15, 0)
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#define SCALER_SRC_PITCH_SHIFT 0
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+/* PITCH0 fields for T-tiled. */
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+#define SCALER_PITCH0_TILE_WIDTH_L_MASK VC4_MASK(22, 16)
|
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+#define SCALER_PITCH0_TILE_WIDTH_L_SHIFT 16
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+#define SCALER_PITCH0_TILE_LINE_DIR BIT(15)
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+#define SCALER_PITCH0_TILE_INITIAL_LINE_DIR BIT(14)
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+/* Y offset within a tile. */
|
||||
+#define SCALER_PITCH0_TILE_Y_OFFSET_MASK VC4_MASK(13, 7)
|
||||
+#define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT 7
|
||||
+#define SCALER_PITCH0_TILE_WIDTH_R_MASK VC4_MASK(6, 0)
|
||||
+#define SCALER_PITCH0_TILE_WIDTH_R_SHIFT 0
|
||||
+
|
||||
#endif /* VC4_REGS_H */
|
||||
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
|
||||
index ef20abb8119b..9aaf633788a7 100644
|
||||
--- a/include/uapi/drm/drm_fourcc.h
|
||||
+++ b/include/uapi/drm/drm_fourcc.h
|
||||
@@ -168,6 +168,7 @@ extern "C" {
|
||||
#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
|
||||
#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
|
||||
#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
|
||||
+#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
|
||||
/* add more to the end as needed */
|
||||
|
||||
#define fourcc_mod_code(vendor, val) \
|
||||
@@ -292,6 +293,27 @@ extern "C" {
|
||||
*/
|
||||
#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
|
||||
|
||||
+/*
|
||||
+ * Broadcom VC4 "T" format
|
||||
+ *
|
||||
+ * This is the primary layout that the V3D GPU can texture from (it
|
||||
+ * can't do linear). The T format has:
|
||||
+ *
|
||||
+ * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
|
||||
+ * pixels at 32 bit depth.
|
||||
+ *
|
||||
+ * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
|
||||
+ * 16x16 pixels).
|
||||
+ *
|
||||
+ * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
|
||||
+ * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
|
||||
+ * they're (TR, BR, BL, TL), where bottom left is start of memory.
|
||||
+ *
|
||||
+ * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
|
||||
+ * tiles) or right-to-left (odd rows of 4k tiles).
|
||||
+ */
|
||||
+#define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
|
||||
+
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
diff --git a/include/uapi/drm/vc4_drm.h b/include/uapi/drm/vc4_drm.h
|
||||
index f07a09016726..6ac4c5c014cb 100644
|
||||
--- a/include/uapi/drm/vc4_drm.h
|
||||
+++ b/include/uapi/drm/vc4_drm.h
|
||||
@@ -38,6 +38,8 @@ extern "C" {
|
||||
#define DRM_VC4_CREATE_SHADER_BO 0x05
|
||||
#define DRM_VC4_GET_HANG_STATE 0x06
|
||||
#define DRM_VC4_GET_PARAM 0x07
|
||||
+#define DRM_VC4_SET_TILING 0x08
|
||||
+#define DRM_VC4_GET_TILING 0x09
|
||||
|
||||
#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
|
||||
#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
|
||||
@@ -47,6 +49,8 @@ extern "C" {
|
||||
#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)
|
||||
#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)
|
||||
#define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param)
|
||||
+#define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling)
|
||||
+#define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling)
|
||||
|
||||
struct drm_vc4_submit_rcl_surface {
|
||||
__u32 hindex; /* Handle index, or ~0 if not present. */
|
||||
@@ -295,6 +299,18 @@ struct drm_vc4_get_param {
|
||||
__u64 value;
|
||||
};
|
||||
|
||||
+struct drm_vc4_get_tiling {
|
||||
+ __u32 handle;
|
||||
+ __u32 flags;
|
||||
+ __u64 modifier;
|
||||
+};
|
||||
+
|
||||
+struct drm_vc4_set_tiling {
|
||||
+ __u32 handle;
|
||||
+ __u32 flags;
|
||||
+ __u64 modifier;
|
||||
+};
|
||||
+
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
--
|
||||
2.13.0
|
||||
|
Loading…
Reference in New Issue