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Qualcomm QDF2432 errata fix

This commit is contained in:
Peter Robinson 2016-08-23 17:11:40 +01:00
parent 3222f9a9b7
commit db34f96e9d
2 changed files with 65 additions and 0 deletions
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6
kernel.spec
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@ -499,6 +499,9 @@ Source5005: kbuild-AFTER_LINK.patch
Patch420: arm64-avoid-needing-console-to-enable-serial-console.patch
# a tempory patch for QCOM hardware enablement. Will be gone by end of 2016/F-26 GA
Patch421: qcom-QDF2432-tmp-errata.patch
# http://www.spinics.net/lists/arm-kernel/msg490981.html
Patch422: geekbox-v4-device-tree-support.patch
@ -2142,6 +2145,9 @@ fi
#
#
%changelog
* Tue Aug 23 2016 Peter Robinson <pbrobinson@fedoraproject.org>
- Qualcomm QDF2432 errata fix
* Mon Aug 22 2016 Justin M. Forbes <jforbes@fedoraproject.org> - 4.8.0-0.rc3.git0.1
- Linux v4.8-rc3
- Disable debugging options.

59
qcom-QDF2432-tmp-errata.patch Normal file
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@ -0,0 +1,59 @@
From edc7986d4d405daebaf2f66269b353da579fce5f Mon Sep 17 00:00:00 2001
From: Christopher Covington <cov@codeaurora.org>
Date: Tue, 31 May 2016 16:19:02 -0400
Subject: arm64: Workaround for QDF2432 ID_AA64 SR accesses
The ARMv8.0 architecture reserves several system register encodings for
future use. These encodings should behave as read-only and always return
zero on a read. As described in Errata 94, the CPU cores in the QDF2432
errantly cause an instruction abort if an AArch64 MRS instruction attempts
to read any of the following system register encodings:
Op0, Op1, CRn, CRm, Op2
3, 0, C0, [C4-C7], [2-3, 6-7]
3, 0, C0, C3, [3-7]
3, 0, C0, [C4,C6,C7], [4-5]
3, 0, C0, C2, [6-7]
Naively projecting ARMv8.0 names, this space includes:
ID_AA64PFR[2-7]_EL1
ID_AA64DFR[2-3]_EL1
ID_AA64AFR[2-3]_EL1
ID_AA64ISAR[2-7]_EL1
ID_AA64MMFR[2-7]_EL1
As of v4.8-rc2, Linux only attempts to query one register in this space,
ID_AA64MMFR2_EL1. As simple workaround, skip that access when the affected
MIDR is detected.
Signed-off-by: Christopher Covington <cov@codeaurora.org>
---
arch/arm64/kernel/cpuinfo.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index ed1b84f..790de6b 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -325,6 +325,8 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
{
+ bool qdf2432_cpu = read_cpuid_id() == 0x510f2811;
+
info->reg_cntfrq = arch_timer_get_cntfrq();
info->reg_ctr = read_cpuid_cachetype();
info->reg_dczid = read_cpuid(DCZID_EL0);
@@ -337,7 +339,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
- info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
+ info->reg_id_aa64mmfr2 = qdf2432_cpu ? 0 : read_cpuid(ID_AA64MMFR2_EL1);
info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
--
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