Some i915 fixes for 5.10 (rhbz 1925346)
Signed-off-by: Justin M. Forbes <jforbes@fedoraproject.org>
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Justin M. Forbes
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From 660fd7a8af42f8715dc6784a2d1d2fe42dc5a72f Mon Sep 17 00:00:00 2001
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From: Chris Wilson <chris@chris-wilson.co.uk>
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Date: Tue, 19 Jan 2021 11:07:57 +0000
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Subject: [PATCH 1/3] drm/i915/gt: One more flush for Baytrail clear residuals
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CI reports that Baytail requires one more invalidate after CACHE_MODE
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for it to be happy.
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Fixes: ace44e13e577 ("drm/i915/gt: Clear CACHE_MODE prior to clearing residuals")
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
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Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Reviewed-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
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Link: https://patchwork.freedesktop.org/patch/msgid/20210119110802.22228-1-chris@chris-wilson.co.uk
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---
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drivers/gpu/drm/i915/gt/gen7_renderclear.c | 9 ++++++---
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1 file changed, 6 insertions(+), 3 deletions(-)
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diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
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index e961ad6a3129..c50b18dd67be 100644
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--- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
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+++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
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@@ -353,19 +353,21 @@ static void gen7_emit_pipeline_flush(struct batch_chunk *batch)
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static void gen7_emit_pipeline_invalidate(struct batch_chunk *batch)
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{
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- u32 *cs = batch_alloc_items(batch, 0, 8);
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+ u32 *cs = batch_alloc_items(batch, 0, 10);
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/* ivb: Stall before STATE_CACHE_INVALIDATE */
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- *cs++ = GFX_OP_PIPE_CONTROL(4);
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+ *cs++ = GFX_OP_PIPE_CONTROL(5);
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*cs++ = PIPE_CONTROL_STALL_AT_SCOREBOARD |
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PIPE_CONTROL_CS_STALL;
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*cs++ = 0;
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*cs++ = 0;
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+ *cs++ = 0;
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- *cs++ = GFX_OP_PIPE_CONTROL(4);
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+ *cs++ = GFX_OP_PIPE_CONTROL(5);
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*cs++ = PIPE_CONTROL_STATE_CACHE_INVALIDATE;
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*cs++ = 0;
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*cs++ = 0;
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+ *cs++ = 0;
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batch_advance(batch, cs);
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}
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@@ -397,6 +399,7 @@ static void emit_batch(struct i915_vma * const vma,
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batch_add(&cmds, 0xffff0000);
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batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1));
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batch_add(&cmds, 0xffff0000 | PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
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+ gen7_emit_pipeline_invalidate(&cmds);
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gen7_emit_pipeline_flush(&cmds);
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/* Switch to the media pipeline and our base address */
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--
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2.30.1
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From b3d131f8d2b9055052b6e072b57fa390b7275443 Mon Sep 17 00:00:00 2001
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From: Chris Wilson <chris@chris-wilson.co.uk>
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Date: Mon, 25 Jan 2021 22:02:47 +0000
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Subject: [PATCH 2/3] drm/i915/gt: Flush before changing register state
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Flush; invalidate; change registers; invalidate; flush.
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Will this finally work on every device? Or will Baytrail complain again?
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On the positive side, we immediately see the benefit of having hsw-gt1 in
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CI.
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Fixes: ace44e13e577 ("drm/i915/gt: Clear CACHE_MODE prior to clearing residuals")
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Testcase: igt/gem_render_tiled_blits # hsw-gt1
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
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Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Link: https://patchwork.freedesktop.org/patch/msgid/20210125220247.31701-1-chris@chris-wilson.co.uk
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---
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drivers/gpu/drm/i915/gt/gen7_renderclear.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
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index c50b18dd67be..e53b409012c0 100644
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--- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
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+++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
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@@ -393,6 +393,7 @@ static void emit_batch(struct i915_vma * const vma,
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desc_count);
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/* Reset inherited context registers */
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+ gen7_emit_pipeline_flush(&cmds);
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gen7_emit_pipeline_invalidate(&cmds);
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batch_add(&cmds, MI_LOAD_REGISTER_IMM(2));
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batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7));
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--
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2.30.1
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From 28f4f465f21f9dc267ce08833b8e79356cbc05f3 Mon Sep 17 00:00:00 2001
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From: Chris Wilson <chris@chris-wilson.co.uk>
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Date: Wed, 10 Feb 2021 12:27:28 +0000
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Subject: [PATCH 3/3] drm/i915/gt: Correct surface base address for renderclear
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The surface_state_base is an offset into the batch, so we need to pass
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the correct batch address for STATE_BASE_ADDRESS.
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Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
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Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
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Cc: Hans de Goede <hdegoede@redhat.com>
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Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Cc: <stable@vger.kernel.org> # v5.7+
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Link: https://patchwork.freedesktop.org/patch/msgid/20210210122728.20097-1-chris@chris-wilson.co.uk
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---
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drivers/gpu/drm/i915/gt/gen7_renderclear.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
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index e53b409012c0..4adbc2bba97f 100644
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--- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
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+++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
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@@ -240,7 +240,7 @@ gen7_emit_state_base_address(struct batch_chunk *batch,
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/* general */
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*cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY;
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/* surface */
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- *cs++ = batch_addr(batch) | surface_state_base | BASE_ADDRESS_MODIFY;
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+ *cs++ = (batch_addr(batch) + surface_state_base) | BASE_ADDRESS_MODIFY;
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/* dynamic */
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*cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY;
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/* indirect */
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--
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2.30.1
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@ -860,6 +860,9 @@ Patch109: 0001-Revert-drm-amd-display-Update-NV1x-SR-latency-values.patch
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# rhbz 1916104 (patch from bluetooth-next)
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Patch110: bluetooth-btusb-qca-fix.patch
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# rhbz 1925346
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Patch111: i915-fixes.patch
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# END OF PATCH DEFINITIONS
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%endif
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@ -2973,6 +2976,9 @@ fi
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#
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#
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%changelog
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* Thu Feb 25 2021 Justin M. Forbes <jforbes@fedoraproject.org>
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- Some i915 fixes for 5.10 (rhbz 1925346)
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* Tue Feb 23 2021 Justin M. Forbes <jforbes@fedoraproject.org> - 5.10.18-200
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- Linux v5.10.18
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