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Add EIC7700 6.6.66

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This commit is contained in:
Jason Montleon 2024-12-15 13:29:23 -05:00
commit d30e57555f
313 changed files with 1282047 additions and 0 deletions
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17599
0001-Added-dts-and-defconfig-files-modified-8250_dwlib.c-.patch Normal file
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3198
0002-Added-clk-reset-driver.patch Normal file
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File diff suppressed because it is too large Load Diff

814
0003-feat-dma-coherent-noncoherent-Support-dma-coherent-n.patch Normal file
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@ -0,0 +1,814 @@
From 21c16908471f3413646e4b151c7022e26576998d Mon Sep 17 00:00:00 2001
From: linmin <linmin@eswincomputing.com>
Date: Sun, 7 Apr 2024 17:38:16 +0800
Subject: [PATCH 003/219] feat(dma coherent/noncoherent):Support dma
coherent/noncoherent
Changelogs:
1.Defined CONFIG_ARCH_ESWIN_EIC770X_SOC_FAMILY in drivers/soc/sifive/Kconfig
2.Modified pfn_pte()/pte_pfn() transformation to support _PAGE_UNCACHE pgtable bit
3.Selected RISCV_DMA_NONCOHERENT
4.Added riscv_noncoherent_supported() in sifive_errata_probe() to support dma-noncohrent
5.Register noncohernt_cache_ops while sifive_ccache_init
---
arch/riscv/configs/win2030_defconfig | 61 +------
arch/riscv/errata/sifive/errata.c | 7 +
arch/riscv/include/asm/pgtable-bits.h | 7 +
arch/riscv/include/asm/pgtable.h | 220 ++++++++++++++++++++++++++
arch/riscv/mm/dma-noncoherent.c | 77 +++++++++
drivers/soc/sifive/Kconfig | 85 ++++++++++
drivers/soc/sifive/sifive_ccache.c | 43 +++++
7 files changed, 444 insertions(+), 56 deletions(-)
diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig
index d5ba4ef1772b..030907121d03 100644
--- a/arch/riscv/configs/win2030_defconfig
+++ b/arch/riscv/configs/win2030_defconfig
@@ -14,14 +14,12 @@ CONFIG_USER_NS=y
CONFIG_CHECKPOINT_RESTORE=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE="${BR_BINARIES_DIR}/rootfs.cpio"
-CONFIG_INITRAMFS_COMPRESSION_NONE=y
CONFIG_EXPERT=y
# CONFIG_SYSFS_SYSCALL is not set
CONFIG_PERF_EVENTS=y
CONFIG_SOC_SIFIVE=y
CONFIG_SOC_VIRT=y
CONFIG_SMP=y
-CONFIG_HOTPLUG_CPU=y
CONFIG_RISCV_SBI_V01=y
# CONFIG_RISCV_BOOT_SPINWAIT is not set
CONFIG_CMDLINE="earlycon=sbi console=ttyS0,115200n8 clk_ignore_unused cma_pernuma=0x2000000 disable_bypass=false"
@@ -40,14 +38,10 @@ CONFIG_JUMP_LABEL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_SPARSEMEM_MANUAL=y
-CONFIG_ESWIN_RSVMEM=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
# CONFIG_IPV6 is not set
CONFIG_NET_SCHED=y
CONFIG_NET_CLS_ACT=y
@@ -60,7 +54,6 @@ CONFIG_PCIE_PTM=y
# CONFIG_PCI_QUIRKS is not set
CONFIG_PCI_PRI=y
CONFIG_PCI_PASID=y
-CONFIG_PCIE_ESWIN=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
@@ -72,10 +65,6 @@ CONFIG_BLK_DEV_RAM_SIZE=32768
CONFIG_VIRTIO_BLK=y
CONFIG_BLK_DEV_NVME=y
CONFIG_NVME_MULTIPATH=y
-CONFIG_LCPU_SMMU_TEST=y
-CONFIG_SCPU_DMAAPI_SMMU_TEST=y
-CONFIG_SMP_IPI_TEST=y
-CONFIG_ESWIN_NUMA_SAMPLE=m
CONFIG_EEPROM_AT24=y
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
@@ -83,7 +72,6 @@ CONFIG_BLK_DEV_SD=y
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_ATA=y
CONFIG_SATA_AHCI=y
-CONFIG_AHCI_ESWIN=y
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_ALACRITECH is not set
# CONFIG_NET_VENDOR_AMAZON is not set
@@ -99,16 +87,16 @@ CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_GOOGLE is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MICROSOFT is not set
# CONFIG_NET_VENDOR_LITEX is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MELLANOX is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_NET_VENDOR_MICROSEMI is not set
+# CONFIG_NET_VENDOR_MICROSOFT is not set
+# CONFIG_NET_VENDOR_NI is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_NETRONOME is not set
-# CONFIG_NET_VENDOR_NI is not set
# CONFIG_NET_VENDOR_PENSANDO is not set
# CONFIG_NET_VENDOR_QUALCOMM is not set
# CONFIG_NET_VENDOR_RENESAS is not set
@@ -119,7 +107,6 @@ CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_SOCIONEXT is not set
CONFIG_STMMAC_ETH=y
CONFIG_STMMAC_SELFTESTS=y
-CONFIG_DWMAC_WIN2030=y
# CONFIG_DWMAC_GENERIC is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_VERTEXCOM is not set
@@ -146,27 +133,20 @@ CONFIG_I2C_CHARDEV=y
# CONFIG_I2C_HELPER_AUTO is not set
CONFIG_I2C_DESIGNWARE_SLAVE=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
-CONFIG_I2C_DESIGNWARE_ESWIN=y
CONFIG_I2C_SLAVE_EEPROM=y
CONFIG_SPI=y
CONFIG_SPI_DESIGNWARE=y
CONFIG_SPI_DW_DMA=y
CONFIG_SPI_DW_MMIO=y
-CONFIG_SPI_DEMO=m
# CONFIG_PTP_1588_CLOCK is not set
CONFIG_PINCTRL=y
-CONFIG_PINCTRL_EIC7700=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_DWAPB=y
-CONFIG_GPIO_ESWIN=y
-CONFIG_SENSORS_ESWIN_FAN_CONTROL=y
-CONFIG_SENSORS_ESWIN_PVT=y
CONFIG_SENSORS_INA2XX=y
CONFIG_WATCHDOG=y
CONFIG_DW_WATCHDOG=y
CONFIG_REGULATOR=y
-CONFIG_REGULATOR_MPQ8785=y
# CONFIG_MEDIA_CEC_SUPPORT is not set
CONFIG_MEDIA_SUPPORT=y
CONFIG_V4L_PLATFORM_DRIVERS=y
@@ -178,23 +158,12 @@ CONFIG_DRM_TOSHIBA_TC358768=m
CONFIG_DRM_LEGACY=y
CONFIG_FB=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_SOC=y
CONFIG_SND_SOC_SOF_TOPLEVEL=y
CONFIG_SND_SOC_SOF_OF=y
-CONFIG_SND_SOC_SOF_ESWIN_TOPLEVEL=y
-CONFIG_SND_SOC_SOF_ESWIN=m
-CONFIG_SND_ESWIN_DW_I2S=y
-CONFIG_SND_ESWIN_DW_PCM=y
-CONFIG_SND_ESWIN_DAI=y
-CONFIG_SND_SOC_HDMI_CODEC=y
CONFIG_SND_SOC_ES8316=y
-CONFIG_SND_SOC_THRU_OUT=y
-CONFIG_ESWIN_SND_SOC_CODECS=y
-CONFIG_ESWIN_SND_ES8388_CODEC=y
-CONFIG_ESWIN_SND_DUMMY_CODEC=y
CONFIG_SND_SIMPLE_CARD=y
CONFIG_SND_AUDIO_GRAPH_CARD=y
CONFIG_USB_ULPI_BUS=y
@@ -241,44 +210,27 @@ CONFIG_MMC_TEST=y
CONFIG_MMC_DEBUG=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MMC_SDHCI_OF_SDIO_FU800=y
-CONFIG_MMC_SDHCI_OF_FU800=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_PCF8563=y
-CONFIG_RTC_DRV_ESWIN=y
CONFIG_DMADEVICES=y
CONFIG_DW_AXI_DMAC=y
CONFIG_DMATEST=y
-CONFIG_DMATEST_UNITEST=y
-CONFIG_DMABUF_HEAPS_SYSTEM_COHERENT=y
-CONFIG_DMABUF_HEAPS_IMPORT_HELPER=y
+CONFIG_DMABUF_HEAPS=y
+CONFIG_DMABUF_HEAPS_SYSTEM=y
CONFIG_VIRTIO_BALLOON=y
CONFIG_VIRTIO_INPUT=y
CONFIG_VIRTIO_MMIO=y
CONFIG_STAGING=y
-# CONFIG_DW200 is not set
CONFIG_COMMON_CLK_WIN2030=y
-CONFIG_TIMER_ESWIN=y
CONFIG_MAILBOX=y
-CONFIG_ESWIN_MBOX=y
-CONFIG_ESWIN_IPC_SCPU=m
-CONFIG_ESWIN_LPCPU=m
-CONFIG_ARM_SMMU_V3=y
CONFIG_RPMSG_VIRTIO=y
-CONFIG_SIFIVE_L2=y
-CONFIG_SIFIVE_L2_FLUSH=y
+CONFIG_ARCH_ESWIN_EIC770X_SOC_FAMILY=y
CONFIG_EXTCON=y
CONFIG_PWM=y
-CONFIG_PWM_ESWIN=y
CONFIG_RESET_ESWIN_WIN2030=y
-CONFIG_PHY_MIXEL_MIPI_DPHY=m
-CONFIG_ARM_SMMU_V3_PMU=y
CONFIG_INTERCONNECT=y
-CONFIG_DSP=y
-CONFIG_ESWIN_DSP_SUBSYS=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_AUTOFS4_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
@@ -288,14 +240,12 @@ CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_NFS_V4_1=y
CONFIG_NFS_V4_2=y
-CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=m
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_DEV_VIRTIO=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC7=y
-CONFIG_XZ_DEC=y
CONFIG_PRINTK_TIME=y
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
CONFIG_CONSOLE_LOGLEVEL_QUIET=15
@@ -316,7 +266,6 @@ CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_RWSEMS=y
CONFIG_DEBUG_ATOMIC_SLEEP=y
-CONFIG_STACKTRACE=y
CONFIG_DEBUG_LIST=y
CONFIG_DEBUG_PLIST=y
CONFIG_DEBUG_SG=y
diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive/errata.c
index 3d9a32d791f7..20dcbd9e76f4 100644
--- a/arch/riscv/errata/sifive/errata.c
+++ b/arch/riscv/errata/sifive/errata.c
@@ -12,6 +12,7 @@
#include <asm/alternative.h>
#include <asm/vendorid_list.h>
#include <asm/errata_list.h>
+#include <asm/cacheflush.h>
struct errata_info_t {
char name[32];
@@ -62,6 +63,12 @@ static u32 __init_or_module sifive_errata_probe(unsigned long archid,
int idx;
u32 cpu_req_errata = 0;
+#if IS_ENABLED(CONFIG_ARCH_ESWIN_EIC770X_SOC_FAMILY)
+ /* Set this just to make core cbo code happy */
+ riscv_cbom_block_size = 1;
+ riscv_noncoherent_supported();
+#endif
+
for (idx = 0; idx < ERRATA_SIFIVE_NUMBER; idx++)
if (errata_list[idx].check_func(archid, impid))
cpu_req_errata |= (1U << idx);
diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
index f896708e8331..dbe56bc01230 100644
--- a/arch/riscv/include/asm/pgtable-bits.h
+++ b/arch/riscv/include/asm/pgtable-bits.h
@@ -18,6 +18,13 @@
#define _PAGE_DIRTY (1 << 7) /* Set by hardware on any write */
#define _PAGE_SOFT (1 << 8) /* Reserved for software */
+#if IS_ENABLED(CONFIG_ARCH_ESWIN_EIC770X_SOC_FAMILY)
+#define _PAGE_UNCACHE (1 << 9) /* Map to system port .i.e, uncached*/
+
+/* Map to system port llc .i.e, through sys port llc space */
+#define _PAGE_LLC (1 << 12)
+#endif
+
#define _PAGE_SPECIAL _PAGE_SOFT
#define _PAGE_TABLE _PAGE_PRESENT
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 37829dab4a0a..00811a820de9 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -205,9 +205,192 @@ extern struct pt_alloc_ops pt_ops __initdata;
#define PAGE_TABLE __pgprot(_PAGE_TABLE)
+#if IS_ENABLED(CONFIG_ARCH_ESWIN_EIC770X_SOC_FAMILY)
+#define _PAGE_IOREMAP (_PAGE_KERNEL | _PAGE_UNCACHE)
+#else
#define _PAGE_IOREMAP ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO)
+#endif
#define PAGE_KERNEL_IO __pgprot(_PAGE_IOREMAP)
+#if IS_ENABLED(CONFIG_ARCH_ESWIN_EIC770X_SOC_FAMILY)
+/* DIE0 */
+#define DIE0_MEM_PORT_PFN_START (CONFIG_RISCV_DIE0_CACHED_OFFSET >> PAGE_SHIFT)
+#define DIE0_MEM_PORT_PFN_END ((CONFIG_RISCV_DIE0_CACHED_OFFSET + CONFIG_RISCV_DIE0_MEM_MAX_SIZE) >> PAGE_SHIFT)
+
+#define DIE0_SYS_PORT_PFN_START (CONFIG_RISCV_DIE0_UNCACHED_OFFSET >> PAGE_SHIFT)
+#define DIE0_MEM_TO_SYS_PFN_ADDRESS(a) (DIE0_SYS_PORT_PFN_START + ((u64)(a) - DIE0_MEM_PORT_PFN_START))
+#define DIE0_SYS_TO_MEM_PFN_ADDRESS(a) (DIE0_MEM_PORT_PFN_START + ((u64)(a) - DIE0_SYS_PORT_PFN_START))
+#define DIE0_SYS_PORT_PFN_END ((CONFIG_RISCV_DIE0_UNCACHED_OFFSET + CONFIG_RISCV_DIE0_MEM_MAX_SIZE) >> PAGE_SHIFT)
+
+#define DIE0_SYS_PORT_LLC_PFN_START ((CONFIG_RISCV_DIE0_UNCACHED_OFFSET + 0x1800000000)>> PAGE_SHIFT)
+#define DIE0_MEM_TO_SYS_LLC_PFN_ADDRESS(a) (DIE0_SYS_PORT_LLC_PFN_START + ((u64)(a) - DIE0_MEM_PORT_PFN_START))
+#define DIE0_SYS_LLC_TO_MEM_PFN_ADDRESS(a) (DIE0_MEM_PORT_PFN_START + ((u64)(a) - DIE0_SYS_PORT_LLC_PFN_START))
+#define DIE0_SYS_PORT_LLC_PFN_END (((CONFIG_RISCV_DIE0_UNCACHED_OFFSET + 0x1800000000) + CONFIG_RISCV_DIE0_MEM_MAX_SIZE) >> PAGE_SHIFT)
+
+/* DIE1 */
+#define DIE1_MEM_PORT_PFN_START (CONFIG_RISCV_DIE1_CACHED_OFFSET >> PAGE_SHIFT)
+#define DIE1_MEM_PORT_PFN_END ((CONFIG_RISCV_DIE1_CACHED_OFFSET + CONFIG_RISCV_DIE1_MEM_MAX_SIZE) >> PAGE_SHIFT)
+
+#define DIE1_SYS_PORT_PFN_START (CONFIG_RISCV_DIE1_UNCACHED_OFFSET >> PAGE_SHIFT)
+#define DIE1_MEM_TO_SYS_PFN_ADDRESS(a) (DIE1_SYS_PORT_PFN_START + ((u64)(a) - DIE1_MEM_PORT_PFN_START))
+#define DIE1_SYS_TO_MEM_PFN_ADDRESS(a) (DIE1_MEM_PORT_PFN_START + ((u64)(a) - DIE1_SYS_PORT_PFN_START))
+#define DIE1_SYS_PORT_PFN_END ((CONFIG_RISCV_DIE1_UNCACHED_OFFSET + CONFIG_RISCV_DIE1_MEM_MAX_SIZE) >> PAGE_SHIFT)
+
+#define DIE1_SYS_PORT_LLC_PFN_START ((CONFIG_RISCV_DIE1_UNCACHED_OFFSET + 0x1800000000) >> PAGE_SHIFT)
+#define DIE1_MEM_TO_SYS_LLC_PFN_ADDRESS(a) (DIE1_SYS_PORT_LLC_PFN_START + ((u64)(a) - DIE1_MEM_PORT_PFN_START))
+#define DIE1_SYS_LLC_TO_MEM_PFN_ADDRESS(a) (DIE1_MEM_PORT_PFN_START + ((u64)(a) - DIE1_SYS_PORT_LLC_PFN_START))
+#define DIE1_SYS_PORT_LLC_PFN_END (((CONFIG_RISCV_DIE1_UNCACHED_OFFSET + 0x1800000000) + CONFIG_RISCV_DIE1_MEM_MAX_SIZE) >> PAGE_SHIFT)
+
+/* interleave */
+#define INTERLEAVE_MEM_PORT_PFN_START (CONFIG_RISCV_INTERLEAVE_CACHED_OFFSET >> PAGE_SHIFT)
+#define INTERLEAVE_MEM_PORT_PFN_END ((CONFIG_RISCV_INTERLEAVE_CACHED_OFFSET + CONFIG_RISCV_INTERLEAVE_MEM_MAX_SIZE) >> PAGE_SHIFT)
+
+#define INTERLEAVE_SYS_PORT_PFN_START (CONFIG_RISCV_INTERLEAVE_UNCACHED_OFFSET >> PAGE_SHIFT)
+#define INTERLEAVE_MEM_TO_SYS_PFN_ADDRESS(a) (INTERLEAVE_SYS_PORT_PFN_START + ((u64)(a) - INTERLEAVE_MEM_PORT_PFN_START))
+#define INTERLEAVE_SYS_TO_MEM_PFN_ADDRESS(a) (INTERLEAVE_MEM_PORT_PFN_START + ((u64)(a) - INTERLEAVE_SYS_PORT_PFN_START))
+#define INTERLEAVE_SYS_PORT_PFN_END ((CONFIG_RISCV_INTERLEAVE_UNCACHED_OFFSET + CONFIG_RISCV_INTERLEAVE_MEM_MAX_SIZE) >> PAGE_SHIFT)
+
+#define INTERLEAVE_SYS_PORT_LLC_PFN_START ((CONFIG_RISCV_INTERLEAVE_UNCACHED_OFFSET + 0x3000000000) >> PAGE_SHIFT)
+#define INTERLEAVE_MEM_TO_SYS_LLC_PFN_ADDRESS(a) (INTERLEAVE_SYS_PORT_LLC_PFN_START + ((u64)(a) - INTERLEAVE_MEM_PORT_PFN_START))
+#define INTERLEAVE_SYS_LLC_TO_MEM_PFN_ADDRESS(a) (INTERLEAVE_MEM_PORT_PFN_START + ((u64)(a) - INTERLEAVE_SYS_PORT_LLC_PFN_START))
+#define INTERLEAVE_SYS_PORT_LLC_PFN_END (((CONFIG_RISCV_INTERLEAVE_UNCACHED_OFFSET + 0x3000000000) + CONFIG_RISCV_INTERLEAVE_MEM_MAX_SIZE) >> PAGE_SHIFT)
+
+/* --------new conversion------- */
+/* DIE0 MEM PORT Address range 0x8000 0000 --- 0xF FFFF FFFF, 62GB */
+#define _MEM_PORT_D0_ADDR_RANGE_VAL ((0x1FUL << 31) >> PAGE_SHIFT)
+#define _MEM_PORT_D0_ADDR_RANGE_BITMASK (GENMASK_ULL(63, 31) >> PAGE_SHIFT)
+
+/* DIE1 MEM PORT Address range 0x20 0000 0000 --- 0x2F FFFF FFFF, 64GB */
+#define _MEM_PORT_D1_ADDR_RANGE_VAL ((0x2UL << 36) >> PAGE_SHIFT)
+#define _MEM_PORT_D1_ADDR_RANGE_BITMASK (GENMASK_ULL(63, 36) >> PAGE_SHIFT)
+
+/* Dual die, MEM PORT Interleave Address range:0x40 0000 0000 --- 0x5F FFFF FFFF, 128GB
+ part 0: 0x40 0000 0000 --- 0x4F FFFF FFFF, 64GB
+ part 1: 0x50 0000 0000 --- 0x5F FFFF FFFF, 64GB
+ */
+#define _MEM_PORT_INTPART0_ADDR_RANGE_VAL ((0x4UL << 36) >> PAGE_SHIFT)
+#define _MEM_PORT_INTPART0_ADDR_RANGE_BITMASK (GENMASK_ULL(63, 36)>> PAGE_SHIFT)
+#define _MEM_PORT_INTPART1_ADDR_RANGE_VAL ((0x5UL << 36) >> PAGE_SHIFT)
+#define _MEM_PORT_INTPART1_ADDR_RANGE_BITMASK (GENMASK_ULL(63, 36) >> PAGE_SHIFT)
+
+
+/* DIE0 SYS PORT Address range 0xC0 0000 0000 --- 0xCF FFFF FFFF, 64GB */
+#define _SYS_PORT_D0_ADDR_RANGE_VAL ((0xCUL << 36) >> PAGE_SHIFT)
+#define _SYS_PORT_D0_ADDR_RANGE_BITMASK (GENMASK_ULL(63, 36) >> PAGE_SHIFT)
+
+/* DIE0 SYS LLC PORT Address range 0xD8 0000 0000 --- 0xDF FFFF FFFF, 32GB */
+#define _SYSLLC_PORT_D0_ADDR_RANGE_VAL ((0x1BUL << 35) >> PAGE_SHIFT)
+#define _SYSLLC_PORT_D0_ADDR_RANGE_BITMASK (GENMASK_ULL(63, 35) >> PAGE_SHIFT)
+
+/* DIE1 SYS PORT Address range 0xE0 0000 0000 --- 0xEF FFFF FFFF, 64GB */
+#define _SYS_PORT_D1_ADDR_RANGE_VAL ((0xEUL << 36) >> PAGE_SHIFT)
+#define _SYS_PORT_D1_ADDR_RANGE_BITMASK (GENMASK_ULL(63, 36) >> PAGE_SHIFT)
+
+/* DIE1 SYS LLC PORT Address range 0xF8 0000 0000 --- 0xFF FFFF FFFF, 32GB */
+#define _SYSLLC_PORT_D1_ADDR_RANGE_VAL ((0x1FUL << 35) >> PAGE_SHIFT)
+#define _SYSLLC_PORT_D1_ADDR_RANGE_BITMASK (GENMASK_ULL(63, 35) >> PAGE_SHIFT)
+
+/* Dual die, SYS PORT Interleave Address range:0x100 0000 0000 --- 0x11F FFFF FFFF, 128GB
+ part 0: 0x100 0000 0000 --- 0x10F FFFF FFFF, 64GB
+ part 1: 0x110 0000 0000 --- 0x11F FFFF FFFF, 64GB
+ */
+#define _SYS_PORT_INTPART0_ADDR_RANGE_VAL ((0x10UL << 36) >> PAGE_SHIFT)
+#define _SYS_PORT_INTPART0_ADDR_RANGE_BITMASK (GENMASK_ULL(63, 36) >> PAGE_SHIFT)
+#define _SYS_PORT_INTPART1_ADDR_RANGE_VAL ((0x11UL << 36) >> PAGE_SHIFT)
+#define _SYS_PORT_INTPART1_ADDR_RANGE_BITMASK (GENMASK_ULL(63, 36) >> PAGE_SHIFT)
+
+/* Dual die, SYS LLC PORT Interleave Address range:0x130 0000 0000 --- 0x13F FFFF FFFF, 64GB */
+#define _SYSLLC_PORT_INT_ADDR_RANGE_VAL ((0x13UL << 36) >> PAGE_SHIFT)
+#define _SYSLLC_PORT_INT_ADDR_RANGE_BITMASK (GENMASK_ULL(63, 36) >> PAGE_SHIFT)
+
+#define CHECK_MEMORY_RANGE_OPFUNC(pfn, range, die) ((pfn & _##range##_PORT_##die##_ADDR_RANGE_BITMASK) == _##range##_PORT_##die##_ADDR_RANGE_VAL)
+
+/* pha conversion between mem port and sys port or sysllc_port */
+static inline unsigned long convert_pfn_from_mem_to_sys_port(unsigned long pfn)
+{
+ if (((pfn & _MEM_PORT_D0_ADDR_RANGE_BITMASK) >= DIE0_MEM_PORT_PFN_START) && ((pfn & _MEM_PORT_D0_ADDR_RANGE_BITMASK) <= DIE0_MEM_PORT_PFN_END)) {
+ return DIE0_MEM_TO_SYS_PFN_ADDRESS(pfn);
+ }
+#if IS_ENABLED(CONFIG_ARCH_ESWIN_EIC7702_SOC)
+ else if (pfn < DIE0_MEM_PORT_PFN_START) {
+ return pfn;
+ }
+ else if (CHECK_MEMORY_RANGE_OPFUNC(pfn, MEM, D1)) {
+ return DIE1_MEM_TO_SYS_PFN_ADDRESS(pfn);
+ }
+ else if (CHECK_MEMORY_RANGE_OPFUNC(pfn, MEM, INTPART0) || CHECK_MEMORY_RANGE_OPFUNC(pfn, MEM, INTPART1)) {
+ return INTERLEAVE_MEM_TO_SYS_PFN_ADDRESS(pfn);
+ }
+#endif
+ else
+ return pfn;
+}
+#define convert_pha_from_mem_to_sys_port(pha) \
+ (convert_pfn_from_mem_to_sys_port(pha >> PAGE_SHIFT) << PAGE_SHIFT)
+
+static inline unsigned long convert_pfn_from_mem_to_sys_port_llc(unsigned long pfn)
+{
+ if (((pfn & _MEM_PORT_D0_ADDR_RANGE_BITMASK) >= DIE0_MEM_PORT_PFN_START) && ((pfn & _MEM_PORT_D0_ADDR_RANGE_BITMASK) <= DIE0_MEM_PORT_PFN_END)) {
+ return DIE0_MEM_TO_SYS_LLC_PFN_ADDRESS(pfn);
+ }
+#if IS_ENABLED(CONFIG_ARCH_ESWIN_EIC7702_SOC)
+ else if (pfn < DIE0_MEM_PORT_PFN_START) {
+ return pfn;
+ }
+ else if (CHECK_MEMORY_RANGE_OPFUNC(pfn, MEM, D1)) {
+ return DIE1_MEM_TO_SYS_LLC_PFN_ADDRESS(pfn);
+ }
+ else if (CHECK_MEMORY_RANGE_OPFUNC(pfn, MEM, INTPART0) || CHECK_MEMORY_RANGE_OPFUNC(pfn, MEM, INTPART1)) {
+ return INTERLEAVE_MEM_TO_SYS_LLC_PFN_ADDRESS(pfn);
+ }
+#endif
+ else
+ return pfn;
+}
+#define convert_pha_from_mem_to_sys_port_llc(pha) \
+ (convert_pfn_from_mem_to_sys_port_llc(pha >> PAGE_SHIFT) << PAGE_SHIFT)
+
+static inline unsigned long convert_pfn_from_sys_to_mem_port(unsigned long pfn)
+{
+ if (likely(CHECK_MEMORY_RANGE_OPFUNC(pfn, SYS, D0))) {
+ return DIE0_SYS_TO_MEM_PFN_ADDRESS(pfn);
+ }
+#if IS_ENABLED(CONFIG_ARCH_ESWIN_EIC7702_SOC)
+ else if (pfn < DIE0_MEM_PORT_PFN_START) {
+ return pfn;
+ }
+ else if (CHECK_MEMORY_RANGE_OPFUNC(pfn, SYS, D1)) {
+ return DIE1_SYS_TO_MEM_PFN_ADDRESS(pfn);
+ }
+ else if (CHECK_MEMORY_RANGE_OPFUNC(pfn, SYS, INTPART0) || CHECK_MEMORY_RANGE_OPFUNC(pfn, SYS, INTPART1)) {
+ return INTERLEAVE_SYS_TO_MEM_PFN_ADDRESS(pfn);
+ }
+#endif
+ else
+ return pfn;
+}
+
+static inline unsigned long convert_pfn_from_sys_llc_to_mem_port(unsigned long pfn)
+{
+ if (likely(CHECK_MEMORY_RANGE_OPFUNC(pfn, SYSLLC, D0))) {
+ return DIE0_SYS_LLC_TO_MEM_PFN_ADDRESS(pfn);
+ }
+#if IS_ENABLED(CONFIG_ARCH_ESWIN_EIC7702_SOC)
+ else if (pfn < DIE0_MEM_PORT_PFN_START) {
+ return pfn;
+ }
+ else if (CHECK_MEMORY_RANGE_OPFUNC(pfn, SYSLLC, D1)) {
+ return DIE1_SYS_LLC_TO_MEM_PFN_ADDRESS(pfn);
+ }
+ else if (CHECK_MEMORY_RANGE_OPFUNC(pfn, SYSLLC, INT)) {
+ return INTERLEAVE_SYS_LLC_TO_MEM_PFN_ADDRESS(pfn);
+ }
+#endif
+ else
+ return pfn;
+}
+#endif
+
extern pgd_t swapper_pg_dir[];
extern pgd_t trampoline_pg_dir[];
extern pgd_t early_pg_dir[];
@@ -325,12 +508,21 @@ static inline unsigned long pte_napot(pte_t pte)
/* Yields the page frame number (PFN) of a page table entry */
static inline unsigned long pte_pfn(pte_t pte)
{
+#if IS_ENABLED(CONFIG_ARCH_ESWIN_EIC770X_SOC_FAMILY)
+ if (unlikely(pte_val(pte) & _PAGE_UNCACHE)) {
+ return convert_pfn_from_sys_to_mem_port(__page_val_to_pfn(pte_val(pte)));
+ }
+ else {
+ return convert_pfn_from_sys_llc_to_mem_port(__page_val_to_pfn(pte_val(pte)));
+ }
+#else
unsigned long res = __page_val_to_pfn(pte_val(pte));
if (has_svnapot() && pte_napot(pte))
res = res & (res - 1UL);
return res;
+#endif
}
#define pte_page(x) pfn_to_page(pte_pfn(x))
@@ -338,11 +530,27 @@ static inline unsigned long pte_pfn(pte_t pte)
/* Constructs a page table entry */
static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
{
+#if IS_ENABLED(CONFIG_ARCH_ESWIN_EIC770X_SOC_FAMILY)
+ unsigned long pfn_new;
+
+ if (unlikely(_PAGE_UNCACHE == (pgprot_val(prot) & _PAGE_UNCACHE))) {
+ pfn_new = convert_pfn_from_mem_to_sys_port(pfn);
+ pr_debug("pfn_pte:pfn_mport 0x%lx to pfn_sysport 0x%lx\n", pfn, pfn_new);
+ return __pte((pfn_new << _PAGE_PFN_SHIFT) | pgprot_val(prot));
+ }
+ else if (unlikely(_PAGE_LLC == (pgprot_val(prot) & _PAGE_LLC))) {
+ pfn_new = convert_pfn_from_mem_to_sys_port_llc(pfn);
+ pr_debug("pfn_pte:pfn_mport 0x%lx to pfn_llc 0x%lx\n", pfn, pfn_new);
+ return __pte((pfn_new << _PAGE_PFN_SHIFT) | (pgprot_val(prot) & ~_PAGE_LLC));
+ }
+ return __pte((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot));
+#else
unsigned long prot_val = pgprot_val(prot);
ALT_THEAD_PMA(prot_val);
return __pte((pfn << _PAGE_PFN_SHIFT) | prot_val);
+#endif
}
#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
@@ -596,6 +804,17 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
return ptep_test_and_clear_young(vma, address, ptep);
}
+#if IS_ENABLED(CONFIG_ARCH_ESWIN_EIC770X_SOC_FAMILY)
+#define pgprot_noncached(prot) \
+ __pgprot(pgprot_val(prot) | _PAGE_UNCACHE)
+
+#define pgprot_writecombine(prot) pgprot_noncached(prot)
+
+#define pgprot_dmacoherent(prot) pgprot_noncached(prot)
+
+#define pgprot_llc(prot) \
+ __pgprot(pgprot_val(prot) | _PAGE_LLC)
+#else
#define pgprot_noncached pgprot_noncached
static inline pgprot_t pgprot_noncached(pgprot_t _prot)
{
@@ -617,6 +836,7 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
return __pgprot(prot);
}
+#endif
/*
* THP functions
diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
index 341bd6706b4c..807cf361156e 100644
--- a/arch/riscv/mm/dma-noncoherent.c
+++ b/arch/riscv/mm/dma-noncoherent.c
@@ -7,6 +7,7 @@
#include <linux/dma-direct.h>
#include <linux/dma-map-ops.h>
+#include <linux/io.h>
#include <linux/mm.h>
#include <asm/cacheflush.h>
#include <asm/dma-noncoherent.h>
@@ -156,3 +157,79 @@ void __init riscv_set_dma_cache_alignment(void)
if (!noncoherent_supported)
dma_cache_alignment = 1;
}
+
+#ifdef CONFIG_ARCH_HAS_DMA_SET_UNCACHED
+static struct page **__iommu_dma_common_find_pages(void *cpu_addr)
+{
+ struct vm_struct *area = find_vm_area(cpu_addr);
+
+ if (!area || area->flags != VM_DMA_COHERENT)
+ return NULL;
+ return area->pages;
+}
+
+void arch_dma_clear_uncached(void *addr, size_t size)
+{
+ struct page **pages = NULL;
+
+ pr_debug("smmu_dbg, %s, remap addr:0x%p, size:0x%lx\n",
+ __func__, addr, size);
+ pages = __iommu_dma_common_find_pages(addr);
+ if (!pages) { // todo: supposed to handle this error
+ pr_err( "smmu_dbg, %s:%d, fail to find pages\n",
+ __func__, __LINE__);
+
+ return;
+ }
+ kvfree(pages);
+ memunmap(addr);
+}
+
+void *arch_dma_set_uncached(void *addr, size_t size)
+{
+ struct page **pages = NULL;
+ static struct page *page = NULL;
+ struct vm_struct *area = NULL;
+ phys_addr_t phys_addr = convert_pha_from_mem_to_sys_port(__pa(addr));
+ void *mem_base = NULL;
+
+ pr_debug("smmu_dbg, %s, pfn:0x%lx, pha:0x%016lx, vaddr:0x%px\n",
+ __func__, virt_to_pfn(addr), __pa(addr), addr);
+ mem_base = memremap(phys_addr, size, MEMREMAP_WT);
+ if (!mem_base) {
+ pr_err("%s memremap failed for addr %px\n", __func__, addr);
+ return ERR_PTR(-EINVAL);
+ }
+
+ pr_debug("smmu_dbg, %s, pha+offset:0x%016llx, remap vaddr:0x%px, size:0x%lx\n",
+ __func__, phys_addr, mem_base, size);
+
+ pages = kvzalloc(sizeof(*pages), GFP_KERNEL);
+ if (!pages) {
+ pr_err("smmu_dbg, %s:%d, failed to alloc memory!\n",
+ __func__, __LINE__);
+ goto err_pages_alloc;
+ }
+ page = virt_to_page(addr);
+ area = find_vm_area(mem_base);
+ if (!area) {
+ pr_err("smmu_dbg, %s:%d, failed to find vm area!\n",
+ __func__, __LINE__);
+ goto err_find_vm_area;
+ }
+ pr_debug("smmu_dbg, %s, check area-pages=0x%px\n", __func__, area->pages);
+ pages[0] = page;
+ area->pages = pages;
+ area->flags = VM_DMA_COHERENT;
+
+ return mem_base;
+
+err_find_vm_area:
+ kvfree(pages);
+
+err_pages_alloc:
+ memunmap(mem_base);
+
+ return NULL;
+}
+#endif
\ No newline at end of file
diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
index e86870be34c9..290b961eb729 100644
--- a/drivers/soc/sifive/Kconfig
+++ b/drivers/soc/sifive/Kconfig
@@ -7,4 +7,89 @@ config SIFIVE_CCACHE
help
Support for the composable cache controller on SiFive platforms.
+config ARCH_ESWIN_EIC770X_SOC_FAMILY
+ bool "ESWIN EIC770X SoC Family"
+ depends on SOC_SIFIVE
+ select SIFIVE_CCACHE
+ select RISCV_NONSTANDARD_CACHE_OPS
+ select DMA_DIRECT_REMAP
+ select RISCV_DMA_NONCOHERENT
+ select ARCH_HAS_DMA_SET_UNCACHED
+ select ARCH_HAS_DMA_CLEAR_UNCACHED
+ select ESWIN_MC
+ select ESWIN_RSV_MEMBLOCK
+ select ESWIN_CODACACHE_CONTROLLER
+
+menu "ESWIN EIC770X SoC Family Selection"
+ depends on ARCH_ESWIN_EIC770X_SOC_FAMILY
+
+choice
+ prompt "ESWIN EIC770X SoC Family Selection"
+ help
+ This option select the SoC type of ESWIN EIC770X Family.
+
+config ARCH_ESWIN_EIC7700_SOC
+ bool "Enable support for ESWIN EIC7700 SoC"
+
+config ARCH_ESWIN_EIC7702_SOC
+ bool "Enable support for ESWIN EIC7702 SoC"
+
+endchoice
+endmenu
+
+if ARCH_ESWIN_EIC770X_SOC_FAMILY
+config RISCV_DIE0_UNCACHED_OFFSET
+ hex "DIE0 system port addr of U84"
+ default 0xc000000000
+ help
+ Access to DDR memory through U84 system port is uncached.
+ Add this offset when allocating memory from memory port(0x80000000~),
+ then memremap to virtual address.
+
+config RISCV_DIE0_CACHED_OFFSET
+ hex "DIE0 memory port addr of U84"
+ default 0x80000000
+ help
+ Access to DDR memory through U84 memory port is cached.
+
+config RISCV_DIE0_MEM_MAX_SIZE
+ hex "DIE0 memory size, default 32GB"
+ default 0x800000000
+
+config RISCV_DIE1_UNCACHED_OFFSET
+ hex "DIE1 system port addr of U84"
+ default 0xe000000000
+ help
+ Access to DIE1 DDR memory through U84 system port is uncached.
+ Add this offset when allocating memory from memory port(0x2000000000~),
+ then memremap to virtual address.
+
+config RISCV_DIE1_CACHED_OFFSET
+ hex "DIE1 memory port addr of U84"
+ default 0x2000000000
+ help
+ Access to DIE1 DDR memory through U84 memory port is cached.
+
+config RISCV_DIE1_MEM_MAX_SIZE
+ hex "DIE1 memory size, default 32GB"
+ default 0x800000000
+
+config RISCV_INTERLEAVE_UNCACHED_OFFSET
+ hex "system port addr of interleave"
+ default 0x10000000000
+ help
+ Access to DDR memory through U84 system port with interleave is uncached.
+ Add this offset when allocating memory from memory port(0x4000000000~),
+ then memremap to virtual address.
+
+config RISCV_INTERLEAVE_CACHED_OFFSET
+ hex "memory port addr of interleave"
+ default 0x4000000000
+ help
+ Access to DDR memory through U84 memory port with interleave is cached.
+
+config RISCV_INTERLEAVE_MEM_MAX_SIZE
+ hex "Interleaving memory size, default 64GB"
+ default 0x1000000000
+endif
endif
diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
index 3684f5b40a80..a88123c81ace 100644
--- a/drivers/soc/sifive/sifive_ccache.c
+++ b/drivers/soc/sifive/sifive_ccache.c
@@ -17,6 +17,8 @@
#include <asm/cacheinfo.h>
#include <soc/sifive/sifive_ccache.h>
+#include <asm/dma-noncoherent.h>
+
#define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100
#define SIFIVE_CCACHE_DIRECCFIX_HIGH 0x104
#define SIFIVE_CCACHE_DIRECCFIX_COUNT 0x108
@@ -44,6 +46,9 @@
#define SIFIVE_CCACHE_MAX_ECCINTR 4
+#define SIFIVE_CCACHE_FLUSH64 0x200
+#define SIFIVE_CCACHE_FLUSH64_LINE_LEN 64
+
static void __iomem *ccache_base;
static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];
static struct riscv_cacheinfo_ops ccache_cache_ops;
@@ -103,6 +108,39 @@ static void ccache_config_read(void)
pr_info("Index of the largest way enabled: %u\n", cfg);
}
+#if IS_ENABLED(CONFIG_ARCH_ESWIN_EIC770X_SOC_FAMILY)
+static void ccache_way_enable(void)
+{
+ u32 cfg, val;
+
+ cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
+ val = FIELD_GET(SIFIVE_CCACHE_CONFIG_WAYS_MASK, cfg);
+ writel(val -1 , ccache_base + SIFIVE_CCACHE_WAYENABLE);
+}
+
+static void ccache_flush64_range(phys_addr_t paddr, size_t size)
+{
+ unsigned long line;
+
+ size = size + (paddr % SIFIVE_CCACHE_FLUSH64_LINE_LEN);
+ paddr = ALIGN_DOWN(paddr, SIFIVE_CCACHE_FLUSH64_LINE_LEN);
+
+ mb(); /* sync */
+
+ for (line = paddr; line < paddr + size;
+ line += SIFIVE_CCACHE_FLUSH64_LINE_LEN) {
+ writeq(line, ccache_base + SIFIVE_CCACHE_FLUSH64);
+ mb();
+ }
+}
+
+static const struct riscv_nonstd_cache_ops ccache_cmo_ops __initdata = {
+ .wback = &ccache_flush64_range,
+ .inv = &ccache_flush64_range,
+ .wback_inv = &ccache_flush64_range,
+};
+#endif
+
static const struct of_device_id sifive_ccache_ids[] = {
{ .compatible = "sifive,fu540-c000-ccache" },
{ .compatible = "sifive,fu740-c000-ccache" },
@@ -249,6 +287,11 @@ static int __init sifive_ccache_init(void)
}
of_node_put(np);
+ #if IS_ENABLED(CONFIG_ARCH_ESWIN_EIC770X_SOC_FAMILY)
+ ccache_way_enable();
+ riscv_noncoherent_register_cache_ops(&ccache_cmo_ops);
+ #endif
+
ccache_config_read();
ccache_cache_ops.get_priv_group = ccache_get_priv_group;
--
2.47.0

3197
0004-feat-eswin-memory-Added-eswin-memory-related-changes.patch Normal file
View File

File diff suppressed because it is too large Load Diff

1758
0005-feat-SMMU-support-Support-SMMU.patch Normal file
View File

File diff suppressed because it is too large Load Diff

610
0006-feat-eswin-mailbox-Added-eswin-mailbox-related-chang.patch Normal file
View File

@ -0,0 +1,610 @@
From 00f407ea25b83d421b11a67d101c0b8faa9eb1e6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E2=80=9Chuangyifeng=E2=80=9D?=
<huangyifeng@eswincomputing.com>
Date: Wed, 17 Apr 2024 13:48:05 +0800
Subject: [PATCH 006/219] feat(eswin mailbox):Added eswin mailbox related
changes
Changelogs:
1.Added eswin mailbox dts
2.Added eswin mailbox driver
3.Select CONFIG_ESWIN_MBOX, and update win2030_defconfig
---
arch/riscv/configs/win2030_defconfig | 1 +
drivers/mailbox/Kconfig | 9 +
drivers/mailbox/Makefile | 2 +
drivers/mailbox/eswin-mailbox.c | 518 ++++++++++++++++++++++++++
include/linux/mailbox/eswin-mailbox.h | 15 +
5 files changed, 545 insertions(+)
create mode 100755 drivers/mailbox/eswin-mailbox.c
create mode 100755 include/linux/mailbox/eswin-mailbox.h
diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig
index 2e2e4e419bd3..5d701e98d635 100644
--- a/arch/riscv/configs/win2030_defconfig
+++ b/arch/riscv/configs/win2030_defconfig
@@ -223,6 +223,7 @@ CONFIG_VIRTIO_MMIO=y
CONFIG_STAGING=y
CONFIG_COMMON_CLK_WIN2030=y
CONFIG_MAILBOX=y
+CONFIG_ESWIN_MBOX=y
CONFIG_ARM_SMMU_V3=y
CONFIG_RPMSG_VIRTIO=y
CONFIG_ARCH_ESWIN_EIC770X_SOC_FAMILY=y
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index bc2e265cb02d..3cc765e1ce8e 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -294,5 +294,14 @@ config QCOM_IPCC
sending interrupts to the clients. On the other hand, the driver also
acts as an interrupt controller for receiving interrupts from clients.
Say Y here if you want to build this driver.
+config ESWIN_MBOX
+ tristate "Eswin Mailbox"
+ depends on OF
+ depends on HAS_IOMEM
+ depends on ARCH_ESWIN_EIC770X_SOC_FAMILY
+ help
+ Mailbox driver implementation for the eswin platform. It is used
+ to send message between application processors and MCU. Say Y here if
+ you want to build the eswin mailbox controller driver.
endif
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index fc9376117111..157518a5d716 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -62,3 +62,5 @@ obj-$(CONFIG_SPRD_MBOX) += sprd-mailbox.o
obj-$(CONFIG_QCOM_IPCC) += qcom-ipcc.o
obj-$(CONFIG_APPLE_MAILBOX) += apple-mailbox.o
+
+obj-$(CONFIG_ESWIN_MBOX) += eswin-mailbox.o
diff --git a/drivers/mailbox/eswin-mailbox.c b/drivers/mailbox/eswin-mailbox.c
new file mode 100755
index 000000000000..4e9b6b224469
--- /dev/null
+++ b/drivers/mailbox/eswin-mailbox.c
@@ -0,0 +1,518 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ESWIN Mailbox Driver
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Authors: HuangYiFeng<huangyifeng@eswincomputing.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mailbox_controller.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/mailbox/eswin-mailbox.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+#define ESWIN_MBOX_FIFO_DEPTH 8
+
+struct eswin_mbox_data {
+ int num_chans;
+};
+
+struct eswin_mbox_chan {
+ int idx;
+ int irq;
+ struct eswin_mbox_msg msg[ESWIN_MBOX_FIFO_DEPTH];
+ int msg_cnt;
+ struct eswin_mbox *mb;
+};
+
+/*
+ * Registers offset
+ */
+#define ESWIN_MBOX_WR_DATA0 0x00
+#define ESWIN_MBOX_WR_DATA1 0x04
+#define ESWIN_MBOX_RD_DATA0 0x08
+#define ESWIN_MBOX_RD_DATA1 0x0C
+#define ESWIN_MBOX_FIFO_STATUS 0x10
+#define ESWIN_MBOX_MB_ERR 0x14
+#define ESWIN_MBOX_INT_CTRL 0x18
+#define ESWIN_MBOX_WR_LOCK 0x1C
+
+struct eswin_mbox {
+ struct mbox_controller mbox;
+ struct clk *pclk;
+ struct clk *pclk_device;
+ struct reset_control *rst;
+ struct reset_control *rst_device;
+ void __iomem *mbox_base;
+ void __iomem *mbox_rx_base;
+ struct regmap *map;
+ struct regmap *rx_map;
+ struct device *dev;
+ u32 lock_bit;
+ u32 irq_bit;
+ struct eswin_mbox_chan *chans;
+ spinlock_t rx_lock;
+};
+
+static int eswin_mbox_send_data(struct mbox_chan *chan, void *data)
+{
+ u32 tmp_data;
+
+ struct eswin_mbox *mb = dev_get_drvdata(chan->mbox->dev);
+ struct eswin_mbox_msg *msg = (struct eswin_mbox_msg *)data;
+
+ dev_dbg(mb->mbox.dev, "send_data\n");
+ if (!msg)
+ return -EINVAL;
+
+ // TX FIFO FULL?
+ if (regmap_test_bits(mb->map, ESWIN_MBOX_FIFO_STATUS, BIT_ULL(0))) {
+ return -EBUSY;
+ }
+
+ tmp_data = (u32)msg->data;
+ regmap_write(mb->map, ESWIN_MBOX_WR_DATA0, tmp_data);
+
+ tmp_data = (u32)(msg->data >> 32) | BIT(31);
+ regmap_write(mb->map, ESWIN_MBOX_WR_DATA1, tmp_data);
+ // 写中断enable bit.
+ regmap_set_bits(mb->map, ESWIN_MBOX_INT_CTRL, mb->irq_bit);
+ return 0;
+}
+
+static int eswin_mbox_startup(struct mbox_chan *chan)
+{
+ struct eswin_mbox *mb = dev_get_drvdata(chan->mbox->dev);
+ int ret;
+
+ if (regmap_test_bits(mb->map, ESWIN_MBOX_WR_LOCK, mb->lock_bit)) {
+ return -1;
+ }
+ ret = regmap_set_bits(mb->map, ESWIN_MBOX_WR_LOCK, mb->lock_bit);
+
+ /*占用标志位写入成功表示占用成功*/
+ dev_dbg(mb->mbox.dev, "start, ret %d, lock_bit 0x%x\n", ret,
+ mb->lock_bit);
+ return ret;
+}
+
+static void eswin_mbox_shutdown(struct mbox_chan *chan)
+{
+ struct eswin_mbox *mb = dev_get_drvdata(chan->mbox->dev);
+ int ret;
+
+ ret = regmap_clear_bits(mb->map, ESWIN_MBOX_WR_LOCK, mb->lock_bit);
+ if (0 != ret)
+ dev_err(mb->mbox.dev, "failed to shutdown mailbox\n");
+
+ ret = regmap_clear_bits(mb->map, ESWIN_MBOX_INT_CTRL, mb->irq_bit);
+ if (0 != ret)
+ dev_err(mb->mbox.dev, "failed to disable mailbox int\n");
+
+ return;
+}
+
+static int eswin_mbox_receive_data(struct eswin_mbox *mb,
+ struct eswin_mbox_msg *msg)
+{
+ u32 tmp_data;
+ u32 tmp_data0;
+ u64 tmp;
+
+ regmap_read(mb->rx_map, ESWIN_MBOX_RD_DATA0, &tmp_data0);
+ regmap_read(mb->rx_map, ESWIN_MBOX_RD_DATA1, &tmp_data);
+
+ // RX FIFO empty ?
+ if (tmp_data == 0) {
+ return -1;
+ }
+ tmp = (u64)tmp_data << 32 | tmp_data0;
+
+ msg->data = tmp;
+
+ /*trigger FIFO dequeue*/
+ regmap_write(mb->rx_map, ESWIN_MBOX_RD_DATA1, 0x0);
+ return 0;
+}
+
+static bool eswin_mbox_peek_data(struct mbox_chan *chan)
+{
+ int idx;
+ struct mbox_controller *mbox = chan->mbox;
+ struct eswin_mbox_msg *msg = NULL;
+ struct eswin_mbox *mb = container_of(mbox, struct eswin_mbox, mbox);
+ bool IsData = false;
+ unsigned long flags;
+
+ for (idx = 0; idx < mb->mbox.num_chans; idx++) {
+ spin_lock_irqsave(&mb->rx_lock, flags);
+ msg = &mb->chans[idx].msg[0];
+ if (0 != eswin_mbox_receive_data(mb, msg)) {
+ spin_unlock_irqrestore(&mb->rx_lock, flags);
+ continue;
+ }
+ IsData = true;
+ mb->chans[idx].msg_cnt--;
+ if (NULL != mb->mbox.chans[idx].cl) {
+ mbox_chan_received_data(&mb->mbox.chans[idx], msg);
+ }
+ spin_unlock_irqrestore(&mb->rx_lock, flags);
+ }
+ return IsData;
+}
+
+/*
+ once the data has been enqueued to mailbox hw FIFO in send_data function,
+ we beleive that tx is done
+*/
+static bool eswin_mbox_last_tx_done(struct mbox_chan *chan)
+{
+ return true;
+}
+
+static const struct mbox_chan_ops eswin_mbox_chan_ops = {
+ .send_data = eswin_mbox_send_data,
+ .peek_data = eswin_mbox_peek_data,
+ .startup = eswin_mbox_startup,
+ .shutdown = eswin_mbox_shutdown,
+ .last_tx_done = eswin_mbox_last_tx_done,
+};
+
+static irqreturn_t eswin_mbox_irq(int irq, void *dev_id)
+{
+ int idx;
+ struct eswin_mbox *mb = (struct eswin_mbox *)dev_id;
+ unsigned long flags;
+
+ for (idx = 0; idx < mb->mbox.num_chans; idx++) {
+ if (irq != mb->chans[idx].irq)
+ continue;
+
+ spin_lock_irqsave(&mb->rx_lock, flags);
+ WARN_ON(0 != mb->chans[idx].msg_cnt);
+ while (0 ==
+ eswin_mbox_receive_data(
+ mb,
+ &mb->chans[idx].msg[mb->chans[idx].msg_cnt])) {
+ mb->chans[idx].msg_cnt++;
+ /*
+ MCU may continue enqeuing fifo when we are dequeuing fifo,
+ So we receive up to ESWIN_MBOX_FIFO_DEPTH cnt msgs one time.
+ The left msgs will be handled after eswin_mbox_isr finished.
+ */
+ if (ESWIN_MBOX_FIFO_DEPTH == mb->chans[idx].msg_cnt) {
+ break;
+ }
+ };
+ spin_unlock_irqrestore(&mb->rx_lock, flags);
+ }
+ return IRQ_WAKE_THREAD;
+}
+
+static irqreturn_t eswin_mbox_isr(int irq, void *dev_id)
+{
+ int idx;
+ struct eswin_mbox_msg *msg = NULL;
+ struct eswin_mbox *mb = (struct eswin_mbox *)dev_id;
+ unsigned long flags;
+ int i;
+
+ for (idx = 0; idx < mb->mbox.num_chans; idx++) {
+ if (irq != mb->chans[idx].irq)
+ continue;
+
+ i = 0;
+ spin_lock_irqsave(&mb->rx_lock, flags);
+ while (mb->chans[idx].msg_cnt) {
+ msg = &mb->chans[idx].msg[i++];
+ if (NULL != mb->mbox.chans[idx].cl) {
+ dev_dbg(mb->mbox.dev,
+ "Chan[%d]: receive MCU message, msg %p\n",
+ idx, msg);
+ mbox_chan_received_data(&mb->mbox.chans[idx],
+ msg);
+ }
+ mb->chans[idx].msg_cnt--;
+ }
+ spin_unlock_irqrestore(&mb->rx_lock, flags);
+ }
+ return IRQ_HANDLED;
+}
+
+static const struct eswin_mbox_data win2030_drv_data = {
+ .num_chans = 1,
+};
+
+static const struct of_device_id eswin_mbox_of_match[] = {
+ { .compatible = "eswin,win2030-mailbox", .data = &win2030_drv_data },
+ {},
+};
+MODULE_DEVICE_TABLE(of, eswin_mbox_of_match);
+
+static int eswin_mbox_reg_read(void *context, unsigned int reg,
+ unsigned int *val)
+{
+ struct eswin_mbox *mb = context;
+
+ *val = readl_relaxed(mb->mbox_base + reg);
+ return 0;
+}
+
+static int eswin_mbox_reg_write(void *context, unsigned int reg,
+ unsigned int val)
+{
+ struct eswin_mbox *mb = context;
+
+ writel_relaxed(val, mb->mbox_base + reg);
+ return 0;
+}
+
+static int eswin_mbox_rx_reg_read(void *context, unsigned int reg,
+ unsigned int *val)
+{
+ struct eswin_mbox *mb = context;
+
+ *val = readl_relaxed(mb->mbox_rx_base + reg);
+ return 0;
+}
+
+static int eswin_mbox__rx_reg_write(void *context, unsigned int reg,
+ unsigned int val)
+{
+ struct eswin_mbox *mb = context;
+
+ writel_relaxed(val, mb->mbox_rx_base + reg);
+ return 0;
+}
+
+/**
+ * eswin_mbox_init_regmap() - Initialize registers map
+ * @dev: device private data
+ *
+ * Autodetects needed register access mode and creates the regmap with
+ * corresponding read/write callbacks. This must be called before doing any
+ * other register access.
+ */
+int eswin_mbox_init_regmap(struct eswin_mbox *mb)
+{
+ struct regmap_config map_cfg = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .use_hwlock = true,
+ .cache_type = REGCACHE_NONE,
+ .can_sleep = false,
+ .reg_read = eswin_mbox_reg_read,
+ .reg_write = eswin_mbox_reg_write,
+ };
+ struct regmap_config rx_map_cfg = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .use_hwlock = true,
+ .cache_type = REGCACHE_NONE,
+ .can_sleep = false,
+ .reg_read = eswin_mbox_rx_reg_read,
+ .reg_write = eswin_mbox__rx_reg_write,
+ };
+
+ /*
+ * Note we'll check the return value of the regmap IO accessors only
+ * at the probe stage. The rest of the code won't do this because
+ * basically we have MMIO-based regmap so non of the read/write methods
+ * can fail.
+ */
+ mb->map = devm_regmap_init(mb->dev, NULL, mb, &map_cfg);
+ if (IS_ERR(mb->map)) {
+ dev_err(mb->dev, "Failed to init the registers map\n");
+ return PTR_ERR(mb->map);
+ }
+ mb->rx_map = devm_regmap_init(mb->dev, NULL, mb, &rx_map_cfg);
+ if (IS_ERR(mb->rx_map)) {
+ dev_err(mb->dev, "Failed to init the registers rx map\n");
+ regmap_exit(mb->map);
+ return PTR_ERR(mb->rx_map);
+ }
+
+ return 0;
+}
+
+static int eswin_mbox_probe(struct platform_device *pdev)
+{
+ struct eswin_mbox *mb;
+ const struct of_device_id *match;
+ const struct eswin_mbox_data *drv_data;
+ struct resource *res;
+ int ret, irq, i;
+
+ if (!pdev->dev.of_node)
+ return -ENODEV;
+
+ match = of_match_node(eswin_mbox_of_match, pdev->dev.of_node);
+ drv_data = (const struct eswin_mbox_data *)match->data;
+
+ mb = devm_kzalloc(&pdev->dev, sizeof(*mb), GFP_KERNEL);
+ if (!mb)
+ return -ENOMEM;
+
+ if (of_property_read_u32(pdev->dev.of_node, "lock-bit",
+ &mb->lock_bit)) {
+ dev_err(&pdev->dev, "failed to get lock_bit: %d\n", ret);
+ }
+
+ if (of_property_read_u32(pdev->dev.of_node, "irq-bit", &mb->irq_bit)) {
+ dev_err(&pdev->dev, "failed to get irq_bit: %d\n", ret);
+ }
+ mb->chans = devm_kcalloc(&pdev->dev, drv_data->num_chans,
+ sizeof(*mb->chans), GFP_KERNEL);
+ if (!mb->chans)
+ return -ENOMEM;
+
+ mb->mbox.chans = devm_kcalloc(&pdev->dev, drv_data->num_chans,
+ sizeof(*mb->mbox.chans), GFP_KERNEL);
+ if (!mb->mbox.chans)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, mb);
+
+ mb->mbox.dev = &pdev->dev;
+ mb->mbox.num_chans = drv_data->num_chans;
+ mb->mbox.ops = &eswin_mbox_chan_ops;
+ mb->mbox.txdone_irq = false;
+ mb->mbox.txdone_poll = true;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENODEV;
+
+ mb->mbox_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(mb->mbox_base))
+ return PTR_ERR(mb->mbox_base);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (!res)
+ return -ENODEV;
+
+ mb->mbox_rx_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(mb->mbox_rx_base))
+ return PTR_ERR(mb->mbox_rx_base);
+
+ mb->pclk = devm_clk_get(&pdev->dev, "pclk_mailbox_host");
+ if (IS_ERR(mb->pclk)) {
+ ret = PTR_ERR(mb->pclk);
+ dev_err(&pdev->dev, "failed to get host mailbox clock: %d\n",
+ ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(mb->pclk);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to enable host mailbox pclk: %d\n",
+ ret);
+ return ret;
+ }
+
+ mb->pclk_device = devm_clk_get(&pdev->dev, "pclk_mailbox_device");
+ if (IS_ERR(mb->pclk_device)) {
+ ret = PTR_ERR(mb->pclk_device);
+ dev_err(&pdev->dev, "failed to get device mailbox clock: %d\n",
+ ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(mb->pclk_device);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "failed to enable device mailbox pclk: %d\n", ret);
+ return ret;
+ }
+
+ mb->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, "rst");
+ if (IS_ERR(mb->rst))
+ return PTR_ERR(mb->rst);
+ reset_control_reset(mb->rst);
+
+ mb->rst_device = devm_reset_control_get_optional_exclusive(
+ &pdev->dev, "rst_device");
+ if (IS_ERR(mb->rst_device))
+ return PTR_ERR(mb->rst_device);
+ reset_control_reset(mb->rst_device);
+
+ for (i = 0; i < mb->mbox.num_chans; i++) {
+ irq = platform_get_irq(pdev, i);
+ if (irq < 0)
+ return irq;
+
+ ret = devm_request_threaded_irq(&pdev->dev, irq, eswin_mbox_irq,
+ eswin_mbox_isr, IRQF_ONESHOT,
+ dev_name(&pdev->dev), mb);
+ if (ret < 0)
+ return ret;
+
+ mb->chans[i].idx = i;
+ mb->chans[i].irq = irq;
+ mb->chans[i].mb = mb;
+ }
+ mb->dev = &pdev->dev;
+ ret = eswin_mbox_init_regmap(mb);
+ if (ret)
+ return ret;
+
+ spin_lock_init(&mb->rx_lock);
+ ret = devm_mbox_controller_register(&pdev->dev, &mb->mbox);
+ if (ret < 0)
+ dev_err(&pdev->dev, "failed to register mailbox: %d\n", ret);
+
+ dev_info(&pdev->dev, "register sucessfully\n");
+ return ret;
+}
+
+static int eswin_mbox_remove(struct platform_device *pdev)
+{
+ int ret;
+ struct eswin_mbox *mb = platform_get_drvdata(pdev);
+
+ ret = reset_control_assert(mb->rst);
+ WARN_ON(ret != 0);
+ ret = reset_control_assert(mb->rst_device);
+ WARN_ON(ret != 0);
+ clk_disable_unprepare(mb->pclk_device);
+ clk_disable_unprepare(mb->pclk);
+ return 0;
+}
+
+static struct platform_driver eswin_mbox_driver = {
+ .probe = eswin_mbox_probe,
+ .remove = eswin_mbox_remove,
+ .driver = {
+ .name = "eswin-mailbox",
+ .of_match_table = of_match_ptr(eswin_mbox_of_match),
+ },
+};
+
+module_platform_driver(eswin_mbox_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Eswin mailbox: communicate between CPU cores and MCUs");
+MODULE_AUTHOR("Huang Yifeng <huangyifeng@eswincomputing.com>");
diff --git a/include/linux/mailbox/eswin-mailbox.h b/include/linux/mailbox/eswin-mailbox.h
new file mode 100755
index 000000000000..6389befb5b90
--- /dev/null
+++ b/include/linux/mailbox/eswin-mailbox.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef _LINUX_ESWIN_MAILBOX_H_
+#define _LINUX_ESWIN_MAILBOX_H_
+
+/**
+ * struct eswin_mbox_msg - Eswin mailbox message structure
+ * @data: message payload, only 63 bit valid
+ *
+ */
+struct eswin_mbox_msg {
+ u64 data;
+};
+
+#endif /* _LINUX_ESWIN_MAILBOX_H_ */
--
2.47.0

1437
0007-feat-eswin-pinctrl-Added-eswin-pinctrl-related-chang.patch Normal file
View File

File diff suppressed because it is too large Load Diff

769
0008-feat-Add-support-for-ethernet-driver.patch Normal file
View File

@ -0,0 +1,769 @@
From 8ccdbdf8e1038748861546ac0205a5730c0cfd74 Mon Sep 17 00:00:00 2001
From: fanglifei <fanglifei@eswincomputing.com>
Date: Mon, 22 Apr 2024 16:15:37 +0800
Subject: [PATCH 008/219] feat: Add support for ethernet driver
Changelogs:
1. Adapt ethernet driver for linux-6.6
2. Change cmdline from force to extend
---
arch/riscv/boot/dts/eswin/eic7700-evb.dts | 12 +-
.../riscv/boot/dts/eswin/eic7700-pinctrl.dtsi | 4 +-
.../dts/eswin/eswin-win2030-die0-soc.dtsi | 4 +-
.../dts/eswin/eswin-win2030-die1-soc.dtsi | 4 +-
arch/riscv/configs/win2030_defconfig | 3 +-
drivers/net/ethernet/stmicro/stmmac/Kconfig | 8 +
drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
.../ethernet/stmicro/stmmac/dwmac-win2030.c | 597 ++++++++++++++++++
8 files changed, 624 insertions(+), 9 deletions(-)
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-win2030.c
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb.dts b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
index 358ea4e7ac84..25bdb68ef921 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
@@ -476,12 +476,20 @@ &sdio1 {
};
&d0_gmac0 {
- mac-address=[00 00 00 00 00 00];
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio94_default>;
+ rst-gpios = <&portc 30 GPIO_ACTIVE_LOW>;
+ eswin,rgmiisel = <&pinctrl 0x290 0x3>;
+ eswin,led-cfgs = <0x6251 0x6251 0x6251>;
status = "okay";
};
&d0_gmac1 {
- mac-address=[00 00 00 00 00 00];
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio16_default>;
+ rst-gpios = <&porta 16 GPIO_ACTIVE_LOW>;
+ eswin,rgmiisel = <&pinctrl 0x294 0x3>;
+ eswin,led-cfgs = <0x6251 0x6251 0x6251>;
status = "okay";
};
diff --git a/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi b/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
index a6dd5aaeee00..1b194f9d04ee 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
@@ -25,7 +25,7 @@ / {
#size-cells = <2>;
soc {
pinctrl: pinctrl@0x51600080 {
- compatible = "eswin,eic7700-pinctrl";
+ compatible = "eswin,eic7700-pinctrl", "syscon";
reg = <0x0 0x51600080 0x0 0x1FFF80>;
status = "disabled";
//func0
@@ -1231,4 +1231,4 @@ mux {
};
};
};
-};
\ No newline at end of file
+};
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
index c3bbfab6fb47..e56ff06664f1 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
@@ -438,7 +438,7 @@ d0_gmac0: ethernet@50400000 {
clock-names = "app", "csr","tx";
resets = <&d0_reset HSPDMA_RST_CTRL SW_HSP_ETH0_ARSTN>;
reset-names = "ethrst";
- iommus = <&smmu0 WIN2030_SID_ETH0>;
+ // iommus = <&smmu0 WIN2030_SID_ETH0>;
tbus = <WIN2030_TBUID_ETH>;
dma-noncoherent;
eswin,hsp_sp_csr = <&d0_hsp_sp_csr 0x1030 0x100 0x108>;
@@ -468,7 +468,7 @@ d0_gmac1: ethernet@50410000 {
clock-names = "app", "csr","tx";
resets = <&d0_reset HSPDMA_RST_CTRL SW_HSP_ETH1_ARSTN>;
reset-names = "ethrst";
- iommus = <&smmu0 WIN2030_SID_ETH1>;
+ // iommus = <&smmu0 WIN2030_SID_ETH1>;
tbus = <WIN2030_TBUID_ETH>;
dma-noncoherent;
eswin,hsp_sp_csr = <&d0_hsp_sp_csr 0x1034 0x200 0x208>;
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
index acd83f4bb20d..9c24a81da4f8 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
@@ -1501,7 +1501,7 @@ d1_gmac0: ethernet@70400000 {
clock-names = "app", "csr","tx";
resets = <&d1_reset HSPDMA_RST_CTRL SW_HSP_ETH0_ARSTN>;
reset-names = "ethrst";
- iommus = <&smmu1 WIN2030_SID_ETH0>;
+ // iommus = <&smmu1 WIN2030_SID_ETH0>;
tbus = <WIN2030_TBUID_ETH>;
dma-noncoherent;
eswin,hsp_sp_csr = <&d1_hsp_sp_csr 0x1030 0x100 0x108>;
@@ -1531,7 +1531,7 @@ d1_gmac1: ethernet@70410000 {
clock-names = "app", "csr","tx";
resets = <&d1_reset HSPDMA_RST_CTRL SW_HSP_ETH1_ARSTN>;
reset-names = "ethrst";
- iommus = <&smmu1 WIN2030_SID_ETH1>;
+ // iommus = <&smmu1 WIN2030_SID_ETH1>;
tbus = <WIN2030_TBUID_ETH>;
dma-noncoherent;
eswin,hsp_sp_csr = <&d1_hsp_sp_csr 0x1034 0x200 0x208>;
diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig
index c7a983e1e21f..c0695f06820c 100644
--- a/arch/riscv/configs/win2030_defconfig
+++ b/arch/riscv/configs/win2030_defconfig
@@ -23,7 +23,7 @@ CONFIG_SMP=y
CONFIG_RISCV_SBI_V01=y
# CONFIG_RISCV_BOOT_SPINWAIT is not set
CONFIG_CMDLINE="earlycon=sbi console=ttyS0,115200n8 clk_ignore_unused cma_pernuma=0x2000000 disable_bypass=false"
-CONFIG_CMDLINE_FORCE=y
+CONFIG_CMDLINE_EXTEND=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
@@ -107,6 +107,7 @@ CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_SOCIONEXT is not set
CONFIG_STMMAC_ETH=y
CONFIG_STMMAC_SELFTESTS=y
+CONFIG_DWMAC_WIN2030=y
# CONFIG_DWMAC_GENERIC is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_VERTEXCOM is not set
diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index 92d7d5a00b84..7b5ff1129461 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
@@ -49,6 +49,14 @@ config DWMAC_DWC_QOS_ETH
help
Support for chips using the snps,dwc-qos-ethernet.txt DT binding.
+config DWMAC_WIN2030
+ tristate "Support for Eswin WIN2030 ethernet driver"
+ select CRC32
+ select MII
+ depends on OF && HAS_DMA && ARCH_ESWIN_EIC770X_SOC_FAMILY
+ help
+ Support for Eswin WIN2030 ethernet driver.
+
config DWMAC_GENERIC
tristate "Generic driver for DWMAC"
default STMMAC_PLATFORM
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index 5b57aee19267..4b22312c5ea8 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_DWMAC_GENERIC) += dwmac-generic.o
obj-$(CONFIG_DWMAC_IMX8) += dwmac-imx.o
obj-$(CONFIG_DWMAC_TEGRA) += dwmac-tegra.o
obj-$(CONFIG_DWMAC_VISCONTI) += dwmac-visconti.o
+obj-$(CONFIG_DWMAC_WIN2030) += dwmac-win2030.o
stmmac-platform-objs:= stmmac_platform.o
dwmac-altr-socfpga-objs := dwmac-socfpga.o
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-win2030.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-win2030.c
new file mode 100644
index 000000000000..0b37eabd6334
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-win2030.c
@@ -0,0 +1,597 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Eswin DWC Ethernet linux driver
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/gpio/consumer.h>
+#include <linux/ethtool.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/ioport.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_net.h>
+#include <linux/mfd/syscon.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/stmmac.h>
+#include <linux/iommu.h>
+#include "stmmac_platform.h"
+#include "dwmac4.h"
+#include <linux/mfd/syscon.h>
+#include <linux/bitfield.h>
+#include <linux/regmap.h>
+#include <linux/eswin-win2030-sid-cfg.h>
+#include <linux/gpio/consumer.h>
+
+/* eth_phy_ctrl_offset eth0:0x100; eth1:0x200 */
+#define ETH_TX_CLK_SEL BIT(16)
+#define ETH_PHY_INTF_SELI BIT(0)
+
+/* eth_axi_lp_ctrl_offset eth0:0x108; eth1:0x208 */
+#define ETH_CSYSREQ_VAL BIT(0)
+
+/* hsp_aclk_ctrl_offset (0x148) */
+#define HSP_ACLK_CLKEN BIT(31)
+#define HSP_ACLK_DIVSOR (0x2 << 4)
+
+/* hsp_cfg_ctrl_offset (0x14c) */
+#define HSP_CFG_CLKEN BIT(31)
+#define SCU_HSP_PCLK_EN BIT(30)
+#define HSP_CFG_CTRL_REGSET (HSP_CFG_CLKEN | SCU_HSP_PCLK_EN)
+
+/* RTL8211F PHY Configurations for LEDs */
+#define PHY_ADDR 0
+#define PHY_PAGE_SWITCH_REG 31
+#define PHY_LED_CFG_REG 16
+#define PHY_LED_PAGE_CFG 0xd04
+
+#define AWSMMUSID GENMASK(31, 24) // The sid of write operation
+#define AWSMMUSSID GENMASK(23, 16) // The ssid of write operation
+#define ARSMMUSID GENMASK(15, 8) // The sid of read operation
+#define ARSMMUSSID GENMASK(7, 0) // The ssid of read operation
+
+struct dwc_qos_priv {
+ struct device *dev;
+ int dev_id;
+ struct regmap *crg_regmap;
+ struct regmap *hsp_regmap;
+ struct reset_control *rst;
+ struct clk *clk_app;
+ struct clk *clk_csr;
+ struct clk *clk_tx;
+ struct regmap *rgmii_sel;
+ struct gpio_desc *phy_reset;
+ struct stmmac_priv *stmpriv;
+ int phyled_cfgs[3];
+};
+
+static int dwc_eth_dwmac_config_dt(struct platform_device *pdev,
+ struct plat_stmmacenet_data *plat_dat)
+{
+ struct device *dev = &pdev->dev;
+ u32 burst_map = 0;
+ u32 bit_index = 0;
+ u32 a_index = 0;
+
+ if (!plat_dat->axi) {
+ plat_dat->axi = kzalloc(sizeof(struct stmmac_axi), GFP_KERNEL);
+
+ if (!plat_dat->axi)
+ return -ENOMEM;
+ }
+
+ plat_dat->axi->axi_lpi_en = device_property_read_bool(dev,
+ "snps,en-lpi");
+ if (device_property_read_u32(dev, "snps,write-requests",
+ &plat_dat->axi->axi_wr_osr_lmt)) {
+ /**
+ * Since the register has a reset value of 1, if property
+ * is missing, default to 1.
+ */
+ plat_dat->axi->axi_wr_osr_lmt = 1;
+ } else {
+ /**
+ * If property exists, to keep the behavior from dwc_eth_qos,
+ * subtract one after parsing.
+ */
+ plat_dat->axi->axi_wr_osr_lmt--;
+ }
+
+ if (device_property_read_u32(dev, "snps,read-requests",
+ &plat_dat->axi->axi_rd_osr_lmt)) {
+ /**
+ * Since the register has a reset value of 1, if property
+ * is missing, default to 1.
+ */
+ plat_dat->axi->axi_rd_osr_lmt = 1;
+ } else {
+ /**
+ * If property exists, to keep the behavior from dwc_eth_qos,
+ * subtract one after parsing.
+ */
+ plat_dat->axi->axi_rd_osr_lmt--;
+ }
+ device_property_read_u32(dev, "snps,burst-map", &burst_map);
+
+ /* converts burst-map bitmask to burst array */
+ for (bit_index = 0; bit_index < 7; bit_index++) {
+ if (burst_map & (1 << bit_index)) {
+ switch (bit_index) {
+ case 0:
+ plat_dat->axi->axi_blen[a_index] = 4; break;
+ case 1:
+ plat_dat->axi->axi_blen[a_index] = 8; break;
+ case 2:
+ plat_dat->axi->axi_blen[a_index] = 16; break;
+ case 3:
+ plat_dat->axi->axi_blen[a_index] = 32; break;
+ case 4:
+ plat_dat->axi->axi_blen[a_index] = 64; break;
+ case 5:
+ plat_dat->axi->axi_blen[a_index] = 128; break;
+ case 6:
+ plat_dat->axi->axi_blen[a_index] = 256; break;
+ default:
+ break;
+ }
+ a_index++;
+ }
+ }
+
+ /* dwc-qos needs GMAC4, AAL, TSO and PMT */
+ plat_dat->has_gmac4 = 1;
+ plat_dat->dma_cfg->aal = 1;
+ plat_dat->flags |= STMMAC_FLAG_TSO_EN;
+ plat_dat->pmt = 1;
+
+ return 0;
+}
+
+static int eswin_eth_sid_cfg(struct device *dev)
+{
+ int ret;
+ struct regmap *regmap;
+ int hsp_mmu_eth_reg;
+ u32 rdwr_sid_ssid;
+ u32 sid;
+ struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
+
+ /* not behind smmu, use the default reset value(0x0) of the reg as streamID*/
+ if (fwspec == NULL) {
+ dev_dbg(dev, "dev is not behind smmu, skip configuration of sid\n");
+ return 0;
+ }
+ sid = fwspec->ids[0];
+
+ regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "eswin,hsp_sp_csr");
+ if (IS_ERR(regmap)) {
+ dev_dbg(dev, "No hsp_sp_csr phandle specified\n");
+ return 0;
+ }
+
+ ret = of_property_read_u32_index(dev->of_node, "eswin,hsp_sp_csr", 1,
+ &hsp_mmu_eth_reg);
+ if (ret) {
+ dev_err(dev, "can't get eth sid cfg reg offset (%d)\n", ret);
+ return ret;
+ }
+
+ /* make the reading sid the same as writing sid, ssid is fixed to zero */
+ rdwr_sid_ssid = FIELD_PREP(AWSMMUSID, sid);
+ rdwr_sid_ssid |= FIELD_PREP(ARSMMUSID, sid);
+ rdwr_sid_ssid |= FIELD_PREP(AWSMMUSSID, 0);
+ rdwr_sid_ssid |= FIELD_PREP(ARSMMUSSID, 0);
+ regmap_write(regmap, hsp_mmu_eth_reg, rdwr_sid_ssid);
+
+ ret = win2030_dynm_sid_enable(dev_to_node(dev));
+ if (ret < 0)
+ dev_err(dev, "failed to config eth streamID(%d)!\n", sid);
+ else
+ dev_dbg(dev, "success to config eth streamID(%d)!\n", sid);
+
+ return ret;
+}
+
+static void dwc_qos_fix_speed(void *priv, unsigned int speed, unsigned int mode)
+{
+ unsigned long rate = 125000000;
+ int err, data = 0;
+ struct dwc_qos_priv *dwc_priv = (struct dwc_qos_priv *)priv;
+
+ switch (speed) {
+ case SPEED_1000:
+ rate = 125000000;
+
+ if (dwc_priv->dev_id == 0) {
+ regmap_write(dwc_priv->hsp_regmap, 0x118, 0x800c8023);
+ regmap_write(dwc_priv->hsp_regmap, 0x11c, 0x0c0c0c0c);
+ regmap_write(dwc_priv->hsp_regmap, 0x114, 0x23232323);
+ } else {
+ regmap_write(dwc_priv->hsp_regmap, 0x218, 0x80268025);
+ regmap_write(dwc_priv->hsp_regmap, 0x21c, 0x26262626);
+ regmap_write(dwc_priv->hsp_regmap, 0x214, 0x25252525);
+ }
+
+ if (dwc_priv->stmpriv) {
+ data = mdiobus_read(dwc_priv->stmpriv->mii, PHY_ADDR, PHY_PAGE_SWITCH_REG);
+ mdiobus_write(dwc_priv->stmpriv->mii, PHY_ADDR, PHY_PAGE_SWITCH_REG, PHY_LED_PAGE_CFG);
+ mdiobus_write(dwc_priv->stmpriv->mii, PHY_ADDR, PHY_LED_CFG_REG, dwc_priv->phyled_cfgs[0]);
+ mdiobus_write(dwc_priv->stmpriv->mii, PHY_ADDR, PHY_PAGE_SWITCH_REG, data);
+ }
+
+ break;
+ case SPEED_100:
+ rate = 25000000;
+
+ if (dwc_priv->dev_id == 0) {
+ regmap_write(dwc_priv->hsp_regmap, 0x118, 0x803f8050);
+ regmap_write(dwc_priv->hsp_regmap, 0x11c, 0x3f3f3f3f);
+ regmap_write(dwc_priv->hsp_regmap, 0x114, 0x50505050);
+ } else {
+ regmap_write(dwc_priv->hsp_regmap, 0x218, 0x80588048);
+ regmap_write(dwc_priv->hsp_regmap, 0x21c, 0x58585858);
+ regmap_write(dwc_priv->hsp_regmap, 0x214, 0x48484848);
+ }
+
+ if (dwc_priv->stmpriv) {
+ data = mdiobus_read(dwc_priv->stmpriv->mii, PHY_ADDR, PHY_PAGE_SWITCH_REG);
+ mdiobus_write(dwc_priv->stmpriv->mii, PHY_ADDR, PHY_PAGE_SWITCH_REG, PHY_LED_PAGE_CFG);
+ mdiobus_write(dwc_priv->stmpriv->mii, PHY_ADDR, PHY_LED_CFG_REG, dwc_priv->phyled_cfgs[1]);
+ mdiobus_write(dwc_priv->stmpriv->mii, PHY_ADDR, PHY_PAGE_SWITCH_REG, data);
+ }
+
+ break;
+ case SPEED_10:
+ rate = 2500000;
+
+ if (dwc_priv->dev_id == 0) {
+ regmap_write(dwc_priv->hsp_regmap, 0x118, 0x0);
+ regmap_write(dwc_priv->hsp_regmap, 0x11c, 0x0);
+ regmap_write(dwc_priv->hsp_regmap, 0x114, 0x0);
+ } else {
+ regmap_write(dwc_priv->hsp_regmap, 0x218, 0x0);
+ regmap_write(dwc_priv->hsp_regmap, 0x21c, 0x0);
+ regmap_write(dwc_priv->hsp_regmap, 0x214, 0x0);
+ }
+
+ if (dwc_priv->stmpriv) {
+ data = mdiobus_read(dwc_priv->stmpriv->mii, PHY_ADDR, PHY_PAGE_SWITCH_REG);
+ mdiobus_write(dwc_priv->stmpriv->mii, PHY_ADDR, PHY_PAGE_SWITCH_REG, PHY_LED_PAGE_CFG);
+ mdiobus_write(dwc_priv->stmpriv->mii, PHY_ADDR, PHY_LED_CFG_REG, dwc_priv->phyled_cfgs[2]);
+ mdiobus_write(dwc_priv->stmpriv->mii, PHY_ADDR, PHY_PAGE_SWITCH_REG, data);
+ }
+
+ break;
+ default:
+ dev_err(dwc_priv->dev, "invalid speed %u\n", speed);
+ break;
+ }
+
+ err = clk_set_rate(dwc_priv->clk_tx, rate);
+ if (err < 0)
+ {
+ dev_err(dwc_priv->dev, "failed to set TX rate: %d\n", err);
+ }
+}
+
+static int dwc_qos_probe(struct platform_device *pdev,
+ struct plat_stmmacenet_data *plat_dat,
+ struct stmmac_resources *stmmac_res)
+{
+ struct dwc_qos_priv *dwc_priv;
+ int ret;
+ int err;
+ u32 hsp_aclk_ctrl_offset;
+ u32 hsp_aclk_ctrl_regset;
+ u32 hsp_cfg_ctrl_offset;
+ u32 eth_axi_lp_ctrl_offset;
+ u32 eth_phy_ctrl_offset;
+ u32 eth_phy_ctrl_regset;
+ u32 rgmiisel_offset;
+ u32 rgmiisel_regset;
+
+ dwc_priv = devm_kzalloc(&pdev->dev, sizeof(*dwc_priv), GFP_KERNEL);
+ if (!dwc_priv)
+ return -ENOMEM;
+
+ if (device_property_read_u32(&pdev->dev, "id", &dwc_priv->dev_id)) {
+ dev_err(&pdev->dev, "Can not read device id!\n");
+ return -EINVAL;
+ }
+
+ dwc_priv->dev = &pdev->dev;
+ dwc_priv->phy_reset = devm_gpiod_get(&pdev->dev, "rst", GPIOD_OUT_LOW);
+ if (IS_ERR(dwc_priv->phy_reset)) {
+ dev_err(&pdev->dev, "Reset gpio not specified\n");
+ return -EINVAL;
+ }
+
+ gpiod_set_value(dwc_priv->phy_reset, 0);
+
+ dwc_priv->rgmii_sel = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "eswin,rgmiisel");
+ if (IS_ERR(dwc_priv->rgmii_sel)){
+ dev_dbg(&pdev->dev, "rgmiisel not specified\n");
+ return -EINVAL;
+ }
+
+ ret = of_property_read_u32_index(pdev->dev.of_node, "eswin,led-cfgs", 0, &dwc_priv->phyled_cfgs[0]);
+ if (ret) {
+ dev_warn(&pdev->dev, "can't get led cfgs for 1Gbps mode (%d)\n", ret);
+ }
+
+ ret = of_property_read_u32_index(pdev->dev.of_node, "eswin,led-cfgs", 1, &dwc_priv->phyled_cfgs[1]);
+ if (ret) {
+ dev_warn(&pdev->dev, "can't get led cfgs for 100Mbps mode (%d)\n", ret);
+ }
+
+ ret = of_property_read_u32_index(pdev->dev.of_node, "eswin,led-cfgs", 2, &dwc_priv->phyled_cfgs[2]);
+ if (ret) {
+ dev_warn(&pdev->dev, "can't get led cfgs for 10Mbps mode (%d)\n", ret);
+ }
+
+ ret = of_property_read_u32_index(pdev->dev.of_node, "eswin,rgmiisel", 1, &rgmiisel_offset);
+ if (ret) {
+ dev_err(&pdev->dev, "can't get rgmiisel_offset (%d)\n", ret);
+ return ret;
+ }
+
+ ret = of_property_read_u32_index(pdev->dev.of_node, "eswin,rgmiisel", 2, &rgmiisel_regset);
+ if (ret) {
+ dev_err(&pdev->dev, "can't get rgmiisel_regset (%d)\n", ret);
+ return ret;
+ }
+
+ regmap_write(dwc_priv->rgmii_sel, rgmiisel_offset, rgmiisel_regset);
+
+ dwc_priv->crg_regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "eswin,syscrg_csr");
+ if (IS_ERR(dwc_priv->crg_regmap)){
+ dev_dbg(&pdev->dev, "No syscrg_csr phandle specified\n");
+ return 0;
+ }
+
+ ret = of_property_read_u32_index(pdev->dev.of_node, "eswin,syscrg_csr", 1,
+ &hsp_aclk_ctrl_offset);
+ if (ret) {
+ dev_err(&pdev->dev, "can't get hsp_aclk_ctrl_offset (%d)\n", ret);
+ return ret;
+ }
+ regmap_read(dwc_priv->crg_regmap, hsp_aclk_ctrl_offset, &hsp_aclk_ctrl_regset);
+ hsp_aclk_ctrl_regset |= (HSP_ACLK_CLKEN | HSP_ACLK_DIVSOR);
+ regmap_write(dwc_priv->crg_regmap, hsp_aclk_ctrl_offset, hsp_aclk_ctrl_regset);
+
+ ret = of_property_read_u32_index(pdev->dev.of_node, "eswin,syscrg_csr", 2,
+ &hsp_cfg_ctrl_offset);
+ if (ret) {
+ dev_err(&pdev->dev, "can't get hsp_cfg_ctrl_offset (%d)\n", ret);
+ return ret;
+ }
+ regmap_write(dwc_priv->crg_regmap, hsp_cfg_ctrl_offset, HSP_CFG_CTRL_REGSET);
+
+ dwc_priv->hsp_regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "eswin,hsp_sp_csr");
+ if (IS_ERR(dwc_priv->hsp_regmap)){
+ dev_dbg(&pdev->dev, "No hsp_sp_csr phandle specified\n");
+ return 0;
+ }
+
+ ret = of_property_read_u32_index(pdev->dev.of_node, "eswin,hsp_sp_csr", 2,
+ &eth_phy_ctrl_offset);
+ if (ret) {
+ dev_err(&pdev->dev, "can't get eth_phy_ctrl_offset (%d)\n", ret);
+ return ret;
+ }
+ regmap_read(dwc_priv->hsp_regmap, eth_phy_ctrl_offset, &eth_phy_ctrl_regset);
+ eth_phy_ctrl_regset |= (ETH_TX_CLK_SEL | ETH_PHY_INTF_SELI);
+ regmap_write(dwc_priv->hsp_regmap, eth_phy_ctrl_offset, eth_phy_ctrl_regset);
+
+ ret = of_property_read_u32_index(pdev->dev.of_node, "eswin,hsp_sp_csr", 3,
+ &eth_axi_lp_ctrl_offset);
+ if (ret) {
+ dev_err(&pdev->dev, "can't get eth_axi_lp_ctrl_offset (%d)\n", ret);
+ return ret;
+ }
+ regmap_write(dwc_priv->hsp_regmap, eth_axi_lp_ctrl_offset, ETH_CSYSREQ_VAL);
+
+ dwc_priv->clk_app = devm_clk_get(&pdev->dev, "app");
+ if (IS_ERR(dwc_priv->clk_app)) {
+ dev_err(&pdev->dev, "app clock not found.\n");
+ return PTR_ERR(dwc_priv->clk_app);
+ }
+
+ err = clk_prepare_enable(dwc_priv->clk_app);
+ if (err < 0) {
+ dev_err(&pdev->dev, "failed to enable app clock: %d\n",
+ err);
+ return err;
+ }
+
+ dwc_priv->clk_csr = devm_clk_get(&pdev->dev, "csr");
+ if (IS_ERR(dwc_priv->clk_csr)) {
+ dev_err(&pdev->dev, "csr clock not found.\n");
+ return PTR_ERR(dwc_priv->clk_csr);
+ }
+
+ err = clk_prepare_enable(dwc_priv->clk_csr);
+ if (err < 0) {
+ dev_err(&pdev->dev, "failed to enable csr clock: %d\n",
+ err);
+ return err;
+ }
+
+ dwc_priv->clk_tx = devm_clk_get(&pdev->dev, "tx");
+ if (IS_ERR(plat_dat->pclk)) {
+ dev_err(&pdev->dev, "tx clock not found.\n");
+ return PTR_ERR(dwc_priv->clk_tx);
+ }
+
+ err = clk_prepare_enable(dwc_priv->clk_tx);
+ if (err < 0) {
+ dev_err(&pdev->dev, "failed to enable tx clock: %d\n",
+ err);
+ return err;
+ }
+ dwc_priv->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, "ethrst");
+ if (IS_ERR(dwc_priv->rst)) {
+ return PTR_ERR(dwc_priv->rst);
+ }
+
+ ret = reset_control_assert(dwc_priv->rst);
+ WARN_ON(0 != ret);
+ ret = reset_control_deassert(dwc_priv->rst);
+ WARN_ON(0 != ret);
+
+ ret = win2030_tbu_power(&pdev->dev, true);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to power on tbu\n");
+ return ret;
+ }
+
+ plat_dat->fix_mac_speed = dwc_qos_fix_speed;
+ plat_dat->bsp_priv = dwc_priv;
+ plat_dat->phy_addr = PHY_ADDR;
+
+ return 0;
+}
+
+static int dwc_qos_remove(struct platform_device *pdev)
+{
+ int ret;
+ struct dwc_qos_priv *dwc_priv = get_stmmac_bsp_priv(&pdev->dev);
+
+ ret = win2030_tbu_power(&pdev->dev, false);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to power down tbu\n");
+ return ret;
+ }
+
+ reset_control_assert(dwc_priv->rst);
+ clk_disable_unprepare(dwc_priv->clk_tx);
+ clk_disable_unprepare(dwc_priv->clk_csr);
+ clk_disable_unprepare(dwc_priv->clk_app);
+
+ devm_gpiod_put(&pdev->dev, dwc_priv->phy_reset);
+
+ return 0;
+}
+
+struct dwc_eth_dwmac_data {
+ int (*probe)(struct platform_device *pdev,
+ struct plat_stmmacenet_data *data,
+ struct stmmac_resources *res);
+ int (*remove)(struct platform_device *pdev);
+};
+
+static const struct dwc_eth_dwmac_data dwc_qos_data = {
+ .probe = dwc_qos_probe,
+ .remove = dwc_qos_remove,
+};
+
+static int dwc_eth_dwmac_probe(struct platform_device *pdev)
+{
+ const struct dwc_eth_dwmac_data *data;
+ struct plat_stmmacenet_data *plat_dat;
+ struct stmmac_resources stmmac_res;
+ struct net_device *ndev = NULL;
+ struct stmmac_priv *stmpriv = NULL;
+ struct dwc_qos_priv *dwc_priv = NULL;
+ int ret;
+
+ data = device_get_match_data(&pdev->dev);
+
+ memset(&stmmac_res, 0, sizeof(struct stmmac_resources));
+
+ /**
+ * Since stmmac_platform supports name IRQ only, basic platform
+ * resource initialization is done in the glue logic.
+ */
+ stmmac_res.irq = platform_get_irq(pdev, 0);
+ if (stmmac_res.irq < 0)
+ return stmmac_res.irq;
+ stmmac_res.wol_irq = stmmac_res.irq;
+ stmmac_res.addr = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(stmmac_res.addr))
+ return PTR_ERR(stmmac_res.addr);
+
+ plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);
+ if (IS_ERR(plat_dat))
+ return PTR_ERR(plat_dat);
+
+ ret = data->probe(pdev, plat_dat, &stmmac_res);
+ if (ret < 0) {
+ if (ret != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "failed to probe subdriver: %d\n",
+ ret);
+
+ goto remove_config;
+ }
+
+ ret = dwc_eth_dwmac_config_dt(pdev, plat_dat);
+ if (ret)
+ goto remove;
+
+ ret = eswin_eth_sid_cfg(&pdev->dev);
+ if (ret)
+ goto remove;
+
+ ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
+ if (ret)
+ goto remove;
+
+ ndev = dev_get_drvdata(&pdev->dev);
+ stmpriv = netdev_priv(ndev);
+ dwc_priv = (struct dwc_qos_priv *)plat_dat->bsp_priv;
+ dwc_priv->stmpriv = stmpriv;
+
+ return ret;
+
+remove:
+ data->remove(pdev);
+remove_config:
+ stmmac_remove_config_dt(pdev, plat_dat);
+
+ return ret;
+}
+
+static int dwc_eth_dwmac_remove(struct platform_device *pdev)
+{
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct stmmac_priv *priv = netdev_priv(ndev);
+ const struct dwc_eth_dwmac_data *data;
+ int err;
+
+ data = device_get_match_data(&pdev->dev);
+
+ stmmac_dvr_remove(&pdev->dev);
+
+ err = data->remove(pdev);
+ if (err < 0)
+ dev_err(&pdev->dev, "failed to remove subdriver: %d\n", err);
+
+ stmmac_remove_config_dt(pdev, priv->plat);
+
+ return err;
+}
+
+static const struct of_device_id dwc_eth_dwmac_match[] = {
+ { .compatible = "eswin,win2030-qos-eth", .data = &dwc_qos_data },
+ { }
+};
+MODULE_DEVICE_TABLE(of, dwc_eth_dwmac_match);
+
+static struct platform_driver win2030_eth_dwmac_driver = {
+ .probe = dwc_eth_dwmac_probe,
+ .remove = dwc_eth_dwmac_remove,
+ .driver = {
+ .name = "win2030-eth-dwmac",
+ .pm = &stmmac_pltfr_pm_ops,
+ .of_match_table = dwc_eth_dwmac_match,
+ },
+};
+module_platform_driver(win2030_eth_dwmac_driver);
+
+MODULE_AUTHOR("Eswin");
+MODULE_DESCRIPTION("Eswin win2030 qos ethernet driver");
+MODULE_LICENSE("GPL v2");
--
2.47.0

4202
0009-feat-EVB-A2-dts-pcie-Added-EVB-A2-dts.patch Normal file
View File

File diff suppressed because it is too large Load Diff

34
0010-feat-CMA-Select-CONFIG_CMA-and-CONFIG_DMA_CMA.patch Normal file
View File

@ -0,0 +1,34 @@
From 6285c72e1cb548489ef4ffaede5a95f33ed01185 Mon Sep 17 00:00:00 2001
From: linmin <linmin@eswincomputing.com>
Date: Tue, 21 May 2024 13:50:46 +0800
Subject: [PATCH 010/219] feat(CMA):Select CONFIG_CMA and CONFIG_DMA_CMA
Changelogs:
1.Select CONFIG_CMA and CONFIG_DMA_CMA, save it to win2030_defconfig
---
arch/riscv/configs/win2030_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig
index 332acc518c31..725ad2400def 100644
--- a/arch/riscv/configs/win2030_defconfig
+++ b/arch/riscv/configs/win2030_defconfig
@@ -36,6 +36,7 @@ CONFIG_JUMP_LABEL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_CMA=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -269,6 +270,7 @@ CONFIG_CRYPTO_DEV_VIRTIO=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC7=y
CONFIG_XZ_DEC=y
+CONFIG_DMA_CMA=y
CONFIG_PRINTK_TIME=y
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
CONFIG_CONSOLE_LOGLEVEL_QUIET=15
--
2.47.0

724
0011-feat-bootspi-Add-bootspi-flash-driver.patch Normal file
View File

@ -0,0 +1,724 @@
From 4f74e928dfa5438e02a55cc907c554e3ada172b0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E2=80=9Chuangyifeng=E2=80=9D?=
<huangyifeng@eswincomputing.com>
Date: Tue, 21 May 2024 10:39:21 +0800
Subject: [PATCH 011/219] feat(bootspi):Add bootspi flash driver
Changelogs:
1.Added bootspi flash driver
---
arch/riscv/configs/win2030_defconfig | 1 +
drivers/spi/Kconfig | 6 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-eswin-bootspi.c | 658 +++++++++++++++++++++++++++
4 files changed, 666 insertions(+)
create mode 100644 drivers/spi/spi-eswin-bootspi.c
diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig
index 725ad2400def..6733030403b9 100644
--- a/arch/riscv/configs/win2030_defconfig
+++ b/arch/riscv/configs/win2030_defconfig
@@ -139,6 +139,7 @@ CONFIG_SPI=y
CONFIG_SPI_DESIGNWARE=y
CONFIG_SPI_DW_DMA=y
CONFIG_SPI_DW_MMIO=y
+CONFIG_SPI_ESWIN_BOOTSPI=y
# CONFIG_PTP_1588_CLOCK is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_EIC7700=y
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 3ce0fd5df8e9..07e874de0ebf 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -360,6 +360,12 @@ config SPI_EP93XX
This enables using the Cirrus EP93xx SPI controller in master
mode.
+config SPI_ESWIN_BOOTSPI
+ tristate "Eswin Computing Boot SPI controller"
+ help
+ This enables using the Eswin Computing Boot SPI controller in master
+ mode.
+
config SPI_FALCON
bool "Falcon SPI controller support"
depends on SOC_FALCON
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 6af54842b9fa..dc4c98c2dd90 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_SPI_DW_BT1) += spi-dw-bt1.o
obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o
obj-$(CONFIG_SPI_DW_PCI) += spi-dw-pci.o
obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o
+obj-$(CONFIG_SPI_ESWIN_BOOTSPI) += spi-eswin-bootspi.o
obj-$(CONFIG_SPI_FALCON) += spi-falcon.o
obj-$(CONFIG_SPI_FSI) += spi-fsi.o
obj-$(CONFIG_SPI_FSL_CPM) += spi-fsl-cpm.o
diff --git a/drivers/spi/spi-eswin-bootspi.c b/drivers/spi/spi-eswin-bootspi.c
new file mode 100644
index 000000000000..c8fbc1b3fc91
--- /dev/null
+++ b/drivers/spi/spi-eswin-bootspi.c
@@ -0,0 +1,658 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ESWIN BootSpi Driver
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Authors: HuangYiFeng<huangyifeng@eswincomputing.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <linux/bitfield.h>
+#include <linux/interrupt.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi-mem.h>
+#include <linux/mtd/spi-nor.h>
+
+/* Register offsets */
+#define ES_SPI_CSR_00 0x00 /*WRITE_STATUS_REG_TIME*/
+#define ES_SPI_CSR_01 0x04 /*SPI_BUS_MODE*/
+#define ES_SPI_CSR_02 0x08 /*ERASE_COUNTER_TAP*/
+#define ES_SPI_CSR_03 0x0c /*DMA_EN_HCLK_STATUS*/
+#define ES_SPI_CSR_04 0x10 /*FAST_READ_CONTROL*/
+#define ES_SPI_CSR_05 0x14 /*SPI_FLASH_WR_NUM*/
+#define ES_SPI_CSR_06 0x18 /*SPI_FLASH_COMMAND*/
+#define ES_SPI_CSR_07 0x1c /*INTERRUPT_CONTROL*/
+#define ES_SPI_CSR_08 0x20 /*DMA_REQUEST_TAP*/
+#define ES_SPI_CSR_09 0x24 /*SPI_FLASH_WR_ADDRESS*/
+#define ES_SPI_CSR_10 0x28 /*PAGE_PROGRAM_TIME*/
+#define ES_SPI_CSR_11 0x2c /*SECTOR_ERASE_TIME*/
+#define ES_SPI_CSR_12 0x30 /*SMALL_BLOCK_ERASE_TIME*/
+#define ES_SPI_CSR_13 0x34 /*LARGE_BLOCK_ERASE_TIME*/
+#define ES_SPI_CSR_14 0x38 /*CHIP_ERASE_TIME*/
+#define ES_SPI_CSR_15 0x3c /*CHIP_DESELECT_TIME*/
+#define ES_SPI_CSR_16 0x40 /*POWER_DOWN_TIME*/
+
+#define ES_SYSCSR_SPIMODECFG 0x340
+
+#define ES_CONCSR_SPI_INTSEL 0x3c0
+
+#define SPI_COMMAND_VALID 0x01
+#define SPI_COMMAND_MOVE_VALUE 0x00
+#define SPI_COMMAND_CODE_FIELD_POSITION 0X06
+#define SPI_COMMAND_MOVE_FIELD_POSITION 0X05
+#define SPI_COMMAND_TYPE_FIELD_POSITION 0X01
+
+/* Bit fields in CTRLR0 */
+/*
+ * Only present when SSI_MAX_XFER_SIZE=16. This is the default, and the only
+ * option before version 3.23a.
+ */
+#define SPI_INTSEL_MASK GENMASK(11, 10)
+#define INT_ROUTED_U84 0x0
+#define INT_ROUTED_LPCPU 0x1
+#define INT_ROUTED_SCPU 0x3u
+
+#define RX_TIMEOUT 5000 /* timeout in ms */
+
+#define SPI_COMMAND_INIT_VALUE 0XFFFFC000
+#define FLASH_PAGE_SIZE 0x100
+
+typedef enum {
+ SPI_FLASH_WR_BYTE = 1,
+ SPI_FLASH_WR_2BYTE = 2,
+ SPI_FLASH_WR_WORD = 4,
+} SPI_FLASH_WR_NUM_T;
+
+typedef enum {
+ SPI_FAST_READ_DEFAULT = 0,
+ SPI_FAST_READ_ENABLE = 3 /*WHEN SPI QUAD0 OR DUAL MODE*/
+} SPI_FAST_READ_CTL_T;
+
+typedef enum { STANDARD_SPI = 0, DUAL_SPI, QUAD_SPI } SPI_BUS_MODE_T;
+
+typedef enum {
+ SPIC_CMD_TYPE_SPI_PROGRAM = 0,
+ SPIC_CMD_TYPE_WRITE_STATUS_REGISTER,
+ SPIC_CMD_TYPE_READ_STATUS_REGISTER,
+ SPIC_CMD_TYPE_SECTOR_ERASE,
+ SPIC_CMD_TYPE_BLOCK_ERASE_TYPE1,
+ SPIC_CMD_TYPE_BLOCK_ERASE_TYPE2,
+ SPIC_CMD_TYPE_CHIP_ERASE,
+ SPIC_CMD_TYPE_POWER_DOWN,
+ SPIC_CMD_TYPE_RELEASE_POWER_DOWM,
+ SPIC_CMD_TYPE_ENTER_OR_EXIT_32BIT_MODE,
+ SPIC_CMD_TYPE_READ_SECURITY_REG,
+ SPIC_CMD_TYPE_ERASE_SECURITY_REG,
+ SPIC_CMD_TYPE_WRITE_SECURITY_REG,
+ SPIC_CMD_TYPE_READ_DATA,
+ SPIC_CMD_TYPE_READ_MANUFACTURED_ID,
+ SPIC_CMD_TYPE_READ_JEDEC_ID
+} SPI_FLASH_COMMAND_TYPE_T;
+
+#define SPIC_CMD_CODE_POWER_DOWN 0xb9
+#define SPIC_CMD_CODE_RELEASE_POWER_DOWN 0xab
+#define SPIC_CMD_CODE_ENABLE_RESET 0x66
+#define SPIC_CMD_CODE_RESET 0x99
+
+struct es_spi_priv {
+ struct clk *cfg_clk;
+ struct clk *clk;
+ struct reset_control *rstc;
+ struct gpio_desc *cs_gpio; /* External chip-select gpio */
+
+ void __iomem *regs;
+ void __iomem *sys_regs;
+ void __iomem *flash_base;
+ unsigned int freq; /* Default frequency */
+ unsigned int mode;
+
+ const void *tx;
+ u32 opcode;
+ u32 cmd_type;
+ u64 addr;
+ void *rx;
+ u32 fifo_len; /* depth of the FIFO buffer */
+ u32 max_xfer; /* Maximum transfer size (in bits) */
+
+ int bits_per_word;
+ int len;
+ u8 cs; /* chip select pin */
+ u8 tmode; /* TR/TO/RO/EEPROM */
+ u8 type; /* SPI/SSP/MicroWire */
+ struct spi_controller *master;
+ struct device *dev;
+ int irq;
+};
+
+static inline u32 eswin_bootspi_read(struct es_spi_priv *priv, u32 offset)
+{
+ return readl(priv->regs + offset);
+}
+
+static inline void eswin_bootspi_write(struct es_spi_priv *priv, u32 offset, u32 val)
+{
+ writel(val, priv->regs + offset);
+}
+
+static inline u32 eswin_bootspi_data_read(struct es_spi_priv *priv, u32 offset)
+{
+ return readl(priv->flash_base + offset);
+}
+
+static inline void eswin_bootspi_data_write(struct es_spi_priv *priv, u32 offset, u32 val)
+{
+ writel(val, priv->flash_base + offset);
+}
+
+static int eswin_bootspi_wait_over(struct es_spi_priv *priv)
+{
+ u32 val;
+ struct device *dev = priv->dev;
+
+ if (readl_poll_timeout(priv->regs + ES_SPI_CSR_06, val,
+ (!(val & 0x1)), 10, RX_TIMEOUT * 1000)) {
+ dev_err(dev, "eswin_bootspi_wait_over : timeout!!\n");
+ return -ETIMEDOUT;
+ }
+ return 0;
+}
+
+/**
+ * @brief spi read and write cfg
+ */
+static void eswin_bootspi_read_write_cfg(struct es_spi_priv *priv, u32 byte, u32 addr)
+{
+ eswin_bootspi_write(priv, ES_SPI_CSR_09, addr);
+ eswin_bootspi_write(priv, ES_SPI_CSR_05, byte);
+ eswin_bootspi_write(priv, ES_SPI_CSR_04, SPI_FAST_READ_DEFAULT);
+ eswin_bootspi_write(priv, ES_SPI_CSR_01, STANDARD_SPI);
+}
+
+/**
+ * @brief write data from dest address to flash
+ */
+static void eswin_bootspi_send_data(struct es_spi_priv *priv,
+ const u8 *dest, u32 size)
+{
+ u32 offset = 0;
+ u8 *buff = (u8 *)dest;
+ u32 data = 0;
+ int i;
+ struct device *dev = priv->dev;
+
+ dev_dbg(dev,"wrtie spi data\n");
+ while (size >= SPI_FLASH_WR_WORD) {
+ data = (buff[0]) | (buff[1] << 8) |(buff[2] << 16) | (buff[3] << 24);
+ for (i = 0; i < 4; i++) {
+ dev_dbg(dev,"0x%x ", buff[i]);
+ }
+ dev_dbg(dev,"0x%x ", data);
+ eswin_bootspi_data_write(priv, offset, data);
+ offset = offset + SPI_FLASH_WR_WORD;
+ size = size - SPI_FLASH_WR_WORD;
+ buff = buff + SPI_FLASH_WR_WORD;
+ }
+ data = 0;
+ if (size != 0) {
+ for (i = 0; i < size; i++) {
+ data |=buff[i] << (8 * i);
+ dev_dbg(dev,"0x%x ", buff[i]);
+ }
+ dev_dbg(dev,"0x%x ", data);
+ eswin_bootspi_data_write(priv, offset, data);
+ }
+}
+
+/**
+ * @brief Read data from flash to dest address
+ */
+static void eswin_bootspi_recv_data(struct es_spi_priv *priv, u8 *dest, u32 size)
+{
+ u32 offset = 0;
+ u8 *buff = NULL;
+ u32 data = 0xFFFFFFFF;
+ int i;
+ struct device *dev = priv->dev;
+
+ dev_dbg(dev,"read spi data\n");
+ while (size >= SPI_FLASH_WR_WORD) {
+ buff = (u8 *)dest;
+ data = eswin_bootspi_data_read(priv, offset);
+ dev_dbg(dev,"0x%x ", data);
+ for (i = 0; i < SPI_FLASH_WR_WORD; i++) {
+ *buff = (u8)(data >> (8 * i));
+ dev_dbg(dev,"0x%x ", *buff);
+ buff++;
+ }
+ dest = dest + SPI_FLASH_WR_WORD;
+ offset = offset + SPI_FLASH_WR_WORD;
+ size = size - SPI_FLASH_WR_WORD;
+ }
+ if (size != 0) {
+ buff = (u8 *)dest;
+ data = eswin_bootspi_data_read(priv, offset);
+ for (i = 0; i < size; i++) {
+ *buff = (u8)(data >> (8 * i));
+ dev_dbg(dev,"0x%x ", *buff);
+ buff++;
+ }
+ }
+ dev_dbg(dev,"\n");
+}
+
+
+/**
+ * @brief spi send command
+ */
+static void eswin_bootspi_cmd_cfg(struct es_spi_priv *priv, u32 code, u32 type)
+{
+ u32 command = eswin_bootspi_read(priv, ES_SPI_CSR_06);
+ struct device *dev = priv->dev;
+
+ command &= ~((0xFF << 6) | (0x1 << 5) | (0xF << 1) | 0x1);
+ command |= ((code << SPI_COMMAND_CODE_FIELD_POSITION) |
+ (SPI_COMMAND_MOVE_VALUE << SPI_COMMAND_MOVE_FIELD_POSITION) |
+ (type << SPI_COMMAND_TYPE_FIELD_POSITION) | SPI_COMMAND_VALID);
+
+ eswin_bootspi_write(priv, ES_SPI_CSR_06, command);
+ dev_dbg(dev, "[%s %d]: write command 0x%x, read back command 0x%x\n",
+ __func__,__LINE__, command, eswin_bootspi_read(priv, ES_SPI_CSR_06));
+}
+/**
+ * @brief spi write flash
+ * @param [in] offset: address of flash to be write
+ * @param [in] wr_dest: Address of data to be sent
+ * @param [in] size: size of flash to be write
+ */
+void eswin_bootspi_writer(struct es_spi_priv *priv)
+{
+ u32 write_size = 0, offset, cmd_code;
+ u32 cmd_type = priv->cmd_type;
+ const u8 *wr_dest = priv->tx;
+ int size = priv->len;
+
+ offset = priv->addr;
+ cmd_code = priv->opcode;
+
+ if (size == 0) {
+ // if(SPIC_CMD_TYPE_SECTOR_ERASE == cmd_type)
+ {
+ eswin_bootspi_read_write_cfg(priv, write_size, offset);
+ eswin_bootspi_cmd_cfg(priv, cmd_code, cmd_type);
+ eswin_bootspi_wait_over(priv);
+ }
+ }
+ while (size > 0) {
+ write_size = size;
+ if (write_size > FLASH_PAGE_SIZE) {
+ write_size = FLASH_PAGE_SIZE;
+ }
+ eswin_bootspi_read_write_cfg(priv, write_size, offset);
+ eswin_bootspi_send_data(priv, wr_dest, write_size);
+ eswin_bootspi_cmd_cfg(priv, cmd_code, cmd_type);
+ eswin_bootspi_wait_over(priv);
+ wr_dest += write_size;
+ offset += write_size;
+ size = size - write_size;
+ }
+}
+
+static void eswin_bootspi_reader(struct es_spi_priv *priv)
+{
+ int read_size = 0;
+ u32 offset = priv->addr;
+ u32 cmd_code = priv->opcode;
+ u32 cmd_type = priv->cmd_type;
+ u8 *mem_dest = priv->rx;
+ int size = priv->len;
+
+ while (size > 0) {
+ read_size = size;
+ if (read_size > FLASH_PAGE_SIZE) {
+ read_size = FLASH_PAGE_SIZE;
+ }
+
+ eswin_bootspi_read_write_cfg(priv, read_size, offset);
+ eswin_bootspi_cmd_cfg(priv, cmd_code, cmd_type);
+ eswin_bootspi_wait_over(priv);
+ eswin_bootspi_recv_data(priv, mem_dest, read_size);
+ mem_dest += read_size;
+ offset += read_size;
+ size = size - read_size;
+ }
+}
+
+/*
+ * We define external_cs_manage function as 'weak' as some targets
+ * (like MSCC Ocelot) don't control the external CS pin using a GPIO
+ * controller. These SoCs use specific registers to control by
+ * software the SPI pins (and especially the CS).
+ */
+
+static void external_cs_manage(struct es_spi_priv *priv, bool on)
+{
+ gpiod_set_value(priv->cs_gpio, on ? 1 : 0);
+}
+
+/* The size of ctrl1 limits data transfers to 64K */
+static int eswin_bootspi_adjust_op_size(struct spi_mem *mem,
+ struct spi_mem_op *op)
+{
+ op->data.nbytes = min(op->data.nbytes, (unsigned int)SZ_64K);
+
+ return 0;
+}
+
+/*
+ * The controller only supports Standard SPI mode, Duall mode and
+ * Quad mode. Double sanitize the ops here to avoid OOB access.
+ */
+static bool eswin_bootspi_supports_op(struct spi_mem *mem,
+ const struct spi_mem_op *op)
+{
+ return spi_mem_default_supports_op(mem, op);
+}
+
+static int eswin_bootspi_exec_op(struct spi_mem *mem,
+ const struct spi_mem_op *op)
+{
+ bool read = op->data.dir == SPI_MEM_DATA_IN;
+ int ret = 0;
+ struct es_spi_priv *priv = spi_master_get_devdata(mem->spi->master);
+ struct device *dev = priv->dev;
+
+ priv->addr = op->addr.val;
+ priv->opcode = op->cmd.opcode;
+
+ dev_dbg(dev, "\n[%s %d]: addr=0x%llx opcode=0x%x\n", __func__,__LINE__,
+ priv->addr, priv->opcode);
+
+ if ( priv->opcode == SPINOR_OP_WREN
+ || priv->opcode == SPINOR_OP_WRDI)
+ return 0;
+
+ switch(priv->opcode) {
+ case SPINOR_OP_RDID:
+ case SPINOR_OP_RDSFDP:
+ priv->cmd_type = SPIC_CMD_TYPE_READ_JEDEC_ID;
+ break;
+ case SPINOR_OP_BE_4K:
+ case SPINOR_OP_BE_4K_PMC:
+ priv->opcode = SPINOR_OP_BE_4K;
+ priv->cmd_type = SPIC_CMD_TYPE_SECTOR_ERASE;
+ break;
+ case SPINOR_OP_BE_32K:
+ priv->cmd_type = SPIC_CMD_TYPE_BLOCK_ERASE_TYPE1;
+ break;
+ case SPINOR_OP_SE:
+ priv->cmd_type = SPIC_CMD_TYPE_BLOCK_ERASE_TYPE2;
+ break;
+ case SPINOR_OP_CHIP_ERASE:
+ priv->cmd_type = SPIC_CMD_TYPE_CHIP_ERASE;
+ break;
+ case SPINOR_OP_PP:
+ case SPINOR_OP_PP_1_1_4:
+ case SPINOR_OP_PP_1_4_4:
+ case SPINOR_OP_PP_1_1_8:
+ case SPINOR_OP_PP_1_8_8:
+ priv->opcode = SPINOR_OP_PP;
+ priv->cmd_type = SPIC_CMD_TYPE_SPI_PROGRAM;
+ break;
+ case SPINOR_OP_READ:
+ case SPINOR_OP_READ_FAST:
+ case SPINOR_OP_READ_1_1_2:
+ case SPINOR_OP_READ_1_2_2:
+ case SPINOR_OP_READ_1_1_4:
+ case SPINOR_OP_READ_1_4_4:
+ case SPINOR_OP_READ_1_1_8:
+ case SPINOR_OP_READ_1_8_8:
+ priv->opcode = SPINOR_OP_READ;
+ priv->cmd_type = SPIC_CMD_TYPE_READ_DATA;
+ break;
+ case SPINOR_OP_RDSR:
+ case SPINOR_OP_RDSR2:
+ priv->cmd_type = SPIC_CMD_TYPE_READ_STATUS_REGISTER;
+ break;
+ case SPINOR_OP_WRSR:
+ case SPINOR_OP_WRSR2:
+ priv->cmd_type = SPIC_CMD_TYPE_WRITE_STATUS_REGISTER;
+ break;
+ case SPIC_CMD_CODE_POWER_DOWN:
+ priv->cmd_type = SPIC_CMD_TYPE_POWER_DOWN;
+ break;
+ case SPIC_CMD_CODE_RELEASE_POWER_DOWN:
+ priv->cmd_type = SPIC_CMD_TYPE_RELEASE_POWER_DOWM;
+ break;
+ case SPIC_CMD_CODE_ENABLE_RESET:
+ case SPIC_CMD_CODE_RESET:
+ priv->cmd_type = SPIC_CMD_TYPE_SPI_PROGRAM;
+ break;
+ default:
+ dev_warn(dev, "[%s %d]: unsupport opcode = 0x%x, return sucess directly!\n",
+ __func__,__LINE__, priv->opcode);
+ return 0;
+ }
+
+ dev_dbg(dev, "[%s %d]: data direction=%d, opcode = 0x%x, cmd_type 0x%x\n",
+ __func__,__LINE__, op->data.dir, priv->opcode, priv->cmd_type);
+ external_cs_manage(priv, false);
+
+ if (read) {
+ priv->rx = op->data.buf.in;
+ priv->len = op->data.nbytes;
+ dev_dbg(dev, "[%s %d]: read len = %u\n", __func__,__LINE__, op->data.nbytes);
+ eswin_bootspi_reader(priv);
+ } else {
+ priv->tx = op->data.buf.out;
+ priv->len = op->data.nbytes;
+ /* Fill up the write fifo before starting the transfer */
+ dev_dbg(dev, "[%s %d]: write len = 0x%x tx_addr 0x%px\n", __func__,__LINE__,
+ op->data.nbytes, priv->tx);
+ eswin_bootspi_writer(priv);
+ if (eswin_bootspi_wait_over(priv) < 0) {
+ dev_err(dev, "eswin_bootspi_wait_over ETIMEDOUT\n");
+ ret = -ETIMEDOUT;
+ }
+ }
+ external_cs_manage(priv, true);
+ dev_dbg(dev, "%u bytes xfered\n", op->data.nbytes);
+ return ret;
+}
+
+static const struct spi_controller_mem_ops eswin_bootspi_mem_ops = {
+ .adjust_op_size = eswin_bootspi_adjust_op_size,
+ .supports_op = eswin_bootspi_supports_op,
+ .exec_op = eswin_bootspi_exec_op,
+};
+
+static int eswin_bootspi_setup(struct spi_device *spi)
+{
+ struct es_spi_priv *priv = spi_master_get_devdata(spi->master);
+ struct device *dev = priv->dev;
+ int vaule = 0;
+ int ret;
+
+ ret = clk_prepare_enable(priv->cfg_clk);
+ if (ret) {
+ dev_err(dev, "could not enable cfg clock: %d\n", ret);
+ goto err_cfg_clk;
+ }
+
+ ret = clk_prepare_enable(priv->clk);
+ if (ret) {
+ dev_err(dev, "could not enable clock: %d\n", ret);
+ goto err_clk;
+ }
+ /* set rate to 50M*/
+ ret = clk_set_rate(priv->clk, 50000000);
+ if (ret) {
+ dev_err(dev, "could not enable clock: %d\n", ret);
+ goto err_clk;
+ }
+
+ reset_control_deassert(priv->rstc);
+
+ /* switch bootspi to cpu mode*/
+ vaule = readl(priv->sys_regs + ES_SYSCSR_SPIMODECFG);
+ vaule |= 0x1;
+ writel(vaule, priv->sys_regs + ES_SYSCSR_SPIMODECFG);
+
+ /* Basic HW init */
+ eswin_bootspi_write(priv, ES_SPI_CSR_08, 0x0);
+ return ret;
+
+err_clk:
+ clk_disable(priv->cfg_clk);
+err_cfg_clk:
+ return ret;
+}
+
+static int eswin_bootspi_probe(struct platform_device *pdev)
+{
+ struct es_spi_priv *priv;
+ struct spi_controller *master;
+ int ret = 0;
+ struct device *dev = &pdev->dev;
+
+ master = spi_alloc_master(&pdev->dev, sizeof(*priv));
+ if (!master)
+ return -ENOMEM;
+
+ master->mode_bits = SPI_CPOL | SPI_CPHA;
+ master->flags = SPI_MASTER_HALF_DUPLEX;
+ master->setup = eswin_bootspi_setup;
+ master->dev.of_node = pdev->dev.of_node;
+ master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
+ SPI_BPW_MASK(8);
+ master->mem_ops = &eswin_bootspi_mem_ops;
+ master->num_chipselect = 1;
+
+ priv = spi_master_get_devdata(master);
+ priv->master = master;
+ priv->dev = &pdev->dev;
+ platform_set_drvdata(pdev, priv);
+
+ priv->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->regs)) {
+ dev_err(dev, "%s %d: failed to map registers\n", __func__,__LINE__);
+ return PTR_ERR(priv->regs);
+ }
+
+ priv->sys_regs = devm_platform_ioremap_resource(pdev, 1);
+ if (IS_ERR(priv->sys_regs)) {
+ dev_err(dev,"%s %d: failed to map sys registers\n", __func__, __LINE__);
+ return PTR_ERR(priv->sys_regs);
+ }
+
+ priv->flash_base = devm_platform_ioremap_resource(pdev, 2);
+ if (IS_ERR(priv->flash_base)) {
+ dev_err(dev,"%s %d: failed to map sys registers\n", __func__, __LINE__);
+ return PTR_ERR(priv->flash_base);
+ }
+
+ priv->cfg_clk = devm_clk_get(dev, "cfg_clk");
+ if (IS_ERR(priv->cfg_clk)) {
+ dev_err(dev, "%s %d:could not get cfg clk: %ld\n", __func__,__LINE__,
+ PTR_ERR(priv->cfg_clk));
+ return PTR_ERR(priv->cfg_clk);
+ }
+
+ priv->clk = devm_clk_get(dev, "clk");
+ if (IS_ERR(priv->clk)) {
+ dev_err(dev, "%s %d:could not get clk: %ld\n",__func__,__LINE__, PTR_ERR(priv->rstc));
+ return PTR_ERR(priv->clk);
+ }
+ priv->rstc = devm_reset_control_get_optional_exclusive(dev, "rst");
+ if (IS_ERR(priv->rstc)) {
+ dev_err(dev, "%s %d:could not get rst: %ld\n", __func__,__LINE__, PTR_ERR(priv->rstc));
+ return PTR_ERR(priv->rstc);
+ }
+
+ priv->cs_gpio = devm_gpiod_get(dev, "cs", GPIOD_OUT_LOW);
+ if (IS_ERR(priv->cs_gpio)) {
+ dev_err(dev, "%s %d: couldn't request gpio! (error %ld)\n", __func__,__LINE__,
+ PTR_ERR(priv->cs_gpio));
+ return PTR_ERR(priv->cs_gpio);
+ }
+
+ priv->max_xfer = 32;
+ dev_info(dev, "ssi_max_xfer_size=%u\n", priv->max_xfer);
+
+ /* Currently only bits_per_word == 8 supported */
+ priv->bits_per_word = 8;
+ priv->tmode = 0; /* Tx & Rx */
+
+ if (!priv->fifo_len) {
+ priv->fifo_len = 256;
+ }
+ ret = devm_spi_register_controller(dev, master);
+ if (ret)
+ goto err_put_master;
+
+ dev_info(&pdev->dev, "fifo_len %d, %s mode.\n", priv->fifo_len, priv->irq ? "irq" : "polling");
+ return 0;
+
+err_put_master:
+ spi_master_put(master);
+ return ret;
+}
+
+static int eswin_bootspi_remove(struct platform_device *pdev)
+{
+ struct es_spi_priv *priv = platform_get_drvdata(pdev);
+ struct spi_controller *master = priv->master;
+
+ spi_master_put(master);
+ return 0;
+}
+
+static const struct of_device_id eswin_bootspi_of_match[] = {
+ { .compatible = "eswin,bootspi", .data = NULL},
+ { /* end of table */}
+};
+MODULE_DEVICE_TABLE(of, eswin_bootspi_of_match);
+
+#ifdef CONFIG_ACPI
+static const struct acpi_device_id eswin_bootspi_acpi_match[] = {
+ {"eswin,bootspi", 0},
+ {}
+};
+MODULE_DEVICE_TABLE(acpi, eswin_bootspi_acpi_match);
+#endif
+
+static struct platform_driver eswin_bootspi_driver = {
+ .probe = eswin_bootspi_probe,
+ .remove = eswin_bootspi_remove,
+ .driver = {
+ .name = "eswin-bootspi",
+ .of_match_table = eswin_bootspi_of_match,
+#ifdef CONFIG_ACPI
+ .acpi_match_table = eswin_bootspi_acpi_match,
+#endif
+ },
+};
+module_platform_driver(eswin_bootspi_driver);
+
+MODULE_AUTHOR("Huangyifeng <huangyifeng@eswincomputing.com>");
+MODULE_DESCRIPTION("Eswin Boot SPI Controller Driver for EIC770X SoCs");
+MODULE_LICENSE("GPL v2");
--
2.47.0

7181
0012-feat-noc-Add-noc-driver.patch Normal file
View File

File diff suppressed because it is too large Load Diff

18485
0013-feat-Add-VO-support-for-linux-6.6.patch Normal file
View File

File diff suppressed because it is too large Load Diff

2898
0014-feat-Add-emmc-and-sdio-driver.patch Normal file
View File

File diff suppressed because it is too large Load Diff

39
0015-fix-vo-add-dma-noncoherent-for-video-ouput-device.patch Normal file
View File

@ -0,0 +1,39 @@
From c8de99e0a4027fb6bb79287b117ebc562316bf79 Mon Sep 17 00:00:00 2001
From: fanglifei <fanglifei@eswincomputing.com>
Date: Thu, 23 May 2024 13:14:03 +0800
Subject: [PATCH 015/219] fix(vo): add dma-noncoherent for video ouput device
Changelogs:
1. Fix display corruption by adding dma-noncoherent dts proporty
---
arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi | 1 +
arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
index 453f15acbd15..1e813abf0819 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
@@ -1739,6 +1739,7 @@ d0_graphcard2: graphcard2 {
video_output: display-subsystem {
compatible = "eswin,display-subsystem";
ports = <&dc_out>;
+ dma-noncoherent;
};
dvb_widgets: dvb-subsystem {
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
index b1b077ceea0e..5a55de6c7b2a 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
@@ -1647,6 +1647,7 @@ d1_spi_demo: spi-demo@0 {
d1_video_output: display-subsystem {
compatible = "eswin,display-subsystem";
ports = <&d1_dc_out>;
+ dma-noncoherent;
};
d1_dc: display_control@702c0000 {
--
2.47.0

725
0016-feat-support-eswin-dwc3-usb.patch Normal file
View File

@ -0,0 +1,725 @@
From f97c43667b3a178ef9d350ed5d62ef224eab1fc8 Mon Sep 17 00:00:00 2001
From: yangwei1 <yangwei1@eswincomputing.com>
Date: Wed, 22 May 2024 20:20:01 +0800
Subject: [PATCH 016/219] feat:support eswin dwc3 usb
Changelogs:
---
drivers/usb/dwc3/Kconfig | 9 +
drivers/usb/dwc3/Makefile | 1 +
drivers/usb/dwc3/dwc3-eswin.c | 671 ++++++++++++++++++++++++++++++++++
3 files changed, 681 insertions(+)
create mode 100755 drivers/usb/dwc3/dwc3-eswin.c
diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index 98efcbb76c88..3571543e8348 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -118,6 +118,15 @@ config USB_DWC3_OF_SIMPLE
Currently supports Xilinx and Qualcomm DWC USB3 IP.
Say 'Y' or 'M' if you have one such device.
+config USB_DWC3_ESWIN
+ tristate "Eswin Platforms"
+ depends on OF
+ depends on USB=y || USB=USB_DWC3
+ default USB_DWC3
+ help
+ Support of USB2/3 functionality in Eswin platforms.
+ say 'Y' or 'M' if you have one such device.
+
config USB_DWC3_ST
tristate "STMicroelectronics Platforms"
depends on (ARCH_STI || COMPILE_TEST) && OF
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
index fe1493d4bbe5..946f9a2b7819 100644
--- a/drivers/usb/dwc3/Makefile
+++ b/drivers/usb/dwc3/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_USB_DWC3_HAPS) += dwc3-haps.o
obj-$(CONFIG_USB_DWC3_KEYSTONE) += dwc3-keystone.o
obj-$(CONFIG_USB_DWC3_MESON_G12A) += dwc3-meson-g12a.o
obj-$(CONFIG_USB_DWC3_OF_SIMPLE) += dwc3-of-simple.o
+obj-$(CONFIG_USB_DWC3_ESWIN) += dwc3-eswin.o
obj-$(CONFIG_USB_DWC3_ST) += dwc3-st.o
obj-$(CONFIG_USB_DWC3_QCOM) += dwc3-qcom.o
obj-$(CONFIG_USB_DWC3_IMX8MP) += dwc3-imx8mp.o
diff --git a/drivers/usb/dwc3/dwc3-eswin.c b/drivers/usb/dwc3/dwc3-eswin.c
new file mode 100755
index 000000000000..1769d9a7ff5f
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-eswin.c
@@ -0,0 +1,671 @@
+
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * eswin Specific Glue layer
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Authors: Han Min <hanmin@eswincomputing.com>
+ */
+
+#include <linux/async.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/pm_runtime.h>
+#include <linux/extcon.h>
+#include <linux/freezer.h>
+#include <linux/iopoll.h>
+#include <linux/reset.h>
+#include <linux/usb.h>
+#include <linux/pm.h>
+#include <linux/usb/hcd.h>
+#include <linux/usb/ch9.h>
+#include <linux/extcon-provider.h>
+#include <linux/iommu.h>
+#include <linux/mfd/syscon.h>
+#include <linux/bitfield.h>
+#include <linux/eswin-win2030-sid-cfg.h>
+#include <linux/regmap.h>
+#include <linux/gpio/consumer.h>
+#include "core.h"
+#include "io.h"
+
+
+#define dwc3_eswin_AUTOSUSPEND_DELAY 500 /* ms */
+#define PERIPHERAL_DISCONNECT_TIMEOUT 1000000 /* us */
+#define WAIT_FOR_HCD_READY_TIMEOUT 5000000 /* us */
+#define XHCI_TSTCTRL_MASK (0xf << 28)
+
+#define AWSMMUSID GENMASK(31, 24) // The sid of write operation
+#define AWSMMUSSID GENMASK(23, 16) // The ssid of write operation
+#define ARSMMUSID GENMASK(15, 8) // The sid of read operation
+#define ARSMMUSSID GENMASK(7, 0) // The ssid of read operation
+
+#define HSP_USB_VBUS_FSEL 0x2a
+#define HSP_USB_MPLL_DEFAULT 0x0
+
+#define HSP_USB_BUS_FILTER_EN (0x1 << 0)
+#define HSP_USB_BUS_CLKEN_GM (0x1 << 9)
+#define HSP_USB_BUS_CLKEN_GS (0x1 << 16)
+#define HSP_USB_BUS_SW_RST (0x1 << 24)
+#define HSP_USB_BUS_CLK_EN (0x1 << 28)
+
+#define HSP_USB_AXI_LP_XM_CSYSREQ (0x1 << 0)
+#define HSP_USB_AXI_LP_XS_CSYSREQ (0x1 << 16)
+
+struct dwc3_eswin {
+ int num_clocks;
+ bool connected;
+ bool skip_suspend;
+ bool suspended;
+ bool force_mode;
+ bool is_phy_on;
+ struct device *dev;
+ struct clk **clks;
+ struct dwc3 *dwc;
+ struct reset_control *otg_rst;
+ struct extcon_dev *edev;
+ struct usb_hcd *hcd;
+ struct notifier_block device_nb;
+ struct notifier_block host_nb;
+ struct work_struct otg_work;
+ struct mutex lock;
+ struct reset_control *vaux_rst;
+ struct device *child_dev;
+ enum usb_role new_usb_role;
+};
+
+static ssize_t dwc3_mode_show(struct device *device,
+ struct device_attribute *attr, char *buf)
+{
+ struct dwc3_eswin *eswin = dev_get_drvdata(device);
+ struct dwc3 *dwc = eswin->dwc;
+ int ret;
+
+ switch (dwc->current_dr_role) {
+ case USB_DR_MODE_HOST:
+ ret = sprintf(buf, "host\n");
+ break;
+ case USB_DR_MODE_PERIPHERAL:
+ ret = sprintf(buf, "peripheral\n");
+ break;
+ case USB_DR_MODE_OTG:
+ ret = sprintf(buf, "otg\n");
+ break;
+ default:
+ ret = sprintf(buf, "UNKNOWN\n");
+ }
+
+ return ret;
+}
+
+static ssize_t dwc3_mode_store(struct device *device,
+ struct device_attribute *attr, const char *buf,
+ size_t count)
+{
+ struct dwc3_eswin *eswin = dev_get_drvdata(device);
+ struct dwc3 *dwc = eswin->dwc;
+ enum usb_role new_role;
+ struct usb_role_switch *role_sw = dwc->role_sw;
+
+ if (!strncmp(buf, "1", 1) || !strncmp(buf, "host", 4)) {
+ new_role = USB_ROLE_HOST;
+ } else if (!strncmp(buf, "0", 1) || !strncmp(buf, "peripheral", 10)) {
+ new_role = USB_ROLE_DEVICE;
+ } else {
+ dev_info(eswin->dev, "illegal dr_mode\n");
+ return count;
+ }
+ eswin->force_mode = true;
+
+ mutex_lock(&eswin->lock);
+ usb_role_switch_set_role(role_sw, new_role);
+ mutex_unlock(&eswin->lock);
+
+ return count;
+}
+
+static DEVICE_ATTR_RW(dwc3_mode);
+
+static struct attribute *dwc3_eswin_attrs[] = {
+ &dev_attr_dwc3_mode.attr,
+ NULL,
+};
+
+static struct attribute_group dwc3_eswin_attr_group = {
+ .name = NULL, /* we want them in the same directory */
+ .attrs = dwc3_eswin_attrs,
+};
+
+static int dwc3_eswin_device_notifier(struct notifier_block *nb,
+ unsigned long event, void *ptr)
+{
+ struct dwc3_eswin *eswin =
+ container_of(nb, struct dwc3_eswin, device_nb);
+
+ mutex_lock(&eswin->lock);
+ eswin->new_usb_role = USB_ROLE_DEVICE;
+ mutex_unlock(&eswin->lock);
+ if (!eswin->suspended)
+ schedule_work(&eswin->otg_work);
+
+ return NOTIFY_DONE;
+}
+
+static int dwc3_eswin_host_notifier(struct notifier_block *nb,
+ unsigned long event, void *ptr)
+{
+ struct dwc3_eswin *eswin = container_of(nb, struct dwc3_eswin, host_nb);
+ mutex_lock(&eswin->lock);
+ eswin->new_usb_role = USB_ROLE_HOST;
+ mutex_unlock(&eswin->lock);
+ if (!eswin->suspended)
+ schedule_work(&eswin->otg_work);
+
+ return NOTIFY_DONE;
+}
+
+static void dwc3_eswin_otg_extcon_evt_work(struct work_struct *work)
+{
+ struct dwc3_eswin *eswin =
+ container_of(work, struct dwc3_eswin, otg_work);
+ struct usb_role_switch *role_sw = eswin->dwc->role_sw;
+
+ if (true == eswin->force_mode) {
+ return;
+ }
+ mutex_lock(&eswin->lock);
+ usb_role_switch_set_role(role_sw, eswin->new_usb_role);
+ mutex_unlock(&eswin->lock);
+}
+
+static int dwc3_eswin_get_extcon_dev(struct dwc3_eswin *eswin)
+{
+ struct device *dev = eswin->dev;
+ struct extcon_dev *edev;
+ s32 ret = 0;
+
+ if (device_property_read_bool(dev, "extcon")) {
+ edev = extcon_get_edev_by_phandle(dev, 0);
+ if (IS_ERR(edev)) {
+ if (PTR_ERR(edev) != -EPROBE_DEFER)
+ dev_err(dev, "couldn't get extcon device\n");
+ return PTR_ERR(edev);
+ }
+ eswin->edev = edev;
+ eswin->device_nb.notifier_call = dwc3_eswin_device_notifier;
+ ret = devm_extcon_register_notifier(dev, edev, EXTCON_USB,
+ &eswin->device_nb);
+ if (ret < 0)
+ dev_err(dev, "failed to register notifier for USB\n");
+
+ eswin->host_nb.notifier_call = dwc3_eswin_host_notifier;
+ ret = devm_extcon_register_notifier(dev, edev, EXTCON_USB_HOST,
+ &eswin->host_nb);
+ if (ret < 0)
+ dev_err(dev,
+ "failed to register notifier for USB-HOST\n");
+ }
+
+ return 0;
+}
+
+static int __init dwc3_eswin_deassert(struct dwc3_eswin *eswin)
+{
+ int rc;
+
+ if (eswin->vaux_rst) {
+ rc = reset_control_deassert(eswin->vaux_rst);
+ WARN_ON(0 != rc);
+ }
+
+ return 0;
+}
+
+static int dwc3_eswin_assert(struct dwc3_eswin *eswin)
+{
+ int rc = 0;
+
+ if (eswin->vaux_rst) {
+ rc = reset_control_assert(eswin->vaux_rst);
+ WARN_ON(0 != rc);
+ }
+
+ return 0;
+}
+
+static int dwc_usb_clk_init(struct device *dev)
+{
+ struct regmap *regmap;
+ u32 hsp_usb_bus;
+ u32 hsp_usb_axi_lp;
+ u32 hsp_usb_vbus_freq;
+ u32 hsp_usb_mpll;
+ int ret;
+
+ regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
+ "eswin,hsp_sp_csr");
+ if (IS_ERR(regmap)) {
+ dev_dbg(dev, "No hsp_sp_csr phandle specified\n");
+ return -1;
+ }
+ ret = of_property_read_u32_index(dev->of_node, "eswin,hsp_sp_csr", 1,
+ &hsp_usb_bus);
+ if (ret) {
+ dev_err(dev, "can't get usb sid cfg reg offset (%d)\n", ret);
+ return ret;
+ }
+ ret = of_property_read_u32_index(dev->of_node, "eswin,hsp_sp_csr", 2,
+ &hsp_usb_axi_lp);
+ if (ret) {
+ dev_err(dev, "can't get usb sid cfg reg offset (%d)\n", ret);
+ return ret;
+ }
+ ret = of_property_read_u32_index(dev->of_node, "eswin,hsp_sp_csr", 3,
+ &hsp_usb_vbus_freq);
+ if (ret) {
+ dev_err(dev, "can't get usb sid cfg reg offset (%d)\n", ret);
+ return ret;
+ }
+ ret = of_property_read_u32_index(dev->of_node, "eswin,hsp_sp_csr", 4,
+ &hsp_usb_mpll);
+ if (ret) {
+ dev_err(dev, "can't get usb sid cfg reg offset (%d)\n", ret);
+ return ret;
+ }
+
+ /*
+ * usb1 clock init
+ * ref clock is 24M, below need to be set to satisfy usb phy requirement(125M)
+ */
+ regmap_write(regmap, hsp_usb_vbus_freq, HSP_USB_VBUS_FSEL);
+ regmap_write(regmap, hsp_usb_mpll, HSP_USB_MPLL_DEFAULT);
+ /*
+ * reset usb core and usb phy
+ */
+ regmap_write(regmap, hsp_usb_bus,
+ HSP_USB_BUS_FILTER_EN | HSP_USB_BUS_CLKEN_GM |
+ HSP_USB_BUS_CLKEN_GS | HSP_USB_BUS_SW_RST |
+ HSP_USB_BUS_CLK_EN);
+ regmap_write(regmap, hsp_usb_axi_lp,
+ HSP_USB_AXI_LP_XM_CSYSREQ | HSP_USB_AXI_LP_XS_CSYSREQ);
+
+ return 0;
+}
+
+int dwc3_sid_cfg(struct device *dev)
+{
+ int ret;
+ struct regmap *regmap;
+ int hsp_mmu_usb_reg;
+ u32 rdwr_sid_ssid;
+ u32 sid;
+ struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
+
+ /* not behind smmu, use the default reset value(0x0) of the reg as streamID*/
+ if (fwspec == NULL) {
+ dev_dbg(dev,
+ "dev is not behind smmu, skip configuration of sid\n");
+ return 0;
+ }
+ sid = fwspec->ids[0];
+
+ regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
+ "eswin,hsp_sp_csr");
+ if (IS_ERR(regmap)) {
+ dev_dbg(dev, "No hsp_sp_csr phandle specified\n");
+ return 0;
+ }
+
+ ret = of_property_read_u32_index(dev->of_node, "eswin,hsp_sp_csr", 1,
+ &hsp_mmu_usb_reg);
+ if (ret) {
+ dev_err(dev, "can't get usb sid cfg reg offset (%d)\n", ret);
+ return ret;
+ }
+
+ /* make the reading sid the same as writing sid, ssid is fixed to zero */
+ rdwr_sid_ssid = FIELD_PREP(AWSMMUSID, sid);
+ rdwr_sid_ssid |= FIELD_PREP(ARSMMUSID, sid);
+ rdwr_sid_ssid |= FIELD_PREP(AWSMMUSSID, 0);
+ rdwr_sid_ssid |= FIELD_PREP(ARSMMUSSID, 0);
+ regmap_write(regmap, hsp_mmu_usb_reg, rdwr_sid_ssid);
+
+ ret = win2030_dynm_sid_enable(dev_to_node(dev));
+ if (ret < 0) {
+ dev_err(dev, "failed to config usb streamID(%d)!\n", sid);
+ } else {
+ dev_dbg(dev, "success to config usb streamID(%d)!\n", sid);
+ }
+
+ return ret;
+}
+
+static int dwc3_eswin_probe(struct platform_device *pdev)
+{
+ struct dwc3_eswin *eswin;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node, *child;
+ struct platform_device *child_pdev;
+ unsigned int count;
+ int ret;
+ int i;
+ int err_desc = 0;
+ struct gpio_desc *hub_gpio;
+
+ hub_gpio = devm_gpiod_get(dev, "hub-rst", GPIOD_OUT_HIGH);
+ err_desc = IS_ERR(hub_gpio);
+
+ if (!err_desc) {
+ gpiod_set_raw_value(hub_gpio, 1);
+ }
+
+ eswin = devm_kzalloc(dev, sizeof(*eswin), GFP_KERNEL);
+ if (!eswin)
+ return -ENOMEM;
+
+ count = of_clk_get_parent_count(np);
+ if (!count)
+ return -ENOENT;
+
+ eswin->num_clocks = count;
+ eswin->force_mode = false;
+ eswin->clks = devm_kcalloc(dev, eswin->num_clocks, sizeof(struct clk *),
+ GFP_KERNEL);
+ if (!eswin->clks)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, eswin);
+
+ mutex_init(&eswin->lock);
+
+ eswin->dev = dev;
+
+ mutex_lock(&eswin->lock);
+
+ for (i = 0; i < eswin->num_clocks; i++) {
+ struct clk *clk;
+ clk = of_clk_get(np, i);
+ if (IS_ERR(clk)) {
+ ret = PTR_ERR(clk);
+ goto err0;
+ }
+ ret = clk_prepare_enable(clk);
+ if (ret < 0) {
+ clk_put(clk);
+ goto err0;
+ }
+
+ eswin->clks[i] = clk;
+ }
+
+ eswin->vaux_rst = devm_reset_control_get(dev, "vaux");
+ if (IS_ERR_OR_NULL(eswin->vaux_rst)) {
+ dev_err(dev, "Failed to asic0_rst handle\n");
+ return -EFAULT;
+ }
+
+ dwc3_eswin_deassert(eswin);
+ dwc_usb_clk_init(dev);
+
+ pm_runtime_set_active(dev);
+ pm_runtime_enable(dev);
+ ret = pm_runtime_get_sync(dev);
+ if (ret < 0) {
+ dev_err(dev, "get_sync failed with err %d\n", ret);
+ goto err1;
+ }
+
+ child = of_get_child_by_name(np, "dwc3");
+ if (!child) {
+ dev_err(dev, "failed to find dwc3 core node\n");
+ ret = -ENODEV;
+ goto err1;
+ }
+ /* Allocate and initialize the core */
+ ret = of_platform_populate(np, NULL, NULL, dev);
+ if (ret) {
+ dev_err(dev, "failed to create dwc3 core\n");
+ goto err1;
+ }
+
+ INIT_WORK(&eswin->otg_work, dwc3_eswin_otg_extcon_evt_work);
+ child_pdev = of_find_device_by_node(child);
+ if (!child_pdev) {
+ dev_err(dev, "failed to find dwc3 core device\n");
+ ret = -ENODEV;
+ goto err2;
+ }
+ eswin->dwc = platform_get_drvdata(child_pdev);
+ if (!eswin->dwc) {
+ dev_err(dev, "failed to get drvdata dwc3\n");
+ ret = -EPROBE_DEFER;
+ goto err2;
+ }
+ eswin->child_dev = &child_pdev->dev;
+ ret = win2030_tbu_power(eswin->child_dev, true);
+ if (ret) {
+ dev_err(dev, "tbu power on failed %d\n", ret);
+ goto err2;
+ }
+ ret = dwc3_sid_cfg(&child_pdev->dev);
+ if (ret)
+ goto err3;
+ ret = dwc3_eswin_get_extcon_dev(eswin);
+ if (ret < 0)
+ goto err3;
+
+ mutex_unlock(&eswin->lock);
+ ret = sysfs_create_group(&dev->kobj, &dwc3_eswin_attr_group);
+ if (ret)
+ dev_err(dev, "failed to create sysfs group: %d\n", ret);
+
+ return ret;
+err3:
+ ret = win2030_tbu_power(eswin->child_dev, false);
+ if (ret) {
+ dev_err(dev, "tbu power2 off failed %d\n", ret);
+ }
+err2:
+ cancel_work_sync(&eswin->otg_work);
+ of_platform_depopulate(dev);
+
+err1:
+ pm_runtime_put_sync(dev);
+ pm_runtime_disable(dev);
+ dwc3_eswin_assert(eswin);
+err0:
+ for (i = 0; i < eswin->num_clocks && eswin->clks[i]; i++) {
+ if (!pm_runtime_status_suspended(dev))
+ clk_disable(eswin->clks[i]);
+ clk_unprepare(eswin->clks[i]);
+ clk_put(eswin->clks[i]);
+ }
+
+ mutex_unlock(&eswin->lock);
+
+ return ret;
+}
+
+static int dwc3_eswin_remove(struct platform_device *pdev)
+{
+ struct dwc3_eswin *eswin = platform_get_drvdata(pdev);
+ struct device *dev = &pdev->dev;
+ int i = 0;
+ int ret = 0;
+ cancel_work_sync(&eswin->otg_work);
+
+ sysfs_remove_group(&dev->kobj, &dwc3_eswin_attr_group);
+
+ /* Restore hcd state before unregistering xhci */
+ if (eswin->edev && !eswin->connected) {
+ struct usb_hcd *hcd = dev_get_drvdata(&eswin->dwc->xhci->dev);
+
+ pm_runtime_get_sync(dev);
+
+ /*
+ * The xhci code does not expect that HCDs have been removed.
+ * It will unconditionally call usb_remove_hcd() when the xhci
+ * driver is unloaded in of_platform_depopulate(). This results
+ * in a crash if the HCDs were already removed. To avoid this
+ * crash, add the HCDs here as dummy operation.
+ * This code should be removed after pm runtime support
+ * has been added to xhci.
+ */
+ if (hcd->state == HC_STATE_HALT) {
+ usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
+ usb_add_hcd(hcd->shared_hcd, hcd->irq, IRQF_SHARED);
+ }
+ }
+
+ of_platform_depopulate(dev);
+
+ pm_runtime_put_sync(dev);
+ pm_runtime_disable(dev);
+
+ ret = win2030_tbu_power(eswin->child_dev, false);
+ if (ret) {
+ dev_err(dev, "tbu power off failed %d\n", ret);
+ }
+
+ dwc3_eswin_assert(eswin);
+ for (i = 0; i < eswin->num_clocks; i++) {
+ if (!pm_runtime_status_suspended(dev))
+ clk_disable(eswin->clks[i]);
+ clk_unprepare(eswin->clks[i]);
+ clk_put(eswin->clks[i]);
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int dwc3_eswin_runtime_suspend(struct device *dev)
+{
+ struct dwc3_eswin *eswin = dev_get_drvdata(dev);
+ int i;
+
+ for (i = 0; i < eswin->num_clocks; i++)
+ clk_disable(eswin->clks[i]);
+
+ device_init_wakeup(dev, false);
+
+ return 0;
+}
+
+static int dwc3_eswin_runtime_resume(struct device *dev)
+{
+ struct dwc3_eswin *eswin = dev_get_drvdata(dev);
+ int i;
+
+ for (i = 0; i < eswin->num_clocks; i++)
+ clk_enable(eswin->clks[i]);
+
+ device_init_wakeup(dev, true);
+
+ return 0;
+}
+
+static int __maybe_unused dwc3_eswin_suspend(struct device *dev)
+{
+ struct dwc3_eswin *eswin = dev_get_drvdata(dev);
+ struct dwc3 *dwc = eswin->dwc;
+
+ eswin->suspended = true;
+ cancel_work_sync(&eswin->otg_work);
+
+ /*
+ * The flag of is_phy_on is only true if
+ * the DWC3 is in Host mode.
+ */
+ if (eswin->is_phy_on) {
+ phy_power_off(dwc->usb2_generic_phy);
+
+ /*
+ * If link state is Rx.Detect, it means that
+ * no usb device is connecting with the DWC3
+ * Host, and need to power off the USB3 PHY.
+ */
+ dwc->link_state = dwc3_gadget_get_link_state(dwc);
+ if (dwc->link_state == DWC3_LINK_STATE_RX_DET)
+ phy_power_off(dwc->usb3_generic_phy);
+ }
+
+ return 0;
+}
+
+static int __maybe_unused dwc3_eswin_resume(struct device *dev)
+{
+ struct dwc3_eswin *eswin = dev_get_drvdata(dev);
+ struct dwc3 *dwc = eswin->dwc;
+
+ eswin->suspended = false;
+
+ if (eswin->is_phy_on) {
+ phy_power_on(dwc->usb2_generic_phy);
+
+ if (dwc->link_state == DWC3_LINK_STATE_RX_DET)
+ phy_power_on(dwc->usb3_generic_phy);
+ }
+
+ if (eswin->edev)
+ schedule_work(&eswin->otg_work);
+
+ return 0;
+}
+
+static const struct dev_pm_ops dwc3_eswin_dev_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(dwc3_eswin_suspend, dwc3_eswin_resume)
+ SET_RUNTIME_PM_OPS(dwc3_eswin_runtime_suspend,
+ dwc3_eswin_runtime_resume, NULL)
+};
+
+#define DEV_PM_OPS (&dwc3_eswin_dev_pm_ops)
+#else
+#define DEV_PM_OPS NULL
+#endif /* CONFIG_PM */
+
+static const struct of_device_id eswin_dwc3_match[] = {
+ { .compatible = "eswin,win2030-dwc3" },
+ { /* Sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, eswin_dwc3_match);
+
+static struct platform_driver dwc3_eswin_driver = {
+ .probe = dwc3_eswin_probe,
+ .remove = dwc3_eswin_remove,
+ .driver = {
+ .name = "eswin-dwc3",
+ .pm = DEV_PM_OPS,
+ .of_match_table = eswin_dwc3_match,
+ },
+};
+
+module_platform_driver(dwc3_eswin_driver);
+
+MODULE_ALIAS("platform:eswin-dwc3");
+MODULE_AUTHOR("Han Min <hanmin@eswin.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("DesignWare USB3 ESWIN Glue Layer");
--
2.47.0

1477
0017-feat-support-ddr-ecc-check-and-report.patch Normal file
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3333
0018-feat-Porting-eswin-audio-to-6.6-kernel.patch Normal file
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1338
0019-feat-support-mpq8785-to-set-npu-voltage.patch Normal file
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461
0020-feat-Add-dma-driver.patch Normal file
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@ -0,0 +1,461 @@
From 08e9577184e3eaa06d7e276047c23bde568988c1 Mon Sep 17 00:00:00 2001
From: xuxiang <xuxiang@eswincomputing.com>
Date: Thu, 23 May 2024 10:01:46 +0800
Subject: [PATCH 020/219] feat:Add dma driver.
Changelogs:
1.Add dma driver for linux-6.6.
---
.../dts/eswin/eswin-win2030-die0-soc.dtsi | 20 ++-
.../dts/eswin/eswin-win2030-die1-soc.dtsi | 10 +-
drivers/clk/eswin/clk-win2030.c | 4 +
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 169 ++++++++++++++++--
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 5 +-
include/dt-bindings/clock/win2030-clock.h | 2 +
6 files changed, 182 insertions(+), 28 deletions(-)
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
index 1e813abf0819..a9f269bd9325 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
@@ -375,13 +375,14 @@ d0_pmu_dsp3: win2030-pmu-controller-port@240 {
};
d0_dmac0: dma-controller-hsp@0x50430000 {
- compatible = "snps,axi-dma-1.01a";
+ compatible = "eswin,eic770x-axi-dma";
reg = <0x0 0x50430000 0x0 0x10000>;
interrupt-parent = <&plic0>;
interrupts = <57>;
#dma-cells = <2>; // change dma-cells value <1> to <2>, to support peripheral selection dma-controller,See the parameter dmas for details;
- clocks = <&d0_clock WIN2030_CLK_HSP_DMA0_CLK>;
- clock-names = "core-clk";
+ clocks = <&d0_clock WIN2030_CLK_HSP_DMA0_CLK>,
+ <&d0_clock WIN2030_CLK_HSP_DMA0_CLK_TEST>;
+ clock-names = "core-clk", "cfgr-clk";
resets = <&d0_reset HSPDMA_RST_CTRL SW_HSP_DMA0_RSTN>,
<&d0_reset HSPDMA_RST_CTRL SW_HSP_DMA_PRSTN>;
reset-names = "arst", "prst";
@@ -401,13 +402,14 @@ d0_dmac0: dma-controller-hsp@0x50430000 {
};
d0_aon_dmac: dma-controller-aon@0x518c0000 {
- compatible = "snps,axi-dma-1.01a";
+ compatible = "eswin,eic770x-axi-dma";
reg = <0x0 0x518c0000 0x0 0x10000>;
interrupt-parent = <&plic0>;
interrupts = <289>;
#dma-cells = <2>; // change dma-cells value <1> to <2>, to support peripheral selection dma-controller,See the parameter dmas for details;
- clocks = <&d0_clock WIN2030_CLK_AONDMA_ACLK>;
- clock-names = "core-clk";
+ clocks = <&d0_clock WIN2030_CLK_AONDMA_ACLK>,
+ <&d0_clock WIN2030_CLK_AONDMA_CFG>;
+ clock-names = "core-clk", "cfgr-clk";
resets = <&d0_reset DMA1_RST_CTRL SW_DMA1_ARSTN>,
<&d0_reset DMA1_RST_CTRL SW_DMA1_HRSTN>;
reset-names = "arst", "prst";
@@ -417,7 +419,7 @@ d0_aon_dmac: dma-controller-aon@0x518c0000 {
snps,data-width = <3>;
snps,block-size = <0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000>;
snps,axi-max-burst-len = <32>;
- snps,max-msize = <64>;
+ // snps,max-msize = <64>;
#size-cells = <2>;
#address-cells = <2>;
dma-ranges = <0x0 0x80000000 0x0 0x80000000 0x100 0x0>;
@@ -806,7 +808,7 @@ msi_ctrl_int : 220
};
ssi0: spi@50810000 {
- compatible = "snps,win2030-spi";
+ compatible = "snps,eic770x-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x50810000 0x0 0x4000>;
@@ -826,7 +828,7 @@ ssi0: spi@50810000 {
};
ssi1: spi@50814000 {
- compatible = "snps,win2030-spi";
+ compatible = "snps,eic770x-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x50814000 0x0 0x4000>;
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
index 5a55de6c7b2a..9e12379cc7d3 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
@@ -323,7 +323,8 @@ d1_dmac0: dma-controller-hsp@0x70430000 {
interrupts = <57>;
#dma-cells = <2>; // change dma-cells value <1> to <2>, to support peripheral selection dma-controller,See the parameter dmas for details;
clocks = <&d1_clock WIN2030_CLK_HSP_DMA0_CLK>;
- clock-names = "core-clk";
+ <&d1_clock WIN2030_CLK_HSP_DMA0_CLK_TEST>;
+ clock-names = "core-clk", "cfgr-clk";
resets = <&d1_reset HSPDMA_RST_CTRL SW_HSP_DMA0_RSTN>,
<&d1_reset HSPDMA_RST_CTRL SW_HSP_DMA_PRSTN>;
reset-names = "arst", "prst";
@@ -348,8 +349,9 @@ d1_aon_dmac: dma-controller-aon@0x718c0000 {
interrupt-parent = <&plic1>;
interrupts = <289>;
#dma-cells = <2>; // change dma-cells value <1> to <2>, to support peripheral selection dma-controller,See the parameter dmas for details;
- clocks = <&d1_clock WIN2030_CLK_AONDMA_ACLK>;
- clock-names = "core-clk";
+ clocks = <&d1_clock WIN2030_CLK_AONDMA_ACLK>,
+ <&d1_clock WIN2030_CLK_AONDMA_CFG>;
+ clock-names = "core-clk", "cfgr-clk";
resets = <&d1_reset DMA1_RST_CTRL SW_DMA1_ARSTN>,
<&d1_reset DMA1_RST_CTRL SW_DMA1_HRSTN>;
reset-names = "arst", "prst";
@@ -1620,7 +1622,7 @@ d1_sdio1: mmc@0x70470000{
};
d1_ssi0: spi1@70810000 {
- compatible = "snps,win2030-spi";
+ compatible = "snps,eic770x-spi";
#address-cells = <2>;
#size-cells = <2>;
reg = <0x0 0x70810000 0x0 0x5000>;
diff --git a/drivers/clk/eswin/clk-win2030.c b/drivers/clk/eswin/clk-win2030.c
index 2ff82f4feba1..64bf0476b4bc 100755
--- a/drivers/clk/eswin/clk-win2030.c
+++ b/drivers/clk/eswin/clk-win2030.c
@@ -906,6 +906,9 @@ static struct eswin_gate_clock win2030_gate_clks[] = {
{ WIN2030_GATE_HSP_SATA_OOB_CLK ,"gate_hsp_sata_oob_clk", "mux_u_sata_phy_2mux1", CLK_SET_RATE_PARENT,
WIN2030_REG_OFFSET_SATA_OOB_CTRL, 31, 0, },
+ { WIN2030_GATE_HSP_DMA0_CLK_TEST ,"gate_hsp_dma0_clk_test", "gate_clk_hsp_aclk", CLK_SET_RATE_PARENT,
+ WIN2030_REG_OFFSET_HSP_ACLK_CTRL, 1, 0, },
+
{ WIN2030_GATE_HSP_DMA0_CLK ,"gate_hsp_dma0_clk", "gate_clk_hsp_aclk", CLK_SET_RATE_PARENT,
WIN2030_REG_OFFSET_HSP_ACLK_CTRL, 0, 0, },
@@ -1110,6 +1113,7 @@ static struct eswin_clock win2030_clks[] = {
{ WIN2030_CLK_VC_MON_PCLK ,"clk_vc_mon_pclk", "gate_vc_mon_pclk", CLK_SET_RATE_PARENT,},
{ WIN2030_CLK_HSP_DMA0_CLK ,"clk_hsp_dma0_clk", "gate_hsp_dma0_clk", CLK_SET_RATE_PARENT,},
+ { WIN2030_CLK_HSP_DMA0_CLK_TEST ,"clk_hsp_dma0_clk_TEST", "gate_hsp_dma0_clk", CLK_SET_RATE_PARENT,},
{ WIN2030_CLK_HSP_RMII_REF_0 ,"clk_hsp_rmii_ref_0", "gate_hsp_rmii_ref_0", CLK_SET_RATE_PARENT,},
{ WIN2030_CLK_HSP_RMII_REF_1 ,"clk_hsp_rmii_ref_1", "gate_hsp_rmii_ref_1", CLK_SET_RATE_PARENT,},
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 72fb40de58b3..dd98cce3dad8 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -28,10 +28,15 @@
#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/types.h>
+#include <linux/iommu.h>
#include "dw-axi-dmac.h"
#include "../dmaengine.h"
#include "../virt-dma.h"
+#include <linux/mfd/syscon.h>
+#include <linux/bitfield.h>
+#include <linux/regmap.h>
+#include <linux/eswin-win2030-sid-cfg.h>
/*
* The set of bus widths supported by the DMA controller. DW AXI DMAC supports
@@ -50,6 +55,14 @@
#define AXI_DMA_FLAG_HAS_APB_REGS BIT(0)
#define AXI_DMA_FLAG_HAS_RESETS BIT(1)
#define AXI_DMA_FLAG_USE_CFG2 BIT(2)
+#define AXI_DMA_FLAG_HAS_2RESETS BIT(3)
+
+#define AWSMMUSID GENMASK(31, 24) // The sid of write operation
+#define AWSMMUSSID GENMASK(23, 16) // The ssid of write operation
+#define ARSMMUSID GENMASK(15, 8) // The sid of read operation
+#define ARSMMUSSID GENMASK(7, 0) // The ssid of read operation
+
+static int eswin_dma_sid_cfg(struct device *dev);
static inline void
axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val)
@@ -228,6 +241,16 @@ static void axi_dma_hw_init(struct axi_dma_chip *chip)
ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(64));
if (ret)
dev_warn(chip->dev, "Unable to set coherent mask\n");
+
+ if (of_node_name_prefix(chip->dev->of_node, "dma-controller-hsp")) {
+ eswin_dma_sid_cfg(chip->dev);
+ }
+ else {
+ win2030_aon_sid_cfg(chip->dev);
+ }
+
+ /* TBU power up */
+ win2030_tbu_power(chip->dev, true);
}
static u32 axi_chan_get_xfer_width(struct axi_dma_chan *chan, dma_addr_t src,
@@ -575,25 +598,43 @@ static void write_desc_dar(struct axi_dma_hw_desc *desc, dma_addr_t adr)
desc->lli->dar = cpu_to_le64(adr);
}
-static void set_desc_src_master(struct axi_dma_hw_desc *desc)
+static void set_desc_src_master(struct axi_dma_hw_desc *hw_desc,
+ struct axi_dma_chan *chan)
{
u32 val;
/* Select AXI0 for source master */
- val = le32_to_cpu(desc->lli->ctl_lo);
- val &= ~CH_CTL_L_SRC_MAST;
- desc->lli->ctl_lo = cpu_to_le32(val);
+ val = le32_to_cpu(hw_desc->lli->ctl_lo);
+ if (chan->chip->dw->hdata->nr_masters > 1)
+ {
+ if(DMA_DEV_TO_MEM == chan->direction || DMA_DEV_TO_DEV == chan->direction) {
+ val |= CH_CTL_L_SRC_MAST;
+ }
+ else
+ {
+ val &= ~CH_CTL_L_SRC_MAST;
+ }
+ }
+ else
+ val &= ~CH_CTL_L_SRC_MAST;
+ hw_desc->lli->ctl_lo = cpu_to_le32(val);
}
static void set_desc_dest_master(struct axi_dma_hw_desc *hw_desc,
- struct axi_dma_desc *desc)
+ struct axi_dma_chan *chan)
{
u32 val;
/* Select AXI1 for source master if available */
val = le32_to_cpu(hw_desc->lli->ctl_lo);
- if (desc->chan->chip->dw->hdata->nr_masters > 1)
- val |= CH_CTL_L_DST_MAST;
+ if (chan->chip->dw->hdata->nr_masters > 1)
+ {
+ if(DMA_MEM_TO_DEV == chan->direction || DMA_DEV_TO_DEV == chan->direction) {
+ val |= CH_CTL_L_DST_MAST;
+ }
+ else
+ val &= ~CH_CTL_L_DST_MAST;
+ }
else
val &= ~CH_CTL_L_DST_MAST;
@@ -676,11 +717,11 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan,
hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1);
ctllo |= DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS |
- DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS;
+ DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS;
hw_desc->lli->ctl_lo = cpu_to_le32(ctllo);
- set_desc_src_master(hw_desc);
-
+ set_desc_src_master(hw_desc, chan);
+ set_desc_dest_master(hw_desc, chan);
hw_desc->len = len;
return 0;
}
@@ -945,8 +986,8 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dst_adr,
DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS);
hw_desc->lli->ctl_lo = cpu_to_le32(reg);
- set_desc_src_master(hw_desc);
- set_desc_dest_master(hw_desc, desc);
+ set_desc_src_master(hw_desc, chan);
+ set_desc_dest_master(hw_desc, chan);
hw_desc->len = xfer_len;
desc->length += hw_desc->len;
@@ -1283,6 +1324,41 @@ static int __maybe_unused axi_dma_runtime_resume(struct device *dev)
return axi_dma_resume(chip);
}
+int win2030_dma_sel_cfg(struct axi_dma_chan *chan, u32 val)
+{
+ struct axi_dma_chip *chip = chan->chip;
+ struct device *dev = chan->chip->dev;
+ int ret = 0;
+ struct regmap *regmap;
+ int dma_sel_reg;
+ u32 dma_sel = 0;
+
+ regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "eswin,syscfg");
+ if (IS_ERR(regmap)) {
+ dev_err(dev, "No eswin,syscfg phandle specified\n");
+ return -1;
+ }
+
+ ret = of_property_read_u32_index(dev->of_node, "eswin,syscfg", 2,
+ &dma_sel_reg);
+ if (ret) {
+ dev_err(dev, "can't get sid cfg reg offset in sys_con(errno:%d)\n", ret);
+ return ret;
+ }
+ regmap_read(regmap, dma_sel_reg, &dma_sel);
+
+ if (of_node_name_prefix(chip->dev->of_node, "dma-controller-hsp")) {
+ if (val < 32)
+ dma_sel &= ~(1 << val);
+ }
+ else {
+ if (val < 32)
+ dma_sel |= (1 << val);
+ }
+ regmap_write(regmap, dma_sel_reg, dma_sel);
+ return 0;
+}
+
static struct dma_chan *dw_axi_dma_of_xlate(struct of_phandle_args *dma_spec,
struct of_dma *ofdma)
{
@@ -1296,6 +1372,8 @@ static struct dma_chan *dw_axi_dma_of_xlate(struct of_phandle_args *dma_spec,
chan = dchan_to_axi_dma_chan(dchan);
chan->hw_handshake_num = dma_spec->args[0];
+ if (dma_spec->args_count > 1)
+ win2030_dma_sel_cfg(chan, dma_spec->args[1]);
return dchan;
}
@@ -1419,6 +1497,23 @@ static int dw_probe(struct platform_device *pdev)
if (ret)
return ret;
}
+ if (flags & AXI_DMA_FLAG_HAS_2RESETS) {
+ resets = devm_reset_control_get_optional(&pdev->dev, "arst");
+ if (IS_ERR(resets))
+ return PTR_ERR(resets);
+
+ ret = reset_control_deassert(resets);
+ if (ret)
+ return ret;
+
+ resets = devm_reset_control_get_optional(&pdev->dev, "prst");
+ if (IS_ERR(resets))
+ return PTR_ERR(resets);
+
+ ret = reset_control_deassert(resets);
+ if (ret)
+ return ret;
+ }
chip->dw->hdata->use_cfg2 = !!(flags & AXI_DMA_FLAG_USE_CFG2);
@@ -1533,6 +1628,51 @@ static int dw_probe(struct platform_device *pdev)
return ret;
}
+static int eswin_dma_sid_cfg(struct device *dev)
+{
+ int ret;
+ struct regmap *regmap;
+ int hsp_mmu_dma_reg;
+ u32 rdwr_sid_ssid;
+ u32 sid;
+ struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
+
+ /* not behind smmu, use the default reset value(0x0) of the reg as streamID*/
+ if (fwspec == NULL) {
+ dev_dbg(dev, "dev is not behind smmu, skip configuration of sid\n");
+ return 0;
+ }
+ sid = fwspec->ids[0];
+
+ regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "eswin,hsp_sp_csr");
+ if (IS_ERR(regmap)) {
+ dev_dbg(dev, "No hsp_sp_csr phandle specified\n");
+ return 0;
+ }
+
+ ret = of_property_read_u32_index(dev->of_node, "eswin,hsp_sp_csr", 1,
+ &hsp_mmu_dma_reg);
+ if (ret) {
+ dev_err(dev, "can't get dma sid cfg reg offset (%d)\n", ret);
+ return ret;
+ }
+
+ /* make the reading sid the same as writing sid, ssid is fixed to zero */
+ rdwr_sid_ssid = FIELD_PREP(AWSMMUSID, sid);
+ rdwr_sid_ssid |= FIELD_PREP(ARSMMUSID, sid);
+ rdwr_sid_ssid |= FIELD_PREP(AWSMMUSSID, 0);
+ rdwr_sid_ssid |= FIELD_PREP(ARSMMUSSID, 0);
+ regmap_write(regmap, hsp_mmu_dma_reg, rdwr_sid_ssid);
+
+ ret = win2030_dynm_sid_enable(dev_to_node(dev));
+ if (ret < 0)
+ dev_err(dev, "failed to config dma streamID(%d)!\n", sid);
+ else
+ dev_dbg(dev, "success to config dma streamID(%d)!\n", sid);
+
+ return ret;
+}
+
static int dw_remove(struct platform_device *pdev)
{
struct axi_dma_chip *chip = platform_get_drvdata(pdev);
@@ -1562,6 +1702,8 @@ static int dw_remove(struct platform_device *pdev)
list_del(&chan->vc.chan.device_node);
tasklet_kill(&chan->vc.task);
}
+ /* TBU power down before reset */
+ win2030_tbu_power(chip->dev, false);
return 0;
}
@@ -1579,6 +1721,9 @@ static const struct of_device_id dw_dma_of_id_table[] = {
}, {
.compatible = "starfive,jh7110-axi-dma",
.data = (void *)(AXI_DMA_FLAG_HAS_RESETS | AXI_DMA_FLAG_USE_CFG2),
+ }, {
+ .compatible = "eswin,eic770x-axi-dma",
+ .data = (void *)(AXI_DMA_FLAG_HAS_2RESETS | AXI_DMA_FLAG_USE_CFG2),
},
{}
};
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 8521530a34ec..cc09abf15aad 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -203,7 +203,7 @@ static inline struct axi_dma_chan *dchan_to_axi_dma_chan(struct dma_chan *dchan)
#define UNUSED_CHANNEL 0x3F /* Set unused DMA channel to 0x3F */
#define DMA_APB_HS_SEL_BIT_SIZE 0x08 /* HW handshake bits per channel */
#define DMA_APB_HS_SEL_MASK 0xFF /* HW handshake select masks */
-#define MAX_BLOCK_SIZE 0x1000 /* 1024 blocks * 4 bytes data width */
+#define MAX_BLOCK_SIZE 0x1000 /* 1024 blocks * 512 bytes data width */
#define DMA_REG_MAP_CH_REF 0x08 /* Channel count to choose register map */
/* DMAC_CFG */
@@ -322,8 +322,7 @@ enum {
#define CH_CFG2_H_TT_FC_POS 0
#define CH_CFG2_H_HS_SEL_SRC_POS 3
#define CH_CFG2_H_HS_SEL_DST_POS 4
-#define CH_CFG2_H_PRIORITY_POS 20
-
+#define CH_CFG2_H_PRIORITY_POS 15
/**
* DW AXI DMA channel interrupts
*
diff --git a/include/dt-bindings/clock/win2030-clock.h b/include/dt-bindings/clock/win2030-clock.h
index 6c85b4b980f2..7793f3925932 100755
--- a/include/dt-bindings/clock/win2030-clock.h
+++ b/include/dt-bindings/clock/win2030-clock.h
@@ -378,6 +378,7 @@
#define WIN2030_GATE_VC_VD_PCLK 411
#define WIN2030_GATE_VC_MON_PCLK 412
#define WIN2030_GATE_HSP_DMA0_CLK 413
+#define WIN2030_GATE_HSP_DMA0_CLK_TEST 414
/*fixed factor clocks*/
#define WIN2030_FIXED_FACTOR_U_CPU_DIV2 450
@@ -596,6 +597,7 @@
#define WIN2030_CLK_VC_MON_PCLK 689
#define WIN2030_CLK_HSP_DMA0_CLK 690
+#define WIN2030_CLK_HSP_DMA0_CLK_TEST 691
#define WIN2030_NR_CLKS 700
--
2.47.0

37
0021-feat-Select-emmc-sdio-wireless-drivers-by-default.patch Normal file
View File

@ -0,0 +1,37 @@
From be768fd90a27a60f89eec58f4070c55ba9499a69 Mon Sep 17 00:00:00 2001
From: liangshuang <liangshuang@eswincomputing.com>
Date: Thu, 23 May 2024 16:53:55 +0800
Subject: [PATCH 021/219] feat:Select emmc/sdio/wireless drivers by default.
Changelogs:
1.Select emmc/sdio/wireless drivers by default.
---
arch/riscv/configs/win2030_defconfig | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig
index 7f8075d825bc..d3524b132481 100644
--- a/arch/riscv/configs/win2030_defconfig
+++ b/arch/riscv/configs/win2030_defconfig
@@ -47,7 +47,8 @@ CONFIG_IP_PNP_BOOTP=y
# CONFIG_IPV6 is not set
CONFIG_NET_SCHED=y
CONFIG_NET_CLS_ACT=y
-# CONFIG_WIRELESS is not set
+CONFIG_CFG80211=y
+CONFIG_CFG80211_WEXT=y
CONFIG_PCI=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCIEAER=y
@@ -228,6 +229,8 @@ CONFIG_MMC_TEST=y
CONFIG_MMC_DEBUG=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_ESWIN=y
+CONFIG_MMC_SDHCI_OF_SDIO_ESWIN=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
--
2.47.0

241
0022-feat-spram-Treat-spram-as-part-of-the-sys-memory-spa.patch Normal file
View File

@ -0,0 +1,241 @@
From 40fca4e3830cc2238326f1a181f50a153f5d10cd Mon Sep 17 00:00:00 2001
From: linmin <linmin@eswincomputing.com>
Date: Thu, 23 May 2024 16:30:23 +0800
Subject: [PATCH 022/219] feat(spram):Treat spram as part of the sys memory
space
Changelogs:
1.Move spram space into the system memory space of the eic7700-evb.dts
and eic7700-evb-a2.dts. Then there is no need to call memblock_reserve()
for adding spram into memblock.
---
arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts | 11 ++--
arch/riscv/boot/dts/eswin/eic7700-evb.dts | 11 ++--
drivers/memory/eswin/codacache/llc_spram.c | 53 ++++----------------
3 files changed, 17 insertions(+), 58 deletions(-)
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
index cddfc166e851..8c2b945ed8a9 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
@@ -56,13 +56,13 @@ chosen {
cpus {
timebase-frequency = <RTCCLK_FREQ>;
};
-/*
+
memory@59000000 {
device_type = "memory";
reg = <0x0 0x59000000 0x0 0x400000>;
numa-node-id = <0>;
};
-*/
+
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 MEMORY_SIZE_H MEMORY_SIZE_L>;
@@ -82,12 +82,12 @@ linux,cma {
alloc-ranges = <0x0 0x80000000 MEMORY_SIZE_H MEMORY_SIZE_L>;
linux,cma-default;
};
-/*
+
npu0_reserved: sprammemory@59000000 {
no-map;
reg = <0x0 0x59000000 0x0 0x400000>;
};
-*/
+
/*
dsp_reserved0: dsp@90000000 {
compatible = "shared-dma-pool";
@@ -146,9 +146,6 @@ reset_test@1e00e000 {
reset-names = "bus", "core", "dbg";
};
};
- npu0_reserved: sprammemory@59000000 {
- reg = <0x0 0x59000000 0x0 0x400000>;
- };
leds {
compatible = "gpio-leds";
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb.dts b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
index 34bc531d58f9..c627133f179c 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
@@ -55,13 +55,13 @@ chosen {
cpus {
timebase-frequency = <RTCCLK_FREQ>;
};
-/*
+
memory@59000000 {
device_type = "memory";
reg = <0x0 0x59000000 0x0 0x400000>;
numa-node-id = <0>;
};
-*/
+
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 MEMORY_SIZE_H MEMORY_SIZE_L>;
@@ -81,12 +81,12 @@ linux,cma {
alloc-ranges = <0x0 0x80000000 MEMORY_SIZE_H MEMORY_SIZE_L>;
linux,cma-default;
};
-/*
+
npu0_reserved: sprammemory@59000000 {
no-map;
reg = <0x0 0x59000000 0x0 0x400000>;
};
-*/
+
/*
dsp_reserved0: dsp@90000000 {
compatible = "shared-dma-pool";
@@ -145,9 +145,6 @@ reset_test@1e00e000 {
reset-names = "bus", "core", "dbg";
};
};
- npu0_reserved: sprammemory@59000000 {
- reg = <0x0 0x59000000 0x0 0x400000>;
- };
};
&d0_clock {
diff --git a/drivers/memory/eswin/codacache/llc_spram.c b/drivers/memory/eswin/codacache/llc_spram.c
index 8bd0912af4b7..2e343f1da43f 100644
--- a/drivers/memory/eswin/codacache/llc_spram.c
+++ b/drivers/memory/eswin/codacache/llc_spram.c
@@ -895,13 +895,6 @@ static int llc_resource_parse(struct platform_device *pdev)
(unsigned int)resource_size(&res_spram),
npu_spram_size);
- /* add to memblock and reserve it */
- ret = memblock_reserve(res_spram.start, npu_spram_size);
- if (ret) {
- dev_err(dev, "Failed to reserve spram!!!\n");
- goto out_spram_region;
- }
-
spram->phys_addr = res_spram.start;
spram->virt_base = devm_ioremap(&pdev->dev, spram->phys_addr, npu_spram_size);
if (spram->virt_base == NULL) {
@@ -1174,7 +1167,7 @@ static void spram_heap_dma_buf_release(struct dma_buf *dmabuf)
struct sg_table *table;
struct spram_dev *spram = buffer->heap->spram;
struct scatterlist *sg;
- int i, page_num = 0;
+ int i;
table = &buffer->sg_table;
for_each_sgtable_sg(table, sg, i) {
@@ -1184,15 +1177,10 @@ static void spram_heap_dma_buf_release(struct dma_buf *dmabuf)
#else
void *vaddr = spram_phys_to_virt(spram, page_to_phys(page));
#endif
- gen_pool_free(spram->pool, (unsigned long)vaddr, PAGE_SIZE);
- page_num++;
+ gen_pool_free(spram->pool, (unsigned long)vaddr, page_size(page));
}
sg_free_table(table);
kfree(buffer);
- pr_info("%s, ---buffer->len=0x%lx, freed size=0x%x, Available:0x%lx\n",
- __func__, buffer->len,
- (page_num << PAGE_SHIFT), gen_pool_avail(spram->pool));
-
}
static const struct dma_buf_ops spram_heap_buf_ops = {
@@ -1208,34 +1196,17 @@ static const struct dma_buf_ops spram_heap_buf_ops = {
.release = spram_heap_dma_buf_release,
};
-struct spram_page {
- struct list_head lru;
- struct page *page;
-};
-
static int spram_noncontiguous_alloc(struct spram_dev *spram, size_t len, struct sg_table *table)
{
struct gen_pool *pool = spram->pool;
struct list_head pages;
- struct page *page;
+ struct page *page, *tmp_page;
struct scatterlist *sg;
unsigned long size_remaining = len;
phys_addr_t phys_addr;
void *vaddr;
- unsigned int page_num;
- struct spram_page *spram_pages, *spram_page, *tmp_spram_page;
int i, ret = -ENOMEM;
- page_num = size_remaining / PAGE_SIZE;
- pr_info("%s, ---try to alloc len=0x%lx, Available:0x%lx\n", __func__, len, gen_pool_avail(spram->pool));
-
- spram_pages = kzalloc(page_num * sizeof(struct spram_page), GFP_KERNEL);
- if (!spram_pages) {
- pr_err("unable to allocate memory.\n");
- return -ENOMEM;
- }
- spram_page = spram_pages;
-
INIT_LIST_HEAD(&pages);
i = 0;
while (size_remaining > 0) {
@@ -1253,45 +1224,39 @@ static int spram_noncontiguous_alloc(struct spram_dev *spram, size_t len, struct
goto free_spram;
page = phys_to_page(phys_addr);
- // pr_debug("---%s:%d, page_to_phys:0x%x,page:0x%px, spram_page:0x%px\n",
- // __func__, __LINE__, (unsigned int)page_to_phys(page), page, spram_page);
+ pr_debug("---%s:%d, phys_to_page->page_to_phys:0x%x,page:0x%px\n",
+ __func__, __LINE__, (unsigned int)page_to_phys(page), page);
/* page->virtual is used for recording the gen pool vaddr which is needed when releasing spram memory */
#ifdef WANT_PAGE_VIRTUAL
page->virtual = vaddr;
set_page_address(page, vaddr);
#endif
- spram_page->page = page;
- list_add_tail(&spram_page->lru, &pages);
+ list_add_tail(&page->lru, &pages);
size_remaining -= PAGE_SIZE;
i++;
- spram_page++;
}
if (sg_alloc_table(table, i, GFP_KERNEL))
goto free_spram;
sg = table->sgl;
- list_for_each_entry_safe(spram_page, tmp_spram_page, &pages, lru) {
- page = spram_page->page;
+ list_for_each_entry_safe(page, tmp_page, &pages, lru) {
sg_set_page(sg, page, PAGE_SIZE, 0);
sg = sg_next(sg);
- list_del(&spram_page->lru);
+ list_del(&page->lru);
}
- kfree(spram_pages);
return 0;
free_spram:
- list_for_each_entry_safe(spram_page, tmp_spram_page, &pages, lru) {
+ list_for_each_entry_safe(page, tmp_page, &pages, lru) {
#ifdef WANT_PAGE_VIRTUAL
vaddr = page_address(page);
#else
- page = spram_page->page;
vaddr = spram_phys_to_virt(spram, page_to_phys(page));
#endif
gen_pool_free(pool, (unsigned long)vaddr, PAGE_SIZE);
}
- kfree(spram_pages);
return ret;
}
--
2.47.0

34
0023-feat-cma-heap-Select-CONFIG_DMABUF_HEAPS_CMA.patch Normal file
View File

@ -0,0 +1,34 @@
From 2d057d41556b09e0549c3fde75b74719200a819b Mon Sep 17 00:00:00 2001
From: linmin <linmin@eswincomputing.com>
Date: Thu, 23 May 2024 18:06:28 +0800
Subject: [PATCH 023/219] feat(cma heap):Select CONFIG_DMABUF_HEAPS_CMA
Changelogs:
1.Select CONFIG_DMABUF_HEAPS_CMA in arch/riscv/configs/win2030_defconfig
---
arch/riscv/configs/win2030_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig
index d3524b132481..0c9b6e662ed4 100644
--- a/arch/riscv/configs/win2030_defconfig
+++ b/arch/riscv/configs/win2030_defconfig
@@ -180,7 +180,6 @@ CONFIG_SND_SOC=y
CONFIG_SND_SOC_SOF_TOPLEVEL=y
CONFIG_SND_SOC_SOF_OF=y
CONFIG_SND_ESWIN_DW_I2S=y
-CONFIG_SND_SOC_HDMI_CODEC=y
CONFIG_ESWIN_SND_SOC_CODECS=y
CONFIG_ESWIN_SND_ES8388_CODEC=y
CONFIG_SND_SIMPLE_CARD=y
@@ -249,6 +248,7 @@ CONFIG_DW_AXI_DMAC=y
CONFIG_DMATEST=y
CONFIG_DMABUF_HEAPS=y
CONFIG_DMABUF_HEAPS_SYSTEM=y
+CONFIG_DMABUF_HEAPS_CMA=y
CONFIG_VIRTIO_BALLOON=y
CONFIG_VIRTIO_INPUT=y
CONFIG_VIRTIO_MMIO=y
--
2.47.0

410
0024-feat-sata-driver-to-linux-6.6.patch Normal file
View File

@ -0,0 +1,410 @@
From f1026d89bfa9e93ddac93076f95b8bffe8237258 Mon Sep 17 00:00:00 2001
From: luyulin <luyulin@eswincomputing.com>
Date: Fri, 24 May 2024 10:47:11 +0800
Subject: [PATCH 024/219] feat:sata driver to linux 6.6.
Changelogs:
sata driver to linux 6.6.
---
arch/riscv/configs/win2030_defconfig | 1 +
drivers/ata/Kconfig | 9 +
drivers/ata/Makefile | 1 +
drivers/ata/ahci_eswin.c | 341 +++++++++++++++++++++++++++
4 files changed, 352 insertions(+)
create mode 100644 drivers/ata/ahci_eswin.c
diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig
index 0c9b6e662ed4..f57a7581943b 100644
--- a/arch/riscv/configs/win2030_defconfig
+++ b/arch/riscv/configs/win2030_defconfig
@@ -73,6 +73,7 @@ CONFIG_BLK_DEV_SD=y
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_ATA=y
CONFIG_SATA_AHCI=y
+CONFIG_AHCI_ESWIN=y
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_ALACRITECH is not set
# CONFIG_NET_VENDOR_AMAZON is not set
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 42b51c9812a0..fcc935629d93 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -136,6 +136,15 @@ config SATA_MOBILE_LPM_POLICY
Note "Minimum power" is known to cause issues, including disk
corruption, with some disks and should not be used.
+config AHCI_ESWIN
+ tristate "Eswin AHCI SATA support"
+ select SATA_HOST
+ help
+ This option enables support for Eswin AHCI Serial ATA
+ controllers.
+
+ If unsure, say N.
+
config SATA_AHCI_PLATFORM
tristate "Platform AHCI SATA support"
select SATA_HOST
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 20e6645ab737..a596e5ea5134 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_SATA_INIC162X) += sata_inic162x.o
obj-$(CONFIG_SATA_SIL24) += sata_sil24.o
obj-$(CONFIG_SATA_DWC) += sata_dwc_460ex.o
obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o
+obj-$(CONFIG_AHCI_ESWIN) += ahci_eswin.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_BRCM) += ahci_brcm.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_CEVA) += ahci_ceva.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_DA850) += ahci_da850.o libahci.o libahci_platform.o
diff --git a/drivers/ata/ahci_eswin.c b/drivers/ata/ahci_eswin.c
new file mode 100644
index 000000000000..d9495dfe9887
--- /dev/null
+++ b/drivers/ata/ahci_eswin.c
@@ -0,0 +1,341 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ESWIN AHCI SATA Driver
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Authors: Yulin Lu <luyulin@eswincomputing.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pm.h>
+#include <linux/device.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/libata.h>
+#include <linux/ahci_platform.h>
+#include <linux/acpi.h>
+#include <linux/pci_ids.h>
+#include <linux/iommu.h>
+#include <linux/eswin-win2030-sid-cfg.h>
+#include <linux/mfd/syscon.h>
+#include <linux/bitfield.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include "ahci.h"
+
+#define DRV_NAME "ahci"
+
+#define AWSMMUSID GENMASK(31, 24) // The sid of write operation
+#define AWSMMUSSID GENMASK(23, 16) // The ssid of write operation
+#define ARSMMUSID GENMASK(15, 8) // The sid of read operation
+#define ARSMMUSSID GENMASK(7, 0) // The ssid of read operation
+#define SATA_REF_CTRL1 0x338
+#define SATA_PHY_CTRL0 0x328
+#define SATA_PHY_CTRL1 0x32c
+#define SATA_LOS_IDEN 0x33c
+#define SATA_AXI_LP_CTRL 0x308
+#define SATA_REG_CTRL 0x334
+#define SATA_MPLL_CTRL 0x320
+#define SATA_RESET_CTRL 0x340
+#define SATA_RESET_CTRL_ASSERT 0x3
+#define SATA_RESET_CTRL_DEASSERT 0x0
+#define SATA_PHY_RESET BIT(0)
+#define SATA_P0_RESET BIT(1)
+#define SATA_LOS_LEVEL 0x9
+#define SATA_LOS_BIAS (0x02 << 16)
+#define SATA_REF_REPEATCLK_EN BIT(0)
+#define SATA_REF_USE_PAD BIT(20)
+#define SATA_P0_AMPLITUDE_GEN1 0x42
+#define SATA_P0_AMPLITUDE_GEN2 (0x46 << 8)
+#define SATA_P0_AMPLITUDE_GEN3 (0x73 << 16)
+#define SATA_P0_PHY_TX_PREEMPH_GEN1 0x05
+#define SATA_P0_PHY_TX_PREEMPH_GEN2 (0x05 << 8)
+#define SATA_P0_PHY_TX_PREEMPH_GEN3 (0x23 << 16)
+#define SATA_MPLL_MULTIPLIER (0x3c << 16)
+#define SATA_M_CSYSREQ BIT(0)
+#define SATA_S_CSYSREQ BIT(16)
+#define HSPDME_RST_CTRL 0x41C
+#define SW_HSP_SATA_ARSTN BIT(27)
+#define SW_SATA_RSTN (0xf << 9)
+
+static const struct ata_port_info ahci_port_info = {
+ .flags = AHCI_FLAG_COMMON,
+ .pio_mask = ATA_PIO4,
+ .udma_mask = ATA_UDMA6,
+ .port_ops = &ahci_platform_ops,
+};
+
+static const struct ata_port_info ahci_port_info_nolpm = {
+ .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_LPM,
+ .pio_mask = ATA_PIO4,
+ .udma_mask = ATA_UDMA6,
+ .port_ops = &ahci_platform_ops,
+};
+
+static struct scsi_host_template ahci_platform_sht = {
+ AHCI_SHT(DRV_NAME),
+};
+
+static int eswin_sata_sid_cfg(struct device *dev)
+{
+ int ret;
+ struct regmap *regmap;
+ int hsp_mmu_sata_reg;
+ u32 rdwr_sid_ssid;
+ u32 sid;
+ struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
+
+ /* not behind smmu, use the default reset value(0x0) of the reg as streamID*/
+ if (fwspec == NULL) {
+ dev_dbg(dev, "dev is not behind smmu, skip configuration of sid\n");
+ return 0;
+ }
+ sid = fwspec->ids[0];
+ regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "eswin,hsp_sp_csr");
+ if (IS_ERR(regmap)) {
+ dev_dbg(dev, "No hsp_sp_csr phandle specified\n");
+ return 0;
+ }
+ ret = of_property_read_u32_index(dev->of_node, "eswin,hsp_sp_csr", 1,
+ &hsp_mmu_sata_reg);
+ if (ret) {
+ dev_err(dev, "can't get sata sid cfg reg offset (%d)\n", ret);
+ return ret;
+ }
+
+ /* make the reading sid the same as writing sid, ssid is fixed to zero */
+ rdwr_sid_ssid = FIELD_PREP(AWSMMUSID, sid);
+ rdwr_sid_ssid |= FIELD_PREP(ARSMMUSID, sid);
+ rdwr_sid_ssid |= FIELD_PREP(AWSMMUSSID, 0);
+ rdwr_sid_ssid |= FIELD_PREP(ARSMMUSSID, 0);
+ regmap_write(regmap, hsp_mmu_sata_reg, rdwr_sid_ssid);
+
+ ret = win2030_dynm_sid_enable(dev_to_node(dev));
+ if (ret < 0)
+ dev_err(dev, "failed to config sata streamID(%d)!\n", sid);
+ else
+ dev_dbg(dev, "success to config sata streamID(%d)!\n", sid);
+ pr_err("eswin_sata_sid_cfg success\n");
+ return ret;
+}
+
+static int eswin_sata_init(struct device *dev)
+{
+ struct regmap *regmap;
+ regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "eswin,hsp_sp_csr");
+ if (IS_ERR(regmap)) {
+ dev_dbg(dev, "No hsp_sp_csr phandle specified\n");
+ return -1;
+ }
+ regmap_write(regmap, SATA_REF_CTRL1, 0x1);
+ regmap_write(regmap, SATA_PHY_CTRL0, (SATA_P0_AMPLITUDE_GEN1|SATA_P0_AMPLITUDE_GEN2|SATA_P0_AMPLITUDE_GEN3));
+ regmap_write(regmap, SATA_PHY_CTRL1, (SATA_P0_PHY_TX_PREEMPH_GEN1|SATA_P0_PHY_TX_PREEMPH_GEN2|SATA_P0_PHY_TX_PREEMPH_GEN3));
+ regmap_write(regmap, SATA_LOS_IDEN, SATA_LOS_LEVEL|SATA_LOS_BIAS);
+ regmap_write(regmap, SATA_AXI_LP_CTRL, (SATA_M_CSYSREQ|SATA_S_CSYSREQ));
+ regmap_write(regmap, SATA_REG_CTRL, (SATA_REF_REPEATCLK_EN|SATA_REF_USE_PAD));
+ regmap_write(regmap, SATA_MPLL_CTRL, SATA_MPLL_MULTIPLIER);
+ regmap_write(regmap, SATA_RESET_CTRL, 0x0);
+ return 0;
+}
+
+static int __init eswin_reset(struct device *dev)
+{
+ struct reset_control *asic0_rst;
+ struct reset_control *oob_rst;
+ struct reset_control *pmalive_rst;
+ struct reset_control *rbc_rst;
+ struct reset_control *apb_rst;
+ int rc;
+ asic0_rst = devm_reset_control_get_shared(dev, "asic0");
+ if (IS_ERR_OR_NULL(asic0_rst)) {
+ dev_err(dev, "Failed to asic0_rst handle\n");
+ return -EFAULT;
+ }
+ oob_rst = devm_reset_control_get_shared(dev, "oob");
+ if (IS_ERR_OR_NULL(oob_rst)) {
+ dev_err(dev, "Failed to oob_rst handle\n");
+ return -EFAULT;
+ }
+ pmalive_rst = devm_reset_control_get_shared(dev, "pmalive");
+ if (IS_ERR_OR_NULL(pmalive_rst)) {
+ dev_err(dev, "Failed to pmalive_rst handle\n");
+ return -EFAULT;
+ }
+ rbc_rst = devm_reset_control_get_shared(dev, "rbc");
+ if (IS_ERR_OR_NULL(rbc_rst)) {
+ dev_err(dev, "Failed to rbc_rst handle\n");
+ return -EFAULT;
+ }
+ apb_rst = devm_reset_control_get_shared(dev, "apb");
+ if (IS_ERR_OR_NULL(apb_rst)) {
+ dev_err(dev, "Failed to apb_rst handle\n");
+ return -EFAULT;
+ }
+ printk("eswin sata before reset control deasser\n");
+ if (asic0_rst) {
+ rc = reset_control_deassert(asic0_rst);
+ WARN_ON(0 != rc);
+ }
+ if (oob_rst) {
+ rc = reset_control_deassert(oob_rst);
+ WARN_ON(0 != rc);
+ }
+ if (pmalive_rst) {
+ rc = reset_control_deassert(pmalive_rst);
+ WARN_ON(0 != rc);
+ }
+ if (rbc_rst) {
+ rc = reset_control_deassert(rbc_rst);
+ WARN_ON(0 != rc);
+ }
+ if (apb_rst) {
+ rc = reset_control_deassert(apb_rst);
+ WARN_ON(0 != rc);
+ }
+ printk("eswin sata after reset control deasser\n");
+ return 0;
+}
+
+
+static int eswin_unreset(struct device *dev)
+{
+ struct reset_control *asic0_rst;
+ struct reset_control *oob_rst;
+ struct reset_control *pmalive_rst;
+ struct reset_control *rbc_rst;
+ int rc;
+
+ asic0_rst = devm_reset_control_get_shared(dev, "asic0");
+ if (IS_ERR_OR_NULL(asic0_rst)) {
+ dev_err(dev, "Failed to asic0_rst handle\n");
+ return -EFAULT;
+ }
+ oob_rst = devm_reset_control_get_shared(dev, "oob");
+ if (IS_ERR_OR_NULL(oob_rst)) {
+ dev_err(dev, "Failed to oob_rst handle\n");
+ return -EFAULT;
+ }
+ pmalive_rst = devm_reset_control_get_shared(dev, "pmalive");
+ if (IS_ERR_OR_NULL(pmalive_rst)) {
+ dev_err(dev, "Failed to pmalive_rst handle\n");
+ return -EFAULT;
+ }
+ rbc_rst = devm_reset_control_get_shared(dev, "rbc");
+ if (IS_ERR_OR_NULL(rbc_rst)) {
+ dev_err(dev, "Failed to rbc_rst handle\n");
+ return -EFAULT;
+ }
+ if (asic0_rst) {
+ rc = reset_control_assert(asic0_rst);
+ WARN_ON(0 != rc);
+ }
+ if (oob_rst) {
+ rc = reset_control_assert(oob_rst);
+ WARN_ON(0 != rc);
+ }
+ if (pmalive_rst) {
+ rc = reset_control_assert(pmalive_rst);
+ WARN_ON(0 != rc);
+ }
+ if (rbc_rst) {
+ rc = reset_control_assert(rbc_rst);
+ WARN_ON(0 != rc);
+ }
+ return 0;
+}
+
+static int ahci_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct ahci_host_priv *hpriv;
+ const struct ata_port_info *port;
+ int rc;
+ hpriv = ahci_platform_get_resources(pdev,
+ 0);
+ if (IS_ERR(hpriv))
+ return PTR_ERR(hpriv);
+
+ rc = eswin_reset(dev);
+ if (rc)
+ return rc;
+ eswin_sata_init(dev);
+ eswin_sata_sid_cfg(dev);
+ win2030_tbu_power(&pdev->dev, true);
+ rc = dma_set_mask_and_coherent(dev,DMA_BIT_MASK(41));
+ of_property_read_u32(dev->of_node,
+ "ports-implemented", &hpriv->saved_port_map);
+
+ if (of_device_is_compatible(dev->of_node, "hisilicon,hisi-ahci"))
+ hpriv->flags |= AHCI_HFLAG_NO_FBS | AHCI_HFLAG_NO_NCQ;
+
+ port = acpi_device_get_match_data(dev);
+ if (!port){
+ port = &ahci_port_info;
+ }
+ rc = ahci_platform_init_host(pdev, hpriv, port,
+ &ahci_platform_sht);
+ if (rc)
+ goto disable_resources;
+
+ return 0;
+disable_resources:
+ ahci_platform_disable_resources(hpriv);
+ return rc;
+}
+
+static int ahci_remove(struct platform_device *pdev)
+{
+ win2030_tbu_power(&pdev->dev, false);
+ eswin_unreset(&pdev->dev);
+ ata_platform_remove_one(pdev);
+ return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspend,
+ ahci_platform_resume);
+
+static const struct of_device_id ahci_of_match[] = {
+ { .compatible = "snps,eswin-ahci", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, ahci_of_match);
+
+static const struct acpi_device_id ahci_acpi_match[] = {
+ { "APMC0D33", (unsigned long)&ahci_port_info_nolpm },
+ { ACPI_DEVICE_CLASS(PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff) },
+ {},
+};
+MODULE_DEVICE_TABLE(acpi, ahci_acpi_match);
+
+static struct platform_driver ahci_driver = {
+ .probe = ahci_probe,
+ .remove = ahci_remove,
+ .shutdown = ahci_platform_shutdown,
+ .driver = {
+ .name = DRV_NAME,
+ .of_match_table = ahci_of_match,
+ .acpi_match_table = ahci_acpi_match,
+ .pm = &ahci_pm_ops,
+ },
+};
+module_platform_driver(ahci_driver);
+
+MODULE_DESCRIPTION("ESWIN AHCI SATA driver");
+MODULE_AUTHOR("Lu Yulin <luyulin@eswincomputing.com>");
+MODULE_LICENSE("GPL");
\ No newline at end of file
--
2.47.0

1025
0025-feat-add-support-pac1934-to-get-som-voltage-info.patch Normal file
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122
0026-fix-modify-ina226-addr-and-hold-time.patch Normal file
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@ -0,0 +1,122 @@
From ed76c49c78653f1060f6d3b8f78bfd9623db4129 Mon Sep 17 00:00:00 2001
From: yangwei1 <yangwei1@eswincomputing.com>
Date: Thu, 23 May 2024 20:30:07 +0800
Subject: [PATCH 026/219] fix:modify ina226 addr and hold time
Changelogs:
1.modify ina226 addr form 0x4c to 0x48 in i2c11
2.modify name of hold time from iic_hold_time to i2c-sda-hold-time-ns
---
arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts | 22 +++++++++-----------
arch/riscv/boot/dts/eswin/eic7700-evb.dts | 21 +++++++++----------
2 files changed, 20 insertions(+), 23 deletions(-)
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
index 8c2b945ed8a9..519c74d06f0e 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
@@ -793,35 +793,33 @@ rtc@51 {
&d0_aon_i2c1 {
/* ina226x4 */
status = "okay";
- eswin,syscfg = <&d0_sys_con 0x3C0 15>;
- iic_hold_time = <0x40>;
-
- u80_cpu: ina226@45 {
+ i2c-sda-hold-time-ns = <0x40>;
+ vdd_cpu: ina226@45 {
compatible = "ti,ina226";
#io-channel-cells = <1>;
- label = "ina226-u80_CPU";
+ label = "vdd_cpu";
reg = <0x45>;
shunt-resistor = <1000>;
};
- u82_soc: ina226@44 {
+ vdd_soc: ina226@44 {
compatible = "ti,ina226";
#io-channel-cells = <1>;
- label = "ina226-u82_soc";
+ label = "vdd_soc";
reg = <0x44>;
shunt-resistor = <1000>;
};
- u83_lpddr4: ina226@41 {
+ vdd_lpddr: ina226@41 {
compatible = "ti,ina226";
#io-channel-cells = <1>;
- label = "ina226-u83_lpddr4";
+ label = "vdd_lpddr";
reg = <0x41>;
shunt-resistor = <1000>;
};
- u99_dc: ina226@4c {
+ dc_in: ina226@48 {
compatible = "ti,ina226";
#io-channel-cells = <1>;
- label = "ina226-u99_dc";
- reg = <0x4c>;
+ label = "dc_in";
+ reg = <0x48>;
shunt-resistor = <1000>;
};
};
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb.dts b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
index c627133f179c..a1e0766efd04 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
@@ -752,8 +752,7 @@ rtc@51 {
&d0_aon_i2c1 {
/* mpq8785 & ina226x4 */
status = "okay";
- eswin,syscfg = <&d0_sys_con 0x3C0 15>;
- iic_hold_time = <0x40>;
+ i2c-sda-hold-time-ns = <0x40>;
mpq8785@10 {
compatible = "mps,mpq8785";
reg = <0x10>;
@@ -771,32 +770,32 @@ npu_vcc1:npu_svcc{
};
};
};
- u80_cpu: ina226@45 {
+ vdd_cpu: ina226@45 {
compatible = "ti,ina226";
#io-channel-cells = <1>;
- label = "ina226-u80_CPU";
+ label = "vdd_cpu";
reg = <0x45>;
shunt-resistor = <1000>;
};
- u82_soc: ina226@44 {
+ vdd_soc: ina226@44 {
compatible = "ti,ina226";
#io-channel-cells = <1>;
- label = "ina226-u82_soc";
+ label = "vdd_soc";
reg = <0x44>;
shunt-resistor = <1000>;
};
- u83_lpddr4: ina226@41 {
+ vdd_lpddr: ina226@41 {
compatible = "ti,ina226";
#io-channel-cells = <1>;
- label = "ina226-u83_lpddr4";
+ label = "vdd_lpddr";
reg = <0x41>;
shunt-resistor = <1000>;
};
- u99_dc: ina226@4c {
+ dc_in: ina226@48 {
compatible = "ti,ina226";
#io-channel-cells = <1>;
- label = "ina226-u99_dc";
- reg = <0x4c>;
+ label = "dc_in";
+ reg = <0x48>;
shunt-resistor = <1000>;
};
};
--
2.47.0

47
0027-fix-IOMMU-Add-ARCH_HAS_TEARDOWN_DMA_OPS.patch Normal file
View File

@ -0,0 +1,47 @@
From 763054bd5b4e8df600d71128ec1698341bd2aa5b Mon Sep 17 00:00:00 2001
From: linmin <linmin@eswincomputing.com>
Date: Mon, 29 Apr 2024 08:59:44 +0800
Subject: [PATCH 027/219] fix(IOMMU):Add ARCH_HAS_TEARDOWN_DMA_OPS
Changelogs:
1.Added "select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT"
in drivers/soc/sifive/Kconfig
2.Added arch_teardown_dma_ops() function in arch/riscv/mm/dma-noncoherent.c
---
arch/riscv/mm/dma-noncoherent.c | 7 +++++++
drivers/soc/sifive/Kconfig | 1 +
2 files changed, 8 insertions(+)
diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
index 75d3f1e6f884..ba27d4765fb7 100644
--- a/arch/riscv/mm/dma-noncoherent.c
+++ b/arch/riscv/mm/dma-noncoherent.c
@@ -138,6 +138,13 @@ void arch_dma_prep_coherent(struct page *page, size_t size)
ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size);
}
+#ifdef CONFIG_IOMMU_DMA
+void arch_teardown_dma_ops(struct device *dev)
+{
+ dev->dma_ops = NULL;
+}
+#endif
+
void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
const struct iommu_ops *iommu, bool coherent)
{
diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
index d78b8c3f72a8..f10259ca60ae 100644
--- a/drivers/soc/sifive/Kconfig
+++ b/drivers/soc/sifive/Kconfig
@@ -20,6 +20,7 @@ config ARCH_ESWIN_EIC770X_SOC_FAMILY
select ESWIN_RSV_MEMBLOCK
select ESWIN_CODACACHE_CONTROLLER
select IOMMU_DMA if IOMMU_SUPPORT
+ select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
menu "ESWIN EIC770X SoC Family Selection"
depends on ARCH_ESWIN_EIC770X_SOC_FAMILY
--
2.47.0

5401
0028-feat-Porting-hdmi-driver-to-linux-6.6.patch Normal file
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File diff suppressed because it is too large Load Diff

1903
0029-feat-DRM-Add-DSI-support-for-linux-6.6.patch Normal file
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File diff suppressed because it is too large Load Diff

1432
0030-feat-add-fan-rtc-wdt-dw-spi-pwm.patch Normal file
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File diff suppressed because it is too large Load Diff

1246
0031-feat-pvt_sensors-driver-to-linux-6.6.patch Normal file
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File diff suppressed because it is too large Load Diff

844
0032-refactor-khandle-dsp-subsys-drv.patch Normal file
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@ -0,0 +1,844 @@
From 69bb286081ce582b89095b4577289beb5e706822 Mon Sep 17 00:00:00 2001
From: donghuawei <donghuawei@eswincomputing.com>
Date: Fri, 24 May 2024 13:59:55 +0800
Subject: [PATCH 032/219] refactor:khandle, dsp subsys drv
Changelogs:
adaptor khandle, dsp subsys drv for linux-6.6
---
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile | 1 +
drivers/soc/eswin/Kconfig | 20 ++
drivers/soc/eswin/Makefile | 4 +
drivers/soc/eswin/dsp_subsys.c | 348 +++++++++++++++++++++++++++
drivers/soc/eswin/eswin-dsp-subsys.h | 44 ++++
drivers/soc/eswin/eswin-khandle.c | 242 +++++++++++++++++++
drivers/soc/eswin/eswin-khandle.h | 84 +++++++
drivers/soc/eswin/eswin_timer.h | 6 +
9 files changed, 750 insertions(+)
create mode 100644 drivers/soc/eswin/Kconfig
create mode 100644 drivers/soc/eswin/Makefile
create mode 100644 drivers/soc/eswin/dsp_subsys.c
create mode 100644 drivers/soc/eswin/eswin-dsp-subsys.h
create mode 100644 drivers/soc/eswin/eswin-khandle.c
create mode 100644 drivers/soc/eswin/eswin-khandle.h
create mode 100644 drivers/soc/eswin/eswin_timer.h
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index d21e75d69294..bc857765a996 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -24,6 +24,7 @@ source "drivers/soc/renesas/Kconfig"
source "drivers/soc/rockchip/Kconfig"
source "drivers/soc/samsung/Kconfig"
source "drivers/soc/sifive/Kconfig"
+source "drivers/soc/eswin/Kconfig"
source "drivers/soc/starfive/Kconfig"
source "drivers/soc/sunxi/Kconfig"
source "drivers/soc/tegra/Kconfig"
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 0706a27d13be..5dbaca5b7bac 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -29,6 +29,7 @@ obj-y += renesas/
obj-y += rockchip/
obj-$(CONFIG_SOC_SAMSUNG) += samsung/
obj-y += sifive/
+obj-y += eswin/
obj-y += sunxi/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-y += ti/
diff --git a/drivers/soc/eswin/Kconfig b/drivers/soc/eswin/Kconfig
new file mode 100644
index 000000000000..54179b920cc8
--- /dev/null
+++ b/drivers/soc/eswin/Kconfig
@@ -0,0 +1,20 @@
+if SOC_SIFIVE || SOC_STARFIVE
+
+config ESWIN_KHANDLE
+ bool "eswin kernel khandle functions"
+ default y
+ help
+ eswin realize this khandle, and mainly use for user process resource
+ mangement.
+
+config ESWIN_DSP_SUBSYS
+ tristate "Eswin dsp subsys"
+ default y
+ help
+ This is hardware-specific DSP subsys kernel driver for the eswin
+ hardware. It should be enabled to support dsp on eswin
+ platform.
+
+ If unsure, say N.
+
+endif
diff --git a/drivers/soc/eswin/Makefile b/drivers/soc/eswin/Makefile
new file mode 100644
index 000000000000..290bd185817f
--- /dev/null
+++ b/drivers/soc/eswin/Makefile
@@ -0,0 +1,4 @@
+obj-$(CONFIG_ESWIN_KHANDLE) += eswin-khandle.o
+obj-$(CONFIG_ESWIN_DSP_SUBSYS) += dsp_subsys.o
+
+
diff --git a/drivers/soc/eswin/dsp_subsys.c b/drivers/soc/eswin/dsp_subsys.c
new file mode 100644
index 000000000000..acf33631926a
--- /dev/null
+++ b/drivers/soc/eswin/dsp_subsys.c
@@ -0,0 +1,348 @@
+/*
+ * Program's name, and a brief idea of what it does（One line）.
+ * Copyright 20XX, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0-only
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/clk.h>
+#include <linux/win2030_noc.h>
+#include <dt-bindings/interconnect/eswin,win2030.h>
+#include "eswin-dsp-subsys.h"
+
+#define DRIVER_NAME "eswin-dsp-subsys"
+
+/**
+ * dsp_subsys_status - query the dsp subsys transaction status
+ *
+ * @void
+ *
+ * return: module transaction status on success , 1 if idle, 0 if busy.
+ * negative for error
+ * if can't get idle status in 3 seconds, return current status.
+ */
+static int dsp_subsys_status(void)
+{
+ unsigned long deadline = jiffies + 3 * HZ;
+ int status = 0;
+
+ do {
+ status = win2030_noc_sideband_mgr_query(SBM_DSPT_SNOC);
+ status |= win2030_noc_sideband_mgr_query(SBM_CNOC_DSPT);
+ if (0 != status) {
+ break;
+ }
+ schedule();
+ } while (time_before(jiffies, deadline));
+
+ return status;
+}
+
+static inline int dsp_subsys_clk_init(struct platform_device *pdev,
+ struct es_dsp_subsys *subsys)
+{
+ int ret;
+
+ subsys->cfg_clk = devm_clk_get(&pdev->dev, "cfg_clk");
+ if (IS_ERR(subsys->cfg_clk)) {
+ ret = PTR_ERR(subsys->cfg_clk);
+ dev_err(&pdev->dev, "failed to get cfg_clk: %d\n", ret);
+ return ret;
+ }
+ return 0;
+}
+
+static int dsp_subsys_reset(struct es_dsp_subsys *subsys)
+{
+ int ret;
+
+ /*reset dsp bus*/
+ ret = reset_control_reset(subsys->rstc_axi);
+ WARN_ON(0 != ret);
+
+ ret = reset_control_reset(subsys->rstc_div4);
+ WARN_ON(0 != ret);
+
+ /*reset dsp cfg*/
+ ret = reset_control_reset(subsys->rstc_cfg);
+ WARN_ON(0 != ret);
+
+ /*reset dsp core clk div*/
+ ret = reset_control_reset(subsys->rstc_div_0);
+ WARN_ON(0 != ret);
+
+ ret = reset_control_reset(subsys->rstc_div_1);
+ WARN_ON(0 != ret);
+
+ ret = reset_control_reset(subsys->rstc_div_2);
+ WARN_ON(0 != ret);
+
+ ret = reset_control_reset(subsys->rstc_div_3);
+ WARN_ON(0 != ret);
+
+ return 0;
+}
+
+static int dsp_subsys_clk_enable(struct es_dsp_subsys *subsys)
+{
+ int ret;
+
+ ret = clk_prepare_enable(subsys->cfg_clk);
+ if (ret) {
+ dev_err(&subsys->pdev->dev, "failed to enable cfg_clk: %d\n", ret);
+ return ret;
+ }
+ return 0;
+}
+
+static int dsp_subsys_reset_init(struct platform_device *pdev,
+ struct es_dsp_subsys *subsys)
+{
+ subsys->rstc_axi = devm_reset_control_get_optional(&pdev->dev, "axi");
+ if (IS_ERR_OR_NULL(subsys->rstc_axi)) {
+ dev_err(&subsys->pdev->dev, "Failed to get axi reset handle\n");
+ return -EFAULT;
+ }
+
+ subsys->rstc_div4 = devm_reset_control_get_optional(&pdev->dev, "div4");
+ if (IS_ERR_OR_NULL(subsys->rstc_div4)) {
+ dev_err(&subsys->pdev->dev, "Failed to div4 reset handle\n");
+ return -EFAULT;
+ }
+
+ subsys->rstc_cfg = devm_reset_control_get_optional(&pdev->dev, "cfg");
+ if (IS_ERR_OR_NULL(subsys->rstc_cfg)) {
+ dev_err(&subsys->pdev->dev, "Failed to get cfg reset handle\n");
+ return -EFAULT;
+ }
+
+ subsys->rstc_div_0 = devm_reset_control_get_optional(&pdev->dev, "div_0");
+ if (IS_ERR_OR_NULL(subsys->rstc_div_0)) {
+ dev_err(&subsys->pdev->dev, "Failed to div_0 reset handle\n");
+ return -EFAULT;
+ }
+ subsys->rstc_div_1 = devm_reset_control_get_optional(&pdev->dev, "div_1");
+ if (IS_ERR_OR_NULL(subsys->rstc_div_1)) {
+ dev_err(&subsys->pdev->dev, "Failed to div_1 reset handle\n");
+ return -EFAULT;
+ }
+ subsys->rstc_div_2 = devm_reset_control_get_optional(&pdev->dev, "div_2");
+ if (IS_ERR_OR_NULL(subsys->rstc_div_2)) {
+ dev_err(&subsys->pdev->dev, "Failed to div_2 reset handle\n");
+ return -EFAULT;
+ }
+ subsys->rstc_div_3 = devm_reset_control_get_optional(&pdev->dev, "div_3");
+ if (IS_ERR_OR_NULL(subsys->rstc_div_3)) {
+ dev_err(&subsys->pdev->dev, "Failed to div_3 reset handle\n");
+ return -EFAULT;
+ }
+ return 0;
+}
+
+static int dsp_subsys_reg_read(void *context, unsigned int reg,
+ unsigned int *val)
+{
+ struct es_dsp_subsys *subsys = context;
+
+ *val = readl_relaxed(subsys->reg_base + reg);
+ return 0;
+}
+
+static int dsp_subsys_reg_write(void *context, unsigned int reg,
+ unsigned int val)
+{
+ struct es_dsp_subsys *subsys = context;
+
+ writel_relaxed(val, subsys->reg_base + reg);
+ return 0;
+}
+
+static int dsp_subsys_con_reg_read(void *context, unsigned int reg,
+ unsigned int *val)
+{
+ struct es_dsp_subsys *subsys = context;
+
+ *val = readl_relaxed(subsys->con_reg_base + reg);
+ return 0;
+}
+
+static int dsp_subsys_con_reg_write(void *context, unsigned int reg,
+ unsigned int val)
+{
+ struct es_dsp_subsys *subsys = context;
+
+ writel_relaxed(val, subsys->con_reg_base + reg);
+ return 0;
+}
+
+/**
+ * dsp_subsys_init_regmap() - Initialize registers map
+ *
+ * Autodetects needed register access mode and creates the regmap with
+ * corresponding read/write callbacks. This must be called before doing any
+ * other register access.
+ */
+static int dsp_subsys_init_regmap(struct es_dsp_subsys *subsys)
+{
+ struct regmap_config map_cfg = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .use_hwlock = true,
+ .cache_type = REGCACHE_NONE,
+ .can_sleep = false,
+ .reg_read = dsp_subsys_reg_read,
+ .reg_write = dsp_subsys_reg_write,
+ };
+ struct regmap_config con_map_cfg = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .use_hwlock = true,
+ .cache_type = REGCACHE_NONE,
+ .can_sleep = false,
+ .reg_read = dsp_subsys_con_reg_read,
+ .reg_write = dsp_subsys_con_reg_write,
+ };
+
+ /*
+ * Note we'll check the return value of the regmap IO accessors only
+ * at the probe stage. The rest of the code won't do this because
+ * basically we have MMIO-based regmap so non of the read/write methods
+ * can fail.
+ */
+ subsys->map = devm_regmap_init(&subsys->pdev->dev, NULL, subsys, &map_cfg);
+ if (IS_ERR(subsys->map)) {
+ dev_err(&subsys->pdev->dev, "Failed to init the registers map\n");
+ return PTR_ERR(subsys->map);
+ }
+
+ subsys->con_map = devm_regmap_init(&subsys->pdev->dev, NULL, subsys, &con_map_cfg);
+ if (IS_ERR(subsys->con_map)) {
+ dev_err(&subsys->pdev->dev, "Failed to init the con registers map\n");
+ return PTR_ERR(subsys->con_map);
+ }
+
+ return 0;
+}
+
+static int es_dsp_subsys_probe(struct platform_device *pdev)
+{
+ struct es_dsp_subsys *subsys;
+ int ret;
+ struct resource *res;
+
+ dev_info(&pdev->dev, "%s\n", __func__);
+ subsys = devm_kzalloc(&pdev->dev, sizeof(*subsys), GFP_KERNEL);
+ if (!subsys) {
+ return -ENOMEM;
+ }
+
+ dev_set_drvdata(&pdev->dev, subsys);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENODEV;
+
+ subsys->reg_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR_OR_NULL(subsys->reg_base)) {
+ return PTR_ERR(subsys->reg_base);
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (!res)
+ return -ENODEV;
+
+ subsys->con_reg_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR_OR_NULL(subsys->con_reg_base)) {
+ return PTR_ERR(subsys->con_reg_base);
+ }
+
+ subsys->pdev = pdev;
+
+ ret = dsp_subsys_init_regmap(subsys);
+ if (0 != ret) {
+ return -ENODEV;
+ }
+
+ ret = dsp_subsys_reset_init(pdev, subsys);
+ if (0 != ret) {
+ return ret;
+ }
+
+ ret = dsp_subsys_clk_init(pdev, subsys);
+ if (0 != ret) {
+ return ret;
+ }
+
+ ret = dsp_subsys_clk_enable(subsys);
+ if (0 != ret) {
+ return ret;
+ }
+
+ ret = dsp_subsys_reset(subsys);
+ if (0 != ret) {
+ return ret;
+ }
+
+ subsys->dsp_subsys_status = dsp_subsys_status;
+
+ /* enable qos */
+ // win2030_noc_qos_set("DSPT");
+
+ return 0;
+}
+
+static int es_dsp_subsys_remove(struct platform_device *pdev)
+{
+ struct es_dsp_subsys *subsys = dev_get_drvdata(&pdev->dev);
+ if (subsys) {
+ clk_disable_unprepare(subsys->cfg_clk);
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id es_dsp_subsys_match[] = {
+ {
+ .compatible = "es-dsp-subsys",
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, es_dsp_subsys_match);
+#endif
+
+static struct platform_driver es_dsp_subsys_driver = {
+ .probe = es_dsp_subsys_probe,
+ .remove = es_dsp_subsys_remove,
+ .driver = {
+ .name = DRIVER_NAME,
+ .of_match_table = of_match_ptr(es_dsp_subsys_match),
+ },
+};
+
+module_platform_driver(es_dsp_subsys_driver);
+
+MODULE_AUTHOR("Eswin");
+MODULE_DESCRIPTION("DSP: Low Level Device Driver For Eswin DSP");
+MODULE_LICENSE("Dual MIT/GPL");
diff --git a/drivers/soc/eswin/eswin-dsp-subsys.h b/drivers/soc/eswin/eswin-dsp-subsys.h
new file mode 100644
index 000000000000..4933411fde94
--- /dev/null
+++ b/drivers/soc/eswin/eswin-dsp-subsys.h
@@ -0,0 +1,44 @@
+/*
+ * Program's name, and a brief idea of what it does（One line）.
+ * Copyright 20XX, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0-only
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ESWIN_DSP_SUBSYS_H__
+#define __ESWIN_DSP_SUBSYS_H__
+#include <linux/reset.h>
+#include <linux/regmap.h>
+#include <linux/platform_device.h>
+
+typedef int (*dsp_subsys_status_pfunc)(void);
+
+struct es_dsp_subsys {
+ void __iomem *reg_base;
+ void __iomem *con_reg_base;
+ struct regmap *map;
+ struct regmap *con_map;
+ struct platform_device *pdev;
+
+ struct reset_control *rstc_axi;
+ struct reset_control *rstc_cfg;
+ struct reset_control *rstc_div4;
+ struct reset_control *rstc_div_0;
+ struct reset_control *rstc_div_1;
+ struct reset_control *rstc_div_2;
+ struct reset_control *rstc_div_3;
+ struct clk *cfg_clk;
+ dsp_subsys_status_pfunc dsp_subsys_status;
+};
+#endif
\ No newline at end of file
diff --git a/drivers/soc/eswin/eswin-khandle.c b/drivers/soc/eswin/eswin-khandle.c
new file mode 100644
index 000000000000..055615a17b7a
--- /dev/null
+++ b/drivers/soc/eswin/eswin-khandle.c
@@ -0,0 +1,242 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include "eswin-khandle.h"
+#include <linux/vmalloc.h>
+#include <asm/atomic.h>
+#include <linux/xarray.h>
+
+struct fd_pool_desc {
+ spinlock_t lock;
+ struct xarray fd_array;
+};
+
+static void init_fd_pool(void *fd_pool)
+{
+ struct fd_pool_desc *pool = (struct fd_pool_desc *)fd_pool;
+ pr_debug("%s, %d, pool=0x%px", __func__, __LINE__, pool);
+ xa_init_flags(&pool->fd_array, XA_FLAGS_ALLOC);
+ spin_lock_init(&pool->lock);
+}
+
+static int alloc_fd(void *fd_pool, struct khandle *h)
+{
+ struct fd_pool_desc *pool = (struct fd_pool_desc *)fd_pool;
+ int ret;
+ u32 fd;
+
+ pr_debug("%s, %d, pool=0x%px", __func__, __LINE__, pool);
+ ret = xa_alloc(&pool->fd_array, &fd, h, xa_limit_32b, GFP_ATOMIC);
+ if (ret < 0) {
+ pr_err("%s, %d, ret=%d.\n", __func__, __LINE__, ret);
+ return ret;
+ }
+ pr_debug("%s, %d, pool=0x%px, fd=%d.\n", __func__, __LINE__, pool, fd);
+ return fd;
+}
+
+static void release_fd(void *fd_pool, int fd)
+{
+ unsigned long flags;
+ struct khandle *h;
+ struct fd_pool_desc *pool = (struct fd_pool_desc *)fd_pool;
+
+ pr_debug("%s, %d, pool=0x%px, fd=%d.\n", __func__, __LINE__, pool, fd);
+
+ spin_lock_irqsave(&pool->lock, flags);
+ h = xa_load(&pool->fd_array, fd);
+ if (!h) {
+ spin_unlock_irqrestore(&pool->lock, flags);
+ return;
+ }
+ xa_erase(&pool->fd_array, fd);
+ spin_unlock_irqrestore(&pool->lock, flags);
+}
+
+static struct khandle *find_khandle_by_fd(void *fd_pool, int fd)
+{
+ unsigned long flags;
+ struct khandle *h;
+ struct fd_pool_desc *pool = (struct fd_pool_desc *)fd_pool;
+
+ spin_lock_irqsave(&pool->lock, flags);
+ h = xa_load(&pool->fd_array, fd);
+ if (h == NULL) {
+ spin_unlock_irqrestore(&pool->lock, flags);
+ return NULL;
+ }
+ kref_get(&h->refcount);
+ spin_unlock_irqrestore(&pool->lock, flags);
+ return h;
+}
+
+static void kref_khandle_fn(struct kref *kref)
+{
+ unsigned long flags;
+ struct khandle *h = container_of(kref, struct khandle, refcount);
+ struct khandle *parent;
+ struct fd_pool_desc *pool;
+
+ pr_debug("%s, h address=0x%px.\n", __func__, h);
+ BUG_ON(h == NULL);
+ BUG_ON(h->fd != INVALID_HANDLE_VALUE);
+
+ pr_debug("%s, k->fd=%d, refcount=%d.\n", __func__, h->fd,
+ kref_read(kref));
+
+ parent = h->parent;
+
+ if (parent == NULL) {
+ pool = h->fd_pool;
+ xa_destroy(&pool->fd_array);
+ vfree(h->fd_pool);
+ } else {
+ spin_lock_irqsave(&parent->lock, flags);
+ list_del_init(&h->entry);
+ spin_unlock_irqrestore(&parent->lock, flags);
+ }
+
+ if (h->fn != NULL) {
+ h->fn(h);
+ }
+
+ if (parent != NULL) {
+ kref_put(&parent->refcount, kref_khandle_fn);
+ }
+}
+
+void kernel_handle_addref(struct khandle *h)
+{
+ BUG_ON(h == NULL);
+
+ kref_get(&h->refcount);
+ pr_debug("%s, h addr=0x%px, fd=%d, refcount=%d.\n", __func__, h, h->fd,
+ kref_read(&h->refcount));
+}
+EXPORT_SYMBOL(kernel_handle_addref);
+
+void kernel_handle_decref(struct khandle *h)
+{
+ BUG_ON(h == NULL);
+
+ kref_put(&h->refcount, kref_khandle_fn);
+ pr_debug("%s, done.\n", __func__);
+}
+EXPORT_SYMBOL(kernel_handle_decref);
+
+static struct list_head *capture_next_khandle_node(struct list_head *head,
+ struct list_head *cur)
+{
+ struct khandle *h;
+
+ while (true) {
+ cur = cur->next;
+ if (cur == head) {
+ return cur;
+ }
+
+ /* Protect child not released until return of kernel_handle_release_family. */
+ h = container_of(cur, struct khandle, entry);
+ if (kref_get_unless_zero(&h->refcount) != 0) {
+ return cur;
+ }
+ }
+}
+
+void kernel_handle_release_family(struct khandle *h)
+{
+ unsigned long flags;
+ struct list_head *child;
+ struct khandle *child_khandle;
+
+ BUG_ON(h == NULL);
+ spin_lock_irqsave(&h->lock, flags);
+ if (h->fd == INVALID_HANDLE_VALUE) {
+ spin_unlock_irqrestore(&h->lock, flags);
+ return;
+ }
+
+ release_fd(h->fd_pool, h->fd);
+ h->fd = INVALID_HANDLE_VALUE;
+ child = capture_next_khandle_node(&h->head, &h->head);
+ while (child != &h->head) {
+ child_khandle = container_of(child, struct khandle, entry);
+ child = capture_next_khandle_node(&h->head, child);
+ spin_unlock_irqrestore(&h->lock, flags);
+ kernel_handle_release_family(child_khandle);
+ kernel_handle_decref(child_khandle);
+ spin_lock_irqsave(&h->lock, flags);
+ }
+
+ spin_unlock_irqrestore(&h->lock, flags);
+ kref_put(&h->refcount, kref_khandle_fn);
+ pr_debug("%s, done.\n", __func__);
+}
+EXPORT_SYMBOL(kernel_handle_release_family);
+
+int init_kernel_handle(struct khandle *h, release_khandle_fn fn, int magic,
+ struct khandle *parent)
+{
+ unsigned long flags;
+ void *fd_pool;
+
+ BUG_ON(h == NULL);
+ kref_init(&h->refcount);
+ kref_get(&h->refcount);
+
+ if ((h->parent = parent) == NULL) {
+ fd_pool = vmalloc(sizeof(struct fd_pool_desc));
+ init_fd_pool(fd_pool);
+ if (fd_pool == NULL) {
+ return -ENOMEM;
+ }
+ } else {
+ fd_pool = parent->fd_pool;
+ }
+ h->fd_pool = fd_pool;
+
+ if ((h->fd = alloc_fd(fd_pool, h)) == INVALID_HANDLE_VALUE) {
+ BUG_ON(parent == NULL);
+ return -EINVAL;
+ }
+
+ pr_debug("%s, hfile addr=%u.\n", __func__, h->fd);
+ h->fn = fn;
+ h->magic = magic;
+ spin_lock_init(&h->lock);
+
+ INIT_LIST_HEAD(&h->head);
+ INIT_LIST_HEAD(&h->entry);
+
+ if (parent != NULL) {
+ spin_lock_irqsave(&parent->lock, flags);
+ if (parent->fd == INVALID_HANDLE_VALUE) {
+ spin_unlock_irqrestore(&parent->lock, flags);
+ release_fd(fd_pool, h->fd);
+ return -EINVAL;
+ }
+
+ list_add_tail(&h->entry, &parent->head);
+ kref_get(&parent->refcount);
+ spin_unlock_irqrestore(&parent->lock, flags);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(init_kernel_handle);
+
+struct khandle *find_kernel_handle(struct khandle *ancestor, int fd, int magic)
+{
+ struct khandle *h;
+
+ h = find_khandle_by_fd(ancestor->fd_pool, fd);
+ if (h == NULL) {
+ return NULL;
+ }
+
+ if (h->magic != magic) {
+ kref_put(&h->refcount, kref_khandle_fn);
+ return NULL;
+ }
+ return h;
+}
+EXPORT_SYMBOL(find_kernel_handle);
diff --git a/drivers/soc/eswin/eswin-khandle.h b/drivers/soc/eswin/eswin-khandle.h
new file mode 100644
index 000000000000..7e086388890a
--- /dev/null
+++ b/drivers/soc/eswin/eswin-khandle.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ESWIN_KHANDLE_H_
+#define __ESWIN_KHANDLE_H_
+
+#include <linux/kref.h>
+#include <linux/types.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+
+#define INVALID_HANDLE_VALUE (-1)
+
+struct khandle;
+typedef void (*release_khandle_fn)(struct khandle *h);
+struct khandle {
+ int fd;
+ int magic;
+ spinlock_t lock;
+ release_khandle_fn fn;
+ struct kref refcount;
+ struct list_head entry;
+ struct list_head head;
+ struct khandle *parent;
+ void *fd_pool;
+};
+
+/**
+ * @brief Remove the family relations hierachy. This function also actively
+ * free the fd of this kernel object and its descendants.
+ *
+ * @param o: This is the kernel object.
+ */
+void kernel_handle_release_family(struct khandle *o);
+
+/**
+ * @brief Decrease the reference of kernel object `o`. If reference reaches 0,
+ * the release delegation function is called.
+ *
+ * @param o: This is the kernel object.
+ */
+void kernel_handle_decref(struct khandle *o);
+
+
+/**
+ * @brief Increase the reference of kernel object `o`.
+ *
+ * @param o: This is the kernel object.
+ */
+void kernel_handle_addref(struct khandle *o);
+
+
+/**
+ * @brief This function intialize an kernel object in the memory specified by
+ * `o`. It returns zero on success or a Linux error code. Note this function
+ * should only be called in IOCtl context. The initial reference is set to 1.
+ *
+ * @param o: This specifies an memory for holding kernel object.
+ * @param fn: This points to a callback delegation function. When the
+ * reference of `o` reaches 0, this callback function is called. It
+ * is intended for releasing resources associated with this kernel
+ * object.
+ * @param magic: This is a magic number for determining the type of kernel
+ * object.
+ * @param parent: Points to the parent of this kernel object.
+ * @return It returns zero on success or a Linux error code.
+ *
+ * when use khandle, host structure release must use kernel_handle_decref function.
+ */
+int init_kernel_handle(struct khandle *o, release_khandle_fn fn, int magic,
+ struct khandle *parent);
+
+
+/**
+ * @brief This function is used to find the kernel object associated with fd.
+ * Note the khandle object has one additional reference so user should dereference
+ * it if not needed.
+ *
+ * @param ancestor: This is one ancestor of kernel object that matches fd.
+ * @param fd: This is the fd associated with a specific kernel object.
+ * @param magic: This is the magic associated with a specific kernel object.
+ * @return It returns the kernel object on success or NULL if the given fd
+ * is invalid.
+ */
+struct khandle *find_kernel_handle(struct khandle *ancestor, int fd, int magic);
+#endif
diff --git a/drivers/soc/eswin/eswin_timer.h b/drivers/soc/eswin/eswin_timer.h
new file mode 100644
index 000000000000..a7fac84ac613
--- /dev/null
+++ b/drivers/soc/eswin/eswin_timer.h
@@ -0,0 +1,6 @@
+#ifndef __ESWIN_TIMER_H_
+#define __ESWIN_TIMER_H_
+
+extern u32 get_perf_timer_cnt(void);
+
+#endif
--
2.47.0

157
0033-fix-modify-fan-control-and-read-fan-speed.patch Normal file
View File

@ -0,0 +1,157 @@
From eca0f7949ff41c8dea336792e91d5863b4ed59af Mon Sep 17 00:00:00 2001
From: yangwei1 <yangwei1@eswincomputing.com>
Date: Fri, 24 May 2024 19:55:33 +0800
Subject: [PATCH 033/219] fix:modify fan control and read fan speed
Changelogs:
eswin,pwm_inverted enable pwm invert
---
arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts | 1 +
.../dts/eswin/eswin-win2030-die0-soc.dtsi | 2 +-
drivers/hwmon/eswin-fan-control.c | 42 ++++++++++++++-----
3 files changed, 33 insertions(+), 12 deletions(-)
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
index 93fa224c75b7..922db5ee1d4c 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
@@ -688,6 +688,7 @@ &d0_mbox7 {
&fan_control {
status = "okay";
+ eswin,pwm_inverted;
};
&d0_i2c0 {
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
index 430c5410bdda..0371d532d2ec 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
@@ -1289,7 +1289,7 @@ fan_control: fan_control@50b50000 {
interrupt-parent = <&plic0>;
interrupt-names = "fanirq";
interrupts = <354>;
- pulses-per-revolution = <1>;
+ pulses-per-revolution = <2>;
pwm-minimun-period = <1000>;
pwms = <&pwm0 0 100000>;
pinctrl-names = "default";
diff --git a/drivers/hwmon/eswin-fan-control.c b/drivers/hwmon/eswin-fan-control.c
index 9c8ab39dee30..f7ca5c29520b 100644
--- a/drivers/hwmon/eswin-fan-control.c
+++ b/drivers/hwmon/eswin-fan-control.c
@@ -62,6 +62,7 @@ struct eswin_fan_control_data {
u32 ppr;
/* revolutions per minute */
u32 rpm;
+ u8 pwm_inverted;
};
static inline void fan_iowrite(const u32 val, const u32 reg,
@@ -81,9 +82,14 @@ static ssize_t eswin_fan_pwm_ctl_show(struct device *dev, struct device_attribut
struct eswin_fan_control_data *ctl = dev_get_drvdata(dev);
struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
long temp = 0;
-
+ long period = 0;
if (FAN_PWM_DUTY == attr->index) {
temp = pwm_get_duty_cycle(ctl->pwm);
+ if(1 == ctl->pwm_inverted)
+ {
+ period = pwm_get_period(ctl->pwm);
+ temp = period- temp;
+ }
}
else if (FAN_PWM_PERIOD == attr->index) {
temp = pwm_get_period(ctl->pwm);
@@ -110,8 +116,14 @@ static ssize_t eswin_fan_pwm_ctl_store(struct device *dev, struct device_attribu
ret = kstrtoul(buf, 10, &val);
if (ret)
return ret;
-
- state.duty_cycle = val;
+ if(1 == ctl->pwm_inverted)
+ {
+ state.duty_cycle = state.period - val;
+ }
+ else
+ {
+ state.duty_cycle = val;
+ }
}
else if (FAN_PWM_PERIOD == attr->index) {
long val = 0;
@@ -168,9 +180,7 @@ static long eswin_fan_control_get_fan_rpm(struct eswin_fan_control_data *ctl)
ctl->wait_flag = false;
period = pwm_get_period(ctl->pwm);
- timeout = TIMEOUT(period);
- if(!timeout)
- timeout = TIMEOUT(ctl->min_period);
+ timeout = msecs_to_jiffies(1500);
val = fan_ioread(REG_FAN_INT, ctl);
val = val | 0x1;
@@ -185,7 +195,6 @@ static long eswin_fan_control_get_fan_rpm(struct eswin_fan_control_data *ctl)
/* timeout, set rpm to 0 */
ctl->rpm = 0;
}
-
if(ctl->rpm)
ctl->rpm = DIV_ROUND_CLOSEST(60 * ctl->clk_rate, ctl->ppr * ctl->rpm);
@@ -215,6 +224,10 @@ static int eswin_fan_control_read_pwm(struct device *dev, u32 attr, long *val)
switch (attr) {
case hwmon_pwm_input:
*val = eswin_fan_control_get_pwm_duty(ctl);
+ if(1 == ctl->pwm_inverted)
+ {
+ *val = 100 - *val;
+ }
return 0;
default:
return -ENOTSUPP;
@@ -235,13 +248,21 @@ static int eswin_fan_control_set_pwm_duty(const long val, struct eswin_fan_contr
static int eswin_fan_control_write_pwm(struct device *dev, u32 attr, long val)
{
struct eswin_fan_control_data *ctl = dev_get_drvdata(dev);
-
switch (attr) {
case hwmon_pwm_input:
- if((val < 0)||(val > 100))
+ if((val < 10) || (val > 99))
+ {
+ dev_err(dev,"pwm range is form 10 to 99\n");
return -EINVAL;
+ }
else
+ {
+ if(1 == ctl->pwm_inverted)
+ {
+ val = 100 - val;
+ }
return eswin_fan_control_set_pwm_duty(val, ctl);
+ }
default:
return -ENOTSUPP;
}
@@ -413,7 +434,6 @@ MODULE_DEVICE_TABLE(of, eswin_fan_control_of_match);
static int eswin_fan_control_probe(struct platform_device *pdev)
{
struct eswin_fan_control_data *ctl;
- struct clk *clk;
const struct of_device_id *id;
const char *name = "eswin_fan_control";
struct pwm_state state;
@@ -455,7 +475,7 @@ static int eswin_fan_control_probe(struct platform_device *pdev)
}
ret = reset_control_reset(ctl->fan_rst);
WARN_ON(0 != ret);
-
+ ctl->pwm_inverted = of_property_read_bool(pdev->dev.of_node, "eswin,pwm_inverted");
init_waitqueue_head(&ctl->wq);
ctl->irq = platform_get_irq(pdev, 0);
--
2.47.0

26
0034-fix-Add-rtc-pcf8573-driver-in-win2030_defconfig.patch Normal file
View File

@ -0,0 +1,26 @@
From 31957579e462e3d7087c52d66980edf6ea207a8f Mon Sep 17 00:00:00 2001
From: huangyifeng <huangyifeng@eswincomputing.com>
Date: Tue, 28 May 2024 09:37:29 +0800
Subject: [PATCH 034/219] fix:Add rtc(pcf8573) driver in win2030_defconfig
Changelogs:
Add rtc(pcf8573) driver in win2030_defconfig
---
arch/riscv/configs/win2030_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig
index 8d5ad3f19306..7311283d7c6d 100644
--- a/arch/riscv/configs/win2030_defconfig
+++ b/arch/riscv/configs/win2030_defconfig
@@ -247,6 +247,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
CONFIG_EDAC=y
CONFIG_EDAC_ESWIN=y
CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PCF8563=y
CONFIG_DMADEVICES=y
CONFIG_DW_AXI_DMAC=y
CONFIG_DMATEST=y
--
2.47.0

142
0035-fix-add-sysfs-in-pac1934-to-set-update-interval.patch Normal file
View File

@ -0,0 +1,142 @@
From c794d32357bd8ae6f652929e9e823ec70157cbbb Mon Sep 17 00:00:00 2001
From: yangwei1 <yangwei1@eswincomputing.com>
Date: Mon, 27 May 2024 14:44:34 +0800
Subject: [PATCH 035/219] fix:add sysfs in pac1934 to set update interval
Changelogs:
1.read and modify the value by update_interval in it's hwmon
2.the path is /sys/class/hwmon/hwmon*/update_interval or /sys/devices/platform/soc/51838000.i2c/i2c-*/*-0010/hwmon/hwmon*/update_interval
---
drivers/hwmon/pac193x.c | 53 +++++++++++++++++++++++++++++++++++++----
1 file changed, 48 insertions(+), 5 deletions(-)
diff --git a/drivers/hwmon/pac193x.c b/drivers/hwmon/pac193x.c
index ebad3bde611e..ae2735139729 100644
--- a/drivers/hwmon/pac193x.c
+++ b/drivers/hwmon/pac193x.c
@@ -252,11 +252,11 @@ static ssize_t pac193x_refresh_store(struct device *dev,
}
static struct sensor_device_attribute pac1934_refreshs[] = {
- SENSOR_ATTR_WO(refresh_clear_acc, pac193x_refresh, PAC193X_CMD_REFRESH),
- SENSOR_ATTR_WO(refresh_all_193x, pac193x_refresh,
+ SENSOR_ATTR_WO(reset_energy_history, pac193x_refresh, PAC193X_CMD_REFRESH),
+ /* SENSOR_ATTR_WO(refresh_all_193x, pac193x_refresh,
PAC193X_CMD_REFRESH_G),
SENSOR_ATTR_WO(refresh_updata_value, pac193x_refresh,
- PAC193X_CMD_REFRESH_V),
+ PAC193X_CMD_REFRESH_V), */
};
static u8 pac193x_read_byte_data(struct pac193x_data *data, u8 command)
@@ -491,14 +491,15 @@ static struct attribute *pac193x_attrs[] = {
&dev_attr_slow_ctrl.attr,
&dev_attr_pac193x_version.attr,
&pac1934_refreshs[0].dev_attr.attr,
- &pac1934_refreshs[1].dev_attr.attr,
- &pac1934_refreshs[2].dev_attr.attr,
+ /* &pac1934_refreshs[1].dev_attr.attr,
+ &pac1934_refreshs[2].dev_attr.attr, */
NULL,
};
ATTRIBUTE_GROUPS(pac193x);
static const struct hwmon_channel_info *pac1931_info[] = {
+ HWMON_CHANNEL_INFO(chip, HWMON_C_UPDATE_INTERVAL),
HWMON_CHANNEL_INFO(in, HWMON_I_INPUT | HWMON_I_AVERAGE,
HWMON_I_INPUT | HWMON_I_AVERAGE),
HWMON_CHANNEL_INFO(curr, HWMON_C_INPUT | HWMON_C_AVERAGE),
@@ -506,6 +507,7 @@ static const struct hwmon_channel_info *pac1931_info[] = {
HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT),
NULL};
static const struct hwmon_channel_info *pac1932_info[] = {
+ HWMON_CHANNEL_INFO(chip, HWMON_C_UPDATE_INTERVAL),
HWMON_CHANNEL_INFO(in, HWMON_I_INPUT | HWMON_I_AVERAGE,
HWMON_I_INPUT | HWMON_I_AVERAGE,
HWMON_I_INPUT | HWMON_I_AVERAGE),
@@ -515,6 +517,7 @@ static const struct hwmon_channel_info *pac1932_info[] = {
HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT, HWMON_E_INPUT),
NULL};
static const struct hwmon_channel_info *pac1933_info[] = {
+ HWMON_CHANNEL_INFO(chip, HWMON_C_UPDATE_INTERVAL),
HWMON_CHANNEL_INFO(in, HWMON_I_INPUT | HWMON_I_AVERAGE,
HWMON_I_INPUT | HWMON_I_AVERAGE,
HWMON_I_INPUT | HWMON_I_AVERAGE,
@@ -526,6 +529,7 @@ static const struct hwmon_channel_info *pac1933_info[] = {
HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT, HWMON_E_INPUT, HWMON_E_INPUT),
NULL};
static const struct hwmon_channel_info *pac1934_info[] = {
+ HWMON_CHANNEL_INFO(chip, HWMON_C_UPDATE_INTERVAL),
HWMON_CHANNEL_INFO(in,
HWMON_I_INPUT | HWMON_I_AVERAGE,
HWMON_I_INPUT | HWMON_I_AVERAGE | HWMON_I_LABEL,
@@ -553,6 +557,13 @@ static umode_t pac1934x_is_visible(const void *_data,
{
switch (type)
{
+ case hwmon_chip:
+ switch (attr)
+ {
+ case hwmon_chip_update_interval:
+ return 0644;
+ }
+ break;
case hwmon_in:
switch (attr)
{
@@ -662,8 +673,17 @@ static int pac1934x_read_string(struct device *dev,
static int pac193x_read(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long *val)
{
+ struct pac193x_data *data = dev_get_drvdata(dev);
switch (type)
{
+ case hwmon_chip:
+ switch (attr)
+ {
+ case hwmon_chip_update_interval:
+ *val = data->update_time_ms;
+ break;
+ }
+ break;
case hwmon_in:
switch (attr)
{
@@ -708,10 +728,33 @@ static int pac193x_read(struct device *dev, enum hwmon_sensor_types type,
return 0;
}
+static int pac193x_write(struct device *dev, enum hwmon_sensor_types type,
+ u32 attr, int channel, long val)
+{
+ struct pac193x_data *data = dev_get_drvdata(dev);
+ switch (type)
+ {
+ case hwmon_chip:
+ switch (attr)
+ {
+ case hwmon_chip_update_interval:
+ data->update_time_ms = val;
+ mod_delayed_work(data->update_workqueue, &data->update_work,
+ msecs_to_jiffies(data->update_time_ms));
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
static const struct hwmon_ops pac193x_hwmon_ops = {
.is_visible = pac1934x_is_visible,
.read = pac193x_read,
.read_string = pac1934x_read_string,
+ .write = pac193x_write,
};
static struct hwmon_chip_info pac193x_chip_info = {
--
2.47.0

287
0036-feat-llc_spram-set-npu-default-freq-to-1.5G.patch Normal file
View File

@ -0,0 +1,287 @@
From 5b1e406cb99c9bb18f107ccd8895140a72173e9c Mon Sep 17 00:00:00 2001
From: yangwei1 <yangwei1@eswincomputing.com>
Date: Tue, 28 May 2024 10:37:37 +0800
Subject: [PATCH 036/219] feat(llc_spram):set npu default freq to 1.5G
Changelogs:
1.Added apply_npu_high_freq attribute in the dev_llc_d0 dts node to set npu default freq to 1.5G
and voltage to 1.05V. If apply_npu_high_freq is not configured, then set npu freq to 1.04G
and voltage to 0.8V
---
arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts | 3 +
arch/riscv/boot/dts/eswin/eic7700-evb.dts | 3 +
.../dts/eswin/eswin-win2030-die0-soc.dtsi | 6 +-
.../dts/eswin/eswin-win2030-die1-soc.dtsi | 6 +-
drivers/memory/eswin/codacache/llc_spram.c | 111 +++++++++++++++---
include/linux/eswin_npu.h | 4 +
6 files changed, 110 insertions(+), 23 deletions(-)
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
index 922db5ee1d4c..584338c8ad4c 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
@@ -902,3 +902,6 @@ gpio111 : mipi dsi resetn(O)
&gpio0 {
status = "okay";
};
+&dev_llc_d0{
+ apply_npu_high_freq;
+};
\ No newline at end of file
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb.dts b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
index 642a62246b54..4ed625ef7bd3 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
@@ -879,3 +879,6 @@ gpio111 : mipi dsi resetn(O)
&gpio0 {
status = "okay";
};
+&dev_llc_d0{
+ apply_npu_high_freq;
+};
\ No newline at end of file
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
index 0371d532d2ec..7c742eb16669 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
@@ -533,9 +533,11 @@ dev_llc_d0: llc@51c00000 {
<&d0_clock WIN2030_CLK_NPU_LLC_ACLK>,
<&d0_clock WIN2030_CLK_NPU_CLK>,
<&d0_clock WIN2030_MUX_U_NPU_CORE_3MUX1_GFREE>,
- <&d0_clock WIN2030_SPLL2_FOUT2>;
+ <&d0_clock WIN2030_SPLL2_FOUT2>,
+ <&d0_clock WIN2030_SPLL1_FOUT1>;
clock-names = "aclk", "cfg_clk", "llc_clk", "core_clk",
- "mux_u_npu_core_3mux1_gfree", "fixed_rate_clk_spll2_fout2";
+ "mux_u_npu_core_3mux1_gfree", "fixed_rate_clk_spll2_fout2",
+ "fixed_rate_clk_spll1_fout1";
resets = <&d0_reset NPU_RST_CTRL SW_NPU_AXI_RSTN>,
<&d0_reset NPU_RST_CTRL SW_NPU_CFG_RSTN>,
<&d0_reset NPU_RST_CTRL SW_NPU_CORE_RSTN>,
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
index 9e12379cc7d3..971b506eaf0b 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
@@ -940,9 +940,11 @@ dev_llc_d1: llc@71c00000 {
<&d1_clock WIN2030_CLK_NPU_LLC_ACLK>,
<&d1_clock WIN2030_CLK_NPU_CLK>,
<&d1_clock WIN2030_MUX_U_NPU_CORE_3MUX1_GFREE>,
- <&d1_clock WIN2030_SPLL2_FOUT2>;
+ <&d1_clock WIN2030_SPLL2_FOUT2>,
+ <&d0_clock WIN2030_SPLL1_FOUT1>;
clock-names = "aclk", "cfg_clk", "llc_clk", "core_clk",
- "mux_u_npu_core_3mux1_gfree", "fixed_rate_clk_spll2_fout2";
+ "mux_u_npu_core_3mux1_gfree", "fixed_rate_clk_spll2_fout2",
+ "fixed_rate_clk_spll1_fout1";
resets = <&d1_reset NPU_RST_CTRL SW_NPU_AXI_RSTN>,
<&d1_reset NPU_RST_CTRL SW_NPU_CFG_RSTN>,
<&d1_reset NPU_RST_CTRL SW_NPU_CORE_RSTN>,
diff --git a/drivers/memory/eswin/codacache/llc_spram.c b/drivers/memory/eswin/codacache/llc_spram.c
index 2e343f1da43f..01744360937c 100644
--- a/drivers/memory/eswin/codacache/llc_spram.c
+++ b/drivers/memory/eswin/codacache/llc_spram.c
@@ -40,7 +40,7 @@
#include <linux/version.h>
#include <linux/eswin_npu.h>
-
+#include <linux/regulator/consumer.h>
#include "llc_spram.h"
#define HAVE_LLC_HARDWARE 1
@@ -96,6 +96,7 @@ struct spram_dev {
struct clk *core_clk;
struct clk *mux_u_npu_core_3mux1_gfree;
struct clk *fixed_rate_clk_spll2_fout2;
+ struct clk *fixed_rate_clk_spll1_fout1;
struct reset_control *rstc_axi;
struct reset_control *rstc_cfg;
struct reset_control *rstc_core;
@@ -603,6 +604,14 @@ static int llc_clk_init(struct platform_device *pdev)
dev_err(&pdev->dev, "failed to get fixed_rate_clk_spll2_fout2: %d\n", ret);
return ret;
}
+ spram->fixed_rate_clk_spll1_fout1 =
+ devm_clk_get(&pdev->dev, "fixed_rate_clk_spll1_fout1");
+ if (IS_ERR(spram->fixed_rate_clk_spll1_fout1))
+ {
+ ret = PTR_ERR(spram->fixed_rate_clk_spll1_fout1);
+ dev_err(&pdev->dev, "failed to get fixed_rate_clk_spll1_fout1: %d\n", ret);
+ return ret;
+ }
return 0;
}
@@ -675,23 +684,62 @@ static int llc_rst_init(struct platform_device *pdev)
return 0;
}
-static int llc_clk_set_parent(struct platform_device *pdev)
+static int llc_clk_set_parent(struct platform_device *pdev, u8 *is_high_freq)
{
int ret;
struct spram_dev *spram = platform_get_drvdata(pdev);
+ struct device_node *np;
+ struct regulator *npu_regulator;
+ struct device *dev = &pdev->dev;
+
if (spram == NULL)
return -EINVAL;
+ np = of_node_get(dev->of_node);
+ npu_regulator = devm_regulator_get_exclusive(dev, "NPU_SVCC");
- ret = clk_set_parent(spram->mux_u_npu_core_3mux1_gfree, spram->fixed_rate_clk_spll2_fout2);
- if (ret){
- dev_err(&pdev->dev, "failed to set mux_u_npu_core_3mux1_gfree parent: %d\n", ret);
+ if ((NULL == npu_regulator) || (IS_ERR(npu_regulator)))
+ {
+ dev_warn(dev, "failed to get npu regulator\n");
+ *is_high_freq = 0;
+ }
+ else
+ {
+ *is_high_freq = of_property_read_bool(np, "apply_npu_high_freq");
+ dev_dbg(dev, "success to get npu regulator,apply_npu_high_freq:%d\n",
+ *is_high_freq);
+ }
+ if (1 == *is_high_freq)
+ {
+ regulator_set_voltage(npu_regulator, NPU_1P5G_VOLTAGE, NPU_1P5G_VOLTAGE);
+ dev_dbg(dev, "set volt:%duV ret:%d\n", NPU_1P5G_VOLTAGE,ret);
+ /* devm_regulator_put(npu_regulator); */
+ mdelay(10);
+ ret = clk_set_parent(spram->mux_u_npu_core_3mux1_gfree,
+ spram->fixed_rate_clk_spll1_fout1);
+ }
+ else
+ {
+ if (((NULL != npu_regulator)) && (!IS_ERR(npu_regulator)))
+ {
+ regulator_set_voltage(npu_regulator, NPU_DEFAULT_VOLTAGE, NPU_DEFAULT_VOLTAGE);
+ dev_dbg(dev, "set volt:%duV ret:%d\n", NPU_1P5G_VOLTAGE,ret);
+ /* devm_regulator_put(npu_regulator); */
+ mdelay(10);
+ }
+ ret = clk_set_parent(spram->mux_u_npu_core_3mux1_gfree,
+ spram->fixed_rate_clk_spll2_fout2);
+ }
+ if (ret)
+ {
+ dev_err(&pdev->dev, "failed to set mux_u_npu_core_3mux1_gfree parent: %d\n",
+ ret);
return ret;
}
return 0;
}
-static int llc_clk_set_frq(struct platform_device *pdev)
+static int llc_clk_set_frq(struct platform_device *pdev, u8 is_high_freq)
{
int ret;
unsigned long rate = 0;
@@ -702,23 +750,47 @@ static int llc_clk_set_frq(struct platform_device *pdev)
rate = clk_round_rate(spram->aclk, NPU_ACLK_RATE);
ret = clk_set_rate(spram->aclk, rate);
- if(ret != 0){
+ if (ret != 0)
+ {
dev_err(&pdev->dev, "failed to set aclk: %d\n", ret);
return ret;
}
- rate = clk_round_rate(spram->llc_clk, NPU_LLC_CLK_RATE);
- ret = clk_set_rate(spram->llc_clk, rate);
- if(ret != 0){
- dev_err(&pdev->dev, "failed to set llc_clk: %d\n", ret);
- return ret;
+ if (1 == is_high_freq)
+ {
+ rate = clk_round_rate(spram->llc_clk, NPU_LLC_CLK_1P5G_RATE);
+ ret = clk_set_rate(spram->llc_clk, rate);
+
+ if (ret != 0)
+ {
+ dev_err(&pdev->dev, "failed to set llc_clk: %d\n", ret);
+ return ret;
+ }
+ rate = clk_round_rate(spram->core_clk, NPU_CORE_CLK_1P5G_RATE);
+ ret = clk_set_rate(spram->core_clk, rate);
+ if (ret != 0)
+ {
+ dev_err(&pdev->dev, "failed to set core_clk: %d\n", ret);
+ return ret;
+ }
}
+ else
+ {
+ rate = clk_round_rate(spram->llc_clk, NPU_LLC_CLK_RATE);
- rate = clk_round_rate(spram->core_clk, NPU_CORE_CLK_RATE);
- ret = clk_set_rate(spram->core_clk, rate);
- if(ret != 0){
- dev_err(&pdev->dev, "failed to set core_clk: %d\n", ret);
- return ret;
+ ret = clk_set_rate(spram->llc_clk, rate);
+ if (ret != 0)
+ {
+ dev_err(&pdev->dev, "failed to set llc_clk: %d\n", ret);
+ return ret;
+ }
+ rate = clk_round_rate(spram->core_clk, NPU_CORE_CLK_RATE);
+ ret = clk_set_rate(spram->core_clk, rate);
+ if (ret != 0)
+ {
+ dev_err(&pdev->dev, "failed to set core_clk: %d\n", ret);
+ return ret;
+ }
}
return 0;
@@ -810,6 +882,7 @@ static int llc_clk_rst_print(struct platform_device *pdev)
static int llc_clk_rst_init(struct platform_device *pdev)
{
int ret = 0;
+ u8 is_high_freq = 0;
dev_dbg(&pdev->dev, "---%s\n", __func__);
@@ -819,7 +892,7 @@ static int llc_clk_rst_init(struct platform_device *pdev)
return ret;
}
- ret = llc_clk_set_parent(pdev);
+ ret = llc_clk_set_parent(pdev, &is_high_freq);
if(ret != 0){
dev_err(&pdev->dev, "llc_clk_set_parent error: %d\n", ret);
return ret;
@@ -831,7 +904,7 @@ static int llc_clk_rst_init(struct platform_device *pdev)
return ret;
}
- ret = llc_clk_set_frq(pdev);
+ ret = llc_clk_set_frq(pdev, is_high_freq);
if(ret != 0){
dev_err(&pdev->dev, "llc_clk_set_frq error: %d\n", ret);
return ret;
diff --git a/include/linux/eswin_npu.h b/include/linux/eswin_npu.h
index d7f3c91491f1..44784eeefba3 100644
--- a/include/linux/eswin_npu.h
+++ b/include/linux/eswin_npu.h
@@ -14,8 +14,12 @@
#define __LINUX_ESWIN_NPU_H
#define NPU_ACLK_RATE 800000000
+#define NPU_DEFAULT_VOLTAGE 800000 //uV
#define NPU_LLC_CLK_RATE 800000000 //nvdla
#define NPU_CORE_CLK_RATE 1040000000 //npu and e31
+#define NPU_1P5G_VOLTAGE 1050000 //uV
+#define NPU_LLC_CLK_1P5G_RATE 1188000000 //nvdla
+#define NPU_CORE_CLK_1P5G_RATE 1500000000 //npu and e31
#define NPU_E31_CLK_RATE 1040000000 //llc
#endif /* __LINUX_ESWIN_NPU_H */
--
2.47.0

32
0037-fix-llc_spram-Removed-linux-version-check.patch Normal file
View File

@ -0,0 +1,32 @@
From b38cc963a513911e268168d723f9a4fd00154943 Mon Sep 17 00:00:00 2001
From: linmin <linmin@eswincomputing.com>
Date: Tue, 28 May 2024 13:14:44 +0800
Subject: [PATCH 037/219] fix(llc_spram):Removed linux version check
Changelogs:
1.Remove the KERNEL_VERSION check from llc_spram.c since it is
a builtin driver.
---
drivers/memory/eswin/codacache/llc_spram.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/memory/eswin/codacache/llc_spram.c b/drivers/memory/eswin/codacache/llc_spram.c
index 01744360937c..e84f3650ae37 100644
--- a/drivers/memory/eswin/codacache/llc_spram.c
+++ b/drivers/memory/eswin/codacache/llc_spram.c
@@ -103,11 +103,10 @@ struct spram_dev {
struct reset_control *rstc_llc;
};
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(6,6,0)
#define dma_buf_map iosys_map
#define dma_buf_map_set_vaddr iosys_map_set_vaddr
#define dma_buf_map_clear iosys_map_clear
-#endif
+
#define spram_phys_to_virt(spram, phys) \
(spram->virt_base + phys - spram->phys_addr)
--
2.47.0

1411
0038-perf-update-dma-pwm-timer-driver.patch Normal file
View File

File diff suppressed because it is too large Load Diff

103
0039-fix-dsp-dma-ranges-buf-fix.patch Normal file
View File

@ -0,0 +1,103 @@
From 7e836a6437e122c826c5d273d832721d6e394679 Mon Sep 17 00:00:00 2001
From: donghuawei <donghuawei@eswincomputing.com>
Date: Wed, 29 May 2024 14:11:20 +0800
Subject: [PATCH 039/219] fix:dsp dma-ranges buf fix
Changelogs:
linux 6.6 reslove dma-ranges from parent.
---
arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi | 5 +----
arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi | 5 +----
2 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
index f4c569697c08..fb5920315be4 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
@@ -553,6 +553,7 @@ d0_dsp_subsys:dsp_subsys@52280400 {
reg = <0x0 0x52280400 0x0 0x10000>,
<0x0 0x51810000 0x0 0x8000>;
ranges;
+ dma-ranges = <0x0 0x30000000 0x0 0xc0000000 0x0 0xce000000>;
compatible = "es-dsp-subsys", "simple-bus";
clocks = <&d0_clock WIN2030_CLK_DSPT_CFG_CLK>;
clock-names = "cfg_clk";
@@ -586,7 +587,6 @@ ESWIN_MAIBOX_U84_IRQ_BIT
host-irq-mode = <1>;
firmware-name = "eic7700_dsp_fw";
process-id = <0>;
- dma-ranges = <0x30000000 0x0 0xc0000000 0xce000000>;
iommus = <&smmu0 WIN2030_SID_DSP_0>;
tbus = <WIN2030_TBUID_DSP0>;
dma-noncoherent;
@@ -616,7 +616,6 @@ ESWIN_MAIBOX_U84_IRQ_BIT
host-irq-mode = <1>;
firmware-name = "eic7700_dsp_fw";
process-id = <1>;
- dma-ranges = <0x30000000 0x0 0xc0000000 0xce000000>;
iommus = <&smmu0 WIN2030_SID_DSP_1>;
tbus = <WIN2030_TBUID_DSP1>;
dma-noncoherent;
@@ -646,7 +645,6 @@ ESWIN_MAIBOX_U84_IRQ_BIT
host-irq-mode = <1>;
firmware-name = "eic7700_dsp_fw";
process-id = <2>;
- dma-ranges = <0x30000000 0x0 0xc0000000 0xce000000>;
iommus = <&smmu0 WIN2030_SID_DSP_2>;
tbus = <WIN2030_TBUID_DSP2>;
dma-noncoherent;
@@ -676,7 +674,6 @@ ESWIN_MAIBOX_U84_IRQ_BIT
host-irq-mode = <1>;
firmware-name = "eic7700_dsp_fw";
process-id = <3>;
- dma-ranges = <0x30000000 0x0 0xc0000000 0xce000000>;
iommus = <&smmu0 WIN2030_SID_DSP_3>;
tbus = <WIN2030_TBUID_DSP3>;
dma-noncoherent;
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
index 971b506eaf0b..bbb403cf4776 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
@@ -1279,6 +1279,7 @@ d1_dsp_subsys:dsp_subsys@72280400 {
reg = <0x0 0x72280400 0x0 0x10000>,
<0x0 0x71810000 0x0 0x8000>;
ranges;
+ dma-ranges = <0x0 0x30000000 0x0 0xc0000000 0x0 0xce000000>;
compatible = "es-dsp-subsys", "simple-bus";
clocks = <&d1_clock WIN2030_CLK_DSPT_CFG_CLK>;
clock-names = "cfg_clk";
@@ -1311,7 +1312,6 @@ ESWIN_MAIBOX_U84_IRQ_BIT
host-irq-mode = <1>;
firmware-name = "eic7702_dsp_fw";
process-id = <0>;
- dma-ranges = <0x30000000 0x0 0xc0000000 0xce000000>;
iommus = <&smmu1 WIN2030_SID_DSP_0>;
tbus = <WIN2030_TBUID_DSP0>;
dma-noncoherent;
@@ -1341,7 +1341,6 @@ ESWIN_MAIBOX_U84_IRQ_BIT
host-irq-mode = <1>;
firmware-name = "eic7702_dsp_fw";
process-id = <1>;
- dma-ranges = <0x30000000 0x0 0xc0000000 0xce000000>;
iommus = <&smmu1 WIN2030_SID_DSP_1>;
tbus = <WIN2030_TBUID_DSP1>;
dma-noncoherent;
@@ -1371,7 +1370,6 @@ ESWIN_MAIBOX_U84_IRQ_BIT
host-irq-mode = <1>;
firmware-name = "eic7702_dsp_fw";
process-id = <2>;
- dma-ranges = <0x30000000 0x0 0xc0000000 0xce000000>;
iommus = <&smmu1 WIN2030_SID_DSP_2>;
tbus = <WIN2030_TBUID_DSP2>;
dma-noncoherent;
@@ -1401,7 +1399,6 @@ ESWIN_MAIBOX_U84_IRQ_BIT
host-irq-mode = <1>;
firmware-name = "eic7702_dsp_fw";
process-id = <3>;
- dma-ranges = <0x30000000 0x0 0xc0000000 0xce000000>;
iommus = <&smmu1 WIN2030_SID_DSP_3>;
tbus = <WIN2030_TBUID_DSP3>;
dma-noncoherent;
--
2.47.0

201
0040-refactor-remove-useless-code-in-emmc-sd-driver.patch Normal file
View File

@ -0,0 +1,201 @@
From 617f4941031f619d9a4b0a3ccd3c5112b36d6fbd Mon Sep 17 00:00:00 2001
From: liangshuang <liangshuang@eswincomputing.com>
Date: Thu, 30 May 2024 09:50:56 +0800
Subject: [PATCH 040/219] refactor:remove useless code in emmc/sd driver.
Changelogs:
1.Remove useless code related to HAPS/ZEBU.
2.Add type attributes in dts.
---
arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts | 4 ++++
arch/riscv/boot/dts/eswin/eic7700-evb.dts | 4 ++++
.../boot/dts/eswin/hifive-premier-550.dts | 6 +++++-
drivers/mmc/host/sdhci-of-eswin-sdio.c | 17 ----------------
drivers/mmc/host/sdhci-of-eswin.c | 20 -------------------
5 files changed, 13 insertions(+), 38 deletions(-)
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
index 584338c8ad4c..008c21b95a6f 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
@@ -482,6 +482,8 @@ &sdhci_emmc {
enable-data-pullup;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc_led_control_default>;
+ no-sdio;
+ no-sd;
};
&sdio0 {
@@ -494,6 +496,7 @@ &sdio0 {
enable-data-pullup;
enable_sw_tuning;
no-sdio;
+ no-mmc;
};
&sdio1 {
@@ -507,6 +510,7 @@ &sdio1 {
enable_sw_tuning;
non-removable;
no-sd;
+ no-mmc;
};
&d0_gmac0 {
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb.dts b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
index 4ed625ef7bd3..4d9aeafa93f7 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
@@ -453,6 +453,8 @@ &sdhci_emmc {
drive-impedance-ohm = <50>;
enable-cmd-pullup;
enable-data-pullup;
+ no-sdio;
+ no-sd;
};
&sdio0 {
@@ -464,6 +466,7 @@ &sdio0 {
enable-data-pullup;
enable_sw_tuning;
no-sdio;
+ no-mmc;
};
&sdio1 {
@@ -476,6 +479,7 @@ &sdio1 {
enable_sw_tuning;
non-removable;
no-sd;
+ no-mmc;
};
&d0_gmac0 {
diff --git a/arch/riscv/boot/dts/eswin/hifive-premier-550.dts b/arch/riscv/boot/dts/eswin/hifive-premier-550.dts
index f0883f403393..e2a203812d12 100644
--- a/arch/riscv/boot/dts/eswin/hifive-premier-550.dts
+++ b/arch/riscv/boot/dts/eswin/hifive-premier-550.dts
@@ -394,6 +394,8 @@ &sdhci_emmc {
enable-data-pullup;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc_led_control_default>;
+ no-sdio;
+ no-sd;
};
&sdio0 {
@@ -406,11 +408,12 @@ &sdio0 {
enable-data-pullup;
enable_sw_tuning;
no-sdio;
+ no-mmc;
};
&sdio1 {
/* wifi module */
- status = "disabled";
+ status = "okay";
delay_code = <0x21>;
drive-impedance-ohm = <33>;
enable-cmd-pullup;
@@ -418,6 +421,7 @@ &sdio1 {
enable_sw_tuning;
non-removable;
no-sd;
+ no-mmc;
};
&d0_gmac0 {
diff --git a/drivers/mmc/host/sdhci-of-eswin-sdio.c b/drivers/mmc/host/sdhci-of-eswin-sdio.c
index fa23d1ded51c..83cbdb61c936 100644
--- a/drivers/mmc/host/sdhci-of-eswin-sdio.c
+++ b/drivers/mmc/host/sdhci-of-eswin-sdio.c
@@ -851,23 +851,6 @@ static int eswin_sdhci_sdio_probe(struct platform_device *pdev)
goto err_pltfm_free;
}
-#if defined(__SDIO_HAPS) || defined(__SDIO_ZEBU)
-#if !defined(__SDIO_UHS)
- /* This macro is only for setting 3.3v speed mode(HAPS) , you can delete it later*/
- eswin_sdhci_sdio->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
-#endif
-#if defined(__SDIO_PIO)
- /* This macro is only for testing PIO , you can delete it later*/
- eswin_sdhci_sdio->host->quirks |= SDHCI_QUIRK_BROKEN_DMA |
- SDHCI_QUIRK_BROKEN_ADMA;
-#elif defined(__SDIO_SDMA)
- /* This macro is only for testing SDMA ,you can delete it later*/
- eswin_sdhci_sdio->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
-#elif defined(__SDIO_ADMA3)
- /* This macro is only for testing ADMA3 ,you can delete it later*/
- sdhci_enable_v4_mode(eswin_sdhci_sdio->host);
-#endif
-#endif
sdhci_get_of_property(pdev);
eswin_sdhci_sdio->clk_ops = data->clk_ops;
diff --git a/drivers/mmc/host/sdhci-of-eswin.c b/drivers/mmc/host/sdhci-of-eswin.c
index 591315f48cbc..41aa80f8dbe3 100644
--- a/drivers/mmc/host/sdhci-of-eswin.c
+++ b/drivers/mmc/host/sdhci-of-eswin.c
@@ -87,7 +87,6 @@ static void eswin_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
msleep(20);
}
-#if !defined(__FPGA) && !defined(__ZEBU)
static void eswin_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc,
struct mmc_ios *ios)
{
@@ -102,7 +101,6 @@ static void eswin_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc,
sdhci_writel(host, vendor, eswin_sdhci_VENDOR_EMMC_CTRL_REGISTER);
}
-#endif
static void eswin_sdhci_config_phy_delay(struct sdhci_host *host, int delay)
{
@@ -890,20 +888,6 @@ static int eswin_sdhci_probe(struct platform_device *pdev)
goto err_pltfm_free;
}
-#if defined(__FPGA) || defined(__ZEBU)
-#if defined __SDMA
- eswin_sdhci->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
-#elif defined(__ADMA2) || defined(__ADMA3)
-#else
- eswin_sdhci->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA |
- SDHCI_QUIRK_BROKEN_DMA;
-#endif
-#endif
-
-#if defined(__FORCE_1BIT)
- eswin_sdhci->host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
-#endif
-
eswin_sdhci->clk_ahb = devm_clk_get(dev, "clk_ahb");
if (IS_ERR(eswin_sdhci->clk_ahb)) {
ret = dev_err_probe(dev, PTR_ERR(eswin_sdhci->clk_ahb),
@@ -990,7 +974,6 @@ static int eswin_sdhci_probe(struct platform_device *pdev)
goto unreg_clk;
}
-#if !defined(__FPGA) && !defined(__ZEBU)
if (of_device_is_compatible(dev->of_node, "eswin,sdhci-5.1")) {
host->mmc_host_ops.hs400_enhanced_strobe =
eswin_sdhci_hs400_enhanced_strobe;
@@ -1000,11 +983,8 @@ static int eswin_sdhci_probe(struct platform_device *pdev)
if (!of_property_read_bool(dev->of_node, "disable-cqe-dcmd"))
host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
}
-#endif
-#if !defined(__ADMA3_DISABLE)
sdhci_enable_v4_mode(eswin_sdhci->host);
-#endif
ret = eswin_sdhci_add_host(eswin_sdhci);
if (ret)
--
2.47.0

61
0041-fix-distinguish-built-in-RTC-and-PCF-RTC.patch Normal file
View File

@ -0,0 +1,61 @@
From 710dfb9f495acf5248d38118520049eae97b0fbe Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E2=80=9Chuangyifeng=E2=80=9D?=
<huangyifeng@eswincomputing.com>
Date: Fri, 31 May 2024 08:52:35 +0800
Subject: [PATCH 041/219] fix :distinguish built-in RTC and PCF RTC
Changelogs:
Setting aliases for the SoC built-in RTC and the PCF RTC, so
that the built-in RTC could be the default rtc
---
arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts | 4 +++-
arch/riscv/boot/dts/eswin/eic7700-evb.dts | 4 +++-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
index 008c21b95a6f..41fb37364295 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
@@ -47,6 +47,8 @@ aliases {
serial0 = &d0_uart0;
ethernet0 = &d0_gmac0;
ethernet1 = &d0_gmac1;
+ rtc0 = &die0_rtc;
+ rtc1 = &pcf_rtc;
};
chosen {
@@ -788,7 +790,7 @@ &d0_aon_i2c0 {
/* temp sensor & rtc */
status = "okay";
eswin,syscfg = <&d0_sys_con 0x3C0 16>;
- rtc@51 {
+ pcf_rtc:rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb.dts b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
index 4d9aeafa93f7..2aebb21a51a0 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
@@ -46,6 +46,8 @@ aliases {
serial0 = &d0_uart0;
ethernet0 = &d0_gmac0;
ethernet1 = &d0_gmac1;
+ rtc0 = &die0_rtc;
+ rtc1 = &pcf_rtc;
};
chosen {
@@ -746,7 +748,7 @@ &d0_aon_i2c0 {
/* temp sensor & rtc */
status = "okay";
eswin,syscfg = <&d0_sys_con 0x3C0 16>;
- rtc@51 {
+ pcf_rtc:rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
--
2.47.0

89
0042-fix-adapt-linux6.6.patch Normal file
View File

@ -0,0 +1,89 @@
From 9e8534a0490fdf7f9037640c97bb4d1ed67e9e0b Mon Sep 17 00:00:00 2001
From: yiguo <yiguo@eswincomputing.com>
Date: Fri, 31 May 2024 17:23:52 +0800
Subject: [PATCH 042/219] fix:adapt linux6.6
Changelogs:
1. add dma-noncoherent; in dts.
2. add func of start repeatly.
3. add hdcp1x enable/disable.
---
arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi | 1 +
arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi | 1 +
drivers/gpu/drm/eswin/dw_hdmi_hdcp2.c | 7 +++----
3 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
index fb5920315be4..3db50303c303 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
@@ -1905,6 +1905,7 @@ dw_hdmi_hdcp2: hdmi-hdcp2@50290000 {
clocks = <&d0_clock WIN2030_CLK_VO_CFG_CLK>,
<&d0_clock WIN2030_CLK_VO_HDMI_IESMCLK>;
clock-names ="pclk_hdcp2", "hdcp2_clk_hdmi";
+ dma-noncoherent;
};
d0_usbdrd3_0: usb0@50480000 {
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
index bbb403cf4776..48a042d05e8e 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
@@ -1836,6 +1836,7 @@ d1_dw_hdmi_hdcp2: hdmi-hdcp2@70290000 {
clocks = <&d1_clock WIN2030_CLK_VO_CFG_CLK>,
<&d1_clock WIN2030_CLK_VO_HDMI_IESMCLK>;
clock-names ="pclk_hdcp2", "hdcp2_clk_hdmi";
+ dma-noncoherent;
};
d1_wdt0: watchdog@0x70800000 {
diff --git a/drivers/gpu/drm/eswin/dw_hdmi_hdcp2.c b/drivers/gpu/drm/eswin/dw_hdmi_hdcp2.c
index 63ce0ae4fde3..e387f079eb89 100644
--- a/drivers/gpu/drm/eswin/dw_hdmi_hdcp2.c
+++ b/drivers/gpu/drm/eswin/dw_hdmi_hdcp2.c
@@ -61,6 +61,7 @@
*/
#define MAX_HL_DEVICES 16
+#define TROOT_GRIFFIN
static bool randomize_mem = false;
module_param(randomize_mem, bool, 0);
@@ -344,7 +345,6 @@ static int alloc_dma_areas(hl_device *hl_dev,
hl_dev->code_base = info->code_base;
hl_dev->code = phys_to_virt(hl_dev->code_base);
} else {
- dma_set_mask_and_coherent(g_dw_hdcp2->dev, DMA_BIT_MASK(32));
hl_dev->code =
dma_alloc_coherent(g_dw_hdcp2->dev, hl_dev->code_size,
&hl_dev->code_base, GFP_KERNEL);
@@ -387,7 +387,6 @@ static long init(struct file *f, void __user *arg)
if (copy_from_user(&info, arg, sizeof info) != 0)
return -EFAULT;
-
hl_dev = alloc_hl_dev_slot(&info);
if (!hl_dev)
return -EMFILE;
@@ -528,9 +527,8 @@ static long hld_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
static const struct file_operations hld_file_operations = {
#ifdef CONFIG_COMPAT
.compat_ioctl = hld_ioctl,
-#else
- .unlocked_ioctl = hld_ioctl,
#endif
+ .unlocked_ioctl = hld_ioctl,
.owner = THIS_MODULE,
};
@@ -708,6 +706,7 @@ static int eswin_hdmi_hdcp2_probe(struct platform_device *pdev)
g_dw_hdcp2->start = dw_hdcp2_start;
hld_init();
dw_hdmi2_hdcp2_clk_enable(hdcp2_dev);
+ dma_set_mask_and_coherent(hdcp2_dev, DMA_BIT_MASK(32));
dw_hdmi_hdcp2_init(g_dw_hdcp2);
dw_hdmi_hdcp2_start(3);
--
2.47.0

409
0043-fix-delete-useless-audio-code.patch Normal file
View File

@ -0,0 +1,409 @@
From 246201ce44642fdaaefaa5920b9727062595bbc1 Mon Sep 17 00:00:00 2001
From: denglei <denglei@eswincomputing.com>
Date: Mon, 3 Jun 2024 14:28:29 +0800
Subject: [PATCH 043/219] fix:delete useless audio code.
Changelogs:
delete useless audio code.
---
arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts | 14 --
arch/riscv/boot/dts/eswin/eic7700-evb.dts | 14 --
.../dts/eswin/eswin-win2030-die1-soc.dtsi | 151 ++----------------
arch/riscv/boot/dts/eswin/eswin-win2030.dts | 71 --------
.../boot/dts/eswin/hifive-premier-550.dts | 5 -
5 files changed, 10 insertions(+), 245 deletions(-)
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
index 41fb37364295..a92e182c073a 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
@@ -90,20 +90,6 @@ npu0_reserved: sprammemory@59000000 {
reg = <0x0 0x59000000 0x0 0x400000>;
};
- /*
- dsp_reserved0: dsp@90000000 {
- compatible = "shared-dma-pool";
- reg = <0x0 0x90000000 0x0 0x1000000>;
- reusable;
- status = "okay";
- };
- */
-
- dsp_reserved1: dsp@91000000 {
- reg = <0 0x91000000 0 0x200000>;
- no-map;
- };
-
smpmemtest_rsv0@91200000 {
reg = <0 0x91200000 0 0x2000000>;
no-map;
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb.dts b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
index 2aebb21a51a0..bec9f0b54367 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
@@ -89,20 +89,6 @@ npu0_reserved: sprammemory@59000000 {
reg = <0x0 0x59000000 0x0 0x400000>;
};
- /*
- dsp_reserved0: dsp@90000000 {
- compatible = "shared-dma-pool";
- reg = <0x0 0x90000000 0x0 0x1000000>;
- reusable;
- status = "okay";
- };
- */
-
- dsp_reserved1: dsp@91000000 {
- reg = <0 0x91000000 0 0x200000>;
- no-map;
- };
-
smpmemtest_rsv0@91200000 {
reg = <0 0x91200000 0 0x2000000>;
no-map;
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
index 48a042d05e8e..2c19ffd3893e 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
@@ -1198,7 +1198,7 @@ d1_pwm0: pwm@0x70818000 {
};
d1_i2s0: i2s0@70200000 {
- compatible = "eswin,i2s-dsp";
+ compatible = "snps,i2s";
clocks = <&d1_clock WIN2030_CLK_VO_I2S_MCLK>;
clock-names = "mclk";
#address-cells = <1>;
@@ -1207,20 +1207,12 @@ d1_i2s0: i2s0@70200000 {
reg = <0x0 0x70200000 0x0 0x10000>;
dma-names = "rx", "tx";
dmas = <&d1_aon_dmac 4 0>, <&d1_aon_dmac 5 0>;
- memory-region = <&dsp_reserved1>;
vo_mclk_sel,syscrg = <&d1_sys_crg 0x1bc>;
resets = <&d1_reset VO_I2SRST_CTRL SW_VO_I2S_RSTN>,
- <&d1_reset VO_I2SRST_CTRL SW_VO_I2S_PRSTN>;
- reset-names = "i2srst", "i2sprst";
+ <&d1_reset VO_I2SRST_CTRL SW_VO_I2S_PRSTN>,
+ <&d1_reset VO_PHYRST_CTRL SW_VO_PRSTN>;
+ reset-names = "i2srst", "i2sprst", "voprst";
dma-noncoherent;
- ports {
- d1_i2s0_port: port@0 {
- d1_i2s0_endpoint: endpoint {
- remote-endpoint = <&d1_codec_endpoint>;
- dai-format = "i2s";
- };
- };
- };
};
d1_i2s1: i2s1@70210000 {
@@ -1235,17 +1227,10 @@ d1_i2s1: i2s1@70210000 {
dmas = <&d1_aon_dmac 2 1>, <&d1_aon_dmac 3 1>;
vo_mclk_sel,syscrg = <&d1_sys_crg 0x1bc>;
resets = <&d1_reset VO_I2SRST_CTRL SW_VO_I2S_RSTN>,
- <&d1_reset VO_I2SRST_CTRL SW_VO_I2S_PRSTN>;
- reset-names = "i2srst", "i2sprst";
+ <&d1_reset VO_I2SRST_CTRL SW_VO_I2S_PRSTN>,
+ <&d1_reset VO_PHYRST_CTRL SW_VO_PRSTN>;
+ reset-names = "i2srst", "i2sprst", "voprst";
dma-noncoherent;
- ports {
- d1_i2s1_port: port@0 {
- d1_i2s1_endpoint: endpoint {
- remote-endpoint = <&d1_dummy_endpoint1>;
- dai-format = "i2s";
- };
- };
- };
};
d1_i2s2: i2s@70220000 {
@@ -1260,17 +1245,10 @@ d1_i2s2: i2s@70220000 {
dmas = <&d1_aon_dmac 0 2>, <&d1_aon_dmac 1 2>;
vo_mclk_sel,syscrg = <&d1_sys_crg 0x1bc>;
resets = <&d1_reset VO_I2SRST_CTRL SW_VO_I2S_RSTN>,
- <&d1_reset VO_I2SRST_CTRL SW_VO_I2S_PRSTN>;
- reset-names = "i2srst", "i2sprst";
+ <&d1_reset VO_I2SRST_CTRL SW_VO_I2S_PRSTN>,
+ <&d1_reset VO_PHYRST_CTRL SW_VO_PRSTN>;
+ reset-names = "i2srst", "i2sprst", "voprst";
dma-noncoherent;
- ports {
- d1_i2s2_port: port@0 {
- d1_i2s2_endpoint: endpoint {
- remote-endpoint = <&d1_dummy_endpoint2>;
- dai-format = "i2s";
- };
- };
- };
};
d1_dsp_subsys:dsp_subsys@72280400 {
@@ -1407,30 +1385,6 @@ ESWIN_MAIBOX_U84_IRQ_BIT
dsp@0 {
};
};
- d1_sofdsp: sofdsp@4 {
- #sound-dai-cells = <1>;
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "eswin,vision-dsp";
- reg = <0x0 0x7b000000 0x0 0x10000>,
- <0x0 0x7b100000 0x0 0x40000>;
- /* memory-region = <&dsp_reserved0>; */
- mbox-names = "sof-dsp0";
- mboxes = <&d1_mbox4 0>;
- tplg-name = "sof-win2030-es8316.tplg";
- machine-drv-name = "asoc-simple-card";
- clocks = <&d1_clock WIN2030_CLK_DSP_ACLK_0>;
- clock-names = "aclk";
- process-id = <0>;
- dma-ranges = <0x0 0x40000000 0x0 0xc0000000 0x0 0xc0000000>;
- iommus = <&smmu1 WIN2030_SID_DSP_0>;
- mailbox-dsp-to-u84-addr = <ESWIN_MAILBOX_DSP_0_TO_U84_REG_BASE>;
- mailbox-u84-to-dsp-addr = <ESWIN_MAILBOX_U84_TO_DSP_0_REG_BASE>;
- dsp-uart = <&d1_uart1>;
- ringbuffer-region = <&dsp_reserved1>;
- numa-node-id = <1>;
- dma-noncoherent;
- };
};
die1_rtc: rtc@71818000 {
compatible = "eswin,win2030-rtc";
@@ -1817,14 +1771,6 @@ d1_hdmi_in_dc: endpoint@0 {
remote-endpoint = <&d1_dc_out_hdmi>;
};
};
- port@1 {
- reg = <2>;
- d1_hdmi_endpoint: endpoint {
- reg = <0>;
- system-clock-frequency = <12288000>;
- remote-endpoint = <&d1_i2s0_endpoint>;
- };
- };
};
};
@@ -1952,85 +1898,8 @@ d1_sdhci_emmc: mmc@70450000 {
dma-noncoherent;
};
- d1_soundcard: soundcard {
- compatible = "simple-audio-card";
- simple-audio-card,name = "Eswin sound card";
- simple-audio-card,widgets = "Headphone", "Headphone Jack";
- simple-audio-card,dai-link@0 {
- format = "i2s";
- cpu {
- sound-dai = <&d1_sofdsp 0>;
- };
- codec {
- sound-dai = <&d1_thruout 0>;
- };
- };
-
- simple-audio-card,dai-link@1 {
- format = "i2s";
- cpu {
- sound-dai = <&d1_sofdsp 1>;
- };
- codec {
- sound-dai = <&d1_thruout 1>;
- };
- };
-
- simple-audio-card,dai-link@2 {
- format = "i2s";
- cpu {
- sound-dai = <&d1_i2s0>;
- };
- codec {
- sound-dai = <&d1_es8316>;
- system-clock-frequency = <12288000>;
- };
- plat {
- sound-dai = <&d1_sofdsp 2>;
- };
- };
- };
-
d1_graphcard: graphcard {
compatible = "audio-graph-card";
- dais = <&d1_i2s0_port
- &d1_i2s1_port
- &d1_i2s2_port>;
- };
-
- d1_dummy_codec:codec@0x70230000 {
- status = "disabled";
- reg = <0x00000000 0x70230000 0x00000000 0x00000100>;
- #sound-dai-cells = <0x00000000>;
- compatible = "eswin_dummy_codec";
- ports {
- /*
- port@0 {
- d1_dummy_endpoint0: endpoint {
- system-clock-frequency = <12288000>;
- remote-endpoint = <&d1_i2s0_endpoint>;
- };
- };
- */
- port@1 {
- d1_dummy_endpoint1: endpoint {
- system-clock-frequency = <12288000>;
- remote-endpoint = <&d1_i2s1_endpoint>;
- };
- };
- port@2 {
- d1_dummy_endpoint2: endpoint {
- system-clock-frequency = <12288000>;
- remote-endpoint = <&d1_i2s2_endpoint>;
- };
- };
- };
- };
-
- d1_thruout: thru-out {
- compatible = "eswin,thru-out";
- #sound-dai-cells = <1>;
- memory-region = <&dsp_reserved1>;
};
d1_usbdrd3_0: usb0@70480000 {
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030.dts b/arch/riscv/boot/dts/eswin/eswin-win2030.dts
index 8e7769e5b509..4f8c9f146ce3 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030.dts
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030.dts
@@ -100,20 +100,6 @@ npu1_reserved: sprammemory@79000000 {
no-map;
reg = <0x0 0x79000000 0x0 0x400000>;
};
- //WRAN: dsp reserved space is fixed to 0x90000000 and 0x91000000 in the code, the below space is not working for dsp,it's just for building
- /*
- dsp_reserved0: dsp@4010000000 {
- compatible = "shared-dma-pool";
- reg = <0x40 0x10000000 0 0x1000000>;
- reusable;
- status = "okay";
- };
- */
-
- dsp_reserved1: dsp@4011000000 {
- reg = <0x40 0x11000000 0 0x200000>;
- no-map;
- };
smpmemtest_rsv0@4011200000 {
reg = <0x40 0x11200000 0 0x2000000>;
@@ -194,19 +180,6 @@ npu1_reserved: sprammemory@79000000 {
no-map;
reg = <0x0 0x79000000 0x0 0x400000>;
};
- /*
- dsp_reserved0: dsp@90000000 {
- compatible = "shared-dma-pool";
- reg = <0x0 0x90000000 0x0 0x1000000>;
- reusable;
- status = "okay";
- };
- */
-
- dsp_reserved1: dsp@91000000 {
- reg = <0 0x91000000 0 0x200000>;
- no-map;
- };
smpmemtest_rsv0@91200000 {
reg = <0 0x91200000 0 0x2000000>;
@@ -317,20 +290,6 @@ npu0_reserved: sprammemory@59000000 {
reg = <0x0 0x59000000 0x0 0x400000>;
};
- /*
- dsp_reserved0: dsp@90000000 {
- compatible = "shared-dma-pool";
- reg = <0x0 0x90000000 0x0 0x1000000>;
- reusable;
- status = "okay";
- };
- */
-
- dsp_reserved1: dsp@91000000 {
- reg = <0 0x91000000 0 0x200000>;
- no-map;
- };
-
smpmemtest_rsv0@91200000 {
reg = <0 0x91200000 0 0x2000000>;
no-map;
@@ -406,20 +365,6 @@ npu1_reserved: sprammemory@79000000 {
no-map;
reg = <0x0 0x79000000 0x0 0x400000>;
};
- //WRAN: dsp reserved space is fixed to 0x90000000 and 0x91000000 in the code, the below space is not working for dsp,it's just for building
- /*
- dsp_reserved0: dsp@2010000000 {
- compatible = "shared-dma-pool";
- reg = <0x20 0x10000000 0x0 0x1000000>;
- reusable;
- status = "okay";
- };
- */
-
- dsp_reserved1: dsp@2011000000 {
- reg = <0x20 0x11000000 0 0x200000>;
- no-map;
- };
smpmemtest_rsv0@2011200000 {
reg = <0x20 0x11200000 0 0x2000000>;
@@ -1146,26 +1091,10 @@ &d1_i2s2 {
status = "disabled";
};
-&d1_sofdsp {
- status = "disabled";
-};
-
-&d1_soundcard {
- status = "disabled";
-};
-
&d1_graphcard {
status = "disabled";
};
-&d1_dummy_codec {
- status = "disabled";
-};
-
-&d1_thruout {
- status = "disabled";
-};
-
&d1_aon_i2c0 {
status = "disabled";
aon_eeprom@50 {
diff --git a/arch/riscv/boot/dts/eswin/hifive-premier-550.dts b/arch/riscv/boot/dts/eswin/hifive-premier-550.dts
index e2a203812d12..271a5881d3de 100644
--- a/arch/riscv/boot/dts/eswin/hifive-premier-550.dts
+++ b/arch/riscv/boot/dts/eswin/hifive-premier-550.dts
@@ -81,11 +81,6 @@ linux,cma {
linux,cma-default;
};
- dsp_reserved1: dsp@91000000 {
- reg = <0 0x91000000 0 0x200000>;
- no-map;
- };
-
lpcpu0_reserved: lpcpu@a0000000 {
no-map;
reg = <0x0 0xa0000000 0x0 0x100000>;
--
2.47.0

219
0044-fix-add-label-for-all-hwmon.patch Normal file
View File

@ -0,0 +1,219 @@
From 9b00b7ee890cab374b37fe82e9f91cfbf8b5375b Mon Sep 17 00:00:00 2001
From: yangwei1 <yangwei1@eswincomputing.com>
Date: Mon, 3 Jun 2024 19:00:03 +0800
Subject: [PATCH 044/219] fix:add label for all hwmon
Changelogs:
ina226,pac1934,sic451,npq8785,pvt,fan control
---
arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts | 17 +++++++++--------
arch/riscv/boot/dts/eswin/eic7700-evb.dts | 17 +++++++++--------
.../boot/dts/eswin/eswin-win2030-die0-soc.dtsi | 3 +++
.../boot/dts/eswin/eswin-win2030-die1-soc.dtsi | 3 +++
.../riscv/boot/dts/eswin/hifive-premier-550.dts | 10 ++++++----
5 files changed, 30 insertions(+), 20 deletions(-)
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
index a92e182c073a..f5c4712de03e 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
@@ -718,6 +718,7 @@ mpq8785@10 {
reg = <0x10>;
eswin,regulator_default-microvolt=<1000000>;
eswin,regulator_label = "supply vdd1", "npu vdd1", "npu current1", "npu temperature1";
+ label = "npu_vdd";
regulators{
npu_vcc1:npu_svcc{
regulator-name="NPU_SVCC";
@@ -786,31 +787,31 @@ &d0_aon_i2c1 {
/* ina226x4 */
status = "okay";
i2c-sda-hold-time-ns = <0x40>;
- vdd_cpu: ina226@45 {
+ ina226@45 {
compatible = "ti,ina226";
#io-channel-cells = <1>;
- label = "vdd_cpu";
+ label = "cpu_vdd";
reg = <0x45>;
shunt-resistor = <1000>;
};
- vdd_soc: ina226@44 {
+ ina226@44 {
compatible = "ti,ina226";
#io-channel-cells = <1>;
- label = "vdd_soc";
+ label = "soc_vdd";
reg = <0x44>;
shunt-resistor = <1000>;
};
- vdd_lpddr: ina226@41 {
+ ina226@41 {
compatible = "ti,ina226";
#io-channel-cells = <1>;
- label = "vdd_lpddr";
+ label = "lpddr_vdd";
reg = <0x41>;
shunt-resistor = <1000>;
};
- dc_in: ina226@48 {
+ ina226@48 {
compatible = "ti,ina226";
#io-channel-cells = <1>;
- label = "dc_in";
+ label = "dc_vdd";
reg = <0x48>;
shunt-resistor = <1000>;
};
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb.dts b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
index bec9f0b54367..e3c9de0ada5d 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
@@ -749,6 +749,7 @@ mpq8785@10 {
reg = <0x10>;
eswin,regulator_default-microvolt=<1000000>;
eswin,regulator_label = "supply vdd1", "npu vdd1", "npu current1", "npu temperature1";
+ label = "npu_vdd";
regulators{
npu_vcc1:npu_svcc{
regulator-name="NPU_SVCC";
@@ -761,31 +762,31 @@ npu_vcc1:npu_svcc{
};
};
};
- vdd_cpu: ina226@45 {
+ ina226@45 {
compatible = "ti,ina226";
#io-channel-cells = <1>;
- label = "vdd_cpu";
+ label = "cpu_vdd";
reg = <0x45>;
shunt-resistor = <1000>;
};
- vdd_soc: ina226@44 {
+ ina226@44 {
compatible = "ti,ina226";
#io-channel-cells = <1>;
- label = "vdd_soc";
+ label = "soc_vdd";
reg = <0x44>;
shunt-resistor = <1000>;
};
- vdd_lpddr: ina226@41 {
+ ina226@41 {
compatible = "ti,ina226";
#io-channel-cells = <1>;
- label = "vdd_lpddr";
+ label = "lpddr_vdd";
reg = <0x41>;
shunt-resistor = <1000>;
};
- dc_in: ina226@48 {
+ ina226@48 {
compatible = "ti,ina226";
#io-channel-cells = <1>;
- label = "dc_in";
+ label = "dc_vdd";
reg = <0x48>;
shunt-resistor = <1000>;
};
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
index 3db50303c303..a499864a4e99 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
@@ -1263,6 +1263,7 @@ pvt0: pvt@0x50b00000 {
interrupts = <349>;
interrupt-parent = <&plic0>;
status = "disabled";
+ label = "pvt0";
};
pvt1: pvt@0x52360000 {
compatible = "eswin,eswin-pvt-ddr";
@@ -1276,6 +1277,7 @@ pvt1: pvt@0x52360000 {
interrupts = <350>;
interrupt-parent = <&plic0>;
status = "disabled";
+ label = "pvt1";
};
fan_control: fan_control@50b50000 {
@@ -1294,6 +1296,7 @@ fan_control: fan_control@50b50000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fan_tach_default>;
status = "disabled";
+ label = "fan_control";
};
d0_i2c0: i2c@50950000 {
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
index 2c19ffd3893e..1805c2bcdccc 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
@@ -674,6 +674,7 @@ d1_pvt0: pvt@0x70b00000 {
interrupts = <349>;
interrupt-parent = <&plic1>;
status = "disabled";
+ label = "d1_pvt0";
};
d1_pvt1: pvt@0x72360000 {
compatible = "eswin,eswin-pvt-ddr";
@@ -687,6 +688,7 @@ d1_pvt1: pvt@0x72360000 {
interrupts = <350>;
interrupt-parent = <&plic1>;
status = "disabled";
+ label = "d1_pvt1";
};
d1_fan_control: fan_control@70b50000 {
@@ -703,6 +705,7 @@ d1_fan_control: fan_control@70b50000 {
pwm-minimun-period = <1000>;
pwms = <&d1_pwm0 0 100000>;
status = "disabled";
+ label = "d1_fan_control";
};
d1_i2c0: i2c@70950000 {
diff --git a/arch/riscv/boot/dts/eswin/hifive-premier-550.dts b/arch/riscv/boot/dts/eswin/hifive-premier-550.dts
index 271a5881d3de..92a708552e52 100644
--- a/arch/riscv/boot/dts/eswin/hifive-premier-550.dts
+++ b/arch/riscv/boot/dts/eswin/hifive-premier-550.dts
@@ -662,19 +662,21 @@ &d0_aon_i2c1 {
status = "okay";
eswin,syscfg = <&d0_sys_con 0x3C0 15>;
iic_hold_time = <0x40>;
- pac1934@10 {
+ pac1934:pmic@10 {
compatible = "microchip,pac1934";
/*update all register data*/
update_time_ms = <1000>;
eswin,chan_label = "som vdd", "soc vdd", "cpu vdd", "ddr lpvdd";
+ label = "som_info";
/*The update number of times the energy accumulates*/
energy_acc_count = <0>;
shunt_resistors=<4 4 4 4>;
reg = <0x10>;
};
- sic451@11 {
+ sic451:pmic@11 {
compatible = "Vishay,sic451";
reg = <0x11>;
+ label = "npu_vdd";
regulators{
vdd_npu1:vdd_npu{
regulator-name="VDD_NPU";
@@ -749,10 +751,10 @@ LDO5 {
};
};
- u71_sys: ina226@44 {
+ sys_power:ina226@44 {
compatible = "ti,ina226";
#io-channel-cells = <1>;
- label = "ina226-u71_sys";
+ label = "sys_power";
reg = <0x44>;
shunt-resistor = <1000>;
};
--
2.47.0

866
0045-feat-add-dirver-for-fsub303-to-support-type-c.patch Normal file
View File

@ -0,0 +1,866 @@
From c1d5962b94369abde9121c7a4cb2a83ecdcfcece Mon Sep 17 00:00:00 2001
From: yangwei1 <yangwei1@eswincomputing.com>
Date: Mon, 3 Jun 2024 19:06:17 +0800
Subject: [PATCH 045/219] feat:add dirver for fsub303 to support type-c
Changelogs:
if you want to otg,Set as follows
1.set dr_mode in dX_usbdrd_dwc3_0 to otg and add usb-role-switch
2.enable port
3.data-role of connector in fusb303b to otg
---
.../boot/dts/eswin/hifive-premier-550.dts | 39 +-
arch/riscv/configs/win2030_defconfig | 10 +-
drivers/usb/typec/Kconfig | 8 +
drivers/usb/typec/Makefile | 1 +
drivers/usb/typec/fusb303b.c | 685 ++++++++++++++++++
5 files changed, 723 insertions(+), 20 deletions(-)
create mode 100644 drivers/usb/typec/fusb303b.c
diff --git a/arch/riscv/boot/dts/eswin/hifive-premier-550.dts b/arch/riscv/boot/dts/eswin/hifive-premier-550.dts
index 92a708552e52..2b08a6bbfd2a 100644
--- a/arch/riscv/boot/dts/eswin/hifive-premier-550.dts
+++ b/arch/riscv/boot/dts/eswin/hifive-premier-550.dts
@@ -61,12 +61,6 @@ memory@80000000 {
reg = <0x0 0x80000000 MEMORY_SIZE_H MEMORY_SIZE_L>;
numa-node-id = <0>;
};
- extcon_usb1: extcon_usb1 {
- compatible = "linux,extcon-usb-gpio";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio6_default>;
- id-gpio = <&porta 6 GPIO_ACTIVE_HIGH>;
- };
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@@ -445,15 +439,22 @@ &d0_sata {
&d0_usbdrd3_0 {
status = "okay";
- extcon = <&extcon_usb1>;
};
&d0_usbdrd_dwc3_0 {
status = "okay";
- dr_mode = "otg";
- usb-role-switch;
- role-switch-default-mode = "host";
+ dr_mode = "host";
+ /* usb-role-switch;
+ role-switch-default-mode = "host"; */
maximum-speed = "super-speed";
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dwc3_0_role_switch: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&usbc0_role_sw>;
+ };
+ };
};
&d0_usbdrd3_1 {
@@ -604,14 +605,20 @@ fusb303b@21 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio5_default>;
int-gpios = <&porta 5 GPIO_ACTIVE_HIGH>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ usbc0_role_sw: endpoint@0 {
+ remote-endpoint = <&dwc3_0_role_switch>;
+ };
+ };
+ };
connector {
- label = "USB-C";
- pd-disable = "true";
- power-role = "dual";
- data-role = "dual";
compatible = "usb-c-connector";
- typec-power-opmode = "default";
- try-power-role = "sink";
+ label = "USB-C";
+ data-role = "host";
};
};
diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig
index 61b8f4de69ad..47122461e3fc 100644
--- a/arch/riscv/configs/win2030_defconfig
+++ b/arch/riscv/configs/win2030_defconfig
@@ -148,6 +148,8 @@ CONFIG_PINCTRL_EIC7700=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_DWAPB=y
+CONFIG_SENSORS_ESWIN_FAN_CONTROL=y
+CONFIG_SENSORS_ESWIN_PVT=y
CONFIG_SENSORS_INA2XX=y
CONFIG_SENSORS_PAC1934=y
CONFIG_WATCHDOG=y
@@ -228,6 +230,8 @@ CONFIG_USB_CONFIGFS_F_LB_SS=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_ZERO=m
CONFIG_USB_MASS_STORAGE=m
+CONFIG_TYPEC=y
+CONFIG_TYPEC_FUSB303B=y
CONFIG_MMC=y
CONFIG_MMC_TEST=y
CONFIG_MMC_DEBUG=y
@@ -248,6 +252,7 @@ CONFIG_EDAC=y
CONFIG_EDAC_ESWIN=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_PCF8563=y
+CONFIG_RTC_DRV_ESWIN=y
CONFIG_DMADEVICES=y
CONFIG_DW_AXI_DMAC=y
CONFIG_DMATEST=y
@@ -259,6 +264,7 @@ CONFIG_VIRTIO_INPUT=y
CONFIG_VIRTIO_MMIO=y
CONFIG_STAGING=y
CONFIG_COMMON_CLK_WIN2030=y
+CONFIG_TIMER_ESWIN=y
CONFIG_MAILBOX=y
CONFIG_ESWIN_MBOX=y
CONFIG_ARM_SMMU_V3=y
@@ -268,9 +274,6 @@ CONFIG_EXTCON=y
CONFIG_MEMORY=y
CONFIG_PWM=y
CONFIG_PWM_ESWIN=y
-CONFIG_SENSORS_ESWIN_FAN_CONTROL=y
-CONFIG_SENSORS_ESWIN_PVT=y
-CONFIG_RTC_DRV_ESWIN=y
CONFIG_RESET_ESWIN_WIN2030=y
CONFIG_INTERCONNECT=y
CONFIG_EXT4_FS=y
@@ -320,4 +323,3 @@ CONFIG_RCU_EQS_DEBUG=y
# CONFIG_FTRACE is not set
# CONFIG_RUNTIME_TESTING_MENU is not set
CONFIG_MEMTEST=y
-CONFIG_TIMER_ESWIN=y
\ No newline at end of file
diff --git a/drivers/usb/typec/Kconfig b/drivers/usb/typec/Kconfig
index 2f80c2792dbd..b8bcb74d8d53 100644
--- a/drivers/usb/typec/Kconfig
+++ b/drivers/usb/typec/Kconfig
@@ -110,6 +110,14 @@ config TYPEC_WUSB3801
If you choose to build this driver as a dynamically linked module, the
module will be called wusb3801.ko.
+config TYPEC_FUSB303B
+ tristate "Onsemi FUSB303B Type-C chip driver"
+ depends on I2C
+ depends on EXTCON || !EXTCON
+ help
+ The Onsemi FUSB303B Type-C chip driver that works with
+ Type-C Port Controller Manager to provide USB
+ Type-C functionalities.
source "drivers/usb/typec/mux/Kconfig"
source "drivers/usb/typec/altmodes/Kconfig"
diff --git a/drivers/usb/typec/Makefile b/drivers/usb/typec/Makefile
index 7a368fea61bc..e53e9ea83d6b 100644
--- a/drivers/usb/typec/Makefile
+++ b/drivers/usb/typec/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_TYPEC_STUSB160X) += stusb160x.o
obj-$(CONFIG_TYPEC_RT1719) += rt1719.o
obj-$(CONFIG_TYPEC_WUSB3801) += wusb3801.o
obj-$(CONFIG_TYPEC) += mux/
+obj-$(CONFIG_TYPEC_FUSB303B) += fusb303b.o
diff --git a/drivers/usb/typec/fusb303b.c b/drivers/usb/typec/fusb303b.c
new file mode 100644
index 000000000000..5ffc27640a05
--- /dev/null
+++ b/drivers/usb/typec/fusb303b.c
@@ -0,0 +1,685 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Onsemi FUSB303B Type-C Chip Driver
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Authors: Yang Wei <yangwei1@eswincomputing.com>
+ */
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/gpio/consumer.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/proc_fs.h>
+#include <linux/regulator/consumer.h>
+#include <linux/sched/clock.h>
+#include <linux/seq_file.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/string.h>
+#include <linux/types.h>
+#include <linux/usb.h>
+#include <linux/usb/typec.h>
+#include <linux/usb/tcpm.h>
+#include <linux/usb/pd.h>
+#include <linux/workqueue.h>
+
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include <linux/usb/role.h>
+
+#define FUSB303B_REG_DEVICE_ID 0X1
+#define FUSB303B_REG_DEVICE_TYPE 0X2
+#define FUSB303B_REG_PORTROLE 0X3
+#define FUSB303B_REG_CONTROL 0X4
+#define FUSB303B_REG_CONTROL1 0X5
+#define FUSB303B_REG_MANUAL 0X9
+#define FUSB303B_REG_RESET 0XA
+#define FUSB303B_REG_MASK 0XE
+#define FUSB303B_REG_MASK1 0XF
+#define FUSB303B_REG_STATUS 0X11
+#define FUSB303B_REG_STATUS1 0X12
+#define FUSB303B_REG_TYPE 0X13
+#define FUSB303B_REG_INTERRUPT 0X14
+#define FUSB303B_REG_INTERRUPT1 0X15
+
+#define FUSB303B_PORTROLE_DRP BIT(2)
+#define FUSB303B_PORTROLE_SINK BIT(1)
+#define FUSB303B_PORTROLE_SOURCE BIT(0)
+
+#define FUSB303B_CONTROL_T_DRP BIT(6)
+#define FUSB303B_CONTROL_DRPTOGGLE BIT(4)
+#define FUSB303B_CONTROL_DCABLE_EN BIT(3)
+#define FUSB303B_CONTROL_HOST_CUR BIT(1)
+#define FUSB303B_CONTROL_INT_MASK BIT(0)
+
+#define FUSB303B_CONTROL1_REMEDY_EN BIT(7)
+#define FUSB303B_CONTROL1_AUTO_SNK_TH BIT(5)
+#define FUSB303B_CONTROL1_AUTO_SNK_EN BIT(4)
+#define FUSB303B_CONTROL1_ENABLE BIT(3)
+#define FUSB303B_CONTROL1_TCCDEB BIT(0)
+
+#define FUSB303B_STATUS_AUTOSNK BIT(7)
+#define FUSB303B_STATUS_VSAFE0V BIT(6)
+#define FUSB303B_STATUS_ORIENT BIT(4)
+#define FUSB303B_STATUS_VBUSOK BIT(3)
+#define FUSB303B_STATUS_BC_LVL BIT(1)
+#define FUSB303B_STATUS_BC_LVL_MASK 0X6
+#define FUSB303B_STATUS_ATTACH BIT(0)
+
+#define FUSB303B_STATUS_MASK 0X30
+
+#define FUSB303B_BC_LVL_SINK_OR_RA 0
+#define FUSB303B_BC_LVL_SINK_DEFAULT 1
+#define FUSB303B_BC_LVL_SINK_1_5A 2
+#define FUSB303B_BC_LVL_SINK_3A 3
+
+#define FUSB303B_INT_I_ORIENT BIT(6)
+#define FUSB303B_INT_I_FAULT BIT(5)
+#define FUSB303B_INT_I_VBUS_CHG BIT(4)
+#define FUSB303B_INT_I_AUTOSNK BIT(3)
+#define FUSB303B_INT_I_BC_LVL BIT(2)
+#define FUSB303B_INT_I_DETACH BIT(1)
+#define FUSB303B_INT_I_ATTACH BIT(0)
+
+#define FUSB303B_INT1_I_REM_VBOFF BIT(6)
+#define FUSB303B_INT1_I_REM_VBON BIT(5)
+#define FUSB303B_INT1_I_REM_FAIL BIT(3)
+#define FUSB303B_INT1_I_FRC_FAIL BIT(2)
+#define FUSB303B_INT1_I_FRC_SUCC BIT(1)
+#define FUSB303B_INT1_I_REMEDY BIT(0)
+
+#define FUSB303B_TYPE_SINK BIT(4)
+#define FUSB303B_TYPE_SOURCE BIT(3)
+
+#define FUSB_REG_MASK_M_ORIENT BIT(6)
+#define FUSB_REG_MASK_M_FAULT BIT(5)
+#define FUSB_REG_MASK_M_VBUS_CHG BIT(4)
+#define FUSB_REG_MASK_M_AUTOSNK BIT(3)
+#define FUSB_REG_MASK_M_BC_LVL BIT(2)
+#define FUSB_REG_MASK_M_DETACH BIT(1)
+#define FUSB_REG_MASK_M_ATTACH BIT(0)
+
+#define LOG_BUFFER_ENTRIES 1024
+#define LOG_BUFFER_ENTRY_SIZE 128
+
+struct fusb303b_chip
+{
+ struct device *dev;
+ struct i2c_client *i2c_client;
+ struct fwnode_handle *fwnode;
+ spinlock_t irq_lock;
+ struct gpio_desc *gpio_int_n;
+ int gpio_int_n_irq;
+ struct usb_role_switch *role_sw;
+ /* lock for sharing chip states */
+ struct mutex lock;
+ bool vbus_ok;
+ bool attch_ok;
+#ifdef CONFIG_DEBUG_FS
+ struct dentry *dentry;
+ /* lock for log buffer access */
+ struct mutex logbuffer_lock;
+ int logbuffer_head;
+ int logbuffer_tail;
+ u8 *logbuffer[LOG_BUFFER_ENTRIES];
+#endif
+};
+
+#ifdef CONFIG_DEBUG_FS
+static bool fusb303b_log_full(struct fusb303b_chip *chip)
+{
+ return chip->logbuffer_tail ==
+ (chip->logbuffer_head + 1) % LOG_BUFFER_ENTRIES;
+}
+
+__printf(2, 0) static void _fusb303b_log(struct fusb303b_chip *chip,
+ const char *fmt, va_list args)
+{
+ char tmpbuffer[LOG_BUFFER_ENTRY_SIZE];
+ u64 ts_nsec = local_clock();
+ unsigned long rem_nsec;
+
+ if (!chip->logbuffer[chip->logbuffer_head])
+ {
+ chip->logbuffer[chip->logbuffer_head] =
+ kzalloc(LOG_BUFFER_ENTRY_SIZE, GFP_KERNEL);
+ if (!chip->logbuffer[chip->logbuffer_head])
+ return;
+ }
+
+ vsnprintf(tmpbuffer, sizeof(tmpbuffer), fmt, args);
+
+ mutex_lock(&chip->logbuffer_lock);
+
+ if (fusb303b_log_full(chip))
+ {
+ chip->logbuffer_head = max(chip->logbuffer_head - 1, 0);
+ strlcpy(tmpbuffer, "overflow", sizeof(tmpbuffer));
+ }
+
+ if (chip->logbuffer_head < 0 ||
+ chip->logbuffer_head >= LOG_BUFFER_ENTRIES)
+ {
+ dev_warn(chip->dev, "Bad log buffer index %d\n",
+ chip->logbuffer_head);
+ goto abort;
+ }
+
+ if (!chip->logbuffer[chip->logbuffer_head])
+ {
+ dev_warn(chip->dev, "Log buffer index %d is NULL\n",
+ chip->logbuffer_head);
+ goto abort;
+ }
+
+ rem_nsec = do_div(ts_nsec, 1000000000);
+ scnprintf(chip->logbuffer[chip->logbuffer_head], LOG_BUFFER_ENTRY_SIZE,
+ "[%5lu.%06lu] %s", (unsigned long)ts_nsec, rem_nsec / 1000,
+ tmpbuffer);
+ chip->logbuffer_head = (chip->logbuffer_head + 1) % LOG_BUFFER_ENTRIES;
+
+abort:
+ mutex_unlock(&chip->logbuffer_lock);
+}
+
+__printf(2, 3) static void fusb303b_log(struct fusb303b_chip *chip,
+ const char *fmt, ...)
+{
+ va_list args;
+
+ va_start(args, fmt);
+ _fusb303b_log(chip, fmt, args);
+ va_end(args);
+}
+
+static int fusb303b_debug_show(struct seq_file *s, void *v)
+{
+ struct fusb303b_chip *chip = (struct fusb303b_chip *)s->private;
+ int tail;
+
+ mutex_lock(&chip->logbuffer_lock);
+ tail = chip->logbuffer_tail;
+ while (tail != chip->logbuffer_head)
+ {
+ seq_printf(s, "%s\n", chip->logbuffer[tail]);
+ tail = (tail + 1) % LOG_BUFFER_ENTRIES;
+ }
+ if (!seq_has_overflowed(s))
+ chip->logbuffer_tail = tail;
+ mutex_unlock(&chip->logbuffer_lock);
+
+ return 0;
+}
+DEFINE_SHOW_ATTRIBUTE(fusb303b_debug);
+
+static void fusb303b_debugfs_init(struct fusb303b_chip *chip)
+{
+ char name[NAME_MAX];
+
+ mutex_init(&chip->logbuffer_lock);
+ snprintf(name, NAME_MAX, "fusb303b-%s", dev_name(chip->dev));
+ chip->dentry = debugfs_create_dir(name, usb_debug_root);
+ debugfs_create_file("log", S_IFREG | 0444, chip->dentry, chip,
+ &fusb303b_debug_fops);
+}
+
+static void fusb303b_debugfs_exit(struct fusb303b_chip *chip)
+{
+ debugfs_remove(chip->dentry);
+}
+
+#else
+
+static void fusb303b_log(const struct fusb303b_chip *chip, const char *fmt, ...)
+{
+}
+static void fusb303b_debugfs_init(const struct fusb303b_chip *chip)
+{
+}
+static void fusb303b_debugfs_exit(const struct fusb303b_chip *chip)
+{
+}
+
+#endif
+
+static int fusb303b_i2c_write(struct fusb303b_chip *chip, u8 address, u8 data)
+{
+ int ret = 0;
+
+ ret = i2c_smbus_write_byte_data(chip->i2c_client, address, data);
+ if (ret < 0)
+ fusb303b_log(chip, "cannot write 0x%02x to 0x%02x, ret=%d",
+ data, address, ret);
+
+ return ret;
+}
+
+static int fusb303b_i2c_read(struct fusb303b_chip *chip, u8 address, u8 *data)
+{
+ int ret = 0;
+
+ ret = i2c_smbus_read_byte_data(chip->i2c_client, address);
+ *data = (u8)ret;
+ if (ret < 0)
+ fusb303b_log(chip, "cannot read %02x, ret=%d", address, ret);
+
+ return ret;
+}
+
+static int fusb303b_i2c_mask_write(struct fusb303b_chip *chip, u8 address,
+ u8 mask, u8 value)
+{
+ int ret = 0;
+ u8 data;
+
+ ret = fusb303b_i2c_read(chip, address, &data);
+ if (ret < 0)
+ return ret;
+ data &= ~mask;
+ data |= value;
+ ret = fusb303b_i2c_write(chip, address, data);
+ if (ret < 0)
+ return ret;
+
+ return ret;
+}
+
+static int fusb303b_i2c_clear_bits(struct fusb303b_chip *chip, u8 address,
+ u8 clear_bits)
+{
+ return fusb303b_i2c_mask_write(chip, address, clear_bits, 0x00);
+}
+
+static int fusb303b_sw_reset(struct fusb303b_chip *chip)
+{
+ int ret = 0;
+
+ ret = fusb303b_i2c_write(chip, FUSB303B_REG_RESET, 1);
+ if (ret < 0)
+ fusb303b_log(chip, "cannot sw reset the chip, ret=%d", ret);
+ else
+ fusb303b_log(chip, "sw reset");
+
+ return ret;
+}
+
+/*
+ * initialize interrupt on the chip
+ * - unmasked interrupt: VBUS_OK
+ */
+static int fusb303b_init_interrupt(struct fusb303b_chip *chip)
+{
+ int ret = 0;
+ u8 int_unmask = FUSB_REG_MASK_M_VBUS_CHG |
+ FUSB_REG_MASK_M_DETACH | FUSB_REG_MASK_M_ATTACH;
+ ret = fusb303b_i2c_write(chip, FUSB303B_REG_MASK,
+ 0xFF & ~(int_unmask));
+ if (ret < 0)
+ return ret;
+ ret = fusb303b_i2c_write(chip, FUSB303B_REG_MASK1, 0xFF);
+ if (ret < 0)
+ return ret;
+
+ ret = fusb303b_i2c_clear_bits(chip, FUSB303B_REG_CONTROL,
+ FUSB303B_CONTROL_INT_MASK);
+ if (ret < 0)
+ return ret;
+
+ return ret;
+}
+
+static int fusb303b_init(struct fusb303b_chip *chip)
+{
+ int ret = 0;
+ u8 data;
+
+ ret = fusb303b_sw_reset(chip);
+ if (ret < 0)
+ return ret;
+ fusb303b_i2c_read(chip, FUSB303B_REG_STATUS, &data);
+ fusb303b_i2c_mask_write(chip, FUSB303B_REG_CONTROL,
+ FUSB303B_CONTROL_DCABLE_EN,
+ FUSB303B_CONTROL_DCABLE_EN);
+ fusb303b_i2c_mask_write(chip, FUSB303B_REG_CONTROL1,
+ FUSB303B_CONTROL1_ENABLE | FUSB303B_CONTROL1_REMEDY_EN,
+ FUSB303B_CONTROL1_ENABLE | FUSB303B_CONTROL1_REMEDY_EN);
+ ret = fusb303b_init_interrupt(chip);
+ if (ret < 0)
+ return ret;
+
+ ret = fusb303b_i2c_read(chip, FUSB303B_REG_STATUS, &data);
+ if (ret < 0)
+ return ret;
+ chip->vbus_ok = !!(data & FUSB303B_STATUS_VBUSOK);
+ chip->attch_ok = !!(data & FUSB303B_STATUS_ATTACH);
+ ret = fusb303b_i2c_read(chip, FUSB303B_REG_DEVICE_ID, &data);
+ if (ret < 0)
+ return ret;
+ fusb303b_log(chip, "fusb303b device ID: 0x%02x", data);
+
+ ret = fusb303b_i2c_read(chip, FUSB303B_REG_DEVICE_TYPE, &data);
+ if (ret < 0)
+ return ret;
+ fusb303b_log(chip, "fusb303b type:0x%02x", data);
+
+ return ret;
+}
+
+static s32 fusb303b_set_port_check(struct fusb303b_chip *chip,
+ enum typec_port_type port_type)
+{
+ s32 ret = 0;
+
+ fusb303b_log(chip, "%s.%d port_type:%d",
+ __FUNCTION__, __LINE__, port_type);
+ switch (port_type)
+ {
+ case TYPEC_PORT_DRP:
+ ret = fusb303b_i2c_write(chip, FUSB303B_REG_PORTROLE,
+ FUSB303B_PORTROLE_DRP);
+ break;
+ case TYPEC_PORT_SRC:
+ ret = fusb303b_i2c_write(chip, FUSB303B_REG_PORTROLE,
+ FUSB303B_PORTROLE_SOURCE);
+ break;
+ default:
+ ret = fusb303b_i2c_write(chip, FUSB303B_REG_PORTROLE,
+ FUSB303B_PORTROLE_SINK);
+ break;
+ }
+
+ return ret;
+}
+
+int fusb303b_set_usb_role(struct fusb303b_chip *chip)
+{
+ u8 type = 0;
+ int ret = 0;
+
+ if ((true == chip->attch_ok) && (true == chip->vbus_ok))
+ {
+ ret = fusb303b_i2c_read(chip, FUSB303B_REG_TYPE, &type);
+ if (ret < 0)
+ {
+ fusb303b_log(chip, "read type error:%d", ret);
+ return ret;
+ }
+ fusb303b_log(chip, "%s type: 0x%02x", __func__, type);
+ if (FUSB303B_TYPE_SOURCE == (FUSB303B_TYPE_SOURCE & type))
+ {
+ usb_role_switch_set_role(chip->role_sw, USB_ROLE_HOST);
+ fusb303b_log(chip, "set usb to host");
+ }
+ else
+ {
+ usb_role_switch_set_role(chip->role_sw, USB_ROLE_DEVICE);
+ fusb303b_log(chip, "set usb to device");
+ if (FUSB303B_TYPE_SINK != (FUSB303B_TYPE_SINK & type))
+ {
+ fusb303b_log(chip, "illegel type:0x%02x,set usb to device", type);
+ }
+ }
+ }
+
+ return 0;
+}
+
+static irqreturn_t fusb303b_irq_intn(int irq, void *dev_id)
+{
+ struct fusb303b_chip *chip = dev_id;
+ int ret = 0;
+ u8 interrupt = 0, interrupt1 = 0, status = 0;
+
+ mutex_lock(&chip->lock);
+ ret = fusb303b_i2c_read(chip, FUSB303B_REG_INTERRUPT, &interrupt);
+ if (ret < 0)
+ goto done;
+ ret = fusb303b_i2c_read(chip, FUSB303B_REG_INTERRUPT1, &interrupt1);
+ if (ret < 0)
+ goto done;
+ ret = fusb303b_i2c_read(chip, FUSB303B_REG_STATUS, &status);
+ if (ret < 0)
+ goto done;
+
+ fusb303b_log(chip, "IRQ: 0x%02x,0x%02x status: 0x%02x",
+ interrupt, interrupt1, status);
+
+ if (interrupt & FUSB303B_INT_I_VBUS_CHG)
+ {
+ chip->vbus_ok = !!(status & FUSB303B_STATUS_VBUSOK);
+ fusb303b_log(chip, "IRQ: VBUS_OK, vbus=%s",
+ chip->vbus_ok ? "On" : "Off");
+ }
+ if (interrupt & (FUSB303B_INT_I_ATTACH | FUSB303B_INT_I_DETACH))
+ {
+ chip->attch_ok = !!(status & FUSB303B_STATUS_ATTACH);
+ fusb303b_log(chip, "IRQ: attach OK, attach=%s",
+ chip->attch_ok ? "On" : "Off");
+ }
+ fusb303b_set_usb_role(chip);
+ if (0 != interrupt)
+ fusb303b_i2c_write(chip, FUSB303B_REG_INTERRUPT, interrupt);
+ if (0 != interrupt1)
+ fusb303b_i2c_write(chip, FUSB303B_REG_INTERRUPT1, interrupt1);
+
+done:
+ mutex_unlock(&chip->lock);
+ // enable_irq(chip->gpio_int_n_irq);
+ return IRQ_HANDLED;
+}
+
+static int init_gpio(struct fusb303b_chip *chip)
+{
+ struct device *dev = chip->dev;
+ int ret = 0;
+
+ chip->gpio_int_n = devm_gpiod_get(dev, "int", GPIOD_IN);
+ if (IS_ERR(chip->gpio_int_n))
+ {
+ fusb303b_log(chip, "failed to request gpio_int_n\n");
+ return PTR_ERR(chip->gpio_int_n);
+ }
+ ret = gpiod_to_irq(chip->gpio_int_n);
+ if (ret < 0)
+ {
+ fusb303b_log(chip, "cannot request IRQ for GPIO Int_N, ret=%d", ret);
+ return ret;
+ }
+ chip->gpio_int_n_irq = ret;
+
+ return 0;
+}
+
+static const struct property_entry port_props[] = {
+ PROPERTY_ENTRY_STRING("data-role", "dual"),
+ PROPERTY_ENTRY_STRING("power-role", "dual"),
+ PROPERTY_ENTRY_STRING("try-power-role", "sink"),
+ {}};
+
+static struct fwnode_handle *fusb303b_fwnode_get(struct device *dev)
+{
+ struct fwnode_handle *fwnode;
+ fwnode = device_get_named_child_node(dev, "connector");
+ if (!fwnode)
+ fwnode = fwnode_create_software_node(port_props, NULL);
+
+ return fwnode;
+}
+
+static int fusb303b_probe(struct i2c_client *client)
+{
+ struct fusb303b_chip *chip;
+ struct device *dev = &client->dev;
+ int ret = 0;
+ struct regmap *regmap;
+ int irq_sel_reg;
+ int irq_sel_bit;
+ const char *cap_str;
+ int usb_data_role = 0;
+ regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "eswin,syscfg");
+ if (!IS_ERR(regmap))
+ {
+ ret = of_property_read_u32_index(dev->of_node, "eswin,syscfg",
+ 1, &irq_sel_reg);
+ if (ret)
+ {
+ dev_err(dev,
+ "can't get irq cfg reg offset in sys_con(errno:%d)\n", ret);
+ return ret;
+ }
+ ret = of_property_read_u32_index(dev->of_node, "eswin,syscfg",
+ 2, &irq_sel_bit);
+ if (ret)
+ {
+ dev_err(dev,
+ "can't get irq cfg bit offset in sys_con(errno:%d)\n", ret);
+ return ret;
+ }
+ regmap_clear_bits(regmap, irq_sel_reg, BIT_ULL(irq_sel_bit));
+ }
+
+ chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
+ if (!chip)
+ return -ENOMEM;
+ chip->i2c_client = client;
+ chip->dev = &client->dev;
+ mutex_init(&chip->lock);
+ spin_lock_init(&chip->irq_lock);
+ fusb303b_init(chip);
+ fusb303b_debugfs_init(chip);
+ if (client->irq)
+ {
+ chip->gpio_int_n_irq = client->irq;
+ }
+ else
+ {
+ ret = init_gpio(chip);
+ if (ret < 0)
+ goto destroy_workqueue;
+ }
+ chip->fwnode = fusb303b_fwnode_get(dev);
+ if (IS_ERR(chip->fwnode))
+ {
+ ret = PTR_ERR(chip->fwnode);
+ goto destroy_workqueue;
+ }
+ /*
+ * This fwnode has a "compatible" property, but is never populated as a
+ * struct device. Instead we simply parse it to read the properties.
+ * This it breaks fw_devlink=on. To maintain backward compatibility
+ * with existing DT files, we work around this by deleting any
+ * fwnode_links to/from this fwnode.
+ */
+ fw_devlink_purge_absent_suppliers(chip->fwnode);
+
+ /* USB data support is optional */
+ ret = fwnode_property_read_string(chip->fwnode, "data-role", &cap_str);
+ if (ret == 0)
+ {
+ ret = typec_find_port_data_role(cap_str);
+ if (ret < 0)
+ {
+ fusb303b_log(chip, "%s is not leage data-role\n", cap_str);
+ goto put_fwnode;
+ }
+ usb_data_role = ret;
+ }
+ else
+ {
+ fusb303b_log(chip, "cannot find data-role in dts\n");
+ }
+ chip->role_sw = usb_role_switch_get(chip->dev);
+ if (IS_ERR(chip->role_sw))
+ {
+ ret = PTR_ERR(chip->role_sw);
+ fusb303b_log(chip, "get role_sw error");
+ goto put_fwnode;
+ }
+
+ ret = devm_request_threaded_irq(dev, chip->gpio_int_n_irq, NULL,
+ fusb303b_irq_intn,
+ IRQF_ONESHOT | IRQF_TRIGGER_LOW,
+ "fusb303b_interrupt_int_n", chip);
+ if (ret < 0)
+ {
+ fusb303b_log(chip, "cannot request IRQ for GPIO Int_N, ret=%d", ret);
+ goto err_put_role;
+ }
+
+ enable_irq_wake(chip->gpio_int_n_irq);
+ fusb303b_set_port_check(chip, usb_data_role);
+
+ i2c_set_clientdata(client, chip);
+
+ fusb303b_log(chip, "Kernel thread created successfully");
+ return ret;
+err_put_role:
+ usb_role_switch_put(chip->role_sw);
+put_fwnode:
+ fwnode_handle_put(chip->fwnode);
+destroy_workqueue:
+ fusb303b_debugfs_exit(chip);
+
+ return ret;
+}
+
+static void fusb303b_remove(struct i2c_client *client)
+{
+ struct fusb303b_chip *chip = i2c_get_clientdata(client);
+
+ disable_irq_wake(chip->gpio_int_n_irq);
+ free_irq(chip->gpio_int_n_irq, chip);
+ usb_role_switch_put(chip->role_sw);
+ fwnode_handle_put(chip->fwnode);
+ fusb303b_debugfs_exit(chip);
+}
+
+static const struct of_device_id fusb303b_dt_match[] = {
+ {.compatible = "fcs,fusb303b"},
+ {},
+};
+MODULE_DEVICE_TABLE(of, fusb303b_dt_match);
+
+static const struct i2c_device_id fusb303b_i2c_device_id[] = {
+ {"typec_fusb303b", 0},
+ {},
+};
+MODULE_DEVICE_TABLE(i2c, fusb303b_i2c_device_id);
+
+static struct i2c_driver fusb303b_driver = {
+ .driver = {
+ .name = "typec_fusb303b",
+ .of_match_table = of_match_ptr(fusb303b_dt_match),
+ },
+ .probe = fusb303b_probe,
+ .remove = fusb303b_remove,
+ .id_table = fusb303b_i2c_device_id,
+};
+module_i2c_driver(fusb303b_driver);
+
+MODULE_AUTHOR("Yang Wei <yangwei1@eswincomputing.com>");
+MODULE_DESCRIPTION("Onsemi FUSB303B Type-C Chip Driver");
+MODULE_LICENSE("GPL");
--
2.47.0

68
0046-chore-es_buddy-Memory-workaround-for-g2d-hardware-pr.patch Normal file
View File

@ -0,0 +1,68 @@
From 221444b660084d7c5ffad322c7ad1d12729b8d98 Mon Sep 17 00:00:00 2001
From: linmin <linmin@eswincomputing.com>
Date: Tue, 4 Jun 2024 14:23:32 +0800
Subject: [PATCH 046/219] chore(es_buddy):Memory workaround for g2d hardware
problem
Changelogs:
1.Modified the buddy_system_init() interface in buddy.h accroding to the
modification of libs/common whose commit id is:f0a47cf4ca77323388f8
This is a workaround for g2d because the g2d hardware has problem
with accessing the 4GB boundary address.
2.Reserved 4kB size of memory at 4GB address boundary in eic7700-evb.dts
and eic7700-evb-a2.dts, so that it is excluded from system memory and
will never be used by g2d.
---
arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts | 5 +++++
arch/riscv/boot/dts/eswin/eic7700-evb.dts | 5 +++++
drivers/memory/eswin/buddy.h | 2 +-
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
index f5c4712de03e..3f35d2201584 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
@@ -112,6 +112,11 @@ secure_memory_nid_0_part_1 {
no-map;
};
+ g2d_4GB_boundary_reserved_4k {
+ no-map;
+ reg = <0x0 0xfffff000 0x0 0x1000>;
+ };
+
mmz_nid_0_part_0 {
compatible = "eswin-reserve-memory";
reg = <0x1 0x40000000 0x2 0x80000000>;
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb.dts b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
index e3c9de0ada5d..f41705285b0b 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
@@ -111,6 +111,11 @@ secure_memory_nid_0_part_1 {
no-map;
};
+ g2d_4GB_boundary_reserved_4k {
+ no-map;
+ reg = <0x0 0xfffff000 0x0 0x1000>;
+ };
+
mmz_nid_0_part_0 {
compatible = "eswin-reserve-memory";
reg = <0x1 0x40000000 0x2 0x80000000>;
diff --git a/drivers/memory/eswin/buddy.h b/drivers/memory/eswin/buddy.h
index e3c509a511c6..bc0fd6eb6ddb 100644
--- a/drivers/memory/eswin/buddy.h
+++ b/drivers/memory/eswin/buddy.h
@@ -105,7 +105,7 @@ struct mem_block {
};
#endif
-void buddy_system_init(struct mem_zone *zone,
+void buddy_system_init(struct mem_block *memblock,
struct esPage_s *start_page,
unsigned long start_addr,
unsigned long page_num);
--
2.47.0

169
0047-feat-ISP-Add-VI-dev-to-linux-6.6.patch Normal file
View File

@ -0,0 +1,169 @@
From 83dc0a0e54d543f8d0b9c74eb072da2aada534e9 Mon Sep 17 00:00:00 2001
From: lilijun <lilijun@eswincomputing.com>
Date: Mon, 27 May 2024 16:19:01 +0800
Subject: [PATCH 047/219] feat(ISP): Add VI dev to linux 6.6
Changelogs:
1.Add csi,isp,i2... vi device nodes to evb&evb-a2
---
arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts | 12 ++++++------
arch/riscv/boot/dts/eswin/eic7700-evb.dts | 12 ++++++------
.../riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi | 10 +++++++---
arch/riscv/configs/win2030_defconfig | 1 +
4 files changed, 20 insertions(+), 15 deletions(-)
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
index 3f35d2201584..93e0e29bf2c7 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
@@ -435,11 +435,11 @@ &d0_graphcard2 {
};
&isp_0 {
- status = "disabled";
+ status = "okay";
};
&isp_1 {
- status = "disabled";
+ status = "okay";
};
&dewarp {
@@ -447,11 +447,11 @@ &dewarp {
};
&mipi_dphy_rx {
- status = "disabled";
+ status = "okay";
};
&csi_dma0 {
- status = "disabled";
+ status = "okay";
};
&csi_dma1 {
@@ -459,7 +459,7 @@ &csi_dma1 {
};
&csi2_0 {
- status = "disabled";
+ status = "okay";
};
&csi2_1 {
@@ -745,7 +745,7 @@ &d0_i2c2 {
&d0_i2c3 {
/* mipi csi0/csi1 */
- status = "disabled";
+ status = "okay";
};
&d0_i2c4 {
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb.dts b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
index f41705285b0b..64a47c750f0d 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
@@ -408,11 +408,11 @@ &d0_graphcard2 {
};
&isp_0 {
- status = "disabled";
+ status = "okay";
};
&isp_1 {
- status = "disabled";
+ status = "okay";
};
&dewarp {
@@ -420,11 +420,11 @@ &dewarp {
};
&mipi_dphy_rx {
- status = "disabled";
+ status = "okay";
};
&csi_dma0 {
- status = "disabled";
+ status = "okay";
};
&csi_dma1 {
@@ -432,7 +432,7 @@ &csi_dma1 {
};
&csi2_0 {
- status = "disabled";
+ status = "okay";
};
&csi2_1 {
@@ -702,7 +702,7 @@ &d0_i2c2 {
&d0_i2c3 {
/* mipi csi0/csi1 */
- status = "disabled";
+ status = "okay";
};
&d0_i2c4 {
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
index a499864a4e99..55aba79102eb 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
@@ -2025,12 +2025,14 @@ vi_top_csr: vi_common_top_csr@0x51030000 {
<&d0_reset SHUTTER_RST_CTRL SW_VI_SHUTTER_RSTN_4>,
<&d0_reset SHUTTER_RST_CTRL SW_VI_SHUTTER_RSTN_5>;
reset-names = "axi", "cfg", "isp0", "isp1", "dvp", "sht0", "sht1", "sht2", "sht3", "sht4", "sht5";
-
+ interrupt-parent = <&plic0>;
+ interrupts = <368 369 370 371 372 373 374 375>;
id = <0>;
#size-cells = <2>;
reg = <0x0 0x51030000 0x0 0x10000>;
};
+
isp_0: isp@0x51000000 {
compatible = "esw,win2030-isp";
@@ -2177,7 +2179,9 @@ csi2_0_1: endpoint {
port@2 {
reg = <2>;
csi2_dma_0_3: endpoint {
- bus-type = <5>;
+ bus-type = <4>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
remote-endpoint = <&csi_dmar_0>;
};
};
@@ -2222,7 +2226,7 @@ csi2_1_1: endpoint {
port@2 {
reg = <2>;
csi2_dma_1_3: endpoint {
- bus-type = <5>;
+ bus-type = <4>;
remote-endpoint = <&csi_dmar_1>;
};
};
diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig
index 47122461e3fc..65b68c9e1d27 100644
--- a/arch/riscv/configs/win2030_defconfig
+++ b/arch/riscv/configs/win2030_defconfig
@@ -159,6 +159,7 @@ CONFIG_REGULATOR_MPQ8785=y
# CONFIG_MEDIA_CEC_SUPPORT is not set
CONFIG_MEDIA_SUPPORT=y
CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VIDEO_XILINX=y
CONFIG_DRM=y
# CONFIG_DRM_I2C_CH7006 is not set
# CONFIG_DRM_I2C_SIL164 is not set
--
2.47.0

31
0048-fix-add-enable-disable-for-hdcp1x.patch Normal file
View File

@ -0,0 +1,31 @@
From 9036865c804a798f2823a2f485146cb1143a9b3a Mon Sep 17 00:00:00 2001
From: yiguo <yiguo@eswincomputing.com>
Date: Thu, 6 Jun 2024 17:04:36 +0800
Subject: [PATCH 048/219] fix:add enable/disable for hdcp1x
Changelogs:
1. add enable/disable for hdcp1x
---
drivers/gpu/drm/eswin/Kconfig | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/eswin/Kconfig b/drivers/gpu/drm/eswin/Kconfig
index 1ad77afba9c3..de77dc0d9101 100644
--- a/drivers/gpu/drm/eswin/Kconfig
+++ b/drivers/gpu/drm/eswin/Kconfig
@@ -71,6 +71,12 @@ config DW_HDMI_HDCP2
Support the HDCP2 interface which is part of the Synopsys
Designware HDMI block.
+config DW_HDMI_HDCP1X_ENABLED
+ bool "Synopsis Designware HDCP1X enabled"
+ depends on DW_HDMI_HDCP
+ help
+ Enable/Disable HDCP1X of the Synopsys Designware HDMI block.
+
config ESWIN_MIPI_DSI
tristate "Eswin mipi dsi and 1080p panel driver"
--
2.47.0

127
0049-fix-optimize-SDHCI-driver.patch Normal file
View File

@ -0,0 +1,127 @@
From e62120e3b77a52a4647585b3f27e56cac7b6b0da Mon Sep 17 00:00:00 2001
From: liangshuang <liangshuang@eswincomputing.com>
Date: Fri, 7 Jun 2024 11:10:10 +0800
Subject: [PATCH 049/219] fix:optimize SDHCI driver.
Changelogs:
1.Fix the issue of failed tuning of the Sandisk SD card.
2.Fix the issue of unexpected interrupts generated by EMMC/SDIO during the probe process.
---
drivers/mmc/host/sdhci-of-eswin-sdio.c | 36 +++++++++++++++++++++-----
drivers/mmc/host/sdhci-of-eswin.c | 8 ++++--
2 files changed, 35 insertions(+), 9 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-eswin-sdio.c b/drivers/mmc/host/sdhci-of-eswin-sdio.c
index 83cbdb61c936..badbee00b39e 100644
--- a/drivers/mmc/host/sdhci-of-eswin-sdio.c
+++ b/drivers/mmc/host/sdhci-of-eswin-sdio.c
@@ -42,7 +42,7 @@
#define ESWIN_SDHCI_SD1_INT_STATUS 0x708
#define ESWIN_SDHCI_SD1_PWR_CTRL 0x70c
-#define DELAY_RANGE_THRESHOLD 40
+#define DELAY_RANGE_THRESHOLD 20
struct eswin_sdio_private {
int phase_code;
@@ -150,7 +150,22 @@ static void eswin_sdhci_sdio_reset(struct sdhci_host *host, u8 mask)
struct eswin_sdhci_data *eswin_sdhci_sdio =
sdhci_pltfm_priv(pltfm_host);
- sdhci_reset(host, mask);
+ sdhci_writel(host, 0, SDHCI_INT_ENABLE);
+ sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
+
+ if (mask & SDHCI_RESET_ALL) {
+ sdhci_reset(host, SDHCI_RESET_ALL);
+ }
+ if (mask & SDHCI_RESET_DATA) {
+ sdhci_reset(host, SDHCI_RESET_DATA);
+ }
+
+ if (mask & SDHCI_RESET_CMD) {
+ sdhci_reset(host, SDHCI_RESET_CMD);
+ }
+
+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
if (eswin_sdhci_sdio->quirks & SDHCI_ESWIN_QUIRK_FORCE_CDTEST) {
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
@@ -181,10 +196,9 @@ static int eswin_sdhci_sdio_delay_tuning(struct sdhci_host *host, u32 opcode)
eswin_sdhci_sdio_config_phy_delay(host, i);
eswin_sdhci_enable_card_clk(host);
ret = mmc_send_tuning(host->mmc, opcode, &cmd_error);
+ host->ops->reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
if (ret) {
- pr_debug("%s: bad delay:0x%x\n", mmc_hostname(host->mmc), i);
- sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
- udelay(200);
+ pr_debug("%s: bad delay:0x%x!\n", mmc_hostname(host->mmc), i);
if (delay_min != -1 && delay_max != -1) {
if (delay_max - delay_min > delay_range) {
delay_range = delay_max - delay_min;
@@ -227,6 +241,14 @@ static int eswin_sdhci_sdio_delay_tuning(struct sdhci_host *host, u32 opcode)
eswin_sdhci_sdio_config_phy_delay(host, delay);
eswin_sdhci_enable_card_clk(host);
+ ret = mmc_send_tuning(host->mmc, opcode, &cmd_error);
+ host->ops->reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+ if (ret) {
+ pr_err("%s: delay code(0x%x) not work, tuning failed!\n",
+ mmc_hostname(host->mmc), delay);
+ return ret;
+ }
+
return 0;
}
@@ -245,9 +267,9 @@ static int eswin_sdhci_sdio_phase_code_tuning(struct sdhci_host *host,
eswin_sdhci_enable_card_clk(host);
ret = mmc_send_tuning(host->mmc, opcode, &cmd_error);
+ host->ops->reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
if (ret) {
- sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
- udelay(200);
+ pr_debug("%s: bad phase_code:0x%x\n", mmc_hostname(host->mmc), phase_code);
if (code_min != -1 && code_max != -1)
break;
} else {
diff --git a/drivers/mmc/host/sdhci-of-eswin.c b/drivers/mmc/host/sdhci-of-eswin.c
index 41aa80f8dbe3..a0347ac5c739 100644
--- a/drivers/mmc/host/sdhci-of-eswin.c
+++ b/drivers/mmc/host/sdhci-of-eswin.c
@@ -181,7 +181,11 @@ static void eswin_sdhci_reset(struct sdhci_host *host, u8 mask)
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct eswin_sdhci_data *eswin_sdhci = sdhci_pltfm_priv(pltfm_host);
+ sdhci_writel(host, 0, SDHCI_INT_ENABLE);
+ sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
sdhci_reset(host, mask);
+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
if (eswin_sdhci->quirks & SDHCI_ESWIN_QUIRK_FORCE_CDTEST) {
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
@@ -243,7 +247,7 @@ static int eswin_sdhci_delay_tuning(struct sdhci_host *host, u32 opcode)
eswin_sdhci_enable_card_clk(host);
ret = mmc_send_tuning(host->mmc, opcode, &cmd_error);
if (ret) {
- sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+ host->ops->reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
udelay(200);
if (delay_min != -1 && delay_max != -1)
break;
@@ -291,7 +295,7 @@ static int eswin_sdhci_phase_code_tuning(struct sdhci_host *host, u32 opcode)
ret = mmc_send_tuning(host->mmc, opcode, &cmd_error);
if (ret) {
- sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+ host->ops->reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
udelay(200);
if (code_min != -1 && code_max != -1)
break;
--
2.47.0

84
0050-feat-Support-tca6416-for-csi-reset.patch Normal file
View File

@ -0,0 +1,84 @@
From 8340cd7890dfce74383c92ffacccbe6d4bbbe756 Mon Sep 17 00:00:00 2001
From: lilijun <lilijun@eswincomputing.com>
Date: Thu, 13 Jun 2024 14:17:37 +0800
Subject: [PATCH 050/219] feat:Support tca6416 for csi reset
Changelogs:
1.Enable tca6416 gpio expaner
2.Sensor reset needed
---
arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts | 23 +++++++++++++++++++-
arch/riscv/boot/dts/eswin/eic7700-evb.dts | 23 +++++++++++++++++++-
2 files changed, 44 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
index 93e0e29bf2c7..7a3702e88b19 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
@@ -770,7 +770,28 @@ &d0_i2c7 {
&d0_i2c8 {
/* io extended for mipi csi */
- status = "disabled";
+ status = "okay";
+ tca6416_0: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* IRQ not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "MIPI_CSI0_PWDN", "MIPI_CSI0_RESET", "MIPI_CSI1_FBC", "MIPI_CSI1_ENB",
+ "MIPI_CSI1_RESET", "MIPI_CSI1_PWDN", "FREX_GP0", "",
+ "MIPI_CSI0_ENB", "MIPI_CSI0_FBC", "FREX_GP2", "MIPI_CSI2_FBC",
+ "MIPI_CSI2_ENB", "FREX_GP1", "MIPI_CSI2_RESET", "MIPI_CSI2_PWDN";
+ };
+ tca6416_1: gpio@21 {
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* IRQ not connected */
+ gpio-line-names = "MIPI_CSI3_PWDN", "MIPI_CSI3_RESET", "MIPI_CSI3_ENB", "MIPI_CSI3_FBC",
+ "MIPI_CSI4_PWDN", "MIPI_CSI4_RESET", "MIPI_CSI4_ENB", "MIPI_CSI4_FBC",
+ "MIPI_CSI5_FBC", "MIPI_CSI5_ENB", "MIPI_CSI5_RESET", "MIPI_CSI5_PWDN",
+ "", "", "", "";
+ };
};
&d0_i2c9 {
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb.dts b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
index 64a47c750f0d..5e18922ba44a 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
@@ -727,7 +727,28 @@ &d0_i2c7 {
&d0_i2c8 {
/* io extended for mipi csi */
- status = "disabled";
+ status = "okay";
+ tca6416_0: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* IRQ not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "MIPI_CSI0_PWDN", "MIPI_CSI0_RESET", "MIPI_CSI1_FBC", "MIPI_CSI1_ENB",
+ "MIPI_CSI1_RESET", "MIPI_CSI1_PWDN", "FREX_GP0", "",
+ "MIPI_CSI0_ENB", "MIPI_CSI0_FBC", "FREX_GP2", "MIPI_CSI2_FBC",
+ "MIPI_CSI2_ENB", "FREX_GP1", "MIPI_CSI2_RESET", "MIPI_CSI2_PWDN";
+ };
+ tca6416_1: gpio@21 {
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* IRQ not connected */
+ gpio-line-names = "MIPI_CSI3_PWDN", "MIPI_CSI3_RESET", "MIPI_CSI3_ENB", "MIPI_CSI3_FBC",
+ "MIPI_CSI4_PWDN", "MIPI_CSI4_RESET", "MIPI_CSI4_ENB", "MIPI_CSI4_FBC",
+ "MIPI_CSI5_FBC", "MIPI_CSI5_ENB", "MIPI_CSI5_RESET", "MIPI_CSI5_PWDN",
+ "", "", "", "";
+ };
};
&d0_i2c9 {
--
2.47.0

549
0051-refactor-Implement-pcie-intx-and-pmu-dtsi-config.patch Normal file
View File

@ -0,0 +1,549 @@
From 064c33488cd5b4541689f47504dcdd9d390da706 Mon Sep 17 00:00:00 2001
From: ningyu <ningyu@eswincomputing.com>
Date: Thu, 13 Jun 2024 18:12:38 +0800
Subject: [PATCH 051/219] refactor:Implement pcie intx and pmu dtsi config
Changelogs:
1. Implement pcie intx, optimize pcie driver
2. Add pmu configuration in dtsi, in order to fully support perf operations, you need to add pmu nodes to uboot's dtsi
3. Added support for pcie wifi rtl8191se
---
.../boot/dts/eswin/eswin-win2030-arch.dtsi | 48 ++---
.../dts/eswin/eswin-win2030-die0-soc.dtsi | 17 +-
arch/riscv/configs/win2030_defconfig | 24 ++-
drivers/pci/controller/dwc/pcie-eswin.c | 195 ++++--------------
4 files changed, 80 insertions(+), 204 deletions(-)
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-arch.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-arch.dtsi
index 997afe1fa6a2..3571f134aacc 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-arch.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-arch.dtsi
@@ -66,7 +66,7 @@ L17: cpu@0 {
mmu-type = "riscv,sv48";
next-level-cache = <&L15>;
reg = <0x0>;
- riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
+ riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb_sscofpmf";
riscv,pmpgranularity = <4096>;
riscv,pmpregions = <8>;
sifive,buserror = <&L16>;
@@ -80,10 +80,6 @@ L14: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
};
- L13: pmu {
- compatible = "riscv,pmu0", "riscv,pmu";
- interrupts-extended = <&L14 13>;
- };
};
L22: cpu@1 {
clock-frequency = <0>;
@@ -112,7 +108,7 @@ L22: cpu@1 {
mmu-type = "riscv,sv48";
next-level-cache = <&L20>;
reg = <0x1>;
- riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
+ riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb_sscofpmf";
riscv,pmpgranularity = <4096>;
riscv,pmpregions = <8>;
sifive,buserror = <&L21>;
@@ -126,10 +122,6 @@ L19: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
};
- L18: pmu {
- compatible = "riscv,pmu0", "riscv,pmu";
- interrupts-extended = <&L19 13>;
- };
};
L27: cpu@2 {
clock-frequency = <0>;
@@ -158,7 +150,7 @@ L27: cpu@2 {
mmu-type = "riscv,sv48";
next-level-cache = <&L25>;
reg = <0x2>;
- riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
+ riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb_sscofpmf";
riscv,pmpgranularity = <4096>;
riscv,pmpregions = <8>;
sifive,buserror = <&L26>;
@@ -172,10 +164,6 @@ L24: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
};
- L23: pmu {
- compatible = "riscv,pmu0", "riscv,pmu";
- interrupts-extended = <&L24 13>;
- };
};
L32: cpu@3 {
clock-frequency = <0>;
@@ -204,7 +192,7 @@ L32: cpu@3 {
mmu-type = "riscv,sv48";
next-level-cache = <&L30>;
reg = <0x3>;
- riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
+ riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb_sscofpmf";
riscv,pmpgranularity = <4096>;
riscv,pmpregions = <8>;
sifive,buserror = <&L31>;
@@ -218,10 +206,6 @@ L29: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
};
- L28: pmu {
- compatible = "riscv,pmu0", "riscv,pmu";
- interrupts-extended = <&L29 13>;
- };
};
};
L50: memory@80000000 {
@@ -235,6 +219,15 @@ SOC: soc {
#size-cells = <2>;
compatible = "SiFive,FU800-soc", "fu800-soc", "sifive-soc", "simple-bus";
ranges;
+ pmu {
+ riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xff 0x1f8
+ 0x0 0x1 0xffffffff 0xfff800ff 0x1f8
+ 0x0 0x2 0xffffffff 0xffffc0ff 0x1f8>;
+ riscv,event-to-mhpmcounters = <0x01 0x01 0x01 0x02 0x02 0x02 0x4 0x6 0x1f8 0x10009 0x10009 0x1f8 0x10019 0x10019 0x1f8 0x10021 0x10021 0x1f8>;
+ riscv,event-to-mhpmevent = <0x4 0x0 0x202 0x5 0x0 0x4000 0x6 0x0 0x2001 0x10009 0x0 0x102 0x10019 0x0 0x1002 0x10021 0x0 0x802>;
+ compatible = "riscv,pmu0", "riscv,pmu";
+ interrupts-extended = <&L14 13 &L19 13 &L24 13 &L29 13>;
+ };
L40: authentication-controller {
compatible = "sifive,authentication0";
sifive,auth-types = "fuse";
@@ -320,14 +313,6 @@ L7: cache-controller@2010000 {
sifive,perfmon-counters = <6>;
numa-node-id = <0>;
};
- /*
- L33: clint@2000000 {
- compatible = "riscv,clint0";
- interrupts-extended = <&L14 3 &L14 7 &L19 3 &L19 7 &L24 3 &L24 7 &L29 3 &L29 7>;
- reg = <0x0 0x2000000 0x0 0x10000>;
- reg-names = "control";
- };
- */
L34: debug-controller@0 {
compatible = "sifive,debug-100", "riscv,debug-100";
debug-attach = "jtag";
@@ -342,13 +327,6 @@ L9: error-device@10003000 {
compatible = "sifive,error0";
reg = <0x0 0x10003000 0x0 0x1000>;
};
- /*
- L49: global-external-interrupts {
- compatible = "sifive,global-external-interrupts0";
- interrupt-parent = <&plic0>;
- interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515>;
- };
- */
plic0: interrupt-controller@c000000 {
#interrupt-cells = <1>;
compatible = "sifive,plic-1.0.0";
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
index 55aba79102eb..9f76de5f0162 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
@@ -784,22 +784,21 @@ pcie: pcie@0x54000000 {
<0x82000000 0x0 0x41000000 0x0 0x41000000 0x0 0xf000000>, /* mem */
<0xc3000000 0x80 0x00000000 0x80 0x00000000 0x2 0x00000000>; /* mem prefetchable */
- /* num-lanes = <0x4>; */
+ num-lanes = <0x4>;
/**********************************
msi_ctrl_io[0~31] : 188~219
msi_ctrl_int : 220
**********************************/
- interrupts = <220>;
- interrupt-names = "msi";
+ interrupts = <220>, <179>, <180>, <181>, <182>, <183>, <184>, <185>, <186>;
+ interrupt-names = "msi", "inta", "intb", "intc", "intd";
interrupt-parent = <&plic0>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &plic0 179>,
+ <0x0 0x0 0x0 0x2 &plic0 180>,
+ <0x0 0x0 0x0 0x3 &plic0 181>,
+ <0x0 0x0 0x0 0x4 &plic0 182>;
iommus = <&smmu0 0xfe0000>;
iommu-map = <0x0 &smmu0 0xff0000 0xffffff>;
- #ifdef PLATFORM_HAPS
- gen-x = <1>;
- #else
- gen-x = <3>;
- #endif
- lane-x = <4>;
tbus = <WIN2030_TBUID_PCIE>;
status = "disabled";
numa-node-id = <0>;
diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig
index 65b68c9e1d27..f12568c50271 100644
--- a/arch/riscv/configs/win2030_defconfig
+++ b/arch/riscv/configs/win2030_defconfig
@@ -49,6 +49,10 @@ CONFIG_NET_SCHED=y
CONFIG_NET_CLS_ACT=y
CONFIG_CFG80211=y
CONFIG_CFG80211_WEXT=y
+CONFIG_MAC80211=y
+CONFIG_RFKILL=y
+CONFIG_RFKILL_INPUT=y
+CONFIG_RFKILL_GPIO=y
CONFIG_PCI=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCIEAER=y
@@ -116,7 +120,25 @@ CONFIG_DWMAC_WIN2030=y
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_NET_VENDOR_XILINX is not set
-# CONFIG_WLAN is not set
+# CONFIG_WLAN_VENDOR_ADMTEK is not set
+# CONFIG_WLAN_VENDOR_ATH is not set
+# CONFIG_WLAN_VENDOR_ATMEL is not set
+# CONFIG_WLAN_VENDOR_BROADCOM is not set
+# CONFIG_WLAN_VENDOR_CISCO is not set
+# CONFIG_WLAN_VENDOR_INTEL is not set
+# CONFIG_WLAN_VENDOR_INTERSIL is not set
+# CONFIG_WLAN_VENDOR_MARVELL is not set
+# CONFIG_WLAN_VENDOR_MEDIATEK is not set
+# CONFIG_WLAN_VENDOR_MICROCHIP is not set
+# CONFIG_WLAN_VENDOR_PURELIFI is not set
+# CONFIG_WLAN_VENDOR_RALINK is not set
+CONFIG_RTL8192SE=m
+# CONFIG_WLAN_VENDOR_RSI is not set
+# CONFIG_WLAN_VENDOR_SILABS is not set
+# CONFIG_WLAN_VENDOR_ST is not set
+# CONFIG_WLAN_VENDOR_TI is not set
+# CONFIG_WLAN_VENDOR_ZYDAS is not set
+# CONFIG_WLAN_VENDOR_QUANTENNA is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
diff --git a/drivers/pci/controller/dwc/pcie-eswin.c b/drivers/pci/controller/dwc/pcie-eswin.c
index 66941cce9dde..ab1f4b421eab 100644
--- a/drivers/pci/controller/dwc/pcie-eswin.c
+++ b/drivers/pci/controller/dwc/pcie-eswin.c
@@ -40,26 +40,10 @@
#include <linux/property.h>
#include "pcie-designware.h"
-#undef _IO_DEBUG_
-
-#ifdef _IO_DEBUG_
-#define _writel_relaxed(v, p) ({ u32 __dbg_v; writel_relaxed(v, p); __dbg_v = readl_relaxed(p); printk("CFG 0x%lx : 0x%08x\n",p, __dbg_v); })
-
-// #define _io_read32(p) ({ u32 __dbg_v; __dbg_v = readl(p); printf("RD 0x%lx : 0x%08x\n",p, __dbg_v); __dbg_v; })
-
-#else
-#define _writel_relaxed(v, p) writel_relaxed(v, p)
-// #define _io_read32(p) io_read32(p)
-#endif
-
-#define to_eswin_pcie(x) dev_get_drvdata((x)->dev)
-
struct eswin_pcie {
struct dw_pcie pci;
void __iomem *mgmt_base;
- // void __iomem *sysmgt_base;
struct gpio_desc *reset;
- // struct gpio_desc *pwren;
struct clk *pcie_aux;
struct clk *pcie_cfg;
struct clk *pcie_cr;
@@ -67,31 +51,26 @@ struct eswin_pcie {
struct reset_control *powerup_rst;
struct reset_control *cfg_rst;
struct reset_control *perst;
- int gen_x;
- int lane_x;
};
-#define PCIEMGMT_ACLK_CTRL 0x170
-#define PCIEMGMT_ACLK_CLKEN BIT(31)
-#define PCIEMGMT_XTAL_SEL BIT(20)
-#define PCIEMGMT_DIVSOR 0xf0
-
-#define PCIEMGMT_CFG_CTRL 0x174
-#define PCIEMGMT_CFG_CLKEN BIT(31)
-#define PCIEMGMT_AUX_CLKEN BIT(1)
-#define PCIEMGMT_CR_CLKEN BIT(0)
-
-#define PCIEMGMT_RST_CTRL 0x420
-#define PCIEMGMT_PERST_N BIT(2)
-#define PCIEMGMT_POWERUP_RST_N BIT(1)
-#define PCIEMGMT_CFG_RST_N BIT(0)
-
#define PCIE_PM_SEL_AUX_CLK BIT(16)
-
#define PCIEMGMT_APP_HOLD_PHY_RST BIT(6)
#define PCIEMGMT_APP_LTSSM_ENABLE BIT(5)
#define PCIEMGMT_DEVICE_TYPE_MASK 0xf
+#define PCIEMGMT_CTRL0_OFFSET 0x0
+#define PCIEMGMT_STATUS0_OFFSET 0x100
+
+#define PCIE_TYPE_DEV_VEND_ID 0x0
+// #define PCIE_DSP_PF0_PM_CAP 0x40
+#define PCIE_DSP_PF0_MSI_CAP 0x50
+#define PCIE_NEXT_CAP_PTR 0x70
+#define DEVICE_CONTROL_DEVICE_STATUS 0x78
+// #define PCIE_DSP_PF0_MSIX_CAP 0xb0
+
+#define PCIE_MSI_MULTIPLE_MSG_32 (0x5<<17)
+#define PCIE_MSI_MULTIPLE_MSG_MASK (0x7<<17)
+
#define PCIEMGMT_LINKUP_STATE_VALIDATE ((0x11<<2)|0x3)
#define PCIEMGMT_LINKUP_STATE_MASK 0xff
@@ -110,9 +89,9 @@ static int eswin_pcie_start_link(struct dw_pcie *pci)
u32 val;
/* Enable LTSSM */
- val = readl_relaxed(pcie->mgmt_base);
+ val = readl_relaxed(pcie->mgmt_base + PCIEMGMT_CTRL0_OFFSET);
val |= PCIEMGMT_APP_LTSSM_ENABLE;
- _writel_relaxed(val, pcie->mgmt_base);
+ writel_relaxed(val, pcie->mgmt_base + PCIEMGMT_CTRL0_OFFSET);
return 0;
}
@@ -122,7 +101,7 @@ static int eswin_pcie_link_up(struct dw_pcie *pci)
struct eswin_pcie *pcie = dev_get_drvdata(dev);
u32 val;
- val = readl_relaxed(pcie->mgmt_base + 0x100);
+ val = readl_relaxed(pcie->mgmt_base + PCIEMGMT_STATUS0_OFFSET);
if ((val & PCIEMGMT_LINKUP_STATE_MASK) == PCIEMGMT_LINKUP_STATE_VALIDATE)
return 1;
else
@@ -172,7 +151,6 @@ static int eswin_pcie_clk_disable(struct eswin_pcie *eswin_pcie)
static int eswin_pcie_power_on(struct eswin_pcie *pcie)
{
- // struct device *dev = &pdev->dev;
int ret = 0;
/* pciet_cfg_rstn */
@@ -183,10 +161,6 @@ static int eswin_pcie_power_on(struct eswin_pcie *pcie)
ret = reset_control_reset(pcie->powerup_rst);
WARN_ON(0 != ret);
- /* pcie_perst_n */
- // ret = reset_control_reset(pcie->perst);
- // WARN_ON(0 != ret);
-
return ret;
}
@@ -201,12 +175,6 @@ static int eswin_pcie_power_off(struct eswin_pcie *eswin_pcie)
return 0;
}
-/*
- pinctrl-0 = <&pinctrl_gpio106_default &pinctrl_gpio9_default>;
- pci-socket-gpios = <&portd 10 GPIO_ACTIVE_LOW>;
- pci-prsnt-gpios = <&porta 9 GPIO_ACTIVE_LOW>;
-*/
-
int eswin_evb_socket_power_on(struct device *dev)
{
int err_desc=0;
@@ -224,8 +192,6 @@ int eswin_evb_socket_power_on(struct device *dev)
return err_desc;
}
-/* Not use gpio9 which mux with JTAG1_TDI in EVB */
-
int eswin_evb_device_scan(struct device *dev)
{
int err_desc=0;
@@ -252,7 +218,7 @@ int eswin_evb_device_scan(struct device *dev)
static int eswin_pcie_host_init(struct dw_pcie_rp *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
- struct eswin_pcie *pcie = to_eswin_pcie(pci);
+ struct eswin_pcie *pcie = dev_get_drvdata(pci->dev);
int ret;
u32 val;
@@ -275,9 +241,9 @@ static int eswin_pcie_host_init(struct dw_pcie_rp *pp)
return ret;
/* set device type : rc */
- val = readl_relaxed(pcie->mgmt_base);
+ val = readl_relaxed(pcie->mgmt_base + PCIEMGMT_CTRL0_OFFSET);
val &= 0xfffffff0;
- _writel_relaxed(val|0x4, pcie->mgmt_base);
+ writel_relaxed(val|0x4, pcie->mgmt_base + PCIEMGMT_CTRL0_OFFSET);
ret = reset_control_assert(pcie->perst);
WARN_ON(0 != ret);
@@ -288,13 +254,13 @@ static int eswin_pcie_host_init(struct dw_pcie_rp *pp)
WARN_ON(0 != ret);
/* app_hold_phy_rst */
- val = readl_relaxed(pcie->mgmt_base);
+ val = readl_relaxed(pcie->mgmt_base + PCIEMGMT_CTRL0_OFFSET);
val &= ~(0x40);
- _writel_relaxed(val, pcie->mgmt_base);
+ writel_relaxed(val, pcie->mgmt_base + PCIEMGMT_CTRL0_OFFSET);
/* wait pm_sel_aux_clk to 0 */
while (1) {
- val = readl_relaxed(pcie->mgmt_base + 0x100);
+ val = readl_relaxed(pcie->mgmt_base + PCIEMGMT_STATUS0_OFFSET);
if (!(val & PCIE_PM_SEL_AUX_CLK)) {
break;
}
@@ -302,110 +268,29 @@ static int eswin_pcie_host_init(struct dw_pcie_rp *pp)
}
/* config eswin vendor id and win2030 device id */
- dw_pcie_writel_dbi(pci, 0, 0x20301fe1);
-
- if (pcie->gen_x == 3) {
- /* GEN3 */
- dw_pcie_writel_dbi(pci, 0xa0, 0x00010003);
-
- /* GEN3 config , this config only for zebu*/
- // val = dw_pcie_readl_dbi(pci, 0x890);
- // val = 0x00012001;
- // dw_pcie_writel_dbi(pci, 0x890, val);
-
- /* LINK_CAPABILITIES_REG : PCIE_CAP_BASE + 0xc */
- val = dw_pcie_readl_dbi(pci, 0x7c);
- val &= 0xfffffff0;
- /* GEN3 */
- val |= 0x3;
- dw_pcie_writel_dbi(pci, 0x7c, val);
- } else if (pcie->gen_x == 2) {
- /* GEN2 */
- dw_pcie_writel_dbi(pci, 0xa0, 0x00010002);
-
- /* LINK_CAPABILITIES_REG : PCIE_CAP_BASE + 0xc */
- val = dw_pcie_readl_dbi(pci, 0x7c);
- val &= 0xfffffff0;
- val |= 0x2;
- dw_pcie_writel_dbi(pci, 0x7c, val);
- }else {
- /* GEN1 */
- dw_pcie_writel_dbi(pci, 0xa0, 0x00010001);
-
- /* LINK_CAPABILITIES_REG : PCIE_CAP_BASE + 0xc */
- val = dw_pcie_readl_dbi(pci, 0x7c);
- val &= 0xfffffff0;
- val |= 0x1;
- dw_pcie_writel_dbi(pci, 0x7c, val);
- }
-
- /* LINK_CAPABILITIES_REG : PCIE_CAP_BASE + 0xc : laneX */
- val = dw_pcie_readl_dbi(pci, 0x7c);
- val &= 0xfffffc0f;
- if (pcie->lane_x == 4) {
- val |= 0x40;
- } else if (pcie->lane_x == 2) {
- val |= 0x20;
- } else {
- val |= 0x10;
- }
-
- dw_pcie_writel_dbi(pci, 0x7c, val);
+ dw_pcie_writel_dbi(pci, PCIE_TYPE_DEV_VEND_ID, 0x20301fe1);
/* lane fix config, real driver NOT need, default x4 */
- val = dw_pcie_readl_dbi(pci, 0x8c0);
+ val = dw_pcie_readl_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL);
val &= 0xffffff80;
- if (pcie->lane_x == 4) {
- val |= 0x44;
- } else if (pcie->lane_x == 2) {
- val |= 0x42;
- } else {
- val |= 0x41;
- }
- dw_pcie_writel_dbi(pci, 0x8c0, val);
-
- /* config msix table size to 0 in RC mode because our RC not support msix */
- val = dw_pcie_readl_dbi(pci, 0xb0);
- val &= ~(0x7ff<<16);
- dw_pcie_writel_dbi(pci, 0xb0, val);
+ val |= 0x44;
+ dw_pcie_writel_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL, val);
- /* config max payload size to 4K */
- val = dw_pcie_readl_dbi(pci, 0x74);
- val &= ~(0x7);
- val |= 0x5;
- dw_pcie_writel_dbi(pci, 0x74, val);
-
- val = dw_pcie_readl_dbi(pci, 0x78);
+ val = dw_pcie_readl_dbi(pci, DEVICE_CONTROL_DEVICE_STATUS);
val &= ~(0x7<<5);
- val |= (0x5<<5);
- dw_pcie_writel_dbi(pci, 0x78, val);
-
-#if 0
- /* config GEN3_EQ_PSET_REQ_VEC */
- val = dw_pcie_readl_dbi(pci, 0x8a8);
- val &= ~(0xffff<<8);
- val |= (0x480<<8);
- dw_pcie_writel_dbi(pci, 0x8a8, val);
-
- /* config preset from lane0 to lane3 */
- val = dw_pcie_readl_dbi(pci, 0x154);
- val &= 0xfff0fff0;
- val |= 0x70007;
- dw_pcie_writel_dbi(pci, 0x154, val);
-
- val = dw_pcie_readl_dbi(pci, 0x158);
- val &= 0xfff0fff0;
- val |= 0x70007;
- dw_pcie_writel_dbi(pci, 0x158, val);
-#endif
+ val |= (0x2<<5);
+ dw_pcie_writel_dbi(pci, DEVICE_CONTROL_DEVICE_STATUS, val);
/* config support 32 msi vectors */
- dw_pcie_writel_dbi(pci, 0x50, 0x018a7005);
+ val = dw_pcie_readl_dbi(pci, PCIE_DSP_PF0_MSI_CAP);
+ val &= ~PCIE_MSI_MULTIPLE_MSG_MASK;
+ val |= PCIE_MSI_MULTIPLE_MSG_32;
+ dw_pcie_writel_dbi(pci, PCIE_DSP_PF0_MSI_CAP, val);
/* disable msix cap */
- val = dw_pcie_readl_dbi(pci, 0x70);
+ val = dw_pcie_readl_dbi(pci, PCIE_NEXT_CAP_PTR);
val &= 0xffff00ff;
- dw_pcie_writel_dbi(pci, 0x70, val);
+ dw_pcie_writel_dbi(pci, PCIE_NEXT_CAP_PTR, val);
return 0;
}
@@ -451,12 +336,7 @@ static int eswin_pcie_probe(struct platform_device *pdev)
if (IS_ERR(pcie->mgmt_base))
return PTR_ERR(pcie->mgmt_base);
- // /* Fetch GPIOs */
- // pcie->reset = devm_gpiod_get_optional(dev, "reset-gpios", GPIOD_OUT_LOW);
- // if (IS_ERR(pcie->reset))
- // return dev_err_probe(dev, PTR_ERR(pcie->reset), "unable to get reset-gpios\n");
-
- // /* Fetch clocks */
+ /* Fetch clocks */
pcie->pcie_aux = devm_clk_get(dev, "pcie_aux_clk");
if (IS_ERR(pcie->pcie_aux)) {
dev_err(dev, "pcie_aux clock source missing or invalid\n");
@@ -498,9 +378,6 @@ static int eswin_pcie_probe(struct platform_device *pdev)
dev_err_probe(dev, PTR_ERR(pcie->perst), "unable to get perst\n");
}
- device_property_read_u32(&pdev->dev, "gen-x", &pcie->gen_x);
- device_property_read_u32(&pdev->dev, "lane-x", &pcie->lane_x);
-
platform_set_drvdata(pdev, pcie);
return dw_pcie_host_init(&pci->pp);
--
2.47.0

63
0052-fix-modify-LSB-for-mpq8785-to-1mdegress-LSB.patch Normal file
View File

@ -0,0 +1,63 @@
From 8b7f4b907eed0a127a41bdcbec95fafa1dc6b056 Mon Sep 17 00:00:00 2001
From: yangwei1 <yangwei1@eswincomputing.com>
Date: Fri, 14 Jun 2024 16:39:47 +0800
Subject: [PATCH 052/219] fix:modify LSB for mpq8785 to 1mdegress/LSB
Changelogs:
modify LSB for mpq8785 to 1mdegress/LSB
---
drivers/regulator/mpq8785.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/regulator/mpq8785.c b/drivers/regulator/mpq8785.c
index 60c48ae47d31..d5dae70d3d50 100644
--- a/drivers/regulator/mpq8785.c
+++ b/drivers/regulator/mpq8785.c
@@ -187,6 +187,7 @@ struct MPQ8785_DRIVER_DATA
#define MPQ8785_FREQUENCY_LSB 10
#define MPQ8785_FREQUENCY_BASE_MINI 300 /* 300kHz=30*10kHz */
#define MPQ8785_FREQUENCY_BASE_MAX 2000
+#define MPQ8785_TEMPERATURE_LSB 1000 /*1mC*/
static u32 garr_volt_numerator[] = {64, 80, 80, 80};
static char garr_bool_string[][2] = {"N", "Y"};
@@ -537,6 +538,7 @@ static int mpq8785_read(struct device *dev, enum hwmon_sensor_types type,
{
case hwmon_temp_input:
*val = mpq8785_read_byte(data, MPQ8785_CMD_READ_TEMPERATURE);
+ *val *= MPQ8785_TEMPERATURE_LSB;
break;
case hwmon_temp_crit_alarm:
get_value = mpq8785_read_word(data, MPQ8785_CMD_STATUS_WORD);
@@ -548,12 +550,12 @@ static int mpq8785_read(struct device *dev, enum hwmon_sensor_types type,
case hwmon_temp_max:
*val = mpq8785_read_mask_word(data, MPQ8785_CMD_OT_WARN_LIMIT,
MPQ8785_MASK_TOUT_LIMIT);
-
+ *val *= MPQ8785_TEMPERATURE_LSB;
break;
case hwmon_temp_crit:
*val = mpq8785_read_mask_word(data, MPQ8785_CMD_OT_FAULT_LIMIT,
MPQ8785_MASK_TOUT_LIMIT);
-
+ *val *= MPQ8785_TEMPERATURE_LSB;
break;
}
break;
@@ -676,11 +678,11 @@ static int mpq8785_write(struct device *dev, enum hwmon_sensor_types type,
{
case hwmon_temp_max:
ret = mpq8785_update_word(data, MPQ8785_CMD_OT_WARN_LIMIT,
- MPQ8785_MASK_TOUT_LIMIT, (u16)val);
+ MPQ8785_MASK_TOUT_LIMIT, (u16)(val / MPQ8785_TEMPERATURE_LSB));
break;
case hwmon_temp_crit:
ret = mpq8785_update_word(data, MPQ8785_CMD_OT_FAULT_LIMIT,
- MPQ8785_MASK_TOUT_LIMIT, (u16)val);
+ MPQ8785_MASK_TOUT_LIMIT, (u16)(val / MPQ8785_TEMPERATURE_LSB));
break;
}
break;
--
2.47.0

378
0053-fix-optimize-SDHCI-driver-tuning.patch Normal file
View File

@ -0,0 +1,378 @@
From 63fcee97515a1941b0b4c0b504db47722155d99d Mon Sep 17 00:00:00 2001
From: liangshuang <liangshuang@eswincomputing.com>
Date: Thu, 13 Jun 2024 14:55:45 +0800
Subject: [PATCH 053/219] fix:optimize SDHCI driver tuning.
Changelogs:
1.rmmove delay tuning in sd driver.
---
arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts | 10 +-
arch/riscv/boot/dts/eswin/eic7700-evb.dts | 8 +-
.../boot/dts/eswin/hifive-premier-550.dts | 7 +-
drivers/mmc/host/sdhci-of-eswin-sdio.c | 160 +++++-------------
4 files changed, 47 insertions(+), 138 deletions(-)
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
index 7a3702e88b19..3b90f64fcdb2 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
@@ -482,12 +482,10 @@ &sdhci_emmc {
&sdio0 {
/* sd card */
status = "okay";
- delay_code = <0x23>;
- phase_code = <0x5>;
+ delay_code = <0x29>;
drive-impedance-ohm = <33>;
enable-cmd-pullup;
enable-data-pullup;
- enable_sw_tuning;
no-sdio;
no-mmc;
};
@@ -495,12 +493,10 @@ &sdio0 {
&sdio1 {
/* wifi module */
status = "okay";
- delay_code = <0x23>;
- phase_code = <0x5>;
+ delay_code = <0x29>;
drive-impedance-ohm = <33>;
enable-cmd-pullup;
enable-data-pullup;
- enable_sw_tuning;
non-removable;
no-sd;
no-mmc;
@@ -923,4 +919,4 @@ &gpio0 {
};
&dev_llc_d0{
apply_npu_high_freq;
-};
\ No newline at end of file
+};
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb.dts b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
index 5e18922ba44a..fd94c6a3aeea 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
@@ -453,11 +453,10 @@ &sdhci_emmc {
&sdio0 {
/* sd card */
status = "okay";
- delay_code = <0x16>;
+ delay_code = <0x29>;
drive-impedance-ohm = <33>;
enable-cmd-pullup;
enable-data-pullup;
- enable_sw_tuning;
no-sdio;
no-mmc;
};
@@ -465,11 +464,10 @@ &sdio0 {
&sdio1 {
/* wifi module */
status = "okay";
- delay_code = <0x21>;
+ delay_code = <0x29>;
drive-impedance-ohm = <33>;
enable-cmd-pullup;
enable-data-pullup;
- enable_sw_tuning;
non-removable;
no-sd;
no-mmc;
@@ -900,4 +898,4 @@ &gpio0 {
};
&dev_llc_d0{
apply_npu_high_freq;
-};
\ No newline at end of file
+};
diff --git a/arch/riscv/boot/dts/eswin/hifive-premier-550.dts b/arch/riscv/boot/dts/eswin/hifive-premier-550.dts
index 2b08a6bbfd2a..bfb59b7d6eb5 100644
--- a/arch/riscv/boot/dts/eswin/hifive-premier-550.dts
+++ b/arch/riscv/boot/dts/eswin/hifive-premier-550.dts
@@ -390,12 +390,10 @@ &sdhci_emmc {
&sdio0 {
/* sd card */
status = "okay";
- delay_code = <0x16>;
- phase_code = <0x1f>;
+ delay_code = <0x29>;
drive-impedance-ohm = <33>;
enable-cmd-pullup;
enable-data-pullup;
- enable_sw_tuning;
no-sdio;
no-mmc;
};
@@ -403,11 +401,10 @@ &sdio0 {
&sdio1 {
/* wifi module */
status = "okay";
- delay_code = <0x21>;
+ delay_code = <0x29>;
drive-impedance-ohm = <33>;
enable-cmd-pullup;
enable-data-pullup;
- enable_sw_tuning;
non-removable;
no-sd;
no-mmc;
diff --git a/drivers/mmc/host/sdhci-of-eswin-sdio.c b/drivers/mmc/host/sdhci-of-eswin-sdio.c
index badbee00b39e..d5ae6a5694f6 100644
--- a/drivers/mmc/host/sdhci-of-eswin-sdio.c
+++ b/drivers/mmc/host/sdhci-of-eswin-sdio.c
@@ -42,12 +42,7 @@
#define ESWIN_SDHCI_SD1_INT_STATUS 0x708
#define ESWIN_SDHCI_SD1_PWR_CTRL 0x70c
-#define DELAY_RANGE_THRESHOLD 20
-
-struct eswin_sdio_private {
- int phase_code;
- unsigned int enable_sw_tuning;
-};
+#define TUNING_RANGE_THRESHOLD 40
static inline void *sdhci_sdio_priv(struct eswin_sdhci_data *sdio)
{
@@ -177,109 +172,54 @@ static void eswin_sdhci_sdio_reset(struct sdhci_host *host, u8 mask)
}
}
-static int eswin_sdhci_sdio_delay_tuning(struct sdhci_host *host, u32 opcode)
-{
- int ret;
- int delay = -1;
- int i = 0;
- int delay_min = -1;
- int delay_max = -1;
- int delay_range = -1;
-
- int cmd_error = 0;
- struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
- struct eswin_sdhci_data *eswin_sdhci =
- sdhci_pltfm_priv(pltfm_host);
-
- for (i = 0; i <= PHY_DELAY_CODE_MAX; i++) {
- eswin_sdhci_disable_card_clk(host);
- eswin_sdhci_sdio_config_phy_delay(host, i);
- eswin_sdhci_enable_card_clk(host);
- ret = mmc_send_tuning(host->mmc, opcode, &cmd_error);
- host->ops->reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
- if (ret) {
- pr_debug("%s: bad delay:0x%x!\n", mmc_hostname(host->mmc), i);
- if (delay_min != -1 && delay_max != -1) {
- if (delay_max - delay_min > delay_range) {
- delay_range = delay_max - delay_min;
- delay = (delay_min + delay_max) / 2;
- if (delay_range > DELAY_RANGE_THRESHOLD)
- break;
- }
- delay_min = -1;
- delay_max = -1;
- }
- } else {
- pr_debug("%s: ok delay:0x%x\n", mmc_hostname(host->mmc), i);
- if (delay_min == -1) {
- delay_min = i;
- }
- delay_max = i;
- if (i == PHY_DELAY_CODE_MAX) {
- if (delay_max - delay_min > delay_range) {
- delay_range = delay_max - delay_min;
- delay = (delay_min + delay_max) / 2;
- }
- }
- continue;
- }
- }
-
- if (delay == -1) {
- pr_err("%s: delay code tuning failed!\n",
- mmc_hostname(host->mmc));
- eswin_sdhci_disable_card_clk(host);
- eswin_sdhci_sdio_config_phy_delay(host,
- eswin_sdhci->phy.delay_code);
- eswin_sdhci_enable_card_clk(host);
-
- return ret;
- }
-
- pr_info("%s: set delay:0x%x\n", mmc_hostname(host->mmc), delay);
- eswin_sdhci_disable_card_clk(host);
- eswin_sdhci_sdio_config_phy_delay(host, delay);
- eswin_sdhci_enable_card_clk(host);
-
- ret = mmc_send_tuning(host->mmc, opcode, &cmd_error);
- host->ops->reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
- if (ret) {
- pr_err("%s: delay code(0x%x) not work, tuning failed!\n",
- mmc_hostname(host->mmc), delay);
- return ret;
- }
-
- return 0;
-}
-
static int eswin_sdhci_sdio_phase_code_tuning(struct sdhci_host *host,
u32 opcode)
{
int cmd_error = 0;
int ret = 0;
- int phase_code = 0;
+ int phase_code = -1;
int code_min = -1;
int code_max = -1;
+ int code_range = -1;
+ int i = 0;
- for (phase_code = 0; phase_code <= MAX_PHASE_CODE; phase_code++) {
+ for (i = 0; i <= MAX_PHASE_CODE; i++) {
eswin_sdhci_disable_card_clk(host);
- sdhci_writew(host, phase_code, VENDOR_AT_SATA_R);
+ sdhci_writew(host, i, VENDOR_AT_SATA_R);
eswin_sdhci_enable_card_clk(host);
ret = mmc_send_tuning(host->mmc, opcode, &cmd_error);
host->ops->reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
if (ret) {
- pr_debug("%s: bad phase_code:0x%x\n", mmc_hostname(host->mmc), phase_code);
- if (code_min != -1 && code_max != -1)
- break;
+ udelay(200);
+ pr_debug("%s: bad phase_code:0x%x!\n", mmc_hostname(host->mmc), i);
+ if (code_min != -1 && code_max != -1) {
+ if (code_max - code_min > code_range) {
+ code_range = code_max - code_min;
+ phase_code = (code_min + code_max) / 2;
+ if (code_range > TUNING_RANGE_THRESHOLD)
+ break;
+ }
+ code_min = -1;
+ code_max = -1;
+ }
} else {
+ pr_debug("%s: ok phase_code:0x%x\n", mmc_hostname(host->mmc), i);
if (code_min == -1) {
- code_min = phase_code;
+ code_min = i;
}
- code_max = phase_code;
+ code_max = i;
+ if (i == MAX_PHASE_CODE) {
+ if (code_max - code_min > code_range) {
+ code_range = code_max - code_min;
+ phase_code = (code_min + code_max) / 2;
+ }
+ }
+ continue;
}
}
- if (code_min == -1 && code_max == -1) {
+
+ if (phase_code == -1) {
pr_err("%s: phase code tuning failed!\n",
mmc_hostname(host->mmc));
eswin_sdhci_disable_card_clk(host);
@@ -288,13 +228,20 @@ static int eswin_sdhci_sdio_phase_code_tuning(struct sdhci_host *host,
return -EIO;
}
- phase_code = (code_min + code_max) / 2;
pr_info("%s: set phase_code:0x%x\n", mmc_hostname(host->mmc), phase_code);
eswin_sdhci_disable_card_clk(host);
sdhci_writew(host, phase_code, VENDOR_AT_SATA_R);
eswin_sdhci_enable_card_clk(host);
+ ret = mmc_send_tuning(host->mmc, opcode, &cmd_error);
+ host->ops->reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+ if (ret) {
+ pr_err("%s: phase_code code(0x%x) not work, tuning failed!\n",
+ mmc_hostname(host->mmc), phase_code);
+ return ret;
+ }
+
return 0;
}
@@ -306,20 +253,9 @@ static int eswin_sdhci_sdio_executing_tuning(struct sdhci_host *host,
int ret = 0;
struct sdhci_pltfm_host *pltfm_host;
struct eswin_sdhci_data *eswin_sdhci_sdio;
- struct eswin_sdio_private *eswin_sdio_priv;
pltfm_host = sdhci_priv(host);
eswin_sdhci_sdio = sdhci_pltfm_priv(pltfm_host);
- eswin_sdio_priv = sdhci_sdio_priv(eswin_sdhci_sdio);
-
- if (!eswin_sdio_priv->enable_sw_tuning) {
- if (eswin_sdio_priv->phase_code != -1) {
- eswin_sdhci_disable_card_clk(host);
- sdhci_writew(host, eswin_sdio_priv->phase_code, VENDOR_AT_SATA_R);
- eswin_sdhci_enable_card_clk(host);
- }
- return 0;
- }
eswin_sdhci_disable_card_clk(host);
@@ -336,11 +272,6 @@ static int eswin_sdhci_sdio_executing_tuning(struct sdhci_host *host,
sdhci_writew(host, 0x0, SDHCI_CMD_DATA);
- ret = eswin_sdhci_sdio_delay_tuning(host, opcode);
- if (ret < 0) {
- return ret;
- }
-
ret = eswin_sdhci_sdio_phase_code_tuning(host, opcode);
if (ret < 0) {
return ret;
@@ -837,14 +768,13 @@ static int eswin_sdhci_sdio_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct eswin_sdhci_data *eswin_sdhci_sdio;
- struct eswin_sdio_private *eswin_sdio_priv;
struct regmap *regmap;
const struct eswin_sdhci_of_data *data;
unsigned int sdio_id = 0;
unsigned int val = 0;
data = of_device_get_match_data(dev);
- host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*eswin_sdhci_sdio) + sizeof(*eswin_sdio_priv));
+ host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*eswin_sdhci_sdio));
if (IS_ERR(host))
return PTR_ERR(host);
@@ -853,7 +783,6 @@ static int eswin_sdhci_sdio_probe(struct platform_device *pdev)
eswin_sdhci_sdio = sdhci_pltfm_priv(pltfm_host);
eswin_sdhci_sdio->host = host;
eswin_sdhci_sdio->has_cqe = false;
- eswin_sdio_priv = sdhci_sdio_priv(eswin_sdhci_sdio);
ret = of_property_read_u32(dev->of_node, "core-clk-reg", &val);
if (ret) {
@@ -982,17 +911,6 @@ static int eswin_sdhci_sdio_probe(struct platform_device *pdev)
else
eswin_sdhci_sdio->phy.enable_data_pullup = DISABLE;
- if (of_property_read_bool(dev->of_node, "enable_sw_tuning"))
- eswin_sdio_priv->enable_sw_tuning = ENABLE;
- else
- eswin_sdio_priv->enable_sw_tuning = DISABLE;
-
- if (!of_property_read_u32(dev->of_node, "phase_code", &val)) {
- eswin_sdio_priv->phase_code = val;
- } else {
- eswin_sdio_priv->phase_code = -1;
- }
-
eswin_sdhci_dt_parse_clk_phases(dev, &eswin_sdhci_sdio->clk_data);
ret = mmc_of_parse(host->mmc);
if (ret) {
--
2.47.0

282
0054-feat-bootspi-flash-support-write-proection.patch Normal file
View File

@ -0,0 +1,282 @@
From 6b8cc0e69850c544290f4209f74b32366986ca31 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E2=80=9Chuangyifeng=E2=80=9D?=
<huangyifeng@eswincomputing.com>
Date: Mon, 17 Jun 2024 09:53:37 +0800
Subject: [PATCH 054/219] feat:bootspi flash support write proection
Changelogs:
bootspi flash support write proection,
echo 0/1 > /sys/devices/platform/soc/51800000.spi/wp_enable to
disable/enable write proection
---
arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts | 1 +
arch/riscv/boot/dts/eswin/eic7700-evb.dts | 1 +
.../boot/dts/eswin/hifive-premier-550.dts | 3 +-
drivers/spi/spi-eswin-bootspi.c | 163 +++++++++++++++++-
4 files changed, 163 insertions(+), 5 deletions(-)
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
index 3b90f64fcdb2..71c26495502d 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
@@ -636,6 +636,7 @@ &bootspi {
status = "okay";
num-cs = <1>;
cs-gpios = <&portd 0 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&portd 4 GPIO_ACTIVE_LOW>;
spi-flash@0 {
compatible = "winbond,w25q128jw",
"jedec,spi-nor";
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb.dts b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
index fd94c6a3aeea..896895768139 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
@@ -603,6 +603,7 @@ &bootspi {
status = "okay";
num-cs = <1>;
cs-gpios = <&portd 0 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&portd 4 GPIO_ACTIVE_LOW>;
spi-flash@0 {
compatible = "winbond,w25q128jw",
"jedec,spi-nor";
diff --git a/arch/riscv/boot/dts/eswin/hifive-premier-550.dts b/arch/riscv/boot/dts/eswin/hifive-premier-550.dts
index bfb59b7d6eb5..7644991dc251 100644
--- a/arch/riscv/boot/dts/eswin/hifive-premier-550.dts
+++ b/arch/riscv/boot/dts/eswin/hifive-premier-550.dts
@@ -512,6 +512,7 @@ &bootspi {
status = "okay";
num-cs = <1>;
cs-gpios = <&portd 0 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&portd 4 GPIO_ACTIVE_LOW>;
spi-flash@0 {
compatible = "winbond,w25q128jw",
"jedec,spi-nor";
@@ -823,7 +824,7 @@ &pinctrl_gpio7_default &pinctrl_gpio8_default &pinctrl_gpio9_default &pinctrl
&pinctrl_gpio35_default &pinctrl_gpio36_default &pinctrl_gpio37_default &pinctrl_gpio38_default &pinctrl_gpio39_default &pinctrl_gpio40_default
&pinctrl_gpio46_default &pinctrl_gpio47_default
&pinctrl_gpio92_default &pinctrl_gpio93_default>;
-
+
/* pin header default function for GPIO
SPI1 (CS0,SCLK,MOSI,MISO,D2,D3): GPIO 35,36,37,38,39,40
I2C1 (SCL,SDA): GPIO 46,47
diff --git a/drivers/spi/spi-eswin-bootspi.c b/drivers/spi/spi-eswin-bootspi.c
index c8fbc1b3fc91..977bc6487e99 100644
--- a/drivers/spi/spi-eswin-bootspi.c
+++ b/drivers/spi/spi-eswin-bootspi.c
@@ -32,6 +32,8 @@
#include <linux/spi/spi.h>
#include <linux/spi/spi-mem.h>
#include <linux/mtd/spi-nor.h>
+#include <linux/sysfs.h>
+#include <linux/kobject.h>
/* Register offsets */
#define ES_SPI_CSR_00 0x00 /*WRITE_STATUS_REG_TIME*/
@@ -119,6 +121,7 @@ struct es_spi_priv {
struct clk *clk;
struct reset_control *rstc;
struct gpio_desc *cs_gpio; /* External chip-select gpio */
+ struct gpio_desc *wp_gpio; /* External chip-write protection gpio */
void __iomem *regs;
void __iomem *sys_regs;
@@ -136,7 +139,7 @@ struct es_spi_priv {
int bits_per_word;
int len;
- u8 cs; /* chip select pin */
+ bool wp_enabled;
u8 tmode; /* TR/TO/RO/EEPROM */
u8 type; /* SPI/SSP/MicroWire */
struct spi_controller *master;
@@ -373,6 +376,126 @@ static bool eswin_bootspi_supports_op(struct spi_mem *mem,
return spi_mem_default_supports_op(mem, op);
}
+uint8_t eswin_bootspi_read_flash_status_register(struct es_spi_priv *priv,
+ uint8_t *register_data, int flash_cmd)
+{
+ u32 command;
+ struct device *dev = priv->dev;
+
+ memset(register_data, 0, sizeof(uint8_t));
+ //Flash status register-2 is 1byte
+ eswin_bootspi_read_write_cfg(priv, 1, 0);
+
+ //Set SPI_FLASH_COMMAND
+ command = eswin_bootspi_read(priv, ES_SPI_CSR_06);
+ command &= ~((0xFF << 6) | (0x1 << 5) | (0xF << 1) | 0x1);
+ command |= ((flash_cmd << SPI_COMMAND_CODE_FIELD_POSITION) |
+ (SPI_COMMAND_MOVE_VALUE << SPI_COMMAND_MOVE_FIELD_POSITION) |
+ (SPIC_CMD_TYPE_READ_STATUS_REGISTER << SPI_COMMAND_TYPE_FIELD_POSITION) | SPI_COMMAND_VALID);
+ eswin_bootspi_write(priv, ES_SPI_CSR_06, command);
+
+ //Wait command finish
+ eswin_bootspi_wait_over(priv);
+
+ //Read back data
+ eswin_bootspi_recv_data(priv, register_data, 1);
+ dev_dbg(dev, "[%s %d]: command 0x%x, status register_data 0x%x\n",__func__,__LINE__,
+ command, *register_data);
+ return 0;
+}
+
+uint8_t eswin_bootspi_write_flash_status_register(struct es_spi_priv *priv,
+ uint8_t register_data, int flash_cmd)
+{
+ u32 command;
+ struct device *dev = priv->dev;
+
+ //Flash status register-2 is 1byte
+ eswin_bootspi_read_write_cfg(priv, 1, 0);
+ eswin_bootspi_send_data(priv, &register_data, 1);
+
+ command = eswin_bootspi_read(priv, ES_SPI_CSR_06);
+ command &= ~((0xFF << 6) | (0x1 << 5) | (0xF << 1) | 0x1);
+ command |= ((flash_cmd << SPI_COMMAND_CODE_FIELD_POSITION) |
+ (SPI_COMMAND_MOVE_VALUE << SPI_COMMAND_MOVE_FIELD_POSITION) |
+ (SPIC_CMD_TYPE_WRITE_STATUS_REGISTER << SPI_COMMAND_TYPE_FIELD_POSITION) | SPI_COMMAND_VALID);
+ eswin_bootspi_write(priv, ES_SPI_CSR_06, command);
+
+ //Wait command finish
+ eswin_bootspi_wait_over(priv);
+ dev_dbg(dev,"[%s %d]: command 0x%x, status register_data 0x%x\n",__func__,__LINE__,
+ command, register_data);
+ return 0;
+}
+
+int eswin_bootspi_flash_write_protection_cfg(struct es_spi_priv *priv, int enable)
+{
+ uint8_t register_data;
+
+ external_cs_manage(priv, false);
+
+ //Update status register1
+ eswin_bootspi_read_flash_status_register(priv, &register_data, SPINOR_OP_RDSR);
+ /*
+ SRP SEC TB BP2 BP1 BP0 WEL BUSY
+ */
+ if (enable) {
+ register_data |= ((1 << 2) | (1 << 3) | (1 << 4) | (1 << 7));
+ } else {
+ register_data &= ~((1 << 2) | (1 << 3) | (1 << 4) | (1 << 7));
+ }
+ eswin_bootspi_write_flash_status_register(priv, register_data, SPINOR_OP_WRSR);
+
+ //eswin_bootspi_read_flash_status_register(priv, &register_data, SPINOR_OP_RDSR);
+
+ external_cs_manage(priv, true);
+ return 0;
+}
+
+/*
+ 0: disable write_protection
+ 1: enable write_protection
+*/
+void eswin_bootspi_wp_cfg(struct es_spi_priv *priv, int enable)
+{
+ struct device *dev = priv->dev;
+
+ dev_info(dev, "Boot spi flash write protection %s\n", enable ? "enable" : "disable");
+ if (enable) {
+ eswin_bootspi_flash_write_protection_cfg(priv, enable);
+ gpiod_set_value(priv->wp_gpio, enable); //gpio output low, enable protection
+ } else {
+ gpiod_set_value(priv->wp_gpio, enable); //gpio output high, disable protection
+ eswin_bootspi_flash_write_protection_cfg(priv, enable);
+ }
+}
+
+static ssize_t wp_enable_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct es_spi_priv *priv = dev_get_drvdata(dev);
+ return sprintf(buf, "%s\n", priv->wp_enabled ? "enabled" : "disabled");
+}
+
+static ssize_t wp_enable_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct es_spi_priv *priv = dev_get_drvdata(dev);
+ unsigned long enable;
+ int ret;
+
+ ret = kstrtoul(buf, 10, &enable);
+ if (ret)
+ return ret;
+
+ eswin_bootspi_wp_cfg(priv, enable);
+ priv->wp_enabled = enable;
+ return count;
+}
+
+static DEVICE_ATTR_RW(wp_enable);
+
static int eswin_bootspi_exec_op(struct spi_mem *mem,
const struct spi_mem_op *op)
{
@@ -455,6 +578,24 @@ static int eswin_bootspi_exec_op(struct spi_mem *mem,
dev_dbg(dev, "[%s %d]: data direction=%d, opcode = 0x%x, cmd_type 0x%x\n",
__func__,__LINE__, op->data.dir, priv->opcode, priv->cmd_type);
+
+ if (priv->wp_enabled) {
+ switch(priv->opcode) {
+ case SPINOR_OP_BE_4K:
+ case SPINOR_OP_BE_4K_PMC:
+ case SPINOR_OP_BE_32K:
+ case SPINOR_OP_SE:
+ case SPINOR_OP_CHIP_ERASE:
+ case SPINOR_OP_PP:
+ case SPINOR_OP_PP_1_1_4:
+ case SPINOR_OP_PP_1_4_4:
+ case SPINOR_OP_PP_1_1_8:
+ case SPINOR_OP_PP_1_8_8:
+ dev_warn_ratelimited(dev, "Write protection is enabled, do not have permission to "
+ "perform this operation(%d)!\n", priv->opcode);
+ return -EACCES;
+ }
+ }
external_cs_manage(priv, false);
if (read) {
@@ -595,9 +736,15 @@ static int eswin_bootspi_probe(struct platform_device *pdev)
return PTR_ERR(priv->cs_gpio);
}
- priv->max_xfer = 32;
- dev_info(dev, "ssi_max_xfer_size=%u\n", priv->max_xfer);
+ priv->wp_gpio = devm_gpiod_get(dev, "wp", GPIOD_OUT_HIGH);
+ if (IS_ERR(priv->cs_gpio)) {
+ dev_err(dev, "%s %d: couldn't request gpio! (error %ld)\n", __func__,__LINE__,
+ PTR_ERR(priv->cs_gpio));
+ return PTR_ERR(priv->cs_gpio);
+ }
+ priv->wp_enabled = 1;
+ priv->max_xfer = 32;
/* Currently only bits_per_word == 8 supported */
priv->bits_per_word = 8;
priv->tmode = 0; /* Tx & Rx */
@@ -609,7 +756,15 @@ static int eswin_bootspi_probe(struct platform_device *pdev)
if (ret)
goto err_put_master;
- dev_info(&pdev->dev, "fifo_len %d, %s mode.\n", priv->fifo_len, priv->irq ? "irq" : "polling");
+ // Create sysfs node
+ ret = device_create_file(&pdev->dev, &dev_attr_wp_enable);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to create wp_enable attribute\n");
+ goto err_put_master;
+ }
+
+ dev_info(&pdev->dev, "ssi_max_xfer_size %d, fifo_len %d, %s mode.\n",
+ priv->max_xfer, priv->fifo_len, priv->irq ? "irq" : "polling");
return 0;
err_put_master:
--
2.47.0

67
0055-fix-spi-del-dma.patch Normal file
View File

@ -0,0 +1,67 @@
From 9c90ed2cdd5a7737b8270810e129a4eabcd1717d Mon Sep 17 00:00:00 2001
From: xuxiang <xuxiang@eswincomputing.com>
Date: Fri, 14 Jun 2024 14:54:27 +0800
Subject: [PATCH 055/219] fix:spi del dma
Changelogs:
1. spi delete dma
---
arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi | 6 ------
arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi | 3 ---
drivers/spi/spi-dw-mmio.c | 2 +-
3 files changed, 1 insertion(+), 10 deletions(-)
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
index 9f76de5f0162..0879dcca2527 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
@@ -817,9 +817,6 @@ ssi0: spi@50810000 {
interrupts = <91>;
resets = <&d0_reset SSI_RST_CTRL SW_SSI_RST_N_0>;
reset-names = "spi";
- eswin,spi_dma = <&d0_aon_dmac>;
- dmas = <&d0_aon_dmac 38 3>, <&d0_aon_dmac 39 3>;
- dma-names = "rx", "tx";
numa-node-id = <0>;
status = "disabled";
dma-noncoherent;
@@ -837,9 +834,6 @@ ssi1: spi@50814000 {
interrupts = <92>;
resets = <&d0_reset SSI_RST_CTRL SW_SSI_RST_N_1>;
reset-names = "spi";
- eswin,spi_dma = <&d0_aon_dmac>;
- dmas = <&d0_aon_dmac 36 4>, <&d0_aon_dmac 37 4>;
- dma-names = "rx", "tx";
numa-node-id = <0>;
status = "disabled";
dma-noncoherent;
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
index 1805c2bcdccc..1417c6298a3c 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
@@ -1589,9 +1589,6 @@ d1_ssi0: spi1@70810000 {
interrupts = <91>;
resets = <&d1_reset SSI_RST_CTRL SW_SSI_RST_N_0>;
reset-names = "spi";
- eswin,spi_dma = <&d1_aon_dmac>;
- dmas = <&d1_aon_dmac 38 3>, <&d1_aon_dmac 39 3>;
- dma-names = "rx", "tx";
numa-node-id = <1>;
status = "disabled";
dma-noncoherent;
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index 39c1ae316ac0..4462f5b87513 100644
--- a/drivers/spi/spi-dw-mmio.c
+++ b/drivers/spi/spi-dw-mmio.c
@@ -440,7 +440,7 @@ static const struct of_device_id dw_spi_mmio_of_match[] = {
{ .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init},
{ .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init},
{ .compatible = "amd,pensando-elba-spi", .data = dw_spi_elba_init},
- { .compatible = "snps,eic770x-spi", .data = dw_spi_eswin_init},
+ { .compatible = "snps,eic770x-spi",},
{ /* end of table */}
};
MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
--
2.47.0

124
0056-fix-vo-Fix-cursor-layer-resolution.patch Normal file
View File

@ -0,0 +1,124 @@
From fa2a4a140a3d9a173c070e8a0687e3229c848bbf Mon Sep 17 00:00:00 2001
From: lilijun <lilijun@eswincomputing.com>
Date: Wed, 19 Jun 2024 15:53:32 +0800
Subject: [PATCH 056/219] fix(vo): Fix cursor layer resolution
Changelogs:
1. Fix cursor layer only supporting 32x32 resolution
2. merged from patch:I67caf1a36104c57a91df18c58858f1d9d6783649
3. merged from patch:I929a0fd069f80b4dd840b9050a5114a0185013b1
---
drivers/gpu/drm/eswin/es_dc.c | 47 ++++++++++++++++++++++++++++----
drivers/gpu/drm/eswin/es_dc_hw.c | 5 ++--
drivers/gpu/drm/eswin/es_dc_hw.h | 8 ++++++
3 files changed, 53 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/eswin/es_dc.c b/drivers/gpu/drm/eswin/es_dc.c
index 9e485f7edcc4..3ae03d20b600 100644
--- a/drivers/gpu/drm/eswin/es_dc.c
+++ b/drivers/gpu/drm/eswin/es_dc.c
@@ -615,17 +615,54 @@ static void update_overlay_plane(struct es_dc *dc, struct es_plane *plane)
dc_hw_set_blend(&dc->hw, &blend);
}
+static void update_cursor_size(struct drm_plane_state *state, struct dc_hw_cursor *cursor)
+{
+ u8 size_type;
+
+ switch (state->crtc_w) {
+ case 32:
+ size_type = CURSOR_SIZE_32X32;
+ break;
+ case 64:
+ size_type = CURSOR_SIZE_64X64;
+ break;
+ case 128:
+ size_type = CURSOR_SIZE_128X128;
+ break;
+ case 256:
+ size_type = CURSOR_SIZE_256X256;
+ break;
+ default:
+ size_type = CURSOR_SIZE_32X32;
+ break;
+ }
+
+ cursor->size = size_type;
+}
+
static void update_cursor_plane(struct es_dc *dc, struct es_plane *plane)
{
struct drm_plane_state *state = plane->base.state;
- struct drm_framebuffer *drm_fb = state->fb;
struct dc_hw_cursor cursor;
cursor.address = plane->dma_addr[0];
- cursor.x = state->crtc_x;
- cursor.y = state->crtc_y;
- cursor.hot_x = drm_fb->hot_x;
- cursor.hot_y = drm_fb->hot_y;
+
+ if (state->crtc_x > 0) {
+ cursor.x = state->crtc_x;
+ cursor.hot_x = 0;
+ } else {
+ cursor.hot_x = -state->crtc_x;
+ cursor.x = 0;
+ }
+ if (state->crtc_y > 0) {
+ cursor.y = state->crtc_y;
+ cursor.hot_y = 0;
+ } else {
+ cursor.hot_y = -state->crtc_y;
+ cursor.y = 0;
+ }
+
+ update_cursor_size(state, &cursor);
cursor.enable = true;
dc_hw_update_cursor(&dc->hw, &cursor);
diff --git a/drivers/gpu/drm/eswin/es_dc_hw.c b/drivers/gpu/drm/eswin/es_dc_hw.c
index 010de5b65250..30bcfb6b759c 100644
--- a/drivers/gpu/drm/eswin/es_dc_hw.c
+++ b/drivers/gpu/drm/eswin/es_dc_hw.c
@@ -1485,8 +1485,9 @@ void dc_hw_commit(struct dc_hw *hw)
dc_write(hw, DC_CURSOR_LOCATION,
hw->cursor.x | (hw->cursor.y << 16));
dc_write(hw, DC_CURSOR_CONFIG,
- (hw->cursor.hot_x << 16) |
- (hw->cursor.hot_y << 8) | 0x02);
+ (hw->cursor.hot_x << 16) |
+ (hw->cursor.hot_y << 8) |
+ (hw->cursor.size << 5) | 0x06);
} else {
dc_write(hw, DC_CURSOR_CONFIG, 0x00);
}
diff --git a/drivers/gpu/drm/eswin/es_dc_hw.h b/drivers/gpu/drm/eswin/es_dc_hw.h
index 885d225c9203..1578aad0d79c 100644
--- a/drivers/gpu/drm/eswin/es_dc_hw.h
+++ b/drivers/gpu/drm/eswin/es_dc_hw.h
@@ -235,6 +235,13 @@ enum dc_hw_swizzle {
SWIZZLE_BGRA,
};
+enum dc_hw_cursor_size {
+ CURSOR_SIZE_32X32 = 0,
+ CURSOR_SIZE_64X64,
+ CURSOR_SIZE_128X128,
+ CURSOR_SIZE_256X256,
+};
+
enum dc_hw_out {
OUT_DPI,
OUT_DP,
@@ -362,6 +369,7 @@ struct dc_hw_cursor {
u16 y;
u16 hot_x;
u16 hot_y;
+ u8 size;
bool enable;
bool dirty;
};
--
2.47.0

29
0057-fix-Solving-HDMI-driver-compilation-issue.patch Normal file
View File

@ -0,0 +1,29 @@
From 57c7b23146a8ba7940be29f99be1b5b711f5e42e Mon Sep 17 00:00:00 2001
From: denglei <denglei@eswincomputing.com>
Date: Thu, 20 Jun 2024 08:56:15 +0800
Subject: [PATCH 057/219] fix:Solving HDMI driver compilation issue.
Changelogs:
Solving HDMI driver compilation issue.
---
drivers/gpu/drm/eswin/Kconfig | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/eswin/Kconfig b/drivers/gpu/drm/eswin/Kconfig
index de77dc0d9101..77733cd77352 100644
--- a/drivers/gpu/drm/eswin/Kconfig
+++ b/drivers/gpu/drm/eswin/Kconfig
@@ -32,7 +32,9 @@ config ESWIN_DW_HDMI
bool "ESWIN specific extensions for Synopsys DW HDMI"
depends on DRM_ESWIN
select CEC_CORE if CEC_NOTIFIER
- select DW_HDMI
+ select DRM_DISPLAY_HDMI_HELPER
+ select DRM_DISPLAY_HELPER
+ select DRM_KMS_HELPER
help
This selects support for ESWIN SoC specific extensions
for the Synopsys DesignWare HDMI driver. If you want to
--
2.47.0

339
0058-feat-add-hifive-premier-550-dts.patch Normal file
View File

@ -0,0 +1,339 @@
From c140af8dd3a7e8c2e31a29d6c02dab524f4efec1 Mon Sep 17 00:00:00 2001
From: ningyu <ningyu@eswincomputing.com>
Date: Fri, 21 Jun 2024 09:53:26 +0800
Subject: [PATCH 058/219] feat:add hifive premier 550 dts
Changelogs:
1.Notes:The hifive-premier-550.dts in linux-6.6 is actually for
DVB-2.
---
.../boot/dts/eswin/hifive-premier-550.dts | 226 +++++++-----------
1 file changed, 91 insertions(+), 135 deletions(-)
diff --git a/arch/riscv/boot/dts/eswin/hifive-premier-550.dts b/arch/riscv/boot/dts/eswin/hifive-premier-550.dts
index 7644991dc251..bde120c77fe1 100644
--- a/arch/riscv/boot/dts/eswin/hifive-premier-550.dts
+++ b/arch/riscv/boot/dts/eswin/hifive-premier-550.dts
@@ -56,11 +56,18 @@ cpus {
timebase-frequency = <RTCCLK_FREQ>;
};
+ memory@59000000 {
+ device_type = "memory";
+ reg = <0x0 0x59000000 0x0 0x400000>;
+ numa-node-id = <0>;
+ };
+
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 MEMORY_SIZE_H MEMORY_SIZE_L>;
numa-node-id = <0>;
};
+
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@@ -75,10 +82,32 @@ linux,cma {
linux,cma-default;
};
+ npu0_reserved: sprammemory@59000000 {
+ no-map;
+ reg = <0x0 0x59000000 0x0 0x400000>;
+ };
+
lpcpu0_reserved: lpcpu@a0000000 {
no-map;
reg = <0x0 0xa0000000 0x0 0x100000>;
};
+
+ g2d_4GB_boundary_reserved_4k {
+ no-map;
+ reg = <0x0 0xfffff000 0x0 0x1000>;
+ };
+
+ mmz_nid_0_part_0 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x1 0x40000000 0x2 0x80000000>;
+ no-map;
+ };
+
+ mmz_nid_0_part_1 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x3 0xf0000000 0x0 0x10000000>;
+ no-map;
+ };
};
soc {
@@ -90,9 +119,6 @@ reset_test@1e00e000 {
reset-names = "bus", "core", "dbg";
};
};
- npu0_reserved: sprammemory@59000000 {
- reg = <0x0 0x59000000 0x0 0x400000>;
- };
};
&d0_clock {
@@ -423,7 +449,7 @@ &d0_gmac1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio111_default>;
- rst-gpios = <&portd 11 GPIO_ACTIVE_LOW>;
+ rst-gpios = <&portd 15 GPIO_ACTIVE_LOW>;
eswin,rgmiisel = <&pinctrl 0x294 0x3>;
eswin,led-cfgs = <0x6100 0xa40 0x420>;
};
@@ -441,17 +467,7 @@ &d0_usbdrd3_0 {
&d0_usbdrd_dwc3_0 {
status = "okay";
dr_mode = "host";
- /* usb-role-switch;
- role-switch-default-mode = "host"; */
maximum-speed = "super-speed";
- port {
- #address-cells = <1>;
- #size-cells = <0>;
- dwc3_0_role_switch: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&usbc0_role_sw>;
- };
- };
};
&d0_usbdrd3_1 {
@@ -462,6 +478,14 @@ &d0_usbdrd_dwc3_1 {
status = "okay";
dr_mode = "host";
maximum-speed = "super-speed";
+ usb-hub {
+ gpio-hog;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio43_default>;
+ gpios = <&portb 11 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "usb-hub-reset";
+ };
};
&d0_dmac0 {
@@ -603,16 +627,6 @@ fusb303b@21 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio5_default>;
int-gpios = <&porta 5 GPIO_ACTIVE_HIGH>;
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- usbc0_role_sw: endpoint@0 {
- remote-endpoint = <&dwc3_0_role_switch>;
- };
- };
- };
connector {
compatible = "usb-c-connector";
label = "USB-C";
@@ -675,86 +689,9 @@ pac1934:pmic@10 {
label = "som_info";
/*The update number of times the energy accumulates*/
energy_acc_count = <0>;
- shunt_resistors=<4 4 4 4>;
+ shunt_resistors=<1 1 1 1>;
reg = <0x10>;
};
- sic451:pmic@11 {
- compatible = "Vishay,sic451";
- reg = <0x11>;
- label = "npu_vdd";
- regulators{
- vdd_npu1:vdd_npu{
- regulator-name="VDD_NPU";
- regulator-min-microvolt=<100000>;
- regulator-max-microvolt=<1600000>;
- /* regulator-max-step-microvolt = <100000>; */
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
- pca9450: pmic@25 {
- compatible = "nxp,pca9450c";
- interrupts = <134 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x25>;
- regulators {
- BUCK1 {
- regulator-name = "BUCK1";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- BUCK2 {
- regulator-name = "BUCK2";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- BUCK4 {
- regulator-name = "BUCK4";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- BUCK5 {
- regulator-name = "BUCK5";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- BUCK6 {
- regulator-name = "BUCK6";
- regulator-min-microvolt = <1075000>;
- regulator-max-microvolt = <1075000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- LDO3 {
- regulator-name = "LDO3";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- LDO5 {
- regulator-name = "LDO5";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
sys_power:ina226@44 {
compatible = "ti,ina226";
@@ -763,6 +700,25 @@ sys_power:ina226@44 {
reg = <0x44>;
shunt-resistor = <1000>;
};
+
+ mpq8785@12 {
+ compatible = "mps,mpq8785";
+ reg = <0x12>;
+ eswin,regulator_default-microvolt=<1000000>;
+ eswin,regulator_label = "supply vdd1", "npu vdd1", "npu current1", "npu temperature1";
+ label = "npu_vdd";
+ regulators{
+ npu_vcc1:npu_svcc{
+ regulator-name="NPU_SVCC";
+ regulator-min-microvolt=<700000>;
+ regulator-max-microvolt=<1100000>;
+ regulator-min-microamp=<20000000>;
+ regulator-max-microamp=<40000000>;
+ regulator-ov-protection-microvolt=<1100000>;
+ regulator-always-on;
+ };
+ };
+ };
};
&pwm0 {
@@ -816,14 +772,14 @@ &timer3 {
&pinctrl {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio21_default &pinctrl_gpio52_default &pinctrl_gpio53_default &pinctrl_gpio42_default
- &pinctrl_gpio17_default &pinctrl_gpio64_default &pinctrl_gpio65_default &pinctrl_gpio66_default
- &pinctrl_gpio67_default &pinctrl_gpio18_default &pinctrl_gpio19_default &pinctrl_gpio20_default
- &pinctrl_gpio7_default &pinctrl_gpio8_default &pinctrl_gpio9_default &pinctrl_gpio10_default
- &pinctrl_gpio35_default &pinctrl_gpio36_default &pinctrl_gpio37_default &pinctrl_gpio38_default &pinctrl_gpio39_default &pinctrl_gpio40_default
- &pinctrl_gpio46_default &pinctrl_gpio47_default
- &pinctrl_gpio92_default &pinctrl_gpio93_default>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio6_default &pinctrl_gpio7_default &pinctrl_gpio8_default &pinctrl_gpio9_default
+ &pinctrl_gpio10_default &pinctrl_gpio17_default &pinctrl_gpio35_default &pinctrl_gpio36_default
+ &pinctrl_gpio37_default &pinctrl_gpio38_default &pinctrl_gpio39_default &pinctrl_gpio40_default
+ &pinctrl_gpio41_default &pinctrl_gpio46_default &pinctrl_gpio52_default
+ &pinctrl_gpio53_default &pinctrl_gpio64_default &pinctrl_gpio65_default &pinctrl_gpio66_default
+ &pinctrl_gpio67_default &pinctrl_gpio70_default &pinctrl_gpio73_default &pinctrl_gpio83_default
+ &pinctrl_gpio86_default &pinctrl_gpio87_default &pinctrl_gpio92_default &pinctrl_gpio93_default>;
/* pin header default function for GPIO
SPI1 (CS0,SCLK,MOSI,MISO,D2,D3): GPIO 35,36,37,38,39,40
@@ -832,36 +788,36 @@ UART3(TX,RX): GPIO 92,93
*/
};
-/* GPIO USED
- gpio0 : FP Audio Jack Sense(I)
- gpio5 : TYPE C cc logic interrupt(I)
- gpio6 : TYPE C cc logic ID(I)
- gpio11 : RP Audio Jack Sense(I)
- gpio12 : PCIE present(I)
- gpio13 : TF card insert detect(I)
- gpio14 : Display touch ctrl interrupt(I)
- gpio15 : Wlan wake host(I)
- gpio16 : VDD NPU Alert(I)
- gpio27 : SATA active led ctrl(O)
- gpio28 : RP audio jack sense(I)
+/*
+GPIO USED ON CarrierBoard:
+ gpio0 : FP Audio Jack Sense(I), active low
+ gpio5 : TYPE C cc logic interrupt(I), active low
+ gpio11 : BT WAKE HOST(I), active low
+ gpio12 : PCIE present(I), active low
+ gpio14 : DSI FPC CON CTRL(J10&J11)
+ gpio15 : Wlan wake host(I), active low
+ gpio28 : RP audio jack sense(I), active low
gpio29 : EMMC active led ctrl(O)
- gpio41 : PWM ctrl led(O)
- gpio43 : USB3.2 Gen1 hub Resetn(O)
- gpio70 : Map on pin header(J46)
+
+ gpio43 : USB3.2 Gen1 hub Resetn(O), active low
gpio71 : CSI fpc con ctrl(O)
- gpio73 : Map on pin header(J46)
gpio74 : CSI fpc con ctrl(O)
- gpio76 : Map on pin header(J46)
gpio77 : CSI fpc con ctrl(O)
- gpio79 : Map on pin header(J46)
+ gpio76 : HOST WAKE BT(O), active low
+ gpio79 : WLAN POWER ON(O), active high
gpio80 : CSI fpc con ctrl(O)
- gpio82 : LED back light power ctrl(O)
- gpio83 : CSI fpc con ctrl(O)
- gpio85 : DSI Resetn(O)
- gpio86 : CSI fpc con ctrl(O)
- gpio94 : Host wake wlan(I)
- gpio106 : gphy0 resern(O)
- gpio111 : gphy1 resern(O)
+ gpio82 : DSI FPC CON CTRL(J10)
+ gpio85 : DSI FPC CON CTRL(J11)
+ gpio84 : GPIO LED CTRL(O), active high
+
+ GPIO USED ON SOM:
+ gpio18 : HOST WAKE WLAN(O), active low
+ gpio19 : HOST WAKE BT(O), active low
+ gpio20 : WLAN WAKE HOST(I), active low
+ gpio21 : BT WAKE HOST(I), active low
+ gpio106 : gphy0 resern(O), active low
+ gpio111 : gphy1 resern(O), active low
+
*/
&gpio0 {
--
2.47.0

127
0059-fix-BootSpi-contronller-check-flash-status-register.patch Normal file
View File

@ -0,0 +1,127 @@
From 0d09b442467d9989981df34b1bb2a0cfa6fad557 Mon Sep 17 00:00:00 2001
From: huangyifeng <huangyifeng@eswincomputing.com>
Date: Fri, 21 Jun 2024 15:09:46 +0800
Subject: [PATCH 059/219] fix:BootSpi contronller check flash status register.
Changelogs:
check the flash status register's busy bit to make sure operation
is finished.
---
drivers/spi/spi-eswin-bootspi.c | 41 +++++++++++++++++++++++++--------
1 file changed, 31 insertions(+), 10 deletions(-)
diff --git a/drivers/spi/spi-eswin-bootspi.c b/drivers/spi/spi-eswin-bootspi.c
index 977bc6487e99..1205ce3941ae 100644
--- a/drivers/spi/spi-eswin-bootspi.c
+++ b/drivers/spi/spi-eswin-bootspi.c
@@ -147,6 +147,9 @@ struct es_spi_priv {
int irq;
};
+uint8_t eswin_bootspi_read_flash_status_register(struct es_spi_priv *priv,
+ uint8_t *register_data, int flash_cmd);
+
static inline u32 eswin_bootspi_read(struct es_spi_priv *priv, u32 offset)
{
return readl(priv->regs + offset);
@@ -171,12 +174,22 @@ static int eswin_bootspi_wait_over(struct es_spi_priv *priv)
{
u32 val;
struct device *dev = priv->dev;
+ uint8_t register_data = 0;
+ unsigned long timeout = jiffies + msecs_to_jiffies(5000); // 5 seconds timeout
if (readl_poll_timeout(priv->regs + ES_SPI_CSR_06, val,
(!(val & 0x1)), 10, RX_TIMEOUT * 1000)) {
- dev_err(dev, "eswin_bootspi_wait_over : timeout!!\n");
+ dev_err(dev, "eswin_bootspi_wait_over : timeout in waiting contronller busy status\n");
return -ETIMEDOUT;
}
+ while (register_data & 0x1) {
+ eswin_bootspi_read_flash_status_register(priv, &register_data, SPINOR_OP_RDSR);
+ // Check for timeout
+ if (time_after(jiffies, timeout)) {
+ dev_err(dev, "eswin_bootspi_wait_over : timeout in wait flash chip busy status!\n");
+ return -ETIMEDOUT;
+ }
+ }
return 0;
}
@@ -395,7 +408,7 @@ uint8_t eswin_bootspi_read_flash_status_register(struct es_spi_priv *priv,
eswin_bootspi_write(priv, ES_SPI_CSR_06, command);
//Wait command finish
- eswin_bootspi_wait_over(priv);
+ mdelay(10);
//Read back data
eswin_bootspi_recv_data(priv, register_data, 1);
@@ -430,7 +443,7 @@ uint8_t eswin_bootspi_write_flash_status_register(struct es_spi_priv *priv,
int eswin_bootspi_flash_write_protection_cfg(struct es_spi_priv *priv, int enable)
{
- uint8_t register_data;
+ uint8_t register_data, request_register_data;
external_cs_manage(priv, false);
@@ -440,11 +453,14 @@ int eswin_bootspi_flash_write_protection_cfg(struct es_spi_priv *priv, int enabl
SRP SEC TB BP2 BP1 BP0 WEL BUSY
*/
if (enable) {
- register_data |= ((1 << 2) | (1 << 3) | (1 << 4) | (1 << 7));
+ request_register_data = register_data | ((1 << 2) | (1 << 3) | (1 << 4) | (1 << 7));
} else {
- register_data &= ~((1 << 2) | (1 << 3) | (1 << 4) | (1 << 7));
+ request_register_data = register_data & (~((1 << 2) | (1 << 3) | (1 << 4) | (1 << 7)));
+ }
+
+ if (request_register_data != register_data) {
+ eswin_bootspi_write_flash_status_register(priv, request_register_data, SPINOR_OP_WRSR);
}
- eswin_bootspi_write_flash_status_register(priv, register_data, SPINOR_OP_WRSR);
//eswin_bootspi_read_flash_status_register(priv, &register_data, SPINOR_OP_RDSR);
@@ -460,7 +476,7 @@ void eswin_bootspi_wp_cfg(struct es_spi_priv *priv, int enable)
{
struct device *dev = priv->dev;
- dev_info(dev, "Boot spi flash write protection %s\n", enable ? "enable" : "disable");
+ dev_info(dev, "Boot spi flash write protection %s\n", enable ? "enabled" : "disabled");
if (enable) {
eswin_bootspi_flash_write_protection_cfg(priv, enable);
gpiod_set_value(priv->wp_gpio, enable); //gpio output low, enable protection
@@ -630,7 +646,6 @@ static int eswin_bootspi_setup(struct spi_device *spi)
{
struct es_spi_priv *priv = spi_master_get_devdata(spi->master);
struct device *dev = priv->dev;
- int vaule = 0;
int ret;
ret = clk_prepare_enable(priv->cfg_clk);
@@ -652,12 +667,18 @@ static int eswin_bootspi_setup(struct spi_device *spi)
}
reset_control_deassert(priv->rstc);
-
+ /*
+ When the bootrom starts from the boot SPI flash, the BootSpi contronller is in boot mode.
+ If the BootSpi contronller is switched to CPU mode here, the bootrom software will crash.
+ Therefore, this part of the code should be disabled.
+ In summary, the boot mode and CPU mode of the BootSpi contronller cannot coexist.
+ */
+#if 0
/* switch bootspi to cpu mode*/
vaule = readl(priv->sys_regs + ES_SYSCSR_SPIMODECFG);
vaule |= 0x1;
writel(vaule, priv->sys_regs + ES_SYSCSR_SPIMODECFG);
-
+#endif
/* Basic HW init */
eswin_bootspi_write(priv, ES_SPI_CSR_08, 0x0);
return ret;
--
2.47.0

32
0060-feat-dts-add-apply_npu_high_freq-in-dts.patch Normal file
View File

@ -0,0 +1,32 @@
From 5e06ab88269c06450326fc3418e19997c762ce3e Mon Sep 17 00:00:00 2001
From: linmin <linmin@eswincomputing.com>
Date: Tue, 2 Jul 2024 15:08:43 +0800
Subject: [PATCH 060/219] feat(dts):add apply_npu_high_freq in dts
Changelogs:
1.Add below property in hifive-premier-550.dts
&dev_llc_d0{
apply_npu_high_freq;
};
Signed-off-by: linmin <linmin@eswincomputing.com>
---
arch/riscv/boot/dts/eswin/hifive-premier-550.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/riscv/boot/dts/eswin/hifive-premier-550.dts b/arch/riscv/boot/dts/eswin/hifive-premier-550.dts
index bde120c77fe1..70b720d094c3 100644
--- a/arch/riscv/boot/dts/eswin/hifive-premier-550.dts
+++ b/arch/riscv/boot/dts/eswin/hifive-premier-550.dts
@@ -823,3 +823,7 @@ gpio111 : gphy1 resern(O), active low
&gpio0 {
status = "okay";
};
+
+&dev_llc_d0{
+ apply_npu_high_freq;
+};
\ No newline at end of file
--
2.47.0

82
0061-fix-add-audio-sound-card-name.patch Normal file
View File

@ -0,0 +1,82 @@
From 517815b15964bf76c6cf633129aa4dc0d998040c Mon Sep 17 00:00:00 2001
From: denglei <denglei@eswincomputing.com>
Date: Tue, 2 Jul 2024 14:36:11 +0800
Subject: [PATCH 061/219] fix:add audio sound card name.
Changelogs:
add audio sound card name.
---
arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts | 3 +++
arch/riscv/boot/dts/eswin/eic7700-evb.dts | 3 +++
arch/riscv/boot/dts/eswin/hifive-premier-550.dts | 2 ++
3 files changed, 8 insertions(+)
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
index 71c26495502d..c95b68dafe7c 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb-a2.dts
@@ -421,16 +421,19 @@ d0_i2s2_endpoint: endpoint {
&d0_graphcard0 {
status = "okay";
+ label = "Analog Audio-0";
dais = <&d0_i2s1_port>;
};
&d0_graphcard1 {
status = "okay";
+ label = "Analog Audio-1";
dais = <&d0_i2s2_port>;
};
&d0_graphcard2 {
status = "okay";
+ label = "HDMI Audio";
dais = <&d0_i2s0_port>;
};
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb.dts b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
index 896895768139..bbabd938baef 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb.dts
@@ -394,16 +394,19 @@ d0_i2s2_endpoint: endpoint {
&d0_graphcard0 {
status = "okay";
+ label = "Analog Audio-0";
dais = <&d0_i2s1_port>;
};
&d0_graphcard1 {
status = "okay";
+ label = "Analog Audio-1";
dais = <&d0_i2s2_port>;
};
&d0_graphcard2 {
status = "okay";
+ label = "HDMI Audio";
dais = <&d0_i2s0_port0>, <&d0_i2s0_port1>;
};
diff --git a/arch/riscv/boot/dts/eswin/hifive-premier-550.dts b/arch/riscv/boot/dts/eswin/hifive-premier-550.dts
index 70b720d094c3..8bd614757b01 100644
--- a/arch/riscv/boot/dts/eswin/hifive-premier-550.dts
+++ b/arch/riscv/boot/dts/eswin/hifive-premier-550.dts
@@ -356,11 +356,13 @@ &d0_i2s2 {
&d0_graphcard0 {
status = "okay";
+ label = "Analog Audio";
dais = <&d0_i2s1_port>;
};
&d0_graphcard1 {
status = "okay";
+ label = "HDMI Audio";
dais = <&d0_i2s0_port>;
};
--
2.47.0

104
0062-fix-set-npu-default-freq-to-1.5G.patch Normal file
View File

@ -0,0 +1,104 @@
From b1864a6ccd0ef2a3ffea21dd1fc91380caf25b73 Mon Sep 17 00:00:00 2001
From: yangwei1 <yangwei1@eswincomputing.com>
Date: Tue, 2 Jul 2024 20:09:02 +0800
Subject: [PATCH 062/219] fix:set npu default freq to 1.5G
Changelogs:
set npu default freq to 1.5G and voltage to 1.05v
---
drivers/memory/eswin/codacache/llc_spram.c | 32 +++++++++++++---------
1 file changed, 19 insertions(+), 13 deletions(-)
diff --git a/drivers/memory/eswin/codacache/llc_spram.c b/drivers/memory/eswin/codacache/llc_spram.c
index e84f3650ae37..4e9027dd5db9 100644
--- a/drivers/memory/eswin/codacache/llc_spram.c
+++ b/drivers/memory/eswin/codacache/llc_spram.c
@@ -683,7 +683,7 @@ static int llc_rst_init(struct platform_device *pdev)
return 0;
}
-static int llc_clk_set_parent(struct platform_device *pdev, u8 *is_high_freq)
+static int llc_clk_set_parent(struct platform_device *pdev, u8 *is_low_freq)
{
int ret;
struct spram_dev *spram = platform_get_drvdata(pdev);
@@ -700,18 +700,24 @@ static int llc_clk_set_parent(struct platform_device *pdev, u8 *is_high_freq)
if ((NULL == npu_regulator) || (IS_ERR(npu_regulator)))
{
dev_warn(dev, "failed to get npu regulator\n");
- *is_high_freq = 0;
+ *is_low_freq = 0;
+ return -ENODEV;
}
else
{
- *is_high_freq = of_property_read_bool(np, "apply_npu_high_freq");
- dev_dbg(dev, "success to get npu regulator,apply_npu_high_freq:%d\n",
- *is_high_freq);
+ *is_low_freq = (of_property_read_bool(np, "apply_npu_1G_freq"));
+ dev_dbg(dev, "success to get npu regulator,apply_npu_1G_freq:%d\n",
+ *is_low_freq);
}
- if (1 == *is_high_freq)
+
+ if (0 == *is_low_freq)
{
- regulator_set_voltage(npu_regulator, NPU_1P5G_VOLTAGE, NPU_1P5G_VOLTAGE);
- dev_dbg(dev, "set volt:%duV ret:%d\n", NPU_1P5G_VOLTAGE,ret);
+ ret = regulator_set_voltage(npu_regulator, NPU_1P5G_VOLTAGE, NPU_1P5G_VOLTAGE);
+ if(0 != ret)
+ {
+ dev_err(dev, "set volt:%duV ret:%d\n", NPU_1P5G_VOLTAGE,ret);
+ return -EINVAL;
+ }
/* devm_regulator_put(npu_regulator); */
mdelay(10);
ret = clk_set_parent(spram->mux_u_npu_core_3mux1_gfree,
@@ -738,7 +744,7 @@ static int llc_clk_set_parent(struct platform_device *pdev, u8 *is_high_freq)
return 0;
}
-static int llc_clk_set_frq(struct platform_device *pdev, u8 is_high_freq)
+static int llc_clk_set_frq(struct platform_device *pdev, u8 is_low_freq)
{
int ret;
unsigned long rate = 0;
@@ -755,7 +761,7 @@ static int llc_clk_set_frq(struct platform_device *pdev, u8 is_high_freq)
return ret;
}
- if (1 == is_high_freq)
+ if (0 == is_low_freq)
{
rate = clk_round_rate(spram->llc_clk, NPU_LLC_CLK_1P5G_RATE);
ret = clk_set_rate(spram->llc_clk, rate);
@@ -881,7 +887,7 @@ static int llc_clk_rst_print(struct platform_device *pdev)
static int llc_clk_rst_init(struct platform_device *pdev)
{
int ret = 0;
- u8 is_high_freq = 0;
+ u8 is_low_freq = 0;
dev_dbg(&pdev->dev, "---%s\n", __func__);
@@ -891,7 +897,7 @@ static int llc_clk_rst_init(struct platform_device *pdev)
return ret;
}
- ret = llc_clk_set_parent(pdev, &is_high_freq);
+ ret = llc_clk_set_parent(pdev, &is_low_freq);
if(ret != 0){
dev_err(&pdev->dev, "llc_clk_set_parent error: %d\n", ret);
return ret;
@@ -903,7 +909,7 @@ static int llc_clk_rst_init(struct platform_device *pdev)
return ret;
}
- ret = llc_clk_set_frq(pdev, is_high_freq);
+ ret = llc_clk_set_frq(pdev, is_low_freq);
if(ret != 0){
dev_err(&pdev->dev, "llc_clk_set_frq error: %d\n", ret);
return ret;
--
2.47.0

29
0063-fix-delete-extra-print.patch Normal file
View File

@ -0,0 +1,29 @@
From 8ec5599c19a55f4d51c8a653f16751ac5ba73abf Mon Sep 17 00:00:00 2001
From: yangqiang <yangqiang1@eswincomputing.com>
Date: Wed, 3 Jul 2024 13:55:36 +0800
Subject: [PATCH 063/219] fix:delete extra print
Changelogs:
delete extra print
---
sound/soc/eswin/esw-audio-proc.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/sound/soc/eswin/esw-audio-proc.c b/sound/soc/eswin/esw-audio-proc.c
index 5ffed4c4ab34..f0c0cbe10f56 100644
--- a/sound/soc/eswin/esw-audio-proc.c
+++ b/sound/soc/eswin/esw-audio-proc.c
@@ -354,10 +354,6 @@ static int audio_dev_mmap(struct file *file, struct vm_area_struct *vma)
enum DEVICES_ID deviceID = INVALID_DEVICE;
unsigned long size = vma->vm_end - vma->vm_start;
- pr_info("audio_dev_mmap:%s\n", file->f_path.dentry->d_name.name);
-
- pr_info("vma->vm_end:%ld,vma->vm_start:%ld\n",vma->vm_end, vma->vm_start);
-
if (size > (MAX_PERF_SIZE * sizeof(int32_t))) {
pr_err("audio_dev_mmap: size:%ld > %ld.\n", size, MAX_PERF_SIZE * sizeof(int32_t));
return -EINVAL;
--
2.47.0

291
0064-fix-support-power-managemnt.patch Normal file
View File

@ -0,0 +1,291 @@
From 77a879491a398f7c91d883d8d540f34fe91b3030 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E2=80=9Chuangyifeng=E2=80=9D?=
<huangyifeng@eswincomputing.com>
Date: Thu, 27 Jun 2024 15:08:57 +0800
Subject: [PATCH 064/219] fix:support power managemnt
Changelogs:
1.temporarily disable pwm pm function since it will prevent system
suspending.
2.mailbox driver support for power managment.
3.add cmdline to prevent console suspending
Signed-off-by: huangyifeng <huangyifeng@eswincomputing.com>
---
arch/riscv/configs/win2030_defconfig | 2 +-
drivers/mailbox/eswin-mailbox.c | 115 ++++++++++++++++++++-------
drivers/pwm/pwm-dwc-eswin.c | 2 +-
3 files changed, 89 insertions(+), 30 deletions(-)
diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig
index f12568c50271..fd95a7c1c3b5 100644
--- a/arch/riscv/configs/win2030_defconfig
+++ b/arch/riscv/configs/win2030_defconfig
@@ -20,7 +20,7 @@ CONFIG_SOC_VIRT=y
CONFIG_SMP=y
CONFIG_RISCV_SBI_V01=y
# CONFIG_RISCV_BOOT_SPINWAIT is not set
-CONFIG_CMDLINE="earlycon=sbi console=tty1 console=ttyS0,115200n8 clk_ignore_unused cma_pernuma=0x2000000 disable_bypass=false"
+CONFIG_CMDLINE="earlycon=sbi console=tty1 console=ttyS0,115200n8 clk_ignore_unused cma_pernuma=0x2000000 disable_bypass=false no_console_suspend"
CONFIG_CMDLINE_EXTEND=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_STAT=y
diff --git a/drivers/mailbox/eswin-mailbox.c b/drivers/mailbox/eswin-mailbox.c
index 4e9b6b224469..6a2c40e4d45e 100755
--- a/drivers/mailbox/eswin-mailbox.c
+++ b/drivers/mailbox/eswin-mailbox.c
@@ -19,7 +19,6 @@
*
* Authors: HuangYiFeng<huangyifeng@eswincomputing.com>
*/
-
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/io.h>
@@ -31,6 +30,8 @@
#include <linux/mailbox/eswin-mailbox.h>
#include <linux/regmap.h>
#include <linux/reset.h>
+#include <linux/pm_runtime.h>
+
#define ESWIN_MBOX_FIFO_DEPTH 8
@@ -96,7 +97,7 @@ static int eswin_mbox_send_data(struct mbox_chan *chan, void *data)
tmp_data = (u32)(msg->data >> 32) | BIT(31);
regmap_write(mb->map, ESWIN_MBOX_WR_DATA1, tmp_data);
- // 写中断enable bit.
+ // Write interrupt enable bit.
regmap_set_bits(mb->map, ESWIN_MBOX_INT_CTRL, mb->irq_bit);
return 0;
}
@@ -106,12 +107,15 @@ static int eswin_mbox_startup(struct mbox_chan *chan)
struct eswin_mbox *mb = dev_get_drvdata(chan->mbox->dev);
int ret;
+ pm_runtime_get_sync(mb->dev);
+
if (regmap_test_bits(mb->map, ESWIN_MBOX_WR_LOCK, mb->lock_bit)) {
+ pm_runtime_put(mb->dev);
return -1;
}
ret = regmap_set_bits(mb->map, ESWIN_MBOX_WR_LOCK, mb->lock_bit);
-
- /*占用标志位写入成功表示占用成功*/
+
+ /* Successfully write the occupancy flag bit, indicating successful occupancy */
dev_dbg(mb->mbox.dev, "start, ret %d, lock_bit 0x%x\n", ret,
mb->lock_bit);
return ret;
@@ -130,6 +134,7 @@ static void eswin_mbox_shutdown(struct mbox_chan *chan)
if (0 != ret)
dev_err(mb->mbox.dev, "failed to disable mailbox int\n");
+ pm_runtime_put(mb->dev);
return;
}
@@ -184,7 +189,7 @@ static bool eswin_mbox_peek_data(struct mbox_chan *chan)
/*
once the data has been enqueued to mailbox hw FIFO in send_data function,
- we beleive that tx is done
+ we believe that tx is done
*/
static bool eswin_mbox_last_tx_done(struct mbox_chan *chan)
{
@@ -271,7 +276,7 @@ static const struct of_device_id eswin_mbox_of_match[] = {
MODULE_DEVICE_TABLE(of, eswin_mbox_of_match);
static int eswin_mbox_reg_read(void *context, unsigned int reg,
- unsigned int *val)
+ unsigned int *val)
{
struct eswin_mbox *mb = context;
@@ -297,7 +302,7 @@ static int eswin_mbox_rx_reg_read(void *context, unsigned int reg,
return 0;
}
-static int eswin_mbox__rx_reg_write(void *context, unsigned int reg,
+static int eswin_mbox_rx_reg_write(void *context, unsigned int reg,
unsigned int val)
{
struct eswin_mbox *mb = context;
@@ -334,7 +339,7 @@ int eswin_mbox_init_regmap(struct eswin_mbox *mb)
.cache_type = REGCACHE_NONE,
.can_sleep = false,
.reg_read = eswin_mbox_rx_reg_read,
- .reg_write = eswin_mbox__rx_reg_write,
+ .reg_write = eswin_mbox_rx_reg_write,
};
/*
@@ -358,6 +363,29 @@ int eswin_mbox_init_regmap(struct eswin_mbox *mb)
return 0;
}
+static int eswin_mbox_prepare_clk(struct device *dev, bool enable)
+{
+ int ret = 0;
+ struct eswin_mbox *mb = dev_get_drvdata(dev);
+
+ if (enable) {
+ ret = clk_prepare_enable(mb->pclk);
+ if (ret) {
+ dev_err(dev, "failed to enable host mailbox pclk: %d\n", ret);
+ return ret;
+ }
+ ret = clk_prepare_enable(mb->pclk_device);
+ if (ret) {
+ dev_err(dev, "failed to enable device mailbox pclk: %d\n", ret);
+ return ret;
+ }
+ } else {
+ clk_disable_unprepare(mb->pclk);
+ clk_disable_unprepare(mb->pclk_device);
+ }
+ return ret;
+}
+
static int eswin_mbox_probe(struct platform_device *pdev)
{
struct eswin_mbox *mb;
@@ -426,13 +454,6 @@ static int eswin_mbox_probe(struct platform_device *pdev)
return ret;
}
- ret = clk_prepare_enable(mb->pclk);
- if (ret) {
- dev_err(&pdev->dev, "failed to enable host mailbox pclk: %d\n",
- ret);
- return ret;
- }
-
mb->pclk_device = devm_clk_get(&pdev->dev, "pclk_mailbox_device");
if (IS_ERR(mb->pclk_device)) {
ret = PTR_ERR(mb->pclk_device);
@@ -440,13 +461,7 @@ static int eswin_mbox_probe(struct platform_device *pdev)
ret);
return ret;
}
-
- ret = clk_prepare_enable(mb->pclk_device);
- if (ret) {
- dev_err(&pdev->dev,
- "failed to enable device mailbox pclk: %d\n", ret);
- return ret;
- }
+ eswin_mbox_prepare_clk(&pdev->dev, true);
mb->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, "rst");
if (IS_ERR(mb->rst))
@@ -465,8 +480,7 @@ static int eswin_mbox_probe(struct platform_device *pdev)
return irq;
ret = devm_request_threaded_irq(&pdev->dev, irq, eswin_mbox_irq,
- eswin_mbox_isr, IRQF_ONESHOT,
- dev_name(&pdev->dev), mb);
+ eswin_mbox_isr, IRQF_ONESHOT, dev_name(&pdev->dev), mb);
if (ret < 0)
return ret;
@@ -480,10 +494,20 @@ static int eswin_mbox_probe(struct platform_device *pdev)
return ret;
spin_lock_init(&mb->rx_lock);
+
+ /* The code below assumes runtime PM to be disabled. */
+ WARN_ON(pm_runtime_enabled(&pdev->dev));
+
+ pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
+ pm_runtime_use_autosuspend(&pdev->dev);
+ pm_runtime_set_active(&pdev->dev);
+ pm_runtime_enable(&pdev->dev);
+
ret = devm_mbox_controller_register(&pdev->dev, &mb->mbox);
- if (ret < 0)
+ if (ret < 0) {
+ pm_runtime_disable(&pdev->dev);
dev_err(&pdev->dev, "failed to register mailbox: %d\n", ret);
-
+ }
dev_info(&pdev->dev, "register sucessfully\n");
return ret;
}
@@ -493,21 +517,56 @@ static int eswin_mbox_remove(struct platform_device *pdev)
int ret;
struct eswin_mbox *mb = platform_get_drvdata(pdev);
+ pm_runtime_dont_use_autosuspend(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+
ret = reset_control_assert(mb->rst);
WARN_ON(ret != 0);
ret = reset_control_assert(mb->rst_device);
WARN_ON(ret != 0);
- clk_disable_unprepare(mb->pclk_device);
- clk_disable_unprepare(mb->pclk);
return 0;
}
+static int eswin_mbox_suspend(struct device *dev)
+{
+ if (!pm_runtime_status_suspended(dev)) {
+ return eswin_mbox_prepare_clk(dev, false);
+ }
+ return 0;
+}
+
+static int eswin_mbox_resume(struct device *dev)
+{
+ if (!pm_runtime_status_suspended(dev)) {
+ eswin_mbox_prepare_clk(dev, true);
+ pm_runtime_mark_last_busy(dev);
+ pm_request_autosuspend(dev);
+ }
+ return 0;
+}
+
+static int eswin_mbox_runtime_suspend(struct device *dev)
+{
+ return eswin_mbox_prepare_clk(dev, false);
+}
+
+static int eswin_mbox_runtime_resume(struct device *dev)
+{
+ return eswin_mbox_prepare_clk(dev, true);
+}
+
+static const struct dev_pm_ops eswin_mbox_dev_pm_ops = {
+ LATE_SYSTEM_SLEEP_PM_OPS(eswin_mbox_suspend, eswin_mbox_resume)
+ RUNTIME_PM_OPS(eswin_mbox_runtime_suspend, eswin_mbox_runtime_resume, NULL)
+};
+
static struct platform_driver eswin_mbox_driver = {
.probe = eswin_mbox_probe,
.remove = eswin_mbox_remove,
.driver = {
.name = "eswin-mailbox",
.of_match_table = of_match_ptr(eswin_mbox_of_match),
+ .pm = pm_ptr(&eswin_mbox_dev_pm_ops),
},
};
diff --git a/drivers/pwm/pwm-dwc-eswin.c b/drivers/pwm/pwm-dwc-eswin.c
index 62c2dfcef719..1873b8351b0c 100644
--- a/drivers/pwm/pwm-dwc-eswin.c
+++ b/drivers/pwm/pwm-dwc-eswin.c
@@ -336,7 +336,7 @@ static struct platform_driver dwc_pwm_driver = {
.remove = dwc_pwm_remove,
.driver = {
.name = "dwc-pwm",
- .pm = &dwc_pwm_pm_ops,
+ //.pm = &dwc_pwm_pm_ops,
.of_match_table = of_match_ptr(dwc_pwm_id_table),
},
};
--
2.47.0

44
0065-fix-es-buddy-add-spin-lock.patch Normal file
View File

@ -0,0 +1,44 @@
From 3366be12f321b43023238a4fce0b26beb9f5784b Mon Sep 17 00:00:00 2001
From: linmin <linmin@eswincomputing.com>
Date: Fri, 5 Jul 2024 17:23:03 +0800
Subject: [PATCH 065/219] fix(es buddy):add spin lock
Changelogs:
1.The es_spin_lock() should be used in es_alloc_pages() and es_free_pages,
otherwise the compound_order of the kernel page may be modified by other
thread while es_free_pages
Signed-off-by: linmin <linmin@eswincomputing.com>
Reviewed-by: ningyu <ningyu@eswincomputing.com>
---
drivers/memory/eswin/buddy.h | 11 +++--------
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/memory/eswin/buddy.h b/drivers/memory/eswin/buddy.h
index bc0fd6eb6ddb..2c40d1116ad8 100644
--- a/drivers/memory/eswin/buddy.h
+++ b/drivers/memory/eswin/buddy.h
@@ -15,17 +15,12 @@
#define buddy_print(fmt...)
#define BUDDY_BUG_ON(condition) WARN_ON(condition)
-#define buddy_spin_lock_init(lock) spin_lock_init(lock)
-#define buddy_spin_lock(lock) spin_lock(lock)
-#define buddy_spin_unlock(lock) spin_unlock(lock)
-/*
#define es_spin_lock_init(esLock) spin_lock_init(esLock)
#define es_spin_lock(esLock) spin_lock(esLock)
#define es_spin_unlock(esLock) spin_unlock(esLock)
-*/
-#define es_spin_lock_init(esLock)
-#define es_spin_lock(esLock)
-#define es_spin_unlock(esLock)
+#define buddy_spin_lock_init(lock)
+#define buddy_spin_lock(lock)
+#define buddy_spin_unlock(lock)
#else
#include "list.h"
#include <stdio.h> //printf
--
2.47.0

498
0066-fix-Delete-HDCP1.4-authentication-key.patch Normal file
View File

@ -0,0 +1,498 @@
From abdcbecb724fea25fa0b45a0ef5a52de9bbaad1d Mon Sep 17 00:00:00 2001
From: denglei <denglei@eswincomputing.com>
Date: Mon, 8 Jul 2024 19:56:12 +0800
Subject: [PATCH 066/219] fix:Delete HDCP1.4 authentication key.
Changelogs:
Delete HDCP1.4 authentication key.
Signed-off-by: denglei <denglei@eswincomputing.com>
---
drivers/gpu/drm/eswin/dw_hdmi_hdcp.c | 396 +++------------------------
1 file changed, 32 insertions(+), 364 deletions(-)
diff --git a/drivers/gpu/drm/eswin/dw_hdmi_hdcp.c b/drivers/gpu/drm/eswin/dw_hdmi_hdcp.c
index b69b1be14e0d..a6bb3a8b939d 100644
--- a/drivers/gpu/drm/eswin/dw_hdmi_hdcp.c
+++ b/drivers/gpu/drm/eswin/dw_hdmi_hdcp.c
@@ -22,7 +22,6 @@
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/spinlock.h>
-//#include <linux/soc/eswin/eswin_vendor_storage.h>
#include <linux/uaccess.h>
#include <linux/fs.h>
#include <linux/module.h>
@@ -43,332 +42,6 @@
#define DPK_WR_OK_TIMEOUT_US 30000
#define HDMI_HDCP1X_ID 5
-/* HDCP DCP KEY & SEED */
-const u8 hdcp_const_data[320] = {
- /* 0 1 2 3 4 5 6 */
- 0x00,
- 0x00,
- 0xf0,
- 0xff,
- 0xff,
- 0x00,
- 0x00,
- 0x00, //KSV
- 0x91,
- 0x71,
- 0x7,
- 0x42,
- 0x86,
- 0xC1,
- 0xD1,
- 0x89,
- 0x0E,
- 0x2D,
- 0xFF,
- 0x92,
- 0x95,
- 0x28,
- 0xF4,
- 0x7D,
- 0x7B,
- 0x1F,
- 0x2A,
- 0xD9,
- 0xBB,
- 0xE4,
- 0xFD,
- 0x10,
- 0x18,
- 0xAA,
- 0xFB,
- 0x99,
- 0x5A,
- 0x83,
- 0x97,
- 0xD5,
- 0xDA,
- 0x85,
- 0x2D,
- 0x52,
- 0x8B,
- 0xB5,
- 0xB2,
- 0x49,
- 0xDC,
- 0x64,
- 0xC6,
- 0x62,
- 0xF0,
- 0xDB,
- 0xAA,
- 0x48,
- 0x2E,
- 0x84,
- 0xAD,
- 0x21,
- 0xCD,
- 0xB9,
- 0xD6,
- 0x47,
- 0xC7,
- 0xD7,
- 0xD1,
- 0x9F,
- 0xD4,
- 0xB1,
- 0x29,
- 0x4E,
- 0x98,
- 0xC6,
- 0xAE,
- 0xA4,
- 0xF5,
- 0xA6,
- 0xFE,
- 0x68,
- 0x3D,
- 0x43,
- 0x97,
- 0x7B,
- 0x52,
- 0xC7,
- 0xA1,
- 0x65,
- 0x7B,
- 0xF9,
- 0x8C,
- 0xCC,
- 0x20,
- 0x8C,
- 0xCB,
- 0x2F,
- 0x7D,
- 0xFA,
- 0xC5,
- 0x80,
- 0xD8,
- 0xDB,
- 0x5A,
- 0x72,
- 0x2D,
- 0xE1,
- 0xA6,
- 0x79,
- 0xF4,
- 0xAE,
- 0x96,
- 0x1D,
- 0xE8,
- 0x28,
- 0x85,
- 0x5F,
- 0xBD,
- 0x64,
- 0xF8,
- 0xBF,
- 0x7A,
- 0xE7,
- 0xFF,
- 0xBC,
- 0x1F,
- 0xC6,
- 0x75,
- 0x56,
- 0xB9,
- 0xF9,
- 0x0F,
- 0x36,
- 0x29,
- 0x5A,
- 0x3B,
- 0xF3,
- 0x76,
- 0x7B,
- 0x8B,
- 0xF8,
- 0xFD,
- 0x13,
- 0x80,
- 0x49,
- 0xAB,
- 0x5C,
- 0x12,
- 0x63,
- 0xB9,
- 0xE7,
- 0x91,
- 0x2A,
- 0xBA,
- 0x82,
- 0xF3,
- 0xCD,
- 0xFA,
- 0xFB,
- 0x4E,
- 0xA7,
- 0xE1,
- 0xBD,
- 0x8B,
- 0xC3,
- 0x24,
- 0xEC,
- 0x31,
- 0xBC,
- 0x1,
- 0xB1,
- 0xCE,
- 0x9A,
- 0x4,
- 0x9C,
- 0x69,
- 0x5D,
- 0xBA,
- 0x3C,
- 0xF7,
- 0x97,
- 0x50,
- 0x88,
- 0xE2,
- 0xA2,
- 0xE1,
- 0x3,
- 0xDB,
- 0x39,
- 0xDD,
- 0x93,
- 0x0A,
- 0x24,
- 0x5C,
- 0x6E,
- 0x17,
- 0xE9,
- 0x1,
- 0x4C,
- 0x25,
- 0xF5,
- 0x9,
- 0x24,
- 0xC6,
- 0x91,
- 0xC6,
- 0x6A,
- 0x7A,
- 0x40,
- 0x89,
- 0x62,
- 0x7F,
- 0xED,
- 0x6B,
- 0x8E,
- 0x5F,
- 0x79,
- 0xAD,
- 0xF2,
- 0x50,
- 0x59,
- 0xC4,
- 0x11,
- 0x2E,
- 0x1,
- 0xC2,
- 0xDC,
- 0x8,
- 0xCE,
- 0xDC,
- 0x51,
- 0x14,
- 0xF4,
- 0x8C,
- 0x3D,
- 0x9E,
- 0xB7,
- 0x16,
- 0xB3,
- 0x9C,
- 0xF3,
- 0x55,
- 0xC0,
- 0xCE,
- 0x74,
- 0x5B,
- 0x19,
- 0x4E,
- 0xF5,
- 0x39,
- 0x37,
- 0xA6,
- 0xEA,
- 0xB5,
- 0x20,
- 0xBF,
- 0xD7,
- 0x79,
- 0x24,
- 0xE2,
- 0x8D,
- 0x13,
- 0xBC,
- 0x38,
- 0x10,
- 0x60,
- 0x93,
- 0xAE,
- 0x70,
- 0xA9,
- 0x66,
- 0x81,
- 0xF3,
- 0x19,
- 0xEC,
- 0x45,
- 0xEC,
- 0xE5,
- 0x5,
- 0x47,
- 0xE4,
- 0x67,
- 0x65,
- 0x4C,
- 0x62,
- 0x1,
- 0x98,
- 0xA3,
- 0x52,
- //SHA1
- 0x18,
- 0xb4,
- 0x70,
- 0x59,
- 0xfe,
- 0x13,
- 0x38,
- 0xc4,
- 0x15,
- 0xae,
- 0xf0,
- 0x81,
- 0xcb,
- 0x96,
- 0x27,
- 0xe7,
- 0xd9,
- 0x7b,
- 0xc5,
- 0x27,
- 0x20, //seed 0x2020
- 0x20,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
-};
-
/* HDCP Registers */
#define HDMI_A_KSVMEMCTRL 0x5016
#define HDMI_HDCPREG_ANCONF 0x7805
@@ -466,15 +139,11 @@ static void hdcp_modb(struct dw_hdcp *hdcp, u8 data, u8 mask, unsigned int reg)
static int hdcp_load_keys_cb(struct dw_hdcp *hdcp)
{
- u32 size;
u8 hdcp_vendor_data[320];
- int i;
-#if 0
- int j;
- struct file *fp;
- loff_t pos = 0;
- ssize_t nread;
-#endif
+ struct file *fp;
+ loff_t pos = 0;
+ ssize_t nread;
+
hdcp->keys = kmalloc(HDCP_KEY_SIZE, GFP_KERNEL);
if (!hdcp->keys)
return -ENOMEM;
@@ -484,27 +153,11 @@ static int hdcp_load_keys_cb(struct dw_hdcp *hdcp)
kfree(hdcp->keys);
return -ENOMEM;
}
-#if 1
- // size = eswin_vendor_read(HDMI_HDCP1X_ID, hdcp_vendor_data, 314);
-
- for (i = 0; i < sizeof(hdcp_vendor_data); i++)
- hdcp_vendor_data[i] = hdcp_const_data[i];
- size = 320;
- if (size < (HDCP_KEY_SIZE + HDCP_KEY_SEED_SIZE)) {
- dev_dbg(hdcp->dev, "HDCP: read size %d\n", size);
- memset(hdcp->keys, 0, HDCP_KEY_SIZE);
- memset(hdcp->seeds, 0, HDCP_KEY_SEED_SIZE);
- } else {
- memcpy(hdcp->keys, hdcp_vendor_data, HDCP_KEY_SIZE);
- memcpy(hdcp->seeds, hdcp_vendor_data + HDCP_KEY_SIZE,
- HDCP_KEY_SEED_SIZE);
- }
-#else
fp = filp_open(HDCP_KEY_PATH, O_RDONLY, 0644);
if (IS_ERR(fp)) {
- printk("Error, Tx_A2_TestDPK_encrypted.txt doesn't exist.\n");
- return 0;
+ printk("Error, Tx_A2_TestDPK_encrypted doesn't exist.\n");
+ goto err;
}
nread = kernel_read(fp, hdcp_vendor_data, sizeof(hdcp_vendor_data),
@@ -513,7 +166,8 @@ static int hdcp_load_keys_cb(struct dw_hdcp *hdcp)
if (nread != sizeof(hdcp_vendor_data)) {
printk("Error, failed to read %ld bytes to non volatile memory area,ret %ld\n",
sizeof(hdcp_vendor_data), nread);
- return -EIO;
+ filp_close(fp, NULL);
+ goto err;
}
memcpy(hdcp->keys, hdcp_vendor_data, HDCP_KEY_SIZE);
@@ -521,9 +175,13 @@ static int hdcp_load_keys_cb(struct dw_hdcp *hdcp)
HDCP_KEY_SEED_SIZE);
filp_close(fp, NULL);
-#endif
-
return 0;
+err:
+ kfree(hdcp->keys);
+ kfree(hdcp->seeds);
+ hdcp->keys = NULL;
+ hdcp->seeds = NULL;
+ return -EIO;
}
static int dw_hdmi_hdcp_load_key(struct dw_hdcp *hdcp)
@@ -599,6 +257,7 @@ static int dw_hdmi_hdcp1x_start(struct dw_hdcp *hdcp)
int i;
int val;
u8 An[8];
+ int ret;
if (!hdcp->enable)
return -EPERM;
@@ -607,11 +266,6 @@ static int dw_hdmi_hdcp1x_start(struct dw_hdcp *hdcp)
hdcp->status == DW_HDCP_AUTH_SUCCESS)
return 0;
- /* disable the pixel clock*/
- dev_dbg(hdcp->dev, "start hdcp with disable hdmi pixel clock\n");
- hdcp_modb(hdcp, HDMI_MC_CLKDIS_PIXELCLK_DISABLE,
- HDMI_MC_CLKDIS_PIXELCLK_MASK, HDMI_MC_CLKDIS);
-
/* Update An */
get_random_bytes(&An, sizeof(An));
for (i = 0; i < 8; i++)
@@ -619,8 +273,18 @@ static int dw_hdmi_hdcp1x_start(struct dw_hdcp *hdcp)
hdcp->write(hdmi, 0x01, HDMI_HDCPREG_ANCONF);
- if (!(hdcp->read(hdmi, HDMI_HDCPREG_RMSTS) & 0x3f))
- dw_hdmi_hdcp_load_key(hdcp);
+ if (!(hdcp->read(hdmi, HDMI_HDCPREG_RMSTS) & 0x3f)) {
+ ret = dw_hdmi_hdcp_load_key(hdcp);
+ if (ret) {
+ dev_err(hdcp->dev, "load hdcp key failed, ret=%d\n", ret);
+ return ret;
+ }
+ }
+
+ /* disable the pixel clock*/
+ dev_dbg(hdcp->dev, "start hdcp with disable hdmi pixel clock\n");
+ hdcp_modb(hdcp, HDMI_MC_CLKDIS_PIXELCLK_DISABLE,
+ HDMI_MC_CLKDIS_PIXELCLK_MASK, HDMI_MC_CLKDIS);
if (hdcp->hdcp2) {
for (i = 0; i < 100; i++) {
@@ -879,6 +543,7 @@ static ssize_t hdcp_enable_write(struct device *device,
{
bool enable;
struct dw_hdcp *hdcp = g_hdcp;
+ int ret;
if (!hdcp)
return -EINVAL;
@@ -895,7 +560,10 @@ static ssize_t hdcp_enable_write(struct device *device,
if (hdcp->read(hdcp->hdmi, HDMI_PHY_STAT0) &
HDMI_PHY_HPD) {
- dw_hdmi_hdcp1x_start(hdcp);
+ ret = dw_hdmi_hdcp1x_start(hdcp);
+ if (ret) {
+ hdcp->enable = 0;
+ }
}
} else {
if (hdcp->status != DW_HDCP_DISABLED) {
--
2.47.0

55
0067-fix-fix-the-issue-of-getting-hub-descriptor-fail.patch Normal file
View File

@ -0,0 +1,55 @@
From 17f96549ef590f22965baea4b85c603f9c06be70 Mon Sep 17 00:00:00 2001
From: liangshuang <liangshuang@eswincomputing.com>
Date: Tue, 9 Jul 2024 09:38:51 +0800
Subject: [PATCH 067/219] fix:fix the issue of getting hub descriptor fail.
Changelogs:
1.fix the issue of hub not being able to read descriptor.
Signed-off-by: liangshuang <liangshuang@eswincomputing.com>
---
drivers/usb/core/hub.c | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
index 1ba3feb5e190..af159223bd48 100644
--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
@@ -1407,6 +1407,7 @@ static int hub_configure(struct usb_hub *hub,
unsigned unit_load;
unsigned full_load;
unsigned maxchild;
+ int try_cnt = 0;
hub->buffer = kmalloc(sizeof(*hub->buffer), GFP_KERNEL);
if (!hub->buffer) {
@@ -1427,6 +1428,7 @@ static int hub_configure(struct usb_hub *hub,
goto fail;
}
+retry:
/* Request the entire hub descriptor.
* hub->descriptor can handle USB_MAXCHILDREN ports,
* but a (non-SS) hub can/will return fewer bytes here.
@@ -1446,9 +1448,15 @@ static int hub_configure(struct usb_hub *hub,
ret = -ENODEV;
goto fail;
} else if (hub->descriptor->bNbrPorts == 0) {
- message = "hub doesn't have any ports!";
- ret = -ENODEV;
- goto fail;
+ try_cnt++;
+ if (try_cnt < 10) {
+ mdelay(10);
+ goto retry;
+ } else {
+ message = "hub doesn't have any ports!";
+ ret = -ENODEV;
+ goto fail;
+ }
}
/*
--
2.47.0

73
0068-fix-fix-the-issue-of-USB-3.0-host-halt.patch Normal file
View File

@ -0,0 +1,73 @@
From 02cf0cb5727d1792395e4ea51e4c23d1297380bf Mon Sep 17 00:00:00 2001
From: liangshuang <liangshuang@eswincomputing.com>
Date: Wed, 10 Jul 2024 09:56:00 +0800
Subject: [PATCH 068/219] fix:fix the issue of USB 3.0 host halt.
Changelogs:
disable parkmod of fix the issue of failed copying large files under USB 3.0.
Signed-off-by: liangshuang <liangshuang@eswincomputing.com>
---
arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi | 10 ++--------
arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi | 10 ++--------
2 files changed, 4 insertions(+), 16 deletions(-)
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
index 0879dcca2527..79a64e2abaf3 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
@@ -1933,10 +1933,7 @@ d0_usbdrd_dwc3_0: dwc3@50480000 {
snps,dis-u2-freeclk-exists-quirk;
snps,dis_u2_susphy_quirk;
snps,dis-del-phy-power-chg-quirk;
- snps,tx-ipgap-linecheck-dis-quirk;
- snps,xhci-slow-suspend-quirk;
- snps,xhci-trb-ent-quirk;
- snps,usb3-warm-reset-on-resume-quirk;
+ snps,parkmode-disable-ss-quirk;
status = "disabled";
numa-node-id = <0>;
tbus = <WIN2030_TBUID_USB>;
@@ -1973,10 +1970,7 @@ d0_usbdrd_dwc3_1: dwc3@50490000 {
snps,dis-u2-freeclk-exists-quirk;
snps,dis_u2_susphy_quirk;
snps,dis-del-phy-power-chg-quirk;
- snps,tx-ipgap-linecheck-dis-quirk;
- snps,xhci-slow-suspend-quirk;
- snps,xhci-trb-ent-quirk;
- snps,usb3-warm-reset-on-resume-quirk;
+ snps,parkmode-disable-ss-quirk;
status = "disabled";
numa-node-id = <0>;
tbus = <WIN2030_TBUID_USB>;
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
index 1417c6298a3c..aff6298f851e 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
@@ -1931,10 +1931,7 @@ d1_usbdrd_dwc3_0: dwc3@70480000 {
snps,dis-u2-freeclk-exists-quirk;
snps,dis_u2_susphy_quirk;
snps,dis-del-phy-power-chg-quirk;
- snps,tx-ipgap-linecheck-dis-quirk;
- snps,xhci-slow-suspend-quirk;
- snps,xhci-trb-ent-quirk;
- snps,usb3-warm-reset-on-resume-quirk;
+ snps,parkmode-disable-ss-quirk;
status = "disabled";
numa-node-id = <1>;
tbus = <WIN2030_TBUID_USB>;
@@ -1971,10 +1968,7 @@ d1_usbdrd_dwc3_1: dwc3@70490000 {
snps,dis-u2-freeclk-exists-quirk;
snps,dis_u2_susphy_quirk;
snps,dis-del-phy-power-chg-quirk;
- snps,tx-ipgap-linecheck-dis-quirk;
- snps,xhci-slow-suspend-quirk;
- snps,xhci-trb-ent-quirk;
- snps,usb3-warm-reset-on-resume-quirk;
+ snps,parkmode-disable-ss-quirk;
status = "disabled";
numa-node-id = <1>;
tbus = <WIN2030_TBUID_USB>;
--
2.47.0

419606
0069-img-gpu-kmd-migrate-from-5.17-to-6.6.patch Normal file
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File diff suppressed because it is too large Load Diff

26
0070-img-gpu-kmd-remove-warning-of-flush_scheduled_work-t.patch Normal file
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@ -0,0 +1,26 @@
From 485367465b9eb1e59d1836e53332ee092903ed54 Mon Sep 17 00:00:00 2001
From: Sakura286 <sakura286@outlook.com>
Date: Fri, 5 Jul 2024 12:11:41 +0800
Subject: [PATCH 070/219] img gpu kmd: remove warning of flush_scheduled_work()
to enable volcanic gpu work
ref: https://github.com/starfive-tech/linux/commit/d89c0fec5e542e859df5dc590caeaff99cae10db
---
include/linux/workqueue.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/linux/workqueue.h b/include/linux/workqueue.h
index 52c6dd6d80ac..629f9dcdc111 100644
--- a/include/linux/workqueue.h
+++ b/include/linux/workqueue.h
@@ -636,7 +636,6 @@ extern void __warn_flushing_systemwide_wq(void)
/* Please stop using this function, for this function will be removed in near future. */
#define flush_scheduled_work() \
({ \
- __warn_flushing_systemwide_wq(); \
__flush_workqueue(system_wq); \
})
--
2.47.0

207
0071-img-gpu-kmd-update-kernel-api-of-dma_resv.patch Normal file
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@ -0,0 +1,207 @@
From b1e976901242ad790fe715075cb9c4cbf466f878 Mon Sep 17 00:00:00 2001
From: Sakura286 <sakura286@outlook.com>
Date: Fri, 5 Jul 2024 13:47:09 +0800
Subject: [PATCH 071/219] img gpu kmd: update kernel api of dma_resv
ref: https://github.com/starfive-tech/linux/commit/8180dc82
https://github.com/cl91/mtgpu-drv/blob/v5.19-fix/patch/0001-mtgpu-Update-to-kernel-v5.19.patch
---
.../server/env/linux/pvr_buffer_sync.c | 156 ++++++++++++++++++
1 file changed, 156 insertions(+)
diff --git a/drivers/gpu/drm/img/img-volcanic/services/server/env/linux/pvr_buffer_sync.c b/drivers/gpu/drm/img/img-volcanic/services/server/env/linux/pvr_buffer_sync.c
index b5426d402eed..5d9ec73376d2 100644
--- a/drivers/gpu/drm/img/img-volcanic/services/server/env/linux/pvr_buffer_sync.c
+++ b/drivers/gpu/drm/img/img-volcanic/services/server/env/linux/pvr_buffer_sync.c
@@ -172,6 +172,145 @@ pvr_buffer_sync_pmrs_unlock(struct pvr_buffer_sync_context *ctx,
mutex_unlock(&ctx->ctx_lock);
}
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0))
+
+static void
+dma_resv_count_fences(struct dma_resv *resv, u32 *read_fence_count_out, u32 *write_fence_count_out)
+{
+ struct dma_resv_iter cursor;
+ u32 write_fence_count = 0;
+ u32 read_fence_count = 0;
+ struct dma_fence *fence;
+
+ dma_resv_iter_begin(&cursor, resv, DMA_RESV_USAGE_READ);
+ dma_resv_for_each_fence_unlocked(&cursor, fence) {
+ if (dma_resv_iter_is_restarted(&cursor)) {
+ read_fence_count = 0;
+ write_fence_count = 0;
+ }
+ if (dma_resv_iter_usage(&cursor) == DMA_RESV_USAGE_READ)
+ read_fence_count++;
+ else if (dma_resv_iter_usage(&cursor) == DMA_RESV_USAGE_WRITE)
+ write_fence_count++;
+ }
+
+ *read_fence_count_out = read_fence_count;
+ *write_fence_count_out = write_fence_count;
+}
+
+static u32
+pvr_buffer_sync_pmrs_fence_count(u32 nr_pmrs, struct _PMR_ **pmrs,
+ u32 *pmr_flags)
+{
+ struct dma_resv *resv;
+ u32 fence_count = 0;
+ bool exclusive;
+ int i;
+
+ for (i = 0; i < nr_pmrs; i++) {
+ u32 write_fence_count = 0;
+ u32 read_fence_count = 0;
+
+ exclusive = !!(pmr_flags[i] & PVR_BUFFER_FLAG_WRITE);
+
+ resv = pmr_reservation_object_get(pmrs[i]);
+ if (WARN_ON_ONCE(!resv))
+ continue;
+
+ dma_resv_count_fences(resv, &read_fence_count, &write_fence_count);
+
+ if (!exclusive || !read_fence_count)
+ fence_count += write_fence_count;
+ if (exclusive)
+ fence_count += read_fence_count;
+ }
+
+ return fence_count;
+}
+
+static struct pvr_buffer_sync_check_data *
+pvr_buffer_sync_check_fences_create(struct pvr_fence_context *fence_ctx,
+ PSYNC_CHECKPOINT_CONTEXT sync_checkpoint_ctx,
+ u32 nr_pmrs,
+ struct _PMR_ **pmrs,
+ u32 *pmr_flags)
+{
+ struct pvr_buffer_sync_check_data *data;
+ struct dma_resv *resv;
+ struct dma_fence *fence;
+ u32 fence_count;
+ bool exclusive;
+ int i;
+
+ data = kzalloc(sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return NULL;
+
+ fence_count = pvr_buffer_sync_pmrs_fence_count(nr_pmrs, pmrs,
+ pmr_flags);
+ if (fence_count) {
+ data->fences = kcalloc(fence_count, sizeof(*data->fences),
+ GFP_KERNEL);
+ if (!data->fences)
+ goto err_check_data_free;
+ }
+
+ for (i = 0; i < nr_pmrs; i++) {
+ struct dma_resv_iter cursor;
+ bool include_write_fences;
+ bool include_read_fences;
+ u32 write_fence_count = 0;
+ u32 read_fence_count = 0;
+
+ resv = pmr_reservation_object_get(pmrs[i]);
+ if (WARN_ON_ONCE(!resv))
+ continue;
+
+ exclusive = !!(pmr_flags[i] & PVR_BUFFER_FLAG_WRITE);
+
+ dma_resv_count_fences(resv, &read_fence_count, &write_fence_count);
+
+ include_write_fences = (!exclusive || !read_fence_count);
+ include_read_fences = exclusive;
+
+ dma_resv_iter_begin(&cursor, resv, DMA_RESV_USAGE_READ);
+ dma_resv_for_each_fence_unlocked(&cursor, fence) {
+ enum dma_resv_usage usage = dma_resv_iter_usage(&cursor);
+
+ if ((!include_write_fences && usage == DMA_RESV_USAGE_WRITE) ||
+ (!include_read_fences && usage == DMA_RESV_USAGE_READ))
+ continue;
+
+ data->fences[data->nr_fences++] =
+ pvr_fence_create_from_fence(fence_ctx,
+ sync_checkpoint_ctx,
+ fence,
+ PVRSRV_NO_FENCE,
+ (usage == DMA_RESV_USAGE_WRITE) ?
+ "write check fence" :
+ "read check fence");
+ if (!data->fences[data->nr_fences - 1]) {
+ data->nr_fences--;
+ PVR_FENCE_TRACE(fence,
+ (usage == DMA_RESV_USAGE_WRITE) ?
+ "waiting on write fence" :
+ "waiting on read fence\n");
+ WARN_ON(dma_fence_wait(fence, true) <= 0);
+ }
+ }
+ }
+
+ WARN_ON((i != nr_pmrs));
+
+ return data;
+
+err_check_data_free:
+ kfree(data);
+ return NULL;
+}
+
+#else
+
static u32
pvr_buffer_sync_pmrs_fence_count(u32 nr_pmrs, struct _PMR_ **pmrs,
u32 *pmr_flags)
@@ -301,6 +440,8 @@ pvr_buffer_sync_check_fences_create(struct pvr_fence_context *fence_ctx,
return NULL;
}
+#endif
+
static void
pvr_buffer_sync_check_fences_destroy(struct pvr_buffer_sync_check_data *data)
{
@@ -527,18 +668,33 @@ pvr_buffer_sync_kick_succeeded(struct pvr_buffer_sync_append_data *data)
if (WARN_ON_ONCE(!resv))
continue;
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0))
+ dma_resv_reserve_fences(resv, 1);
+#endif
if (data->pmr_flags[i] & PVR_BUFFER_FLAG_WRITE) {
PVR_FENCE_TRACE(&data->update_fence->base,
"added exclusive fence (%s) to resv %p\n",
data->update_fence->name, resv);
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0))
+ dma_resv_add_fence(resv,
+ &data->update_fence->base,
+ DMA_RESV_USAGE_WRITE);
+#else
dma_resv_add_excl_fence(resv,
&data->update_fence->base);
+#endif
} else if (data->pmr_flags[i] & PVR_BUFFER_FLAG_READ) {
PVR_FENCE_TRACE(&data->update_fence->base,
"added non-exclusive fence (%s) to resv %p\n",
data->update_fence->name, resv);
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0))
+ dma_resv_add_fence(resv,
+ &data->update_fence->base,
+ DMA_RESV_USAGE_READ);
+#else
dma_resv_add_shared_fence(resv,
&data->update_fence->base);
+#endif
}
}
--
2.47.0

36
0072-img-gpu-kmd-update-kernel-api-dma_buf_map-to-iosys_m.patch Normal file
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@ -0,0 +1,36 @@
From 820aa09bc82e75178468c10cc50c0c8c6519526e Mon Sep 17 00:00:00 2001
From: Sakura286 <sakura286@outlook.com>
Date: Fri, 5 Jul 2024 13:35:25 +0800
Subject: [PATCH 072/219] img gpu kmd: update kernel api dma_buf_map to
iosys_map
ref: https://github.com/torvalds/linux/commit/7938f421
---
.../img-volcanic/services/server/env/linux/physmem_dmabuf.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/img/img-volcanic/services/server/env/linux/physmem_dmabuf.c b/drivers/gpu/drm/img/img-volcanic/services/server/env/linux/physmem_dmabuf.c
index 576980ed45cf..a90b3b5879d0 100644
--- a/drivers/gpu/drm/img/img-volcanic/services/server/env/linux/physmem_dmabuf.c
+++ b/drivers/gpu/drm/img/img-volcanic/services/server/env/linux/physmem_dmabuf.c
@@ -170,7 +170,7 @@ typedef struct _PMR_DMA_BUF_DATA_
IMG_BOOL bPoisonOnFree;
/* Mapping information. */
- struct dma_buf_map sMap;
+ struct iosys_map sMap;
/* Modified by PMR lock/unlock */
struct sg_table *psSgTable;
@@ -196,7 +196,7 @@ static IMG_UINT32 g_ui32HashRefCount;
static int
DmaBufSetValue(struct dma_buf *psDmaBuf, int iValue, const char *szFunc)
{
- struct dma_buf_map sMap;
+ struct iosys_map sMap;
int err, err_end_access;
#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0))
int i;
--
2.47.0

43
0073-img-gpu-kmd-update-kernel-api-register_shrinker.patch Normal file
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@ -0,0 +1,43 @@
From bb30e9c2ba203ce22139c0198e82cf52da03780c Mon Sep 17 00:00:00 2001
From: Sakura286 <sakura286@outlook.com>
Date: Wed, 10 Jul 2024 17:24:52 +0800
Subject: [PATCH 073/219] img gpu kmd: update kernel api - register_shrinker
ref: https://github.com/torvalds/linux/commit/e33c267a
---
.../services/server/env/linux/physmem_osmem_linux.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/img/img-volcanic/services/server/env/linux/physmem_osmem_linux.c b/drivers/gpu/drm/img/img-volcanic/services/server/env/linux/physmem_osmem_linux.c
index a36b769bc6d6..3a664506de4f 100644
--- a/drivers/gpu/drm/img/img-volcanic/services/server/env/linux/physmem_osmem_linux.c
+++ b/drivers/gpu/drm/img/img-volcanic/services/server/env/linux/physmem_osmem_linux.c
@@ -512,7 +512,13 @@ void LinuxInitPhysmem(void)
if (g_psLinuxPagePoolCache)
{
/* Only create the shrinker if we created the cache OK */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 0, 0))
register_shrinker(&g_sShrinker);
+#elif (LINUX_VERSION_CODE < KERNEL_VERSION(6, 7, 0))
+ register_shrinker(&g_sShrinker, "pvr-pp");
+#else
+ shrinker_register(&g_sShrinker);
+#endif
}
OSAtomicWrite(&g_iPoolCleanTasks, 0);
@@ -561,7 +567,11 @@ void LinuxDeinitPhysmem(void)
/* Free the page cache */
kmem_cache_destroy(g_psLinuxPagePoolCache);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 7, 0))
unregister_shrinker(&g_sShrinker);
+#else
+ shrinker_free(&g_sShrinker);
+#endif
_PagePoolUnlock();
kmem_cache_destroy(g_psLinuxPageArray);
--
2.47.0

35
0074-img-gpu-kmd-use-arch_sync_dma_for_device-instead-of-.patch Normal file
View File

@ -0,0 +1,35 @@
From e4f3a95e17a01c53efed1dbc6841d0f04af347b0 Mon Sep 17 00:00:00 2001
From: Sakura286 <sakura286@outlook.com>
Date: Wed, 10 Jul 2024 18:03:36 +0800
Subject: [PATCH 074/219] img gpu kmd: use arch_sync_dma_for_device() instead
of sifive_l2_flush64_range()
---
.../img/img-volcanic/services/system/eswin_cpu/sysconfig.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/img/img-volcanic/services/system/eswin_cpu/sysconfig.c b/drivers/gpu/drm/img/img-volcanic/services/system/eswin_cpu/sysconfig.c
index e6750e7b49a0..d94c76cc68b9 100644
--- a/drivers/gpu/drm/img/img-volcanic/services/system/eswin_cpu/sysconfig.c
+++ b/drivers/gpu/drm/img/img-volcanic/services/system/eswin_cpu/sysconfig.c
@@ -34,7 +34,7 @@
#include <linux/platform_device.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
-#include <soc/sifive/sifive_l2_cache.h>
+#include <linux/dma-map-ops.h>
#include <linux/clk.h>
#include <linux/reset.h>
@@ -55,7 +55,7 @@ IMG_UINT64 *cpu_cache_flush_addr = NULL;
extern void eswin_l2_flush64(phys_addr_t addr, size_t size);
#else
void eswin_l2_flush64(phys_addr_t addr, size_t size) {
- sifive_l2_flush64_range(addr,size);
+ arch_sync_dma_for_device(addr, size, DMA_TO_DEVICE);
};
#endif
void riscv_invalidate_addr(phys_addr_t addr, size_t size,IMG_BOOL virtual) {
--
2.47.0

80
0075-img-gpu-kmd-fix-vm_flags-setting-issue.patch Normal file
View File

@ -0,0 +1,80 @@
From 4e2c1ae5da9ee856c47112dde95816bc1e0c2ccc Mon Sep 17 00:00:00 2001
From: Sakura286 <sakura286@outlook.com>
Date: Fri, 5 Jul 2024 11:34:07 +0800
Subject: [PATCH 075/219] img gpu kmd: fix vm_flags setting issue
ref: https://gist.github.com/vejeta/9078219f082d2bfd62b08b6eada780e6
---
.../img-volcanic/services/server/env/linux/osfunc.c | 4 ++--
.../img-volcanic/services/server/env/linux/pmr_os.c | 13 +++++++------
2 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/img/img-volcanic/services/server/env/linux/osfunc.c b/drivers/gpu/drm/img/img-volcanic/services/server/env/linux/osfunc.c
index 1a7d406fb085..6d060ddc97d7 100644
--- a/drivers/gpu/drm/img/img-volcanic/services/server/env/linux/osfunc.c
+++ b/drivers/gpu/drm/img/img-volcanic/services/server/env/linux/osfunc.c
@@ -1796,7 +1796,7 @@ PVRSRV_ERROR OSChangeSparseMemCPUAddrMap(void **psPageArray,
if ((psVMA->vm_flags & VM_MIXEDMAP) || bIsLMA)
{
- psVMA->vm_flags |= VM_MIXEDMAP;
+ vm_flags_set(psVMA, VM_MIXEDMAP);
bMixedMap = IMG_TRUE;
}
else
@@ -1818,7 +1818,7 @@ PVRSRV_ERROR OSChangeSparseMemCPUAddrMap(void **psPageArray,
#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 5, 0)) */
{
bMixedMap = IMG_TRUE;
- psVMA->vm_flags |= VM_MIXEDMAP;
+ vm_flags_set(psVMA, VM_MIXEDMAP);
break;
}
}
diff --git a/drivers/gpu/drm/img/img-volcanic/services/server/env/linux/pmr_os.c b/drivers/gpu/drm/img/img-volcanic/services/server/env/linux/pmr_os.c
index fac2bd45a371..7cf4df444089 100644
--- a/drivers/gpu/drm/img/img-volcanic/services/server/env/linux/pmr_os.c
+++ b/drivers/gpu/drm/img/img-volcanic/services/server/env/linux/pmr_os.c
@@ -393,19 +393,20 @@ OSMMapPMRGeneric(PMR *psPMR, PMR_MMAP_DATA pOSMMapData)
}
ps_vma->vm_page_prot = sPageProt;
- ps_vma->vm_flags |= VM_IO;
+ vm_flags_set(ps_vma, VM_IO);
/* Don't include the mapping in core dumps */
- ps_vma->vm_flags |= VM_DONTDUMP;
+ vm_flags_set(ps_vma, VM_DONTDUMP);
/*
* Disable mremap because our nopage handler assumes all
* page requests have already been validated.
*/
- ps_vma->vm_flags |= VM_DONTEXPAND;
+ vm_flags_set(ps_vma, VM_DONTEXPAND);
+
/* Don't allow mapping to be inherited across a process fork */
- ps_vma->vm_flags |= VM_DONTCOPY;
+ vm_flags_set(ps_vma, VM_DONTCOPY);
uiLength = ps_vma->vm_end - ps_vma->vm_start;
@@ -492,12 +493,12 @@ OSMMapPMRGeneric(PMR *psPMR, PMR_MMAP_DATA pOSMMapData)
if (bUseMixedMap)
{
- ps_vma->vm_flags |= VM_MIXEDMAP;
+ vm_flags_set(ps_vma, VM_MIXEDMAP);
}
}
else
{
- ps_vma->vm_flags |= VM_PFNMAP;
+ vm_flags_set(ps_vma, VM_PFNMAP);
}
/* For each PMR page-size contiguous bytes, map page(s) into user VMA */
--
2.47.0

60
0076-regulator-mpq8785-mpq8785_label-add-label-len-for-np.patch Normal file
View File

@ -0,0 +1,60 @@
From a95f548f64797d765c1a5b9536b72095fdcefc26 Mon Sep 17 00:00:00 2001
From: Han Gao <gaohan@iscas.ac.cn>
Date: Sun, 7 Jul 2024 00:45:36 +0800
Subject: [PATCH 076/219] regulator: mpq8785: mpq8785_label: add label len for
"npu temperature1"
detected buffer overflow in strcpy
[ 1.391721] detected buffer overflow in strcpy
[ 1.396122] ------------[ cut here ]------------
[ 1.396124] Kernel BUG at fortify_panic+0x1a/0x1c [verbose debug info unavailable]
[ 1.396142] Kernel BUG [#1]
[ 1.396145] Modules linked in:
[ 1.396150] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 6.6.36 #0
[ 1.396155] Hardware name: ESWIN EIC7700 (DT)
[ 1.396157] epc : fortify_panic+0x1a/0x1c
[ 1.396163] ra : fortify_panic+0x1a/0x1c
[ 1.396168] epc : ffffffff8030b2de ra : ffffffff8030b2de sp : ffffaf80a7177b20
[ 1.396171] gp : ffffffff812e47a8 tp : ffffaf80a714cd00 t0 : 2000000000000000
[ 1.396174] t1 : 0000000000000064 t2 : 2064657463657465 s0 : ffffaf80a7177b30
[ 1.396177] s1 : ffffaf80a8755c40 a0 : 0000000000000022 a1 : ffffffff81283d48
[ 1.396180] a2 : 0000000000000010 a3 : ffffffff81283d48 a4 : ffffffff81283d60
[ 1.396183] a5 : 0000000000000000 a6 : ffffffff81213cf0 a7 : 0000000000000001
[ 1.396186] s2 : ffffaf80a794a000 s3 : ffffaf80a8755c60 s4 : ffff8d7ffec18dae
[ 1.396189] s5 : ffffaf82a6f9fb00 s6 : ffffaf80a794a020 s7 : ffffaf80a8755cd0
[ 1.396192] s8 : 0000000000000000 s9 : 0000000000000000 s10: 0000000000000000
[ 1.396194] s11: 0000000000000000 t3 : ffffffff812f5ad7 t4 : ffffffff812f5ad7
[ 1.396197] t5 : ffffffff812f5ad8 t6 : ffffaf80a7177970
[ 1.396199] status: 0000000200000120 badaddr: 0000000000000000 cause: 0000000000000003
[ 1.396203] [<ffffffff8030b2de>] fortify_panic+0x1a/0x1c
[ 1.396209] [<ffffffff80393d18>] mpq8785_probe+0x3d8/0x462
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/regulator/mpq8785.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/regulator/mpq8785.c b/drivers/regulator/mpq8785.c
index d5dae70d3d50..3787fe244618 100644
--- a/drivers/regulator/mpq8785.c
+++ b/drivers/regulator/mpq8785.c
@@ -153,7 +153,7 @@ struct MPQ8785_DRIVER_DATA
struct regulator_desc *dev_desc;
struct i2c_client *client;
struct mutex config_lock;
- char mpq8785_label[MPQ8785_LABEL_CNT][16];
+ char mpq8785_label[MPQ8785_LABEL_CNT][20];
};
#define MPQ8785_MASK_OPERATION_ENABLE 0X80
@@ -1216,4 +1216,4 @@ module_i2c_driver(mpq8785_driver);
MODULE_AUTHOR("Yang Wei <yangwei1@eswincomputing.com>");
MODULE_DESCRIPTION("mpq8785 driver");
-MODULE_LICENSE("GPL");
\ No newline at end of file
+MODULE_LICENSE("GPL");
--
2.47.0

26
0077-chore-dtb_install-in-boot.patch Normal file
View File

@ -0,0 +1,26 @@
From 0208bec6b871e5d5d7b93becea808d3209b33cef Mon Sep 17 00:00:00 2001
From: Han Gao <gaohan@iscas.ac.cn>
Date: Wed, 26 Jun 2024 21:40:08 +0800
Subject: [PATCH 077/219] chore: dtb_install in /boot
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
scripts/package/builddeb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/package/builddeb b/scripts/package/builddeb
index d7dd0d04c70c..cbcf14820fb9 100755
--- a/scripts/package/builddeb
+++ b/scripts/package/builddeb
@@ -59,7 +59,7 @@ install_linux_image () {
# Only some architectures with OF support have this target
if is_enabled CONFIG_OF_EARLY_FLATTREE && [ -d "${srctree}/arch/${SRCARCH}/boot/dts" ]; then
- ${MAKE} -f ${srctree}/Makefile INSTALL_DTBS_PATH="${pdir}/usr/lib/linux-image-${KERNELRELEASE}" dtbs_install
+ ${MAKE} -f ${srctree}/Makefile INSTALL_DTBS_PATH="${pdir}/boot/dtbs/linux-image-${KERNELRELEASE}" dtbs_install
fi
${MAKE} -f ${srctree}/Makefile INSTALL_MOD_PATH="${pdir}" modules_install
--
2.47.0

130
0078-feat-enable-h-ext.patch Normal file
View File

@ -0,0 +1,130 @@
From 4a181c48feb934f1c53af5cdf55db0c4b3e5a2d6 Mon Sep 17 00:00:00 2001
From: Han Gao <gaohan@iscas.ac.cn>
Date: Wed, 26 Jun 2024 21:42:42 +0800
Subject: [PATCH 078/219] feat: enable h ext
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../boot/dts/eswin/eswin-win2030-arch-d2d.dtsi | 16 ++++++++--------
.../riscv/boot/dts/eswin/eswin-win2030-arch.dtsi | 8 ++++----
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-arch-d2d.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-arch-d2d.dtsi
index 08b35addb5b7..725d93d2165f 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-arch-d2d.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-arch-d2d.dtsi
@@ -99,7 +99,7 @@ cpu_0: cpu@0 {
mmu-type = "riscv,sv48";
next-level-cache = <&L15>;
reg = <0x0>;
- riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb";
riscv,pmpgranularity = <4096>;
riscv,pmpregions = <8>;
sifive,buserror = <&L16>;
@@ -146,7 +146,7 @@ cpu_1: cpu@1 {
mmu-type = "riscv,sv48";
next-level-cache = <&L20>;
reg = <0x1>;
- riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb";
riscv,pmpgranularity = <4096>;
riscv,pmpregions = <8>;
sifive,buserror = <&L21>;
@@ -193,7 +193,7 @@ cpu_2: cpu@2 {
mmu-type = "riscv,sv48";
next-level-cache = <&L25>;
reg = <0x2>;
- riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb";
riscv,pmpgranularity = <4096>;
riscv,pmpregions = <8>;
sifive,buserror = <&L26>;
@@ -240,7 +240,7 @@ cpu_3: cpu@3 {
mmu-type = "riscv,sv48";
next-level-cache = <&L30>;
reg = <0x3>;
- riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb";
riscv,pmpgranularity = <4096>;
riscv,pmpregions = <8>;
sifive,buserror = <&L31>;
@@ -297,7 +297,7 @@ cpu_4: cpu@4 {
#else
reg = <0x4>;
#endif
- riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb";
riscv,pmpgranularity = <4096>;
riscv,pmpregions = <8>;
#if (CHIPLET_AND_DIE & 0x2)
@@ -344,7 +344,7 @@ cpu_5: cpu@5 {
mmu-type = "riscv,sv48";
next-level-cache = <&D2L2_1>;
reg = <0x5>;
- riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb";
riscv,pmpgranularity = <4096>;
riscv,pmpregions = <8>;
#if (CHIPLET_AND_DIE & 0x2)
@@ -390,7 +390,7 @@ cpu_6: cpu@6 {
mmu-type = "riscv,sv48";
next-level-cache = <&D2L2_2>;
reg = <0x6>;
- riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb";
riscv,pmpgranularity = <4096>;
riscv,pmpregions = <8>;
#if (CHIPLET_AND_DIE & 0x2)
@@ -436,7 +436,7 @@ cpu_7: cpu@7 {
mmu-type = "riscv,sv48";
next-level-cache = <&D2L2_3>;
reg = <0x7>;
- riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb";
+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb";
riscv,pmpgranularity = <4096>;
riscv,pmpregions = <8>;
#if (CHIPLET_AND_DIE & 0x2)
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-arch.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-arch.dtsi
index 3571f134aacc..cde282a61863 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-arch.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-arch.dtsi
@@ -66,7 +66,7 @@ L17: cpu@0 {
mmu-type = "riscv,sv48";
next-level-cache = <&L15>;
reg = <0x0>;
- riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb_sscofpmf";
+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf";
riscv,pmpgranularity = <4096>;
riscv,pmpregions = <8>;
sifive,buserror = <&L16>;
@@ -108,7 +108,7 @@ L22: cpu@1 {
mmu-type = "riscv,sv48";
next-level-cache = <&L20>;
reg = <0x1>;
- riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb_sscofpmf";
+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf";
riscv,pmpgranularity = <4096>;
riscv,pmpregions = <8>;
sifive,buserror = <&L21>;
@@ -150,7 +150,7 @@ L27: cpu@2 {
mmu-type = "riscv,sv48";
next-level-cache = <&L25>;
reg = <0x2>;
- riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb_sscofpmf";
+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf";
riscv,pmpgranularity = <4096>;
riscv,pmpregions = <8>;
sifive,buserror = <&L26>;
@@ -192,7 +192,7 @@ L32: cpu@3 {
mmu-type = "riscv,sv48";
next-level-cache = <&L30>;
reg = <0x3>;
- riscv,isa = "rv64imafdc_zicsr_zifencei_zba_zbb_sscofpmf";
+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf";
riscv,pmpgranularity = <4096>;
riscv,pmpregions = <8>;
sifive,buserror = <&L31>;
--
2.47.0

114
0079-ttm-disallow-cached-mapping.patch Normal file
View File

@ -0,0 +1,114 @@
From ce39936608037e67cb2c14b24ecca92b1fe5a2d2 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <uwu@icenowy.me>
Date: Fri, 24 Feb 2023 17:23:17 +0800
Subject: [PATCH 079/219] ttm: disallow cached mapping
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
---
drivers/gpu/drm/drm_gem_vram_helper.c | 2 +-
drivers/gpu/drm/ttm/ttm_bo_util.c | 5 ++++-
drivers/gpu/drm/ttm/ttm_module.c | 3 ++-
drivers/gpu/drm/ttm/ttm_resource.c | 7 ++++---
drivers/gpu/drm/ttm/ttm_tt.c | 2 +-
5 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c b/drivers/gpu/drm/drm_gem_vram_helper.c
index b67eafa55715..5ebe418bd383 100644
--- a/drivers/gpu/drm/drm_gem_vram_helper.c
+++ b/drivers/gpu/drm/drm_gem_vram_helper.c
@@ -870,7 +870,7 @@ static struct ttm_tt *bo_driver_ttm_tt_create(struct ttm_buffer_object *bo,
if (!tt)
return NULL;
- ret = ttm_tt_init(tt, bo, page_flags, ttm_cached, 0);
+ ret = ttm_tt_init(tt, bo, page_flags, ttm_write_combined, 0);
if (ret < 0)
goto err_ttm_tt_init;
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c
index 0b3f4267130c..f469067c8187 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -354,6 +354,7 @@ static int ttm_bo_kmap_ttm(struct ttm_buffer_object *bo,
if (ret)
return ret;
+#if 0
if (num_pages == 1 && ttm->caching == ttm_cached &&
!(man->use_tt && (ttm->page_flags & TTM_TT_FLAG_DECRYPTED))) {
/*
@@ -364,7 +365,9 @@ static int ttm_bo_kmap_ttm(struct ttm_buffer_object *bo,
map->bo_kmap_type = ttm_bo_map_kmap;
map->page = ttm->pages[start_page];
map->virtual = kmap(map->page);
- } else {
+ } else
+#endif
+ {
/*
* We need to use vmap to get the desired page protection
* or to make the buffer object look contiguous.
diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c
index b3fffe7b5062..aa137ead5cc5 100644
--- a/drivers/gpu/drm/ttm/ttm_module.c
+++ b/drivers/gpu/drm/ttm/ttm_module.c
@@ -74,7 +74,8 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching caching, pgprot_t tmp)
#endif /* CONFIG_UML */
#endif /* __i386__ || __x86_64__ */
#if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \
- defined(__powerpc__) || defined(__mips__) || defined(__loongarch__)
+ defined(__powerpc__) || defined(__mips__) || defined(__loongarch__) || \
+ defined(__riscv)
if (caching == ttm_write_combined)
tmp = pgprot_writecombine(tmp);
else
diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c
index 46ff9c75bb12..63a9b8d41b94 100644
--- a/drivers/gpu/drm/ttm/ttm_resource.c
+++ b/drivers/gpu/drm/ttm/ttm_resource.c
@@ -187,7 +187,7 @@ void ttm_resource_init(struct ttm_buffer_object *bo,
res->bus.addr = NULL;
res->bus.offset = 0;
res->bus.is_iomem = false;
- res->bus.caching = ttm_cached;
+ res->bus.caching = ttm_write_combined;
res->bo = bo;
man = ttm_manager_type(bo->bdev, place->mem_type);
@@ -670,17 +670,18 @@ ttm_kmap_iter_linear_io_init(struct ttm_kmap_iter_linear_io *iter_io,
} else {
iter_io->needs_unmap = true;
memset(&iter_io->dmap, 0, sizeof(iter_io->dmap));
- if (mem->bus.caching == ttm_write_combined)
+ if (mem->bus.caching == ttm_write_combined || mem->bus.caching == ttm_cached)
iosys_map_set_vaddr_iomem(&iter_io->dmap,
ioremap_wc(mem->bus.offset,
mem->size));
+#if 0
else if (mem->bus.caching == ttm_cached)
iosys_map_set_vaddr(&iter_io->dmap,
memremap(mem->bus.offset, mem->size,
MEMREMAP_WB |
MEMREMAP_WT |
MEMREMAP_WC));
-
+#endif
/* If uncached requested or if mapping cached or wc failed */
if (iosys_map_is_null(&iter_io->dmap))
iosys_map_set_vaddr_iomem(&iter_io->dmap,
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index bf9601351fa3..af3ab03200c0 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -154,7 +154,7 @@ static void ttm_tt_init_fields(struct ttm_tt *ttm,
ttm->dma_address = NULL;
ttm->swap_storage = NULL;
ttm->sg = bo->sg;
- ttm->caching = caching;
+ ttm->caching = ttm_write_combined;
}
int ttm_tt_init(struct ttm_tt *ttm, struct ttm_buffer_object *bo,
--
2.47.0

65
0080-drm-eswin-fbdev-fix-es-fbdev.patch Normal file
View File

@ -0,0 +1,65 @@
From 82350728bf13a1d61517983279e71813ebeb29b4 Mon Sep 17 00:00:00 2001
From: Han Gao <gaohan@iscas.ac.cn>
Date: Fri, 14 Jun 2024 17:58:40 +0800
Subject: [PATCH 080/219] drm: eswin: fbdev: fix es-fbdev
fix es-fbdev
Co-authored-by: Icenowy Zheng <uwu@icenowy.me>
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/gpu/drm/eswin/es_drv.c | 3 +++
drivers/gpu/drm/eswin/es_gem.c | 9 ++++++++-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/eswin/es_drv.c b/drivers/gpu/drm/eswin/es_drv.c
index 936198b1c351..2596e8e492a3 100644
--- a/drivers/gpu/drm/eswin/es_drv.c
+++ b/drivers/gpu/drm/eswin/es_drv.c
@@ -22,6 +22,7 @@
#include <drm/drm_vblank.h>
#include <drm/drm_framebuffer.h>
#include <drm/drm_atomic_helper.h>
+#include <drm/drm_fbdev_generic.h>
#include "es_drv.h"
#include "es_fb.h"
@@ -277,6 +278,8 @@ static int es_drm_bind(struct device *dev)
if (ret)
goto err_helper;
+ drm_fbdev_generic_setup(drm_dev, 32);
+
return 0;
err_helper:
diff --git a/drivers/gpu/drm/eswin/es_gem.c b/drivers/gpu/drm/eswin/es_gem.c
index 4898c86d5d87..5406448ee2fb 100644
--- a/drivers/gpu/drm/eswin/es_gem.c
+++ b/drivers/gpu/drm/eswin/es_gem.c
@@ -103,7 +103,7 @@ static int es_gem_alloc_buf(struct es_gem_object *es_obj)
return 0;
}
- es_obj->dma_attrs = DMA_ATTR_WRITE_COMBINE | DMA_ATTR_NO_KERNEL_MAPPING;
+ es_obj->dma_attrs = DMA_ATTR_WRITE_COMBINE;
if (!is_iommu_enabled(dev))
es_obj->dma_attrs |= DMA_ATTR_FORCE_CONTIGUOUS;
@@ -395,6 +395,13 @@ struct sg_table *es_gem_prime_get_sg_table(struct drm_gem_object *obj)
static int es_gem_prime_vmap(struct drm_gem_object *obj,
struct iosys_map *map)
{
+ struct es_gem_object *es_obj = to_es_gem_object(obj);
+
+ void * vaddr = es_obj->dma_attrs & DMA_ATTR_NO_KERNEL_MAPPING ?
+ page_address(es_obj->cookie) : es_obj->cookie;
+
+ iosys_map_set_vaddr(map, vaddr);
+
return 0;
}
--
2.47.0

30
0081-configs-remove-CONFIG_LOCALVERSION_AUTO.patch Normal file
View File

@ -0,0 +1,30 @@
From 6222e119bfc1df0653b52a346fe1a1044a5237c1 Mon Sep 17 00:00:00 2001
From: Han Gao <gaohan@iscas.ac.cn>
Date: Thu, 30 May 2024 20:32:21 +0800
Subject: [PATCH 081/219] configs: remove CONFIG_LOCALVERSION_AUTO
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/configs/win2030_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig
index 5a06fbd7c31b..9234bf09feb9 100644
--- a/arch/riscv/configs/win2030_defconfig
+++ b/arch/riscv/configs/win2030_defconfig
@@ -1,3 +1,4 @@
+# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
@@ -32,7 +33,6 @@ CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
CONFIG_CPUFREQ_DT=y
CONFIG_JUMP_LABEL=y
-# CONFIG_GCC_PLUGINS is not set
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_SPARSEMEM_MANUAL=y
--
2.47.0

33
0082-configs-enable-initrd.patch Normal file
View File

@ -0,0 +1,33 @@
From 894ca038e703ccc0a6ce8989ab969edb8232e32f Mon Sep 17 00:00:00 2001
From: Han Gao <gaohan@iscas.ac.cn>
Date: Thu, 30 May 2024 20:34:08 +0800
Subject: [PATCH 082/219] configs: enable initrd
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/configs/win2030_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig
index 9234bf09feb9..d32dd5f08021 100644
--- a/arch/riscv/configs/win2030_defconfig
+++ b/arch/riscv/configs/win2030_defconfig
@@ -13,6 +13,7 @@ CONFIG_CGROUP_BPF=y
CONFIG_NAMESPACES=y
CONFIG_USER_NS=y
CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
# CONFIG_SYSFS_SYSCALL is not set
CONFIG_PERF_EVENTS=y
@@ -318,7 +319,6 @@ CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_DEV_VIRTIO=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC7=y
-CONFIG_XZ_DEC=y
CONFIG_DMA_CMA=y
CONFIG_PRINTK_TIME=y
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
--
2.47.0

41
0083-configs-enable-amd-gpu-driver.patch Normal file
View File

@ -0,0 +1,41 @@
From e211eeeeb0149889b4d857ddd4fca6dee86c1ddd Mon Sep 17 00:00:00 2001
From: Han Gao <gaohan@iscas.ac.cn>
Date: Thu, 30 May 2024 20:43:13 +0800
Subject: [PATCH 083/219] configs: enable amd gpu driver
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/configs/win2030_defconfig | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig
index d32dd5f08021..60ae1c7268e6 100644
--- a/arch/riscv/configs/win2030_defconfig
+++ b/arch/riscv/configs/win2030_defconfig
@@ -194,9 +194,12 @@ CONFIG_DRM_AMDGPU_CIK=y
CONFIG_DRM_AMDGPU_USERPTR=y
CONFIG_DRM_AMD_ACP=y
CONFIG_DRM_NOUVEAU=y
+CONFIG_DRM_AMD_DC_HDCP=y
+CONFIG_DRM_AMD_DC_SI=y
CONFIG_DRM_DISPLAY_CONNECTOR=y
CONFIG_DRM_SIMPLE_BRIDGE=y
CONFIG_DRM_TOSHIBA_TC358768=m
+CONFIG_DRM_SIMPLEDRM=m
CONFIG_DRM_ESWIN=y
CONFIG_ESWIN_VIRTUAL_DISPLAY=y
CONFIG_ESWIN_MMU=y
@@ -206,6 +209,10 @@ CONFIG_DW_HDMI_CEC=y
CONFIG_DRM_IMG_VOLCANIC=m
CONFIG_DRM_LEGACY=y
CONFIG_FB=y
+CONFIG_FB_RADEON=m
+CONFIG_FB_SIMPLE=m
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_SOC=y
--
2.47.0

26
0084-configs-enable-kvm.patch Normal file
View File

@ -0,0 +1,26 @@
From b10fea4ce89e245352a8ca1f9bb475176f2f4de5 Mon Sep 17 00:00:00 2001
From: Han Gao <gaohan@iscas.ac.cn>
Date: Thu, 30 May 2024 20:44:53 +0800
Subject: [PATCH 084/219] configs: enable kvm
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/configs/win2030_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig
index 60ae1c7268e6..2b7beb5b3495 100644
--- a/arch/riscv/configs/win2030_defconfig
+++ b/arch/riscv/configs/win2030_defconfig
@@ -33,6 +33,8 @@ CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
CONFIG_CPUFREQ_DT=y
+CONFIG_VIRTUALIZATION=y
+CONFIG_KVM=m
CONFIG_JUMP_LABEL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
--
2.47.0

40
0085-configs-enable-hd-audio-pci-support.patch Normal file
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@ -0,0 +1,40 @@
From d565fc073c537c9c5f9e5d8008e7d4231e1629a4 Mon Sep 17 00:00:00 2001
From: Han Gao <gaohan@iscas.ac.cn>
Date: Thu, 30 May 2024 20:48:25 +0800
Subject: [PATCH 085/219] configs: enable hd audio pci support
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/configs/win2030_defconfig | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig
index 2b7beb5b3495..a739278985ab 100644
--- a/arch/riscv/configs/win2030_defconfig
+++ b/arch/riscv/configs/win2030_defconfig
@@ -217,6 +217,11 @@ CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_SOUND=y
CONFIG_SND=y
+CONFIG_SND_HDA_INTEL=m
+CONFIG_SND_HDA_PATCH_LOADER=y
+CONFIG_SND_HDA_CODEC_REALTEK=m
+CONFIG_SND_HDA_CODEC_HDMI=m
+CONFIG_SND_HDA_PREALLOC_SIZE=2048
CONFIG_SND_SOC=y
CONFIG_SND_SOC_SOF_TOPLEVEL=y
CONFIG_SND_SOC_SOF_OF=y
@@ -273,10 +278,8 @@ CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_ESWIN=y
CONFIG_MMC_SDHCI_OF_SDIO_ESWIN=y
-CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
--
2.47.0

360
0086-config-enable-option-for-docker-podman.patch Normal file
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@ -0,0 +1,360 @@
From e281dc983583c8afcffd574eb1c8296ad8e3a0fb Mon Sep 17 00:00:00 2001
From: Han Gao <gaohan@iscas.ac.cn>
Date: Fri, 7 Jun 2024 12:08:13 +0800
Subject: [PATCH 086/219] config: enable option for docker/podman
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/configs/win2030_defconfig | 281 ++++++++++++++++++++++++++-
1 file changed, 280 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig
index a739278985ab..398b6db958bb 100644
--- a/arch/riscv/configs/win2030_defconfig
+++ b/arch/riscv/configs/win2030_defconfig
@@ -1,15 +1,28 @@
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_WATCH_QUEUE=y
+CONFIG_AUDIT=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_BPF_SYSCALL=y
+CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_CGROUPS=y
+CONFIG_MEMCG=y
+CONFIG_BLK_CGROUP=y
CONFIG_CGROUP_SCHED=y
CONFIG_CFS_BANDWIDTH=y
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_RDMA=y
+CONFIG_CGROUP_FREEZER=y
CONFIG_CPUSETS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_PERF=y
CONFIG_CGROUP_BPF=y
+CONFIG_CGROUP_MISC=y
CONFIG_NAMESPACES=y
CONFIG_USER_NS=y
CONFIG_CHECKPOINT_RESTORE=y
@@ -38,17 +51,239 @@ CONFIG_KVM=m
CONFIG_JUMP_LABEL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLK_DEV_THROTTLING=y
CONFIG_SPARSEMEM_MANUAL=y
CONFIG_CMA=y
CONFIG_NET=y
CONFIG_PACKET=y
+CONFIG_PACKET_DIAG=m
CONFIG_UNIX=y
+CONFIG_UNIX_DIAG=m
+CONFIG_TLS=m
+CONFIG_TLS_DEVICE=y
+CONFIG_TLS_TOE=y
+CONFIG_XDP_SOCKETS=y
CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IPV6 is not set
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPVTI=m
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_HSTCP=m
+CONFIG_TCP_CONG_HYBLA=m
+CONFIG_TCP_CONG_NV=m
+CONFIG_TCP_CONG_SCALABLE=m
+CONFIG_TCP_CONG_LP=m
+CONFIG_TCP_CONG_VENO=m
+CONFIG_TCP_CONG_YEAH=m
+CONFIG_TCP_CONG_ILLINOIS=m
+CONFIG_TCP_CONG_DCTCP=m
+CONFIG_TCP_CONG_CDG=m
+CONFIG_TCP_CONG_BBR=y
+CONFIG_DEFAULT_BBR=y
+CONFIG_IPV6=m
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+CONFIG_IPV6_MIP6=m
+CONFIG_IPV6_ILA=m
+CONFIG_IPV6_VTI=m
+CONFIG_IPV6_MROUTE=y
+CONFIG_IPV6_SEG6_LWTUNNEL=y
+CONFIG_IPV6_SEG6_HMAC=y
+CONFIG_IPV6_RPL_LWTUNNEL=y
+CONFIG_IPV6_IOAM6_LWTUNNEL=y
+CONFIG_NETFILTER=y
+CONFIG_BRIDGE_NETFILTER=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_SNMP=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NF_TABLES=m
+CONFIG_NF_TABLES_INET=y
+CONFIG_NF_TABLES_NETDEV=y
+CONFIG_NFT_NUMGEN=m
+CONFIG_NFT_CT=m
+CONFIG_NFT_CONNLIMIT=m
+CONFIG_NFT_LOG=m
+CONFIG_NFT_LIMIT=m
+CONFIG_NFT_MASQ=m
+CONFIG_NFT_REDIR=m
+CONFIG_NFT_NAT=m
+CONFIG_NFT_TUNNEL=m
+CONFIG_NFT_OBJREF=m
+CONFIG_NFT_QUEUE=m
+CONFIG_NFT_QUOTA=m
+CONFIG_NFT_REJECT=m
+CONFIG_NFT_COMPAT=m
+CONFIG_NFT_HASH=m
+CONFIG_NFT_FIB_INET=m
+CONFIG_NFT_XFRM=m
+CONFIG_NFT_SOCKET=m
+CONFIG_NFT_OSF=m
+CONFIG_NFT_TPROXY=m
+CONFIG_NFT_SYNPROXY=m
+CONFIG_NFT_DUP_NETDEV=m
+CONFIG_NFT_FWD_NETDEV=m
+CONFIG_NFT_FIB_NETDEV=m
+CONFIG_NFT_REJECT_NETDEV=m
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_CT=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HMARK=m
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
+CONFIG_NETFILTER_XT_TARGET_LED=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_TEE=m
+CONFIG_NETFILTER_XT_TARGET_TPROXY=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_BPF=m
+CONFIG_NETFILTER_XT_MATCH_CGROUP=m
+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_CPU=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_IPVS=m
+CONFIG_NETFILTER_XT_MATCH_L2TP=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_RECENT=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_SOCKET=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_IP_SET=m
+CONFIG_IP_VS=m
+CONFIG_IP_VS_IPV6=y
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_RR=m
+CONFIG_IP_VS_NFCT=y
+CONFIG_NFT_DUP_IPV4=m
+CONFIG_NFT_FIB_IPV4=m
+CONFIG_NF_TABLES_ARP=y
+CONFIG_NF_LOG_ARP=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_RPFILTER=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_SYNPROXY=m
+CONFIG_IP_NF_NAT=m
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+CONFIG_NFT_DUP_IPV6=m
+CONFIG_NFT_FIB_IPV6=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RPFILTER=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_MATCH_SRH=m
+CONFIG_IP6_NF_TARGET_HL=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_TARGET_SYNPROXY=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_RAW=m
+CONFIG_IP6_NF_NAT=m
+CONFIG_IP6_NF_TARGET_MASQUERADE=m
+CONFIG_IP6_NF_TARGET_NPT=m
+CONFIG_NF_TABLES_BRIDGE=m
+CONFIG_NF_CONNTRACK_BRIDGE=m
+CONFIG_BRIDGE_NF_EBTABLES=m
+CONFIG_BRIDGE_EBT_BROUTE=m
+CONFIG_BRIDGE_EBT_T_FILTER=m
+CONFIG_BRIDGE_EBT_T_NAT=m
+CONFIG_BRIDGE_EBT_802_3=m
+CONFIG_BRIDGE_EBT_AMONG=m
+CONFIG_BRIDGE_EBT_ARP=m
+CONFIG_BRIDGE_EBT_IP=m
+CONFIG_BRIDGE_EBT_IP6=m
+CONFIG_BRIDGE_EBT_LIMIT=m
+CONFIG_BRIDGE_EBT_MARK=m
+CONFIG_BRIDGE_EBT_PKTTYPE=m
+CONFIG_BRIDGE_EBT_STP=m
+CONFIG_BRIDGE_EBT_VLAN=m
+CONFIG_BRIDGE_EBT_ARPREPLY=m
+CONFIG_BRIDGE_EBT_DNAT=m
+CONFIG_BRIDGE_EBT_MARK_T=m
+CONFIG_BRIDGE_EBT_REDIRECT=m
+CONFIG_BRIDGE_EBT_SNAT=m
+CONFIG_BRIDGE_EBT_LOG=m
+CONFIG_BRIDGE_EBT_NFLOG=m
+CONFIG_BPFILTER=y
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_VLAN_FILTERING=y
+CONFIG_BRIDGE_MRP=y
+CONFIG_BRIDGE_CFM=y
+CONFIG_VLAN_8021Q=m
+CONFIG_VLAN_8021Q_GVRP=y
+CONFIG_LLC2=m
CONFIG_NET_SCHED=y
+CONFIG_NET_CLS_CGROUP=m
CONFIG_NET_CLS_ACT=y
CONFIG_CFG80211=y
CONFIG_CFG80211_WEXT=y
@@ -56,6 +291,15 @@ CONFIG_MAC80211=y
CONFIG_RFKILL=y
CONFIG_RFKILL_INPUT=y
CONFIG_RFKILL_GPIO=y
+CONFIG_CGROUP_NET_PRIO=y
+CONFIG_BT=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+CONFIG_MCTP=y
+# CONFIG_WIRELESS is not set
CONFIG_PCI=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCIEAER=y
@@ -82,6 +326,25 @@ CONFIG_ATA=y
CONFIG_SATA_AHCI=y
CONFIG_AHCI_ESWIN=y
CONFIG_NETDEVICES=y
+CONFIG_LOCALVERSION="-win2030"
+CONFIG_BONDING=m
+CONFIG_DUMMY=m
+CONFIG_WIREGUARD=m
+CONFIG_NET_FC=y
+CONFIG_NET_TEAM=m
+CONFIG_NET_TEAM_MODE_BROADCAST=m
+CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
+CONFIG_NET_TEAM_MODE_RANDOM=m
+CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
+CONFIG_NET_TEAM_MODE_LOADBALANCE=m
+CONFIG_MACVLAN=m
+CONFIG_MACVTAP=m
+CONFIG_IPVLAN=m
+CONFIG_IPVTAP=m
+CONFIG_VXLAN=m
+CONFIG_GENEVE=m
+CONFIG_VETH=m
+CONFIG_VIRTIO_NET=m
# CONFIG_NET_VENDOR_ALACRITECH is not set
# CONFIG_NET_VENDOR_AMAZON is not set
# CONFIG_NET_VENDOR_AQUANTIA is not set
@@ -315,6 +578,15 @@ CONFIG_RESET_ESWIN_WIN2030=y
CONFIG_INTERCONNECT=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_BTRFS_FS=m
+CONFIG_BTRFS_FS_POSIX_ACL=y
+CONFIG_FS_ENCRYPTION=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_OVERLAY_FS=m
+CONFIG_OVERLAY_FS_REDIRECT_DIR=y
+CONFIG_OVERLAY_FS_INDEX=y
+CONFIG_OVERLAY_FS_XINO_AUTO=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
@@ -327,7 +599,14 @@ CONFIG_NFS_V4_2=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=m
+CONFIG_CRYPTO_CBC=m
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_XTS is not set
+CONFIG_CRYPTO_HMAC=m
CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_AES=m
CONFIG_CRYPTO_DEV_VIRTIO=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC7=y
--
2.47.0

25
0087-fix-remove-win2030-localversion.patch Normal file
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@ -0,0 +1,25 @@
From a21b486aee49da789f5375f9cc65127f4ba88d65 Mon Sep 17 00:00:00 2001
From: Han Gao <gaohan@iscas.ac.cn>
Date: Thu, 13 Jun 2024 22:21:56 +0800
Subject: [PATCH 087/219] fix: remove win2030 localversion
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/configs/win2030_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig
index 398b6db958bb..f0c03fda4b3b 100644
--- a/arch/riscv/configs/win2030_defconfig
+++ b/arch/riscv/configs/win2030_defconfig
@@ -326,7 +326,6 @@ CONFIG_ATA=y
CONFIG_SATA_AHCI=y
CONFIG_AHCI_ESWIN=y
CONFIG_NETDEVICES=y
-CONFIG_LOCALVERSION="-win2030"
CONFIG_BONDING=m
CONFIG_DUMMY=m
CONFIG_WIREGUARD=m
--
2.47.0

25
0088-fix-disable-CONFIG_ESWIN_VIRTUAL_DISPLAY.patch Normal file
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@ -0,0 +1,25 @@
From 7267101e0a25cda58a6e959df3658cb66343d76f Mon Sep 17 00:00:00 2001
From: Han Gao <gaohan@iscas.ac.cn>
Date: Thu, 13 Jun 2024 23:08:12 +0800
Subject: [PATCH 088/219] fix: disable CONFIG_ESWIN_VIRTUAL_DISPLAY
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/configs/win2030_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig
index f0c03fda4b3b..9a186bcd4be7 100644
--- a/arch/riscv/configs/win2030_defconfig
+++ b/arch/riscv/configs/win2030_defconfig
@@ -465,7 +465,6 @@ CONFIG_DRM_SIMPLE_BRIDGE=y
CONFIG_DRM_TOSHIBA_TC358768=m
CONFIG_DRM_SIMPLEDRM=m
CONFIG_DRM_ESWIN=y
-CONFIG_ESWIN_VIRTUAL_DISPLAY=y
CONFIG_ESWIN_MMU=y
CONFIG_ESWIN_DW_HDMI=y
CONFIG_DW_HDMI_I2S_AUDIO=y
--
2.47.0

25
0089-configs-enable-CONFIG_BINFMT_MISC.patch Normal file
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@ -0,0 +1,25 @@
From 0288bf7209ed555fc9f27fd463b1a835da61cd49 Mon Sep 17 00:00:00 2001
From: Han Gao <gaohan@iscas.ac.cn>
Date: Fri, 14 Jun 2024 13:05:45 +0800
Subject: [PATCH 089/219] configs: enable CONFIG_BINFMT_MISC
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/configs/win2030_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig
index 9a186bcd4be7..78c1df17d734 100644
--- a/arch/riscv/configs/win2030_defconfig
+++ b/arch/riscv/configs/win2030_defconfig
@@ -53,6 +53,7 @@ CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_BLK_DEV_THROTTLING=y
+CONFIG_BINFMT_MISC=m
CONFIG_SPARSEMEM_MANUAL=y
CONFIG_CMA=y
CONFIG_NET=y
--
2.47.0

25
0090-configs-enable-CONFIG_DEBUG_FS.patch Normal file
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@ -0,0 +1,25 @@
From 4d1522230b4b6e77f0d4653680acf9ddab9e6834 Mon Sep 17 00:00:00 2001
From: Han Gao <gaohan@iscas.ac.cn>
Date: Fri, 14 Jun 2024 16:42:44 +0800
Subject: [PATCH 090/219] configs: enable CONFIG_DEBUG_FS
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/configs/win2030_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig
index 78c1df17d734..9854a9a16996 100644
--- a/arch/riscv/configs/win2030_defconfig
+++ b/arch/riscv/configs/win2030_defconfig
@@ -615,6 +615,7 @@ CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
CONFIG_CONSOLE_LOGLEVEL_QUIET=15
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_FS=y
CONFIG_DEBUG_PAGEALLOC=y
CONFIG_SCHED_STACK_END_CHECK=y
CONFIG_DEBUG_VM=y
--
2.47.0

173
0091-configs-enable-MEDIA_USB_SUPPORT-MEDIA_PCI_SUPPORT.patch Normal file
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@ -0,0 +1,173 @@
From 79808c07ecb9782b6904d0886e9a40b4e9c0b07f Mon Sep 17 00:00:00 2001
From: Han Gao <gaohan@iscas.ac.cn>
Date: Fri, 28 Jun 2024 17:27:25 +0800
Subject: [PATCH 091/219] configs: enable MEDIA_USB_SUPPORT & MEDIA_PCI_SUPPORT
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
---
arch/riscv/configs/win2030_defconfig | 146 ++++++++++++++++++++++++++-
1 file changed, 145 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig
index 9854a9a16996..c30b74940c05 100644
--- a/arch/riscv/configs/win2030_defconfig
+++ b/arch/riscv/configs/win2030_defconfig
@@ -444,9 +444,153 @@ CONFIG_WATCHDOG=y
CONFIG_DW_WATCHDOG=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_MPQ8785=y
-# CONFIG_MEDIA_CEC_SUPPORT is not set
+CONFIG_REGULATOR_PCA9450=y
CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_SUPPORT_FILTER=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
+CONFIG_MEDIA_RADIO_SUPPORT=y
+CONFIG_MEDIA_SDR_SUPPORT=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_PWC=m
+CONFIG_MEDIA_PCI_SUPPORT=y
CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_CXD2880_SPI_DRV=m
+CONFIG_MEDIA_TUNER_TDA18250=m
+CONFIG_MEDIA_TUNER_MSI001=m
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2063=m
+CONFIG_MEDIA_TUNER_MT2266=m
+CONFIG_MEDIA_TUNER_MT2131=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_MXL5005S=m
+CONFIG_MEDIA_TUNER_MXL5007T=m
+CONFIG_MEDIA_TUNER_MAX2165=m
+CONFIG_MEDIA_TUNER_TDA18218=m
+CONFIG_MEDIA_TUNER_FC0011=m
+CONFIG_MEDIA_TUNER_FC0012=m
+CONFIG_MEDIA_TUNER_FC0013=m
+CONFIG_MEDIA_TUNER_TDA18212=m
+CONFIG_MEDIA_TUNER_E4000=m
+CONFIG_MEDIA_TUNER_FC2580=m
+CONFIG_MEDIA_TUNER_M88RS6000T=m
+CONFIG_MEDIA_TUNER_TUA9001=m
+CONFIG_MEDIA_TUNER_SI2157=m
+CONFIG_MEDIA_TUNER_IT913X=m
+CONFIG_MEDIA_TUNER_R820T=m
+CONFIG_MEDIA_TUNER_MXL301RF=m
+CONFIG_MEDIA_TUNER_QM1D1C0042=m
+CONFIG_MEDIA_TUNER_QM1D1B0004=m
+CONFIG_DVB_STB0899=m
+CONFIG_DVB_STB6100=m
+CONFIG_DVB_STV090x=m
+CONFIG_DVB_STV0910=m
+CONFIG_DVB_STV6110x=m
+CONFIG_DVB_STV6111=m
+CONFIG_DVB_MXL5XX=m
+CONFIG_DVB_DRXK=m
+CONFIG_DVB_TDA18271C2DD=m
+CONFIG_DVB_SI2165=m
+CONFIG_DVB_MN88472=m
+CONFIG_DVB_MN88473=m
+CONFIG_DVB_CX24110=m
+CONFIG_DVB_CX24123=m
+CONFIG_DVB_MT312=m
+CONFIG_DVB_ZL10036=m
+CONFIG_DVB_ZL10039=m
+CONFIG_DVB_S5H1420=m
+CONFIG_DVB_STV0288=m
+CONFIG_DVB_STB6000=m
+CONFIG_DVB_STV0299=m
+CONFIG_DVB_STV6110=m
+CONFIG_DVB_STV0900=m
+CONFIG_DVB_TDA8083=m
+CONFIG_DVB_TDA10086=m
+CONFIG_DVB_TDA8261=m
+CONFIG_DVB_VES1X93=m
+CONFIG_DVB_TUNER_ITD1000=m
+CONFIG_DVB_TUNER_CX24113=m
+CONFIG_DVB_TDA826X=m
+CONFIG_DVB_TUA6100=m
+CONFIG_DVB_CX24116=m
+CONFIG_DVB_CX24117=m
+CONFIG_DVB_CX24120=m
+CONFIG_DVB_SI21XX=m
+CONFIG_DVB_TS2020=m
+CONFIG_DVB_DS3000=m
+CONFIG_DVB_MB86A16=m
+CONFIG_DVB_TDA10071=m
+CONFIG_DVB_SP887X=m
+CONFIG_DVB_CX22700=m
+CONFIG_DVB_CX22702=m
+CONFIG_DVB_S5H1432=m
+CONFIG_DVB_DRXD=m
+CONFIG_DVB_L64781=m
+CONFIG_DVB_TDA1004X=m
+CONFIG_DVB_NXT6000=m
+CONFIG_DVB_MT352=m
+CONFIG_DVB_ZL10353=m
+CONFIG_DVB_DIB3000MB=m
+CONFIG_DVB_DIB3000MC=m
+CONFIG_DVB_DIB7000M=m
+CONFIG_DVB_DIB7000P=m
+CONFIG_DVB_DIB9000=m
+CONFIG_DVB_TDA10048=m
+CONFIG_DVB_EC100=m
+CONFIG_DVB_STV0367=m
+CONFIG_DVB_CXD2820R=m
+CONFIG_DVB_CXD2841ER=m
+CONFIG_DVB_ZD1301_DEMOD=m
+CONFIG_DVB_CXD2880=m
+CONFIG_DVB_VES1820=m
+CONFIG_DVB_TDA10021=m
+CONFIG_DVB_TDA10023=m
+CONFIG_DVB_STV0297=m
+CONFIG_DVB_NXT200X=m
+CONFIG_DVB_OR51211=m
+CONFIG_DVB_OR51132=m
+CONFIG_DVB_BCM3510=m
+CONFIG_DVB_LGDT330X=m
+CONFIG_DVB_LGDT3305=m
+CONFIG_DVB_LG2160=m
+CONFIG_DVB_S5H1409=m
+CONFIG_DVB_AU8522_DTV=m
+CONFIG_DVB_AU8522_V4L=m
+CONFIG_DVB_S5H1411=m
+CONFIG_DVB_MXL692=m
+CONFIG_DVB_S921=m
+CONFIG_DVB_DIB8000=m
+CONFIG_DVB_MB86A20S=m
+CONFIG_DVB_TC90522=m
+CONFIG_DVB_MN88443X=m
+CONFIG_DVB_PLL=m
+CONFIG_DVB_TUNER_DIB0070=m
+CONFIG_DVB_TUNER_DIB0090=m
+CONFIG_DVB_DRX39XYJ=m
+CONFIG_DVB_LNBH25=m
+CONFIG_DVB_LNBH29=m
+CONFIG_DVB_LNBP21=m
+CONFIG_DVB_LNBP22=m
+CONFIG_DVB_ISL6405=m
+CONFIG_DVB_ISL6421=m
+CONFIG_DVB_ISL6423=m
+CONFIG_DVB_A8293=m
+CONFIG_DVB_LGS8GL5=m
+CONFIG_DVB_LGS8GXX=m
+CONFIG_DVB_ATBM8830=m
+CONFIG_DVB_TDA665x=m
+CONFIG_DVB_IX2505V=m
+CONFIG_DVB_M88RS2000=m
+CONFIG_DVB_AF9033=m
+CONFIG_DVB_HORUS3A=m
+CONFIG_DVB_ASCOT2E=m
+CONFIG_DVB_HELENE=m
+CONFIG_DVB_CXD2099=m
+CONFIG_DVB_SP2=m
CONFIG_VIDEO_XILINX=y
# CONFIG_DRM=y
# CONFIG_DRM_I2C_CH7006 is not set
--
2.47.0

80
0092-fix-eswin-load-kvm-module-failed.patch Normal file
View File

@ -0,0 +1,80 @@
From 58d07ca01dc6452536d593a4e7f8d8a16094ee8f Mon Sep 17 00:00:00 2001
From: Han Gao <gaohan@iscas.ac.cn>
Date: Mon, 15 Jul 2024 23:51:22 +0800
Subject: [PATCH 092/219] fix: eswin: load kvm module failed
riscv_noncoherent_supported should not be called multiple times
in the sifive_errata_probe function
[ 72.659708] Unable to handle kernel paging request at virtual address ffffffff81389380
[ 72.667661] Oops [#1]
[ 72.669934] Modules linked in: es_iommu_rsv es_dev_dma_buf es_vdec es_rsvmem_heap es_buddy_driver nfnetlink ip_tables x_tables sha1_generic hmac ipv6 pvrsrvkm
[ 72.684133] CPU: 0 PID: 696 Comm: modprobe Not tainted 6.6.36-win2030 #10
[ 72.690922] Hardware name: ESWIN EIC7700 (DT)
[ 72.695277] epc : riscv_noncoherent_supported+0x10/0x3e
[ 72.700507] ra : sifive_errata_patch_func+0x44/0x1e2
[ 72.705560] epc : ffffffff8000bff6 ra : ffffffff8000c4da sp : ffff8f8008273ac0
[ 72.712781] gp : ffffffff81948e40 tp : ffffaf80b1115400 t0 : 0000000000000000
[ 72.720001] t1 : 0000000000000000 t2 : 0000000000000002 s0 : ffff8f8008273b30
[ 72.727221] s1 : ffffffff01d5e388 a0 : ffffffff01d5e388 a1 : ffffffff01d5e3c8
[ 72.734441] a2 : 8000000000000008 a3 : 0000000006220425 a4 : ffffffff81388ff2
[ 72.741661] a5 : 0000000000000001 a6 : 0000000000000006 a7 : 0000000000000010
[ 72.748881] s2 : ffffffff01d5e3c8 s3 : 8000000000000008 s4 : 0000000000000001
[ 72.756101] s5 : 0000000006220425 s6 : ffffffff8180f660 s7 : 0000000000000001
[ 72.763321] s8 : ffff8f8008273d58 s9 : ffffffff01dcb8c0 s10: ffffffff01dcb758
[ 72.770542] s11: 0000000000000000 t3 : ffffffffffffffff t4 : ffffffffffffffff
[ 72.777761] t5 : ffffffffffffffff t6 : ffffaf82a5ecc1c8
[ 72.783071] status: 0000000200000120 badaddr: ffffffff81389380 cause: 000000000000000f
[ 72.790986] [<ffffffff8000bff6>] riscv_noncoherent_supported+0x10/0x3e
[ 72.797514] [<ffffffff800027f6>] _apply_alternatives+0x84/0x86
[ 72.803348] [<ffffffff800029cc>] apply_module_alternatives+0x10/0x18
[ 72.809701] [<ffffffff80007c8c>] module_finalize+0x5e/0x74
[ 72.815193] [<ffffffff80083b54>] load_module+0x1110/0x18b4
[ 72.820682] [<ffffffff80084496>] init_module_from_file+0x76/0xaa
[ 72.826688] [<ffffffff800846e4>] __riscv_sys_finit_module+0x1e2/0x2a8
[ 72.833129] [<ffffffff80a9ccbc>] do_trap_ecall_u+0xbe/0x130
[ 72.838703] [<ffffffff80aa51f8>] ret_from_exception+0x0/0x64
[ 72.844376] Code: 0009 b7ed e797 0193 a783 12e7 c799 4785 d717 0137 (0723) 38f7
[ 72.851970] ---[ end trace 0000000000000000 ]---
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
---
arch/riscv/errata/sifive/errata.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive/errata.c
index 20dcbd9e76f4..57fac9c2ccba 100644
--- a/arch/riscv/errata/sifive/errata.c
+++ b/arch/riscv/errata/sifive/errata.c
@@ -63,12 +63,6 @@ static u32 __init_or_module sifive_errata_probe(unsigned long archid,
int idx;
u32 cpu_req_errata = 0;
-#if IS_ENABLED(CONFIG_ARCH_ESWIN_EIC770X_SOC_FAMILY)
- /* Set this just to make core cbo code happy */
- riscv_cbom_block_size = 1;
- riscv_noncoherent_supported();
-#endif
-
for (idx = 0; idx < ERRATA_SIFIVE_NUMBER; idx++)
if (errata_list[idx].check_func(archid, impid))
cpu_req_errata |= (1U << idx);
@@ -101,6 +95,14 @@ void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
return;
+#if IS_ENABLED(CONFIG_ARCH_ESWIN_EIC770X_SOC_FAMILY)
+ /* Set this just to make core cbo code happy */
+ if (stage == RISCV_ALTERNATIVES_BOOT) {
+ riscv_cbom_block_size = 1;
+ riscv_noncoherent_supported();
+ }
+#endif
+
cpu_req_errata = sifive_errata_probe(archid, impid);
for (alt = begin; alt < end; alt++) {
--
2.47.0

60
0093-Revert-add-envcfgh-for-kvm.patch Normal file
View File

@ -0,0 +1,60 @@
From 462eefc9102eadf01b481000c979c4f2b1a5eff0 Mon Sep 17 00:00:00 2001
From: Han Gao <gaohan@iscas.ac.cn>
Date: Tue, 16 Jul 2024 11:58:36 +0800
Subject: [PATCH 093/219] Revert: add envcfgh for kvm
Revert commitid: 6bb2e00ea304ffc0446f345c46fe22713ce43cbf
EIC770X is not support it.
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
---
arch/riscv/kvm/vcpu.c | 24 ------------------------
1 file changed, 24 deletions(-)
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 82229db1ce73..960ff0f5b477 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -471,28 +471,6 @@ int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
return -EINVAL;
}
-static void kvm_riscv_vcpu_update_config(const unsigned long *isa)
-{
- u64 henvcfg = 0;
-
- if (riscv_isa_extension_available(isa, SVPBMT))
- henvcfg |= ENVCFG_PBMTE;
-
- if (riscv_isa_extension_available(isa, SSTC))
- henvcfg |= ENVCFG_STCE;
-
- if (riscv_isa_extension_available(isa, ZICBOM))
- henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE);
-
- if (riscv_isa_extension_available(isa, ZICBOZ))
- henvcfg |= ENVCFG_CBZE;
-
- csr_write(CSR_HENVCFG, henvcfg);
-#ifdef CONFIG_32BIT
- csr_write(CSR_HENVCFGH, henvcfg >> 32);
-#endif
-}
-
void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
{
struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
@@ -507,8 +485,6 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
csr_write(CSR_HVIP, csr->hvip);
csr_write(CSR_VSATP, csr->vsatp);
- kvm_riscv_vcpu_update_config(vcpu->arch.isa);
-
kvm_riscv_gstage_update_hgatp(vcpu);
kvm_riscv_vcpu_timer_restore(vcpu);
--
2.47.0

106
0094-config-enable-some-options-for-the-distribution.patch Normal file
View File

@ -0,0 +1,106 @@
From 34bc15142a72ec360ae62888e9f7cf0268bcbd83 Mon Sep 17 00:00:00 2001
From: Han Gao <gaohan@iscas.ac.cn>
Date: Mon, 22 Jul 2024 17:32:51 +0800
Subject: [PATCH 094/219] config: enable some options for the distribution
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
---
arch/riscv/configs/win2030_defconfig | 42 +++++++++++++++++++++++++++-
1 file changed, 41 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig
index c30b74940c05..c9ffac16a286 100644
--- a/arch/riscv/configs/win2030_defconfig
+++ b/arch/riscv/configs/win2030_defconfig
@@ -2,7 +2,7 @@
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_WATCH_QUEUE=y
-CONFIG_AUDIT=y
+CONFIG_AUDIT=m
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_BPF_SYSCALL=y
@@ -292,6 +292,7 @@ CONFIG_MAC80211=y
CONFIG_RFKILL=y
CONFIG_RFKILL_INPUT=y
CONFIG_RFKILL_GPIO=y
+CONFIG_NETLINK_DIAG=m
CONFIG_CGROUP_NET_PRIO=y
CONFIG_BT=m
CONFIG_BT_RFCOMM=m
@@ -323,9 +324,27 @@ CONFIG_EEPROM_AT24=y
CONFIG_BLK_DEV_SD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_SCSI_DH=y
+CONFIG_SCSI_DH_RDAC=m
+CONFIG_SCSI_DH_EMC=m
CONFIG_ATA=y
CONFIG_SATA_AHCI=y
CONFIG_AHCI_ESWIN=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_DM=m
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_THIN_PROVISIONING=m
+CONFIG_DM_WRITECACHE=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_RAID=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_MULTIPATH_QL=m
+CONFIG_DM_MULTIPATH_ST=m
+CONFIG_DM_MULTIPATH_HST=m
+CONFIG_DM_MULTIPATH_IOA=m
+CONFIG_DM_DELAY=m
+CONFIG_DM_VERITY=m
CONFIG_NETDEVICES=y
CONFIG_BONDING=m
CONFIG_DUMMY=m
@@ -726,14 +745,29 @@ CONFIG_BTRFS_FS=m
CONFIG_BTRFS_FS_POSIX_ACL=y
CONFIG_FS_ENCRYPTION=y
CONFIG_AUTOFS4_FS=y
+CONFIG_FANOTIFY=y
CONFIG_OVERLAY_FS=m
CONFIG_OVERLAY_FS_REDIRECT_DIR=y
CONFIG_OVERLAY_FS_INDEX=y
CONFIG_OVERLAY_FS_XINO_AUTO=y
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
+CONFIG_EXFAT_FS=m
+CONFIG_NTFS_FS=m
+CONFIG_NTFS_RW=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_SQUASHFS=m
+CONFIG_SQUASHFS_FILE_DIRECT=y
+CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU=y
+CONFIG_SQUASHFS_XATTR=y
+CONFIG_SQUASHFS_LZ4=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_SQUASHFS_ZSTD=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
@@ -742,6 +776,12 @@ CONFIG_NFS_V4_2=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=m
+CONFIG_SECURITY=y
+CONFIG_SECURITY_SELINUX=y
+CONFIG_SECURITY_SELINUX_BOOTPARAM=y
+CONFIG_SECURITY_APPARMOR=y
+CONFIG_DEFAULT_SECURITY_APPARMOR=y
+CONFIG_LSM="landlock,lockdown,yama,integrity,apparmor"
CONFIG_CRYPTO_CBC=m
# CONFIG_CRYPTO_CTS is not set
CONFIG_CRYPTO_ECB=m
--
2.47.0

29
0095-perf-dw-axi-dmac-print.patch Normal file
View File

@ -0,0 +1,29 @@
From 197589f0fc57298f76fb4eafeb0254c6fd7881f4 Mon Sep 17 00:00:00 2001
From: xuxiang <xuxiang@eswincomputing.com>
Date: Fri, 12 Jul 2024 16:12:45 +0800
Subject: [PATCH 095/219] perf:dw-axi-dmac print
Changelogs:
1. Change source code : dev_err(chip->dev, "apb_regs not initialized\n"); to dev_dbg(...);
Signed-off-by: xuxiang <xuxiang@eswincomputing.com>
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 54c1396d974b..cddc9a612ee3 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -550,7 +550,7 @@ static void dw_axi_dma_set_hw_channel(struct axi_dma_chan *chan, bool set)
unsigned long reg_value, val;
if (!chip->apb_regs) {
- dev_err(chip->dev, "apb_regs not initialized\n");
+ dev_dbg(chip->dev, "apb_regs not initialized\n");
return;
}
--
2.47.0

329
0096-fix-bootspi-support-power-managemnt.patch Normal file
View File

@ -0,0 +1,329 @@
From e261a906662d58a1efc32088812273ba55cd2fc2 Mon Sep 17 00:00:00 2001
From: huangyifeng <huangyifeng@eswincomputing.com>
Date: Thu, 4 Jul 2024 17:28:16 +0800
Subject: [PATCH 096/219] fix:bootspi support power managemnt
Changelogs:
1.bootspi driver support power managemnt
2.enable power debug sysfs
Signed-off-by: huangyifeng <huangyifeng@eswincomputing.com>
---
arch/riscv/configs/win2030_defconfig | 2 +
drivers/mailbox/eswin-mailbox.c | 8 +-
drivers/spi/spi-eswin-bootspi.c | 172 ++++++++++++++++++++-------
3 files changed, 137 insertions(+), 45 deletions(-)
diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig
index c9ffac16a286..e7c3b818c598 100644
--- a/arch/riscv/configs/win2030_defconfig
+++ b/arch/riscv/configs/win2030_defconfig
@@ -37,6 +37,8 @@ CONFIG_RISCV_SBI_V01=y
# CONFIG_RISCV_BOOT_SPINWAIT is not set
CONFIG_CMDLINE="earlycon=sbi console=tty1 console=ttyS0,115200n8 clk_ignore_unused cma_pernuma=0x2000000 disable_bypass=false no_console_suspend"
CONFIG_CMDLINE_EXTEND=y
+CONFIG_PM_DEBUG=y
+CONFIG_PM_ADVANCED_DEBUG=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
diff --git a/drivers/mailbox/eswin-mailbox.c b/drivers/mailbox/eswin-mailbox.c
index 6a2c40e4d45e..6727882ee682 100755
--- a/drivers/mailbox/eswin-mailbox.c
+++ b/drivers/mailbox/eswin-mailbox.c
@@ -527,7 +527,7 @@ static int eswin_mbox_remove(struct platform_device *pdev)
return 0;
}
-static int eswin_mbox_suspend(struct device *dev)
+__maybe_unused static int eswin_mbox_suspend(struct device *dev)
{
if (!pm_runtime_status_suspended(dev)) {
return eswin_mbox_prepare_clk(dev, false);
@@ -535,7 +535,7 @@ static int eswin_mbox_suspend(struct device *dev)
return 0;
}
-static int eswin_mbox_resume(struct device *dev)
+__maybe_unused static int eswin_mbox_resume(struct device *dev)
{
if (!pm_runtime_status_suspended(dev)) {
eswin_mbox_prepare_clk(dev, true);
@@ -545,12 +545,12 @@ static int eswin_mbox_resume(struct device *dev)
return 0;
}
-static int eswin_mbox_runtime_suspend(struct device *dev)
+__maybe_unused static int eswin_mbox_runtime_suspend(struct device *dev)
{
return eswin_mbox_prepare_clk(dev, false);
}
-static int eswin_mbox_runtime_resume(struct device *dev)
+__maybe_unused static int eswin_mbox_runtime_resume(struct device *dev)
{
return eswin_mbox_prepare_clk(dev, true);
}
diff --git a/drivers/spi/spi-eswin-bootspi.c b/drivers/spi/spi-eswin-bootspi.c
index 1205ce3941ae..9d3447538e38 100644
--- a/drivers/spi/spi-eswin-bootspi.c
+++ b/drivers/spi/spi-eswin-bootspi.c
@@ -23,7 +23,6 @@
#include <linux/clk.h>
#include <linux/reset.h>
#include <linux/bitfield.h>
-#include <linux/interrupt.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
@@ -34,6 +33,7 @@
#include <linux/mtd/spi-nor.h>
#include <linux/sysfs.h>
#include <linux/kobject.h>
+#include <linux/pm_runtime.h>
/* Register offsets */
#define ES_SPI_CSR_00 0x00 /*WRITE_STATUS_REG_TIME*/
@@ -645,26 +645,6 @@ static const struct spi_controller_mem_ops eswin_bootspi_mem_ops = {
static int eswin_bootspi_setup(struct spi_device *spi)
{
struct es_spi_priv *priv = spi_master_get_devdata(spi->master);
- struct device *dev = priv->dev;
- int ret;
-
- ret = clk_prepare_enable(priv->cfg_clk);
- if (ret) {
- dev_err(dev, "could not enable cfg clock: %d\n", ret);
- goto err_cfg_clk;
- }
-
- ret = clk_prepare_enable(priv->clk);
- if (ret) {
- dev_err(dev, "could not enable clock: %d\n", ret);
- goto err_clk;
- }
- /* set rate to 50M*/
- ret = clk_set_rate(priv->clk, 50000000);
- if (ret) {
- dev_err(dev, "could not enable clock: %d\n", ret);
- goto err_clk;
- }
reset_control_deassert(priv->rstc);
/*
@@ -681,12 +661,7 @@ static int eswin_bootspi_setup(struct spi_device *spi)
#endif
/* Basic HW init */
eswin_bootspi_write(priv, ES_SPI_CSR_08, 0x0);
- return ret;
-
-err_clk:
- clk_disable(priv->cfg_clk);
-err_cfg_clk:
- return ret;
+ return 0;
}
static int eswin_bootspi_probe(struct platform_device *pdev)
@@ -696,7 +671,7 @@ static int eswin_bootspi_probe(struct platform_device *pdev)
int ret = 0;
struct device *dev = &pdev->dev;
- master = spi_alloc_master(&pdev->dev, sizeof(*priv));
+ master = devm_spi_alloc_master(&pdev->dev, sizeof(*priv));
if (!master)
return -ENOMEM;
@@ -708,6 +683,7 @@ static int eswin_bootspi_probe(struct platform_device *pdev)
SPI_BPW_MASK(8);
master->mem_ops = &eswin_bootspi_mem_ops;
master->num_chipselect = 1;
+ master->auto_runtime_pm = true;
priv = spi_master_get_devdata(master);
priv->master = master;
@@ -734,11 +710,9 @@ static int eswin_bootspi_probe(struct platform_device *pdev)
priv->cfg_clk = devm_clk_get(dev, "cfg_clk");
if (IS_ERR(priv->cfg_clk)) {
- dev_err(dev, "%s %d:could not get cfg clk: %ld\n", __func__,__LINE__,
- PTR_ERR(priv->cfg_clk));
+ dev_err(dev, "%s %d:could not get cfg clk: %ld\n", __func__,__LINE__, PTR_ERR(priv->cfg_clk));
return PTR_ERR(priv->cfg_clk);
}
-
priv->clk = devm_clk_get(dev, "clk");
if (IS_ERR(priv->clk)) {
dev_err(dev, "%s %d:could not get clk: %ld\n",__func__,__LINE__, PTR_ERR(priv->rstc));
@@ -773,35 +747,150 @@ static int eswin_bootspi_probe(struct platform_device *pdev)
if (!priv->fifo_len) {
priv->fifo_len = 256;
}
- ret = devm_spi_register_controller(dev, master);
- if (ret)
- goto err_put_master;
-
// Create sysfs node
ret = device_create_file(&pdev->dev, &dev_attr_wp_enable);
if (ret) {
- dev_err(&pdev->dev, "Failed to create wp_enable attribute\n");
- goto err_put_master;
+ dev_err(&pdev->dev, "Failed to create wp_enable attribute ret %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(priv->cfg_clk);
+ if (ret) {
+ dev_err(dev, "could not enable cfg clock: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(priv->clk);
+ if (ret) {
+ dev_err(dev, "could not enable clock: %d\n", ret);
+ goto out_cfg_clk;
+ }
+
+ /* set rate to 50M*/
+ ret = clk_set_rate(priv->clk, 50000000);
+ if (ret) {
+ dev_err(dev, "could not enable clock: %d\n", ret);
+ goto out_clk;
}
+ pm_runtime_set_autosuspend_delay(dev, 2000);
+ pm_runtime_use_autosuspend(dev);
+ pm_runtime_get_noresume(dev);
+ pm_runtime_set_active(dev);
+ pm_runtime_enable(dev);
+
+ ret = devm_spi_register_controller(dev, master);
+ if (ret)
+ goto out_register_controller;
+
+ pm_runtime_mark_last_busy(dev);
+ pm_runtime_put_autosuspend(dev);
+
dev_info(&pdev->dev, "ssi_max_xfer_size %d, fifo_len %d, %s mode.\n",
- priv->max_xfer, priv->fifo_len, priv->irq ? "irq" : "polling");
+ priv->max_xfer, priv->fifo_len, priv->irq ? "irq" : "polling");
return 0;
-err_put_master:
- spi_master_put(master);
+out_register_controller:
+ pm_runtime_dont_use_autosuspend(dev);
+ pm_runtime_set_suspended(dev);
+ pm_runtime_disable(dev);
+out_clk:
+ clk_disable_unprepare(priv->clk);
+out_cfg_clk:
+ clk_disable_unprepare(priv->cfg_clk);
return ret;
}
static int eswin_bootspi_remove(struct platform_device *pdev)
{
struct es_spi_priv *priv = platform_get_drvdata(pdev);
+
+ pm_runtime_dont_use_autosuspend(&pdev->dev);
+ pm_runtime_set_suspended(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+ clk_disable_unprepare(priv->cfg_clk);
+ clk_disable_unprepare(priv->clk);
+ return 0;
+}
+
+static int __maybe_unused eswin_bootspi_runtime_resume(struct device *dev)
+{
+ struct es_spi_priv *priv = dev_get_drvdata(dev);
+ int ret;
+
+ ret = clk_prepare_enable(priv->cfg_clk);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(priv->clk);
+ if (ret) {
+ clk_disable_unprepare(priv->cfg_clk);
+ return ret;
+ }
+ return 0;
+}
+
+static int __maybe_unused eswin_bootspi_runtime_suspend(struct device *dev)
+{
+ struct es_spi_priv *priv = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(priv->clk);
+ clk_disable_unprepare(priv->cfg_clk);
+ return 0;
+}
+
+static int __maybe_unused eswin_bootspi_suspend(struct device *dev)
+{
+
+ int ret;
+ struct es_spi_priv *priv = dev_get_drvdata(dev);
struct spi_controller *master = priv->master;
- spi_master_put(master);
+ ret = spi_master_suspend(master);
+ if (ret)
+ return ret;
+
+ if (!pm_runtime_suspended(dev)) {
+ clk_disable_unprepare(priv->clk);
+ clk_disable_unprepare(priv->cfg_clk);
+ }
return 0;
}
+static int __maybe_unused eswin_bootspi_resume(struct device *dev)
+{
+ int ret;
+ struct es_spi_priv *priv = dev_get_drvdata(dev);
+ struct spi_controller *master = priv->master;
+
+ if (!pm_runtime_suspended(dev)) {
+ ret = clk_prepare_enable(priv->cfg_clk);
+ if (ret < 0) {
+ dev_err(dev, "failed to enable cfg_clk (%d)\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(priv->clk);
+ if (ret < 0) {
+ dev_err(dev, "failed to enable clk (%d)\n", ret);
+ clk_disable_unprepare(priv->cfg_clk);
+ return ret;
+ }
+ }
+ ret = spi_master_resume(master);
+ if (ret < 0) {
+ clk_disable_unprepare(priv->cfg_clk);
+ clk_disable_unprepare(priv->cfg_clk);
+ }
+ return ret;
+}
+
+static const struct dev_pm_ops eswin_bootspi_pm = {
+ SET_RUNTIME_PM_OPS(eswin_bootspi_runtime_suspend,
+ eswin_bootspi_runtime_resume, NULL)
+ SET_SYSTEM_SLEEP_PM_OPS(eswin_bootspi_suspend, eswin_bootspi_resume)
+};
+
static const struct of_device_id eswin_bootspi_of_match[] = {
{ .compatible = "eswin,bootspi", .data = NULL},
{ /* end of table */}
@@ -825,6 +914,7 @@ static struct platform_driver eswin_bootspi_driver = {
#ifdef CONFIG_ACPI
.acpi_match_table = eswin_bootspi_acpi_match,
#endif
+ .pm = &eswin_bootspi_pm,
},
};
module_platform_driver(eswin_bootspi_driver);
--
2.47.0

29
0097-chore-change-CONFIG_DMATEST-m.patch Normal file
View File

@ -0,0 +1,29 @@
From 50391d384720f7649d09051166a5a1c93051aa06 Mon Sep 17 00:00:00 2001
From: xuxiang <xuxiang@eswincomputing.com>
Date: Mon, 15 Jul 2024 11:12:23 +0800
Subject: [PATCH 097/219] chore:change CONFIG_DMATEST=m
Changelogs:
1. CONFIG_DMATEST change to m
Signed-off-by: xuxiang <xuxiang@eswincomputing.com>
---
arch/riscv/configs/win2030_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/configs/win2030_defconfig b/arch/riscv/configs/win2030_defconfig
index e7c3b818c598..370b8dbe4a2e 100644
--- a/arch/riscv/configs/win2030_defconfig
+++ b/arch/riscv/configs/win2030_defconfig
@@ -719,7 +719,7 @@ CONFIG_RTC_DRV_PCF8563=y
CONFIG_RTC_DRV_ESWIN=y
CONFIG_DMADEVICES=y
CONFIG_DW_AXI_DMAC=y
-CONFIG_DMATEST=y
+CONFIG_DMATEST=m
CONFIG_DMABUF_HEAPS=y
CONFIG_DMABUF_HEAPS_SYSTEM=y
CONFIG_DMABUF_HEAPS_CMA=y
--
2.47.0

130
0098-feat-eth-ETH-support-power-management.patch Normal file
View File

@ -0,0 +1,130 @@
From ea8d7972140f0af84aec4f5954db62f4217ff5c3 Mon Sep 17 00:00:00 2001
From: fanglifei <fanglifei@eswincomputing.com>
Date: Thu, 11 Jul 2024 14:04:35 +0800
Subject: [PATCH 098/219] feat(eth): ETH support power management
Changelogs:
1. Add a callback func clks_config() which will be called
by PM framework
Signed-off-by: fanglifei <fanglifei@eswincomputing.com>
---
.../ethernet/stmicro/stmmac/dwmac-win2030.c | 63 ++++++++++++-------
1 file changed, 39 insertions(+), 24 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-win2030.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-win2030.c
index 0b37eabd6334..5a83b55357fb 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-win2030.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-win2030.c
@@ -278,13 +278,44 @@ static void dwc_qos_fix_speed(void *priv, unsigned int speed, unsigned int mode)
}
}
+static int dwc_clks_config(void *priv, bool enabled)
+{
+ int ret = 0;
+ struct dwc_qos_priv *dwc_priv = (struct dwc_qos_priv *)priv;
+
+ if (enabled) {
+ ret = clk_prepare_enable(dwc_priv->clk_app);
+ if (ret) {
+ dev_err(dwc_priv->dev, "failed to enable app clk, err = %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(dwc_priv->clk_csr);
+ if (ret< 0) {
+ dev_err(dwc_priv->dev, "failed to enable csr clk: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(dwc_priv->clk_tx);
+ if (ret < 0) {
+ dev_err(dwc_priv->dev, "failed to enable tx clock: %d\n", ret);
+ return ret;
+ }
+ } else {
+ clk_disable_unprepare(dwc_priv->clk_tx);
+ clk_disable_unprepare(dwc_priv->clk_csr);
+ clk_disable_unprepare(dwc_priv->clk_app);
+ }
+
+ return ret;
+}
+
static int dwc_qos_probe(struct platform_device *pdev,
struct plat_stmmacenet_data *plat_dat,
struct stmmac_resources *stmmac_res)
{
struct dwc_qos_priv *dwc_priv;
int ret;
- int err;
u32 hsp_aclk_ctrl_offset;
u32 hsp_aclk_ctrl_regset;
u32 hsp_cfg_ctrl_offset;
@@ -401,38 +432,23 @@ static int dwc_qos_probe(struct platform_device *pdev,
return PTR_ERR(dwc_priv->clk_app);
}
- err = clk_prepare_enable(dwc_priv->clk_app);
- if (err < 0) {
- dev_err(&pdev->dev, "failed to enable app clock: %d\n",
- err);
- return err;
- }
-
dwc_priv->clk_csr = devm_clk_get(&pdev->dev, "csr");
if (IS_ERR(dwc_priv->clk_csr)) {
dev_err(&pdev->dev, "csr clock not found.\n");
return PTR_ERR(dwc_priv->clk_csr);
}
- err = clk_prepare_enable(dwc_priv->clk_csr);
- if (err < 0) {
- dev_err(&pdev->dev, "failed to enable csr clock: %d\n",
- err);
- return err;
- }
-
dwc_priv->clk_tx = devm_clk_get(&pdev->dev, "tx");
- if (IS_ERR(plat_dat->pclk)) {
+ if (IS_ERR(dwc_priv->clk_tx)) {
dev_err(&pdev->dev, "tx clock not found.\n");
return PTR_ERR(dwc_priv->clk_tx);
}
- err = clk_prepare_enable(dwc_priv->clk_tx);
- if (err < 0) {
- dev_err(&pdev->dev, "failed to enable tx clock: %d\n",
- err);
- return err;
+ ret = dwc_clks_config(dwc_priv, true);
+ if (ret) {
+ return ret;
}
+
dwc_priv->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, "ethrst");
if (IS_ERR(dwc_priv->rst)) {
return PTR_ERR(dwc_priv->rst);
@@ -452,6 +468,7 @@ static int dwc_qos_probe(struct platform_device *pdev,
plat_dat->fix_mac_speed = dwc_qos_fix_speed;
plat_dat->bsp_priv = dwc_priv;
plat_dat->phy_addr = PHY_ADDR;
+ plat_dat->clks_config = dwc_clks_config;
return 0;
}
@@ -468,9 +485,7 @@ static int dwc_qos_remove(struct platform_device *pdev)
}
reset_control_assert(dwc_priv->rst);
- clk_disable_unprepare(dwc_priv->clk_tx);
- clk_disable_unprepare(dwc_priv->clk_csr);
- clk_disable_unprepare(dwc_priv->clk_app);
+ dwc_clks_config(dwc_priv, false);
devm_gpiod_put(&pdev->dev, dwc_priv->phy_reset);
--
2.47.0

106
0099-feat-npu-drv-support-low-power.patch Normal file
View File

@ -0,0 +1,106 @@
From 2d9e9081b856128e3bdd8dfe473cd8fb82823a54 Mon Sep 17 00:00:00 2001
From: donghuawei <donghuawei@eswincomputing.com>
Date: Tue, 16 Jul 2024 10:15:29 +0800
Subject: [PATCH 099/219] feat: npu drv support low power
Changelogs:
support npu clock enable and disable for low power
Signed-off-by: donghuawei <donghuawei@eswincomputing.com>
---
drivers/memory/eswin/codacache/llc_spram.c | 56 ++++++++++++++++++++++
drivers/memory/eswin/codacache/llc_spram.h | 3 +-
2 files changed, 58 insertions(+), 1 deletion(-)
diff --git a/drivers/memory/eswin/codacache/llc_spram.c b/drivers/memory/eswin/codacache/llc_spram.c
index 4e9027dd5db9..c26567e5aa80 100644
--- a/drivers/memory/eswin/codacache/llc_spram.c
+++ b/drivers/memory/eswin/codacache/llc_spram.c
@@ -38,6 +38,7 @@
#include <linux/mfd/syscon.h>
#include <linux/memblock.h>
#include <linux/version.h>
+#include <linux/clk-provider.h>
#include <linux/eswin_npu.h>
#include <linux/regulator/consumer.h>
@@ -471,6 +472,61 @@ int npu_cfg_rst(int nid, bool enable)
}
EXPORT_SYMBOL(npu_cfg_rst);
+static int npu_clk_enable(struct platform_device *pdev, struct spram_dev *spram)
+{
+ int ret;
+
+ if (!__clk_is_enabled(spram->cfg_clk)) {
+ ret = clk_prepare_enable(spram->cfg_clk);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to enable cfg_clk: %d\n", ret);
+ return ret;
+ }
+ }
+
+ if (!__clk_is_enabled(spram->core_clk)) {
+ ret = clk_prepare_enable(spram->core_clk);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to enable core_clk: %d\n", ret);
+ return ret;
+ }
+ }
+ return 0;
+}
+
+static int npu_clk_disable(struct platform_device *pdev, struct spram_dev *spram)
+{
+ clk_disable_unprepare(spram->core_clk);
+ clk_disable_unprepare(spram->cfg_clk);
+ return 0;
+}
+
+int npu_clk_gate_set(int nid, bool enable)
+{
+ struct platform_device *pdev = pdevs[nid];
+ struct spram_dev *spram;
+
+ if (NULL == pdev) {
+ pr_err("%s, Invalid node id:%d\n", __func__, nid);
+ return -EINVAL;
+ }
+
+ spram = platform_get_drvdata(pdev);
+ if (spram == NULL)
+ return -EINVAL;
+
+ if (enable == true) {
+ return npu_clk_enable(pdev, spram);
+ } else if (enable == false) {
+ return npu_clk_disable(pdev, spram);
+ } else {
+ pr_err("param enable=%d error.\n", enable);
+ return -EINVAL;
+ }
+ return 0;
+}
+EXPORT_SYMBOL(npu_clk_gate_set);
+
int npu_core_rst(int nid, bool enable)
{
struct platform_device *pdev = pdevs[nid];
diff --git a/drivers/memory/eswin/codacache/llc_spram.h b/drivers/memory/eswin/codacache/llc_spram.h
index 40dd35efec5c..44863a70efbd 100644
--- a/drivers/memory/eswin/codacache/llc_spram.h
+++ b/drivers/memory/eswin/codacache/llc_spram.h
@@ -84,7 +84,8 @@ struct llc_cache_ops {
int llc_user_register(struct device *user_dev);
int npu_cfg_rst(int nid, bool enable);
int npu_core_rst(int nid, bool enable);
+int npu_clk_gate_set(int nid, bool enable);
int llc_spram_avail_size(int nid, uint32_t *pSpramSize);
int llc_flush_operation(unsigned long start, unsigned long len);
-#endif
\ No newline at end of file
+#endif
--
2.47.0

346
0100-feat-emmc-sd-sdio-sdhci-support-power-management.patch Normal file
View File

@ -0,0 +1,346 @@
From b47be619cd529585a070ea68d93e94c72ff859a8 Mon Sep 17 00:00:00 2001
From: liangshuang <liangshuang@eswincomputing.com>
Date: Tue, 16 Jul 2024 17:32:14 +0800
Subject: [PATCH 100/219] feat(emmc sd sdio):sdhci support power management
Changelogs:
1.sdhci driver support power management.
2.fix the issue of actual_clock is wrong.
Signed-off-by: liangshuang <liangshuang@eswincomputing.com>
---
drivers/mmc/host/sdhci-eswin.c | 2 +
drivers/mmc/host/sdhci-of-eswin-sdio.c | 107 +++++++++++++++++--------
drivers/mmc/host/sdhci-of-eswin.c | 95 +++++++++++++++-------
3 files changed, 144 insertions(+), 60 deletions(-)
diff --git a/drivers/mmc/host/sdhci-eswin.c b/drivers/mmc/host/sdhci-eswin.c
index c823d034ce6b..e75d8b77acdb 100644
--- a/drivers/mmc/host/sdhci-eswin.c
+++ b/drivers/mmc/host/sdhci-eswin.c
@@ -112,6 +112,8 @@ void eswin_sdhci_set_core_clock(struct sdhci_host *host,
unsigned int div, divide;
unsigned int flag_sel, max_clk;
+ host->mmc->actual_clock = clock;
+
if (clock == 0) {
eswin_mshc_coreclk_disable(host);
return;
diff --git a/drivers/mmc/host/sdhci-of-eswin-sdio.c b/drivers/mmc/host/sdhci-of-eswin-sdio.c
index d5ae6a5694f6..f9090ece0f65 100644
--- a/drivers/mmc/host/sdhci-of-eswin-sdio.c
+++ b/drivers/mmc/host/sdhci-of-eswin-sdio.c
@@ -64,16 +64,15 @@ static void eswin_sdhci_sdio_set_clock(struct sdhci_host *host,
}
eswin_sdhci_set_core_clock(host, clock);
- sdhci_set_clock(host, clock);
if (eswin_sdhci_sdio->quirks & SDHCI_ESWIN_QUIRK_CLOCK_UNSTABLE)
/*
- * Some controllers immediately report SDHCI_CLOCK_INT_STABLE
- * after enabling the clock even though the clock is not
- * stable. Trying to use a clock without waiting here results
- * in EILSEQ while detecting some older/slower cards. The
- * chosen delay is the maximum delay from sdhci_set_clock.
- */
+ * Some controllers immediately report SDHCI_CLOCK_INT_STABLE
+ * after enabling the clock even though the clock is not
+ * stable. Trying to use a clock without waiting here results
+ * in EILSEQ while detecting some older/slower cards. The
+ * chosen delay is the maximum delay from sdhci_set_clock.
+ */
msleep(20);
}
@@ -357,21 +356,10 @@ static int eswin_sdhci_sdio_suspend(struct device *dev)
sdhci_pltfm_priv(pltfm_host);
int ret;
- if (host->tuning_mode != SDHCI_TUNING_MODE_3)
- mmc_retune_needed(host->mmc);
-
- if (eswin_sdhci_sdio->has_cqe) {
- ret = cqhci_suspend(host->mmc);
- if (ret)
- return ret;
- }
-
- ret = sdhci_suspend_host(host);
+ ret = sdhci_pltfm_suspend(dev);
if (ret)
return ret;
-
- clk_disable(pltfm_host->clk);
- clk_disable(eswin_sdhci_sdio->clk_ahb);
+ clk_disable_unprepare(eswin_sdhci_sdio->clk_ahb);
return 0;
}
@@ -392,33 +380,80 @@ static int eswin_sdhci_sdio_resume(struct device *dev)
sdhci_pltfm_priv(pltfm_host);
int ret;
- ret = clk_enable(eswin_sdhci_sdio->clk_ahb);
+ ret = clk_prepare_enable(eswin_sdhci_sdio->clk_ahb);
if (ret) {
- dev_err(dev, "Cannot enable AHB clock.\n");
+ dev_err(dev, "can't enable clk_ahb\n");
return ret;
}
- ret = clk_enable(pltfm_host->clk);
+ ret = sdhci_pltfm_resume(dev);
if (ret) {
- dev_err(dev, "Cannot enable SD clock.\n");
- return ret;
+ dev_err(dev, "pltfm resume failed!\n");
+ goto clk_disable;
}
- ret = sdhci_resume_host(host);
+ return 0;
+clk_disable:
+ clk_disable_unprepare(eswin_sdhci_sdio->clk_ahb);
+
+ return ret;
+}
+
+static int eswin_sdhci_sdio_runtime_suspend(struct device *dev)
+{
+ struct sdhci_host *host = dev_get_drvdata(dev);
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct eswin_sdhci_data *eswin_sdhci_sdio = sdhci_pltfm_priv(pltfm_host);
+ int ret;
+
+ ret = sdhci_runtime_suspend_host(host);
+ if (ret)
+ return ret;
+
+ if (host->tuning_mode != SDHCI_TUNING_MODE_3)
+ mmc_retune_needed(host->mmc);
+
+ clk_disable_unprepare(pltfm_host->clk);
+ clk_disable_unprepare(eswin_sdhci_sdio->clk_ahb);
+
+ return 0;
+}
+
+static int eswin_sdhci_sdio_runtime_resume(struct device *dev)
+{
+ struct sdhci_host *host = dev_get_drvdata(dev);
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct eswin_sdhci_data *eswin_sdhci_sdio = sdhci_pltfm_priv(pltfm_host);
+ int ret;
+
+ ret = clk_prepare_enable(eswin_sdhci_sdio->clk_ahb);
if (ret) {
- dev_err(dev, "Cannot resume host.\n");
+ dev_err(dev, "can't enable clk_ahb\n");
return ret;
}
- if (eswin_sdhci_sdio->has_cqe)
- return cqhci_resume(host->mmc);
+ ret = clk_prepare_enable(pltfm_host->clk);
+ if (ret) {
+ dev_err(dev, "can't enable mainck\n");
+ goto clk_ahb_disable;
+ }
+
+ ret = sdhci_runtime_resume_host(host, 0);
+ if (ret) {
+ dev_err(dev, "runtime resume failed!\n");
+ goto clk_disable;
+ }
return 0;
+clk_disable:
+ clk_disable_unprepare(pltfm_host->clk);
+clk_ahb_disable:
+ clk_disable_unprepare(eswin_sdhci_sdio->clk_ahb);
+
+ return ret;
}
-#endif /* ! CONFIG_PM_SLEEP */
-static SIMPLE_DEV_PM_OPS(eswin_sdhci_sdio_dev_pm_ops, eswin_sdhci_sdio_suspend,
- eswin_sdhci_sdio_resume);
+#endif /* ! CONFIG_PM_SLEEP */
/**
* eswin_sdhci_sdio_sdcardclk_recalc_rate- Return the card clock rate
@@ -980,12 +1015,18 @@ static int eswin_sdhci_sdio_remove(struct platform_device *pdev)
return 0;
}
+static const struct dev_pm_ops eswin_sdhci_sdio_pmops = {
+ SET_SYSTEM_SLEEP_PM_OPS(eswin_sdhci_sdio_suspend, eswin_sdhci_sdio_resume)
+ SET_RUNTIME_PM_OPS(eswin_sdhci_sdio_runtime_suspend,
+ eswin_sdhci_sdio_runtime_resume, NULL)
+};
+
static struct platform_driver eswin_sdhci_sdio_driver = {
.driver = {
.name = "eswin-sdhci-sdio",
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
.of_match_table = eswin_sdhci_sdio_of_match,
- .pm = &eswin_sdhci_sdio_dev_pm_ops,
+ .pm = &eswin_sdhci_sdio_pmops,
},
.probe = eswin_sdhci_sdio_probe,
.remove = eswin_sdhci_sdio_remove,
diff --git a/drivers/mmc/host/sdhci-of-eswin.c b/drivers/mmc/host/sdhci-of-eswin.c
index a0347ac5c739..3e2912aca476 100644
--- a/drivers/mmc/host/sdhci-of-eswin.c
+++ b/drivers/mmc/host/sdhci-of-eswin.c
@@ -74,7 +74,6 @@ static void eswin_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
clk_data->set_clk_delays(host);
eswin_sdhci_set_core_clock(host, clock);
- sdhci_set_clock(host, clock);
/*
* Some controllers immediately report SDHCI_CLOCK_INT_STABLE
@@ -477,21 +476,10 @@ static int eswin_sdhci_suspend(struct device *dev)
struct eswin_sdhci_data *eswin_sdhci = sdhci_pltfm_priv(pltfm_host);
int ret;
- if (host->tuning_mode != SDHCI_TUNING_MODE_3)
- mmc_retune_needed(host->mmc);
-
- if (eswin_sdhci->has_cqe) {
- ret = cqhci_suspend(host->mmc);
- if (ret)
- return ret;
- }
-
- ret = sdhci_suspend_host(host);
+ ret = sdhci_pltfm_suspend(dev);
if (ret)
return ret;
-
- clk_disable(pltfm_host->clk);
- clk_disable(eswin_sdhci->clk_ahb);
+ clk_disable_unprepare(eswin_sdhci->clk_ahb);
return 0;
}
@@ -511,33 +499,80 @@ static int eswin_sdhci_resume(struct device *dev)
struct eswin_sdhci_data *eswin_sdhci = sdhci_pltfm_priv(pltfm_host);
int ret;
- ret = clk_enable(eswin_sdhci->clk_ahb);
+ ret = clk_prepare_enable(eswin_sdhci->clk_ahb);
if (ret) {
- dev_err(dev, "Cannot enable AHB clock.\n");
+ dev_err(dev, "can't enable clk_ahb\n");
return ret;
}
- ret = clk_enable(pltfm_host->clk);
+ ret = sdhci_pltfm_resume(dev);
if (ret) {
- dev_err(dev, "Cannot enable SD clock.\n");
- return ret;
+ dev_err(dev, "pltfm resume failed!\n");
+ goto clk_disable;
}
- ret = sdhci_resume_host(host);
+ return 0;
+clk_disable:
+ clk_disable_unprepare(eswin_sdhci->clk_ahb);
+
+ return ret;
+}
+
+static int eswin_sdhci_runtime_suspend(struct device *dev)
+{
+ struct sdhci_host *host = dev_get_drvdata(dev);
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct eswin_sdhci_data *eswin_sdhci = sdhci_pltfm_priv(pltfm_host);
+ int ret;
+
+ ret = sdhci_runtime_suspend_host(host);
+ if (ret)
+ return ret;
+
+ if (host->tuning_mode != SDHCI_TUNING_MODE_3)
+ mmc_retune_needed(host->mmc);
+
+ clk_disable_unprepare(pltfm_host->clk);
+ clk_disable_unprepare(eswin_sdhci->clk_ahb);
+
+ return 0;
+}
+
+static int eswin_sdhci_runtime_resume(struct device *dev)
+{
+ struct sdhci_host *host = dev_get_drvdata(dev);
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct eswin_sdhci_data *eswin_sdhci = sdhci_pltfm_priv(pltfm_host);
+ int ret;
+
+ ret = clk_prepare_enable(eswin_sdhci->clk_ahb);
if (ret) {
- dev_err(dev, "Cannot resume host.\n");
+ dev_err(dev, "can't enable clk_ahb\n");
return ret;
}
- if (eswin_sdhci->has_cqe)
- return cqhci_resume(host->mmc);
+ ret = clk_prepare_enable(pltfm_host->clk);
+ if (ret) {
+ dev_err(dev, "can't enable mainck\n");
+ goto clk_ahb_disable;
+ }
+
+ ret = sdhci_runtime_resume_host(host, 0);
+ if (ret) {
+ dev_err(dev, "runtime resume failed!\n");
+ goto clk_disable;
+ }
return 0;
+clk_disable:
+ clk_disable_unprepare(pltfm_host->clk);
+clk_ahb_disable:
+ clk_disable_unprepare(eswin_sdhci->clk_ahb);
+
+ return ret;
}
-#endif /* ! CONFIG_PM_SLEEP */
-static SIMPLE_DEV_PM_OPS(eswin_sdhci_dev_pm_ops, eswin_sdhci_suspend,
- eswin_sdhci_resume);
+#endif /* ! CONFIG_PM_SLEEP */
/**
* eswin_sdhci_sdcardclk_recalc_rate - Return the card clock rate
@@ -1073,13 +1108,19 @@ static void eswin_sdhci_shutdown(struct platform_device *pdev)
platform_set_drvdata(pdev, NULL);
}
+static const struct dev_pm_ops eswin_sdhci_pmops = {
+ SET_SYSTEM_SLEEP_PM_OPS(eswin_sdhci_suspend, eswin_sdhci_resume)
+ SET_RUNTIME_PM_OPS(eswin_sdhci_runtime_suspend,
+ eswin_sdhci_runtime_resume, NULL)
+};
+
static struct platform_driver eswin_sdhci_driver =
{
.driver = {
.name = "sdhci-eswin",
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
.of_match_table = eswin_sdhci_of_match,
- .pm = &eswin_sdhci_dev_pm_ops,
+ .pm = &eswin_sdhci_pmops,
},
.probe = eswin_sdhci_probe,
.remove = eswin_sdhci_remove,
--
2.47.0

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