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Update riscv64 configs

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Cannot disable IRQ_STACKS thus let's disable V for testing.

Signed-off-by: David Abdurachmanov <davidlt@rivosinc.com>
This commit is contained in:
David Abdurachmanov 2023-08-02 15:27:58 +03:00
parent a6ee8f7303
commit cd73e6a5be
Signed by: davidlt
GPG Key ID: 8B7F1DA0E2C9FDBB
2 changed files with 6 additions and 6 deletions
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6
kernel-riscv64-debug-fedora.config
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@ -2858,7 +2858,7 @@ CONFIG_IR_NEC_DECODER=m
CONFIG_IR_NUVOTON=m
CONFIG_IR_PWM_TX=m
# CONFIG_IRQSOFF_TRACER is not set
# CONFIG_IRQ_STACKS is not set
CONFIG_IRQ_STACKS=y
CONFIG_IRQ_TIME_ACCOUNTING=y
CONFIG_IR_RC5_DECODER=m
CONFIG_IR_RC6_DECODER=m
@ -5170,8 +5170,8 @@ CONFIG_RISCV_INTC=y
CONFIG_RISCV_ISA_C=y
CONFIG_RISCV_ISA_SVNAPOT=y
CONFIG_RISCV_ISA_SVPBMT=y
CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y
CONFIG_RISCV_ISA_V=y
# CONFIG_RISCV_ISA_V_DEFAULT_ENABLE is not set
# CONFIG_RISCV_ISA_V is not set
CONFIG_RISCV_ISA_ZBB=y
CONFIG_RISCV_ISA_ZICBOM=y
CONFIG_RISCV_ISA_ZICBOZ=y

6
kernel-riscv64-fedora.config
View File

@ -2838,7 +2838,7 @@ CONFIG_IR_NEC_DECODER=m
CONFIG_IR_NUVOTON=m
CONFIG_IR_PWM_TX=m
# CONFIG_IRQSOFF_TRACER is not set
# CONFIG_IRQ_STACKS is not set
CONFIG_IRQ_STACKS=y
CONFIG_IRQ_TIME_ACCOUNTING=y
CONFIG_IR_RC5_DECODER=m
CONFIG_IR_RC6_DECODER=m
@ -5141,8 +5141,8 @@ CONFIG_RISCV_INTC=y
CONFIG_RISCV_ISA_C=y
CONFIG_RISCV_ISA_SVNAPOT=y
CONFIG_RISCV_ISA_SVPBMT=y
CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y
CONFIG_RISCV_ISA_V=y
# CONFIG_RISCV_ISA_V_DEFAULT_ENABLE is not set
# CONFIG_RISCV_ISA_V is not set
CONFIG_RISCV_ISA_ZBB=y
CONFIG_RISCV_ISA_ZICBOM=y
CONFIG_RISCV_ISA_ZICBOZ=y