edac: Fix memory filling order
After testing it on a machine with in asynchronous mode, it was noticed that the memories are not filled in the proper order. Fix it. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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@ -853,3 +853,101 @@ index f998d2c..082e91e 100644
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fail0:
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return rc;
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}
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commit ad28406017c4f225f10cb78931214e48fde866ae
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Author: Mauro Carvalho Chehab <mchehab@redhat.com>
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Date: Wed Oct 24 10:30:01 2012 -0200
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edac: Fix the dimm filling for csrows-based layouts
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The driver is currently filling data in a wrong way, on drivers
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for csrows-based memory controller, when the first layer is a
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csrow.
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This is not easily to notice, as, in general, memories are
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filed in dual, interleaved, symetric mode, as very few memory
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controllers support asymetric modes.
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While digging into a bug for i82795_edac driver, the asymetric
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mode there is now working, allowing us to fill the machine with
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4x1GB ranks at channel 0, and 2x512GB at channel 1:
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Channel 0 ranks:
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EDAC DEBUG: i82975x_init_csrows: DIMM A0: from page 0x00000000 to 0x0003ffff (size: 0x00040000 pages)
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EDAC DEBUG: i82975x_init_csrows: DIMM A1: from page 0x00040000 to 0x0007ffff (size: 0x00040000 pages)
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EDAC DEBUG: i82975x_init_csrows: DIMM A2: from page 0x00080000 to 0x000bffff (size: 0x00040000 pages)
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EDAC DEBUG: i82975x_init_csrows: DIMM A3: from page 0x000c0000 to 0x000fffff (size: 0x00040000 pages)
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Channel 1 ranks:
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EDAC DEBUG: i82975x_init_csrows: DIMM B0: from page 0x00100000 to 0x0011ffff (size: 0x00020000 pages)
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EDAC DEBUG: i82975x_init_csrows: DIMM B1: from page 0x00120000 to 0x0013ffff (size: 0x00020000 pages)
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Instead of properly showing the memories as such, before this patch, it
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shows the memory layout as:
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+-----------------------------------+
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| mc0 |
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| csrow0 | csrow1 | csrow2 |
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----------+-----------------------------------+
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channel1: | 1024 MB | 1024 MB | 512 MB |
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channel0: | 1024 MB | 1024 MB | 512 MB |
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----------+-----------------------------------+
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as if both channels were symetric, grouping the DIMMs on a wrong
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layout.
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After this patch, the memory is correctly represented.
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So, for csrows at layers[0], it shows:
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+-----------------------------------------------+
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| mc0 |
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| csrow0 | csrow1 | csrow2 | csrow3 |
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----------+-----------------------------------------------+
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channel1: | 512 MB | 512 MB | 0 MB | 0 MB |
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channel0: | 1024 MB | 1024 MB | 1024 MB | 1024 MB |
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----------+-----------------------------------------------+
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For csrows at layers[1], it shows:
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+-----------------------+
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| mc0 |
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| channel0 | channel1 |
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--------+-----------------------+
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csrow3: | 1024 MB | 0 MB |
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csrow2: | 1024 MB | 0 MB |
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--------+-----------------------+
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csrow1: | 1024 MB | 512 MB |
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csrow0: | 1024 MB | 512 MB |
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--------+-----------------------+
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So, no matter of what comes first, the information between
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channel and csrow will be properly represented.
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Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c
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index d5dc9da..81eb9fd 100644
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--- a/drivers/edac/edac_mc.c
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+++ b/drivers/edac/edac_mc.c
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@@ -416,10 +416,18 @@ struct mem_ctl_info *edac_mc_alloc(unsigned mc_num,
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dimm->cschannel = chn;
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/* Increment csrow location */
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- row++;
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- if (row == tot_csrows) {
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- row = 0;
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+ if (layers[0].is_virt_csrow) {
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chn++;
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+ if (chn == tot_channels) {
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+ chn = 0;
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+ row++;
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+ }
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+ } else {
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+ row++;
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+ if (row == tot_csrows) {
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+ row = 0;
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+ chn++;
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+ }
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}
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/* Increment dimm location */
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@ -2360,6 +2360,9 @@ fi
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# '-' | |
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# '-'
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%changelog
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* Tue Oct 30 2012 Mauro Carvalho Chehab <mchehab@redhat.com>
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- Fix EDAC memory filling for csrow-based memory controllers
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* Tue Oct 30 2012 Josh Boyer <jwboyer@redhat.com>
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- Move power-x86-destdir.patch to apply on vanilla kernels (thanks knurd)
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