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Update RISC-V (riscv64) configs

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New options added:

CONFIG_SOC_SIFIVE=y
CONFIG_EDAC_SIFIVE=y
CONFIG_PWM_SIFIVE=y

Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
This commit is contained in:
David Abdurachmanov 2019-08-24 23:10:49 -07:00
parent 6bc8810bf1
commit c12dd026dd
Signed by: davidlt
GPG Key ID: 8B7F1DA0E2C9FDBB
5 changed files with 9 additions and 0 deletions
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1
configs/fedora/generic/riscv/CONFIG_EDAC_SIFIVE Normal file
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@ -0,0 +1 @@
CONFIG_EDAC_SIFIVE=y

1
configs/fedora/generic/riscv/CONFIG_PWM_SIFIVE Normal file
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@ -0,0 +1 @@
CONFIG_PWM_SIFIVE=y

1
configs/fedora/generic/riscv/CONFIG_SOC_SIFIVE Normal file
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@ -0,0 +1 @@
CONFIG_SOC_SIFIVE=y

3
kernel-riscv64-debug.config
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@ -1302,6 +1302,7 @@ CONFIG_ECRYPT_FS=m
# CONFIG_EDAC_DEBUG is not set
CONFIG_EDAC_GHES=y
CONFIG_EDAC_LEGACY_SYSFS=y
CONFIG_EDAC_SIFIVE=y
# CONFIG_EDAC_SYNOPSYS is not set
CONFIG_EDAC=y
CONFIG_EEPROM_93CX6=m
@ -3907,6 +3908,7 @@ CONFIG_PVPANIC=m
# CONFIG_PWM_FSL_FTM is not set
CONFIG_PWM_HIBVT=m
# CONFIG_PWM_PCA9685 is not set
CONFIG_PWM_SIFIVE=y
CONFIG_PWM=y
CONFIG_PWRSEQ_EMMC=m
CONFIG_PWRSEQ_SD8787=m
@ -5020,6 +5022,7 @@ CONFIG_SND_VX222=m
# CONFIG_SND_XEN_FRONTEND is not set
CONFIG_SND_YMFPCI=m
# CONFIG_SOC_CAMERA is not set
CONFIG_SOC_SIFIVE=y
# CONFIG_SOC_TI is not set
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_SOFT_WATCHDOG=m

3
kernel-riscv64.config
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@ -1293,6 +1293,7 @@ CONFIG_ECRYPT_FS=m
# CONFIG_EDAC_DEBUG is not set
CONFIG_EDAC_GHES=y
CONFIG_EDAC_LEGACY_SYSFS=y
CONFIG_EDAC_SIFIVE=y
# CONFIG_EDAC_SYNOPSYS is not set
CONFIG_EDAC=y
CONFIG_EEPROM_93CX6=m
@ -3885,6 +3886,7 @@ CONFIG_PVPANIC=m
# CONFIG_PWM_FSL_FTM is not set
CONFIG_PWM_HIBVT=m
# CONFIG_PWM_PCA9685 is not set
CONFIG_PWM_SIFIVE=y
CONFIG_PWM=y
CONFIG_PWRSEQ_EMMC=m
CONFIG_PWRSEQ_SD8787=m
@ -4997,6 +4999,7 @@ CONFIG_SND_VX222=m
# CONFIG_SND_XEN_FRONTEND is not set
CONFIG_SND_YMFPCI=m
# CONFIG_SOC_CAMERA is not set
CONFIG_SOC_SIFIVE=y
# CONFIG_SOC_TI is not set
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_SOFT_WATCHDOG=m