From 4919ac334fe18dddd72d36baf3ab1bf652725403 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sun, 25 Aug 2019 18:44:48 +0100 Subject: [PATCH 1/3] minor Arm cleanups --- ARM-cpufreq-support-for-Raspberry-Pi.patch | 539 ------------------ ...p-Update-DWC3-modules-on-RK3399-SoCs.patch | 145 ----- kernel.spec | 32 +- 3 files changed, 12 insertions(+), 704 deletions(-) delete mode 100644 ARM-cpufreq-support-for-Raspberry-Pi.patch delete mode 100644 arm64-dts-rockchip-Update-DWC3-modules-on-RK3399-SoCs.patch diff --git a/ARM-cpufreq-support-for-Raspberry-Pi.patch b/ARM-cpufreq-support-for-Raspberry-Pi.patch deleted file mode 100644 index 601caa070..000000000 --- a/ARM-cpufreq-support-for-Raspberry-Pi.patch +++ /dev/null @@ -1,539 +0,0 @@ -From ba60a01e02086b0a242cf5ea3c59419108ada40b Mon Sep 17 00:00:00 2001 -From: Nicolas Saenz Julienne -Date: Tue, 11 Jun 2019 19:58:34 +0200 -Subject: [PATCH 1/5] clk: bcm2835: remove pllb - -Raspberry Pi's firmware controls this pll, we should use the firmware -interface to access it. - -Signed-off-by: Nicolas Saenz Julienne -Acked-by: Eric Anholt ---- - drivers/clk/bcm/clk-bcm2835.c | 28 ++++------------------------ - 1 file changed, 4 insertions(+), 24 deletions(-) - -diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c -index 770bb01f523e..867ae3c20041 100644 ---- a/drivers/clk/bcm/clk-bcm2835.c -+++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -1651,30 +1651,10 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { - .fixed_divider = 1, - .flags = CLK_SET_RATE_PARENT), - -- /* PLLB is used for the ARM's clock. */ -- [BCM2835_PLLB] = REGISTER_PLL( -- .name = "pllb", -- .cm_ctrl_reg = CM_PLLB, -- .a2w_ctrl_reg = A2W_PLLB_CTRL, -- .frac_reg = A2W_PLLB_FRAC, -- .ana_reg_base = A2W_PLLB_ANA0, -- .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE, -- .lock_mask = CM_LOCK_FLOCKB, -- -- .ana = &bcm2835_ana_default, -- -- .min_rate = 600000000u, -- .max_rate = 3000000000u, -- .max_fb_rate = BCM2835_MAX_FB_RATE), -- [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV( -- .name = "pllb_arm", -- .source_pll = "pllb", -- .cm_reg = CM_PLLB, -- .a2w_reg = A2W_PLLB_ARM, -- .load_mask = CM_PLLB_LOADARM, -- .hold_mask = CM_PLLB_HOLDARM, -- .fixed_divider = 1, -- .flags = CLK_SET_RATE_PARENT), -+ /* -+ * PLLB is used for the ARM's clock. Controlled by firmware, see -+ * clk-raspberrypi.c. -+ */ - - /* - * PLLC is the core PLL, used to drive the core VPU clock. --- -2.21.0 - -From 64482a97a0a2f14ebdbfe80a8eb0e063d293807b Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Wed, 12 Jun 2019 17:23:12 +0100 -Subject: [PATCH 2/5] clk: bcm283x: add driver interfacing with Raspberry Pi's - firmware - -Raspberry Pi's firmware offers an interface though which update it's -clock's frequencies. This is specially useful in order to change the CPU -clock (pllb_arm) which is 'owned' by the firmware and we're unable to -scale using the register interface provided by clk-bcm2835. - -Signed-off-by: Nicolas Saenz Julienne -Acked-by: Eric Anholt -Signed-off-by: Peter Robinson ---- - drivers/clk/bcm/Kconfig | 7 + - drivers/clk/bcm/Makefile | 1 + - drivers/clk/bcm/clk-raspberrypi.c | 300 ++++++++++++++++++++++++++++++ - 3 files changed, 308 insertions(+) - create mode 100644 drivers/clk/bcm/clk-raspberrypi.c - -diff --git a/drivers/clk/bcm/Kconfig b/drivers/clk/bcm/Kconfig -index 29ee7b776cd4..a4a2775d65e1 100644 ---- a/drivers/clk/bcm/Kconfig -+++ b/drivers/clk/bcm/Kconfig -@@ -64,3 +64,10 @@ config CLK_BCM_SR - default ARCH_BCM_IPROC - help - Enable common clock framework support for the Broadcom Stingray SoC -+ -+config CLK_RASPBERRYPI -+ tristate "Raspberry Pi firmware based clock support" -+ depends on RASPBERRYPI_FIRMWARE || (COMPILE_TEST && !RASPBERRYPI_FIRMWARE) -+ help -+ Enable common clock framework support for Raspberry Pi's firmware -+ dependent clocks -diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile -index 002661d39128..eb7159099d82 100644 ---- a/drivers/clk/bcm/Makefile -+++ b/drivers/clk/bcm/Makefile -@@ -7,6 +7,7 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o - obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o - obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o - obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835-aux.o -+obj-$(CONFIG_CLK_RASPBERRYPI) += clk-raspberrypi.o - obj-$(CONFIG_ARCH_BCM_53573) += clk-bcm53573-ilp.o - obj-$(CONFIG_CLK_BCM_CYGNUS) += clk-cygnus.o - obj-$(CONFIG_CLK_BCM_HR2) += clk-hr2.o -diff --git a/drivers/clk/bcm/clk-raspberrypi.c b/drivers/clk/bcm/clk-raspberrypi.c -new file mode 100644 -index 000000000000..467933767106 ---- /dev/null -+++ b/drivers/clk/bcm/clk-raspberrypi.c -@@ -0,0 +1,300 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Raspberry Pi driver for firmware controlled clocks -+ * -+ * Even though clk-bcm2835 provides an interface to the hardware registers for -+ * the system clocks we've had to factor out 'pllb' as the firmware 'owns' it. -+ * We're not allowed to change it directly as we might race with the -+ * over-temperature and under-voltage protections provided by the firmware. -+ * -+ * Copyright (C) 2019 Nicolas Saenz Julienne -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define RPI_FIRMWARE_ARM_CLK_ID 0x000000003 -+ -+#define RPI_FIRMWARE_STATE_ENABLE_BIT BIT(0) -+#define RPI_FIRMWARE_STATE_WAIT_BIT BIT(1) -+ -+/* -+ * Even though the firmware interface alters 'pllb' the frequencies are -+ * provided as per 'pllb_arm'. We need to scale before passing them trough. -+ */ -+#define RPI_FIRMWARE_PLLB_ARM_DIV_RATE 2 -+ -+#define A2W_PLL_FRAC_BITS 20 -+ -+struct raspberrypi_clk { -+ struct device *dev; -+ struct rpi_firmware *firmware; -+ -+ unsigned long min_rate; -+ unsigned long max_rate; -+ -+ struct clk_hw pllb; -+ struct clk_hw *pllb_arm; -+ struct clk_lookup *pllb_arm_lookup; -+}; -+ -+/* -+ * Structure of the message passed to Raspberry Pi's firmware in order to -+ * change clock rates. The 'disable_turbo' option is only available to the ARM -+ * clock (pllb) which we enable by default as turbo mode will alter multiple -+ * clocks at once. -+ * -+ * Even though we're able to access the clock registers directly we're bound to -+ * use the firmware interface as the firmware ultimately takes care of -+ * mitigating overheating/undervoltage situations and we would be changing -+ * frequencies behind his back. -+ * -+ * For more information on the firmware interface check: -+ * https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface -+ */ -+struct raspberrypi_firmware_prop { -+ __le32 id; -+ __le32 val; -+ __le32 disable_turbo; -+} __packed; -+ -+static int raspberrypi_clock_property(struct rpi_firmware *firmware, u32 tag, -+ u32 clk, u32 *val) -+{ -+ struct raspberrypi_firmware_prop msg = { -+ .id = clk, -+ .val = *val, -+ .disable_turbo = 1, -+ }; -+ int ret; -+ -+ ret = rpi_firmware_property(firmware, tag, &msg, sizeof(msg)); -+ if (ret) -+ return ret; -+ -+ *val = msg.val; -+ -+ return 0; -+} -+ -+static int raspberrypi_fw_pll_is_on(struct clk_hw *hw) -+{ -+ struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk, -+ pllb); -+ u32 val = 0; -+ int ret; -+ -+ ret = raspberrypi_clock_property(rpi->firmware, -+ RPI_FIRMWARE_GET_CLOCK_STATE, -+ RPI_FIRMWARE_ARM_CLK_ID, &val); -+ if (ret) -+ return 0; -+ -+ return !!(val & RPI_FIRMWARE_STATE_ENABLE_BIT); -+} -+ -+ -+static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk, -+ pllb); -+ u32 val = 0; -+ int ret; -+ -+ ret = raspberrypi_clock_property(rpi->firmware, -+ RPI_FIRMWARE_GET_CLOCK_RATE, -+ RPI_FIRMWARE_ARM_CLK_ID, -+ &val); -+ if (ret) -+ return ret; -+ -+ return val * RPI_FIRMWARE_PLLB_ARM_DIV_RATE; -+} -+ -+static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk, -+ pllb); -+ u32 new_rate = rate / RPI_FIRMWARE_PLLB_ARM_DIV_RATE; -+ int ret; -+ -+ ret = raspberrypi_clock_property(rpi->firmware, -+ RPI_FIRMWARE_SET_CLOCK_RATE, -+ RPI_FIRMWARE_ARM_CLK_ID, -+ &new_rate); -+ if (ret) -+ dev_err_ratelimited(rpi->dev, "Failed to change %s frequency: %d", -+ clk_hw_get_name(hw), ret); -+ -+ return ret; -+} -+ -+/* -+ * Sadly there is no firmware rate rounding interface. We borrowed it from -+ * clk-bcm2835. -+ */ -+static int raspberrypi_pll_determine_rate(struct clk_hw *hw, -+ struct clk_rate_request *req) -+{ -+ struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk, -+ pllb); -+ u64 div, final_rate; -+ u32 ndiv, fdiv; -+ -+ /* We can't use req->rate directly as it would overflow */ -+ final_rate = clamp(req->rate, rpi->min_rate, rpi->max_rate); -+ -+ div = (u64)final_rate << A2W_PLL_FRAC_BITS; -+ do_div(div, req->best_parent_rate); -+ -+ ndiv = div >> A2W_PLL_FRAC_BITS; -+ fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1); -+ -+ final_rate = ((u64)req->best_parent_rate * -+ ((ndiv << A2W_PLL_FRAC_BITS) + fdiv)); -+ -+ req->rate = final_rate >> A2W_PLL_FRAC_BITS; -+ -+ return 0; -+} -+ -+static const struct clk_ops raspberrypi_firmware_pll_clk_ops = { -+ .is_prepared = raspberrypi_fw_pll_is_on, -+ .recalc_rate = raspberrypi_fw_pll_get_rate, -+ .set_rate = raspberrypi_fw_pll_set_rate, -+ .determine_rate = raspberrypi_pll_determine_rate, -+}; -+ -+static int raspberrypi_register_pllb(struct raspberrypi_clk *rpi) -+{ -+ u32 min_rate = 0, max_rate = 0; -+ struct clk_init_data init; -+ int ret; -+ -+ memset(&init, 0, sizeof(init)); -+ -+ /* All of the PLLs derive from the external oscillator. */ -+ init.parent_names = (const char *[]){ "osc" }; -+ init.num_parents = 1; -+ init.name = "pllb"; -+ init.ops = &raspberrypi_firmware_pll_clk_ops; -+ init.flags = CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED; -+ -+ /* Get min & max rates set by the firmware */ -+ ret = raspberrypi_clock_property(rpi->firmware, -+ RPI_FIRMWARE_GET_MIN_CLOCK_RATE, -+ RPI_FIRMWARE_ARM_CLK_ID, -+ &min_rate); -+ if (ret) { -+ dev_err(rpi->dev, "Failed to get %s min freq: %d\n", -+ init.name, ret); -+ return ret; -+ } -+ -+ ret = raspberrypi_clock_property(rpi->firmware, -+ RPI_FIRMWARE_GET_MAX_CLOCK_RATE, -+ RPI_FIRMWARE_ARM_CLK_ID, -+ &max_rate); -+ if (ret) { -+ dev_err(rpi->dev, "Failed to get %s max freq: %d\n", -+ init.name, ret); -+ return ret; -+ } -+ -+ if (!min_rate || !max_rate) { -+ dev_err(rpi->dev, "Unexpected frequency range: min %u, max %u\n", -+ min_rate, max_rate); -+ return -EINVAL; -+ } -+ -+ dev_info(rpi->dev, "CPU frequency range: min %u, max %u\n", -+ min_rate, max_rate); -+ -+ rpi->min_rate = min_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE; -+ rpi->max_rate = max_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE; -+ -+ rpi->pllb.init = &init; -+ -+ return devm_clk_hw_register(rpi->dev, &rpi->pllb); -+} -+ -+static int raspberrypi_register_pllb_arm(struct raspberrypi_clk *rpi) -+{ -+ rpi->pllb_arm = clk_hw_register_fixed_factor(rpi->dev, -+ "pllb_arm", "pllb", -+ CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, -+ 1, 2); -+ if (IS_ERR(rpi->pllb_arm)) { -+ dev_err(rpi->dev, "Failed to initialize pllb_arm\n"); -+ return PTR_ERR(rpi->pllb_arm); -+ } -+ -+ rpi->pllb_arm_lookup = clkdev_hw_create(rpi->pllb_arm, NULL, "cpu0"); -+ if (!rpi->pllb_arm_lookup) { -+ dev_err(rpi->dev, "Failed to initialize pllb_arm_lookup\n"); -+ clk_hw_unregister_fixed_factor(rpi->pllb_arm); -+ return -ENOMEM; -+ } -+ -+ return 0; -+} -+ -+static int raspberrypi_clk_probe(struct platform_device *pdev) -+{ -+ struct device_node *firmware_node; -+ struct device *dev = &pdev->dev; -+ struct rpi_firmware *firmware; -+ struct raspberrypi_clk *rpi; -+ int ret; -+ -+ firmware_node = of_find_compatible_node(NULL, NULL, -+ "raspberrypi,bcm2835-firmware"); -+ if (!firmware_node) { -+ dev_err(dev, "Missing firmware node\n"); -+ return -ENOENT; -+ } -+ -+ firmware = rpi_firmware_get(firmware_node); -+ of_node_put(firmware_node); -+ if (!firmware) -+ return -EPROBE_DEFER; -+ -+ rpi = devm_kzalloc(dev, sizeof(*rpi), GFP_KERNEL); -+ if (!rpi) -+ return -ENOMEM; -+ -+ rpi->dev = dev; -+ rpi->firmware = firmware; -+ -+ ret = raspberrypi_register_pllb(rpi); -+ if (ret) { -+ dev_err(dev, "Failed to initialize pllb, %d\n", ret); -+ return ret; -+ } -+ -+ ret = raspberrypi_register_pllb_arm(rpi); -+ if (ret) -+ return ret; -+ -+ return 0; -+} -+ -+static struct platform_driver raspberrypi_clk_driver = { -+ .driver = { -+ .name = "raspberrypi-clk", -+ }, -+ .probe = raspberrypi_clk_probe, -+}; -+module_platform_driver(raspberrypi_clk_driver); -+ -+MODULE_AUTHOR("Nicolas Saenz Julienne "); -+MODULE_DESCRIPTION("Raspberry Pi firmware clock driver"); -+MODULE_LICENSE("GPL"); -+MODULE_ALIAS("platform:raspberrypi-clk"); --- -2.21.0 - -From e750e62addb9ee00f47ab4a73c0645d44172ab12 Mon Sep 17 00:00:00 2001 -From: Nicolas Saenz Julienne -Date: Tue, 11 Jun 2019 19:58:38 +0200 -Subject: [PATCH 3/5] firmware: raspberrypi: register clk device - -Since clk-raspberrypi is tied to the VC4 firmware instead of particular -hardware it's registration should be performed by the firmware driver. - -Signed-off-by: Nicolas Saenz Julienne -Acked-by: Eric Anholt ---- - drivers/firmware/raspberrypi.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/drivers/firmware/raspberrypi.c b/drivers/firmware/raspberrypi.c -index 61be15d9df7d..da26a584dca0 100644 ---- a/drivers/firmware/raspberrypi.c -+++ b/drivers/firmware/raspberrypi.c -@@ -20,6 +20,7 @@ - #define MBOX_CHAN_PROPERTY 8 - - static struct platform_device *rpi_hwmon; -+static struct platform_device *rpi_clk; - - struct rpi_firmware { - struct mbox_client cl; -@@ -207,6 +208,12 @@ rpi_register_hwmon_driver(struct device *dev, struct rpi_firmware *fw) - -1, NULL, 0); - } - -+static void rpi_register_clk_driver(struct device *dev) -+{ -+ rpi_clk = platform_device_register_data(dev, "raspberrypi-clk", -+ -1, NULL, 0); -+} -+ - static int rpi_firmware_probe(struct platform_device *pdev) - { - struct device *dev = &pdev->dev; -@@ -234,6 +241,7 @@ static int rpi_firmware_probe(struct platform_device *pdev) - - rpi_firmware_print_firmware_revision(fw); - rpi_register_hwmon_driver(dev, fw); -+ rpi_register_clk_driver(dev); - - return 0; - } -@@ -254,6 +262,8 @@ static int rpi_firmware_remove(struct platform_device *pdev) - - platform_device_unregister(rpi_hwmon); - rpi_hwmon = NULL; -+ platform_device_unregister(rpi_clk); -+ rpi_clk = NULL; - mbox_free_channel(fw->chan); - - return 0; --- -2.21.0 - -From af32d83d10976ff357c56adba79fa3cb06e1c32d Mon Sep 17 00:00:00 2001 -From: Nicolas Saenz Julienne -Date: Tue, 11 Jun 2019 19:58:42 +0200 -Subject: [PATCH 5/5] clk: raspberrypi: register platform device for - raspberrypi-cpufreq - -As 'clk-raspberrypi' depends on RPi's firmware interface, which might be -configured as a module, the cpu clock might not be available for the -cpufreq driver during it's init process. So we register the -'raspberrypi-cpufreq' platform device after the probe sequence succeeds. - -Signed-off-by: Nicolas Saenz Julienne -Acked-by: Eric Anholt ---- - drivers/clk/bcm/clk-raspberrypi.c | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - -diff --git a/drivers/clk/bcm/clk-raspberrypi.c b/drivers/clk/bcm/clk-raspberrypi.c -index 467933767106..7f9b001f8d70 100644 ---- a/drivers/clk/bcm/clk-raspberrypi.c -+++ b/drivers/clk/bcm/clk-raspberrypi.c -@@ -34,6 +34,7 @@ - struct raspberrypi_clk { - struct device *dev; - struct rpi_firmware *firmware; -+ struct platform_device *cpufreq; - - unsigned long min_rate; - unsigned long max_rate; -@@ -272,6 +273,7 @@ static int raspberrypi_clk_probe(struct platform_device *pdev) - - rpi->dev = dev; - rpi->firmware = firmware; -+ platform_set_drvdata(pdev, rpi); - - ret = raspberrypi_register_pllb(rpi); - if (ret) { -@@ -283,6 +285,18 @@ static int raspberrypi_clk_probe(struct platform_device *pdev) - if (ret) - return ret; - -+ rpi->cpufreq = platform_device_register_data(dev, "raspberrypi-cpufreq", -+ -1, NULL, 0); -+ -+ return 0; -+} -+ -+static int raspberrypi_clk_remove(struct platform_device *pdev) -+{ -+ struct raspberrypi_clk *rpi = platform_get_drvdata(pdev); -+ -+ platform_device_unregister(rpi->cpufreq); -+ - return 0; - } - -@@ -291,6 +305,7 @@ static struct platform_driver raspberrypi_clk_driver = { - .name = "raspberrypi-clk", - }, - .probe = raspberrypi_clk_probe, -+ .remove = raspberrypi_clk_remove, - }; - module_platform_driver(raspberrypi_clk_driver); - --- -2.21.0 - diff --git a/arm64-dts-rockchip-Update-DWC3-modules-on-RK3399-SoCs.patch b/arm64-dts-rockchip-Update-DWC3-modules-on-RK3399-SoCs.patch deleted file mode 100644 index c5ce675d4..000000000 --- a/arm64-dts-rockchip-Update-DWC3-modules-on-RK3399-SoCs.patch +++ /dev/null @@ -1,145 +0,0 @@ -From patchwork Thu Jun 13 16:27:45 2019 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Enric Balletbo i Serra -X-Patchwork-Id: 10992783 -Return-Path: - -Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org - [172.30.200.125]) - by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3C69976 - for ; - Thu, 13 Jun 2019 16:31:35 +0000 (UTC) -Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) - by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2A407202A5 - for ; - Thu, 13 Jun 2019 16:31:35 +0000 (UTC) -Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) - id 1E11D205F8; Thu, 13 Jun 2019 16:31:35 +0000 (UTC) -X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on - pdx-wl-mail.web.codeaurora.org -X-Spam-Level: -X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, - DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,UNPARSEABLE_RELAY - autolearn=ham version=3.3.1 -Received: from bombadil.infradead.org (bombadil.infradead.org - [198.137.202.133]) - (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E8E5E26253 - for ; - Thu, 13 Jun 2019 16:31:32 +0000 (UTC) -DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; - d=lists.infradead.org; s=bombadil.20170209; h=Sender: - Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: - List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To - :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: - Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: - List-Owner; bh=DvpejaNT4eBhDns4FxJHLSG+zmWCjPWj3DUJGU1HA+0=; b=U5HR+BVOuAC/E8 - nFHo3NNnf/apQ+ctinRwRfb2KfTsAUb7ZUpIl54fuCw/9GaxhMVGPvViCELEYZSqU3In+Fo3+hP3s - kMyQxkFXCOuAawwfHbC5O/B5rW4mu3/wtmY6WU8/7j0+z295Xf6bcbL61ViJl004E6RRiw+o3AvsX - k5tb581Re61dLl+MWGJETzSUGZZl9OzPmwJiQ2MrQltCsHWXJM4Q+PjSa/figIf9yD8w3MUbDmtfX - Cj28FmfT2DfWi2kNlitMG7EqEvpPnc51G2u3JVUOnj1/C2UkRjWqMkbyLlzDAnqntyXFKePRDd2Uq - I2tA62mw1OY4IxFiP+Qw==; -Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) - by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) - id 1hbSdK-00080h-F1; Thu, 13 Jun 2019 16:31:26 +0000 -Received: from bhuna.collabora.co.uk ([46.235.227.227]) - by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) - id 1hbSZw-00036Y-Gr; Thu, 13 Jun 2019 16:27:58 +0000 -Received: from [127.0.0.1] (localhost [127.0.0.1]) - (Authenticated sender: eballetbo) with ESMTPSA id 2E34F27D7A1 -From: Enric Balletbo i Serra -To: devicetree@vger.kernel.org -Subject: [PATCH] arm64: dts: rockchip: Update DWC3 modules on RK3399 SoCs -Date: Thu, 13 Jun 2019 18:27:45 +0200 -Message-Id: <20190613162745.12195-1-enric.balletbo@collabora.com> -X-Mailer: git-send-email 2.20.1 -MIME-Version: 1.0 -X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 -X-CRM114-CacheID: sfid-20190613_092756_843034_D5C41B2D -X-CRM114-Status: GOOD ( 10.09 ) -X-BeenThere: linux-arm-kernel@lists.infradead.org -X-Mailman-Version: 2.1.29 -Precedence: list -List-Id: -List-Unsubscribe: - , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: - , - -Cc: Mark Rutland , Heiko Stuebner , - Felipe Balbi , - linux-rockchip@lists.infradead.org, Tony Xie , - Viresh Kumar , Randy Li , - linux-kernel@vger.kernel.org, Vicente Bergas , - Masahiro Yamada , - Rob Herring , - Klaus Goger , - Matthias Brugger , - Collabora Kernel ML , - linux-arm-kernel@lists.infradead.org, - Christoph Muellner -Content-Type: text/plain; charset="us-ascii" -Sender: "linux-arm-kernel" -Errors-To: - linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org -X-Virus-Scanned: ClamAV using ClamSMTP - -As per binding documentation [1], the DWC3 core should have the "ref", -"bus_early" and "suspend" clocks. As explained in the binding, those -clocks are required for new platforms but not for existing platforms -before commit fe8abf332b8f ("usb: dwc3: support clocks and resets for -DWC3 core"). - -However, as those clocks are really treated as required, this ends with -having some annoying messages when the "rockchip,rk3399-dwc3" is used: - -[ 1.724107] dwc3 fe800000.dwc3: Failed to get clk 'ref': -2 -[ 1.731893] dwc3 fe900000.dwc3: Failed to get clk 'ref': -2 -[ 2.495937] dwc3 fe800000.dwc3: Failed to get clk 'ref': -2 -[ 2.647239] dwc3 fe900000.dwc3: Failed to get clk 'ref': -2 - -In order to remove those annoying messages, update the DWC3 hardware -module node and add all the required clocks. With this change, both, the -glue node and the DWC3 core node, have the clocks defined, but that's -not really a problem and there isn't a side effect on do this. So, we -can get rid of the annoying get clk error messages. - -[1] Documentation/devicetree/bindings/usb/dwc3.txt - -Signed-off-by: Enric Balletbo i Serra ---- - - arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 196ac9b78076..a15348d185ce 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -414,6 +414,9 @@ - compatible = "snps,dwc3"; - reg = <0x0 0xfe800000 0x0 0x100000>; - interrupts = ; -+ clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>, -+ <&cru SCLK_USB3OTG0_SUSPEND>; -+ clock-names = "ref", "bus_early", "suspend"; - dr_mode = "otg"; - phys = <&u2phy0_otg>, <&tcphy0_usb3>; - phy-names = "usb2-phy", "usb3-phy"; -@@ -447,6 +450,9 @@ - compatible = "snps,dwc3"; - reg = <0x0 0xfe900000 0x0 0x100000>; - interrupts = ; -+ clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>, -+ <&cru SCLK_USB3OTG1_SUSPEND>; -+ clock-names = "ref", "bus_early", "suspend"; - dr_mode = "otg"; - phys = <&u2phy1_otg>, <&tcphy1_usb3>; - phy-names = "usb2-phy", "usb3-phy"; diff --git a/kernel.spec b/kernel.spec index 9211ceb1e..e94f8e79d 100644 --- a/kernel.spec +++ b/kernel.spec @@ -538,34 +538,26 @@ Patch212: efi-secureboot.patch # 300 - ARM patches Patch300: arm64-Add-option-of-13-for-FORCE_MAX_ZONEORDER.patch -# http://www.spinics.net/lists/linux-tegra/msg26029.html -Patch301: usb-phy-tegra-Add-38.4MHz-clock-table-entry.patch -# http://patchwork.ozlabs.org/patch/587554/ -Patch302: ARM-tegra-usb-no-reset.patch +# RHBZ Bug 1576593 - work around while vendor investigates +Patch301: arm-make-highpte-not-expert.patch # https://patchwork.kernel.org/patch/10351797/ -Patch303: ACPI-scan-Fix-regression-related-to-X-Gene-UARTs.patch +Patch302: ACPI-scan-Fix-regression-related-to-X-Gene-UARTs.patch # rhbz 1574718 -Patch304: ACPI-irq-Workaround-firmware-issue-on-X-Gene-based-m400.patch +Patch303: ACPI-irq-Workaround-firmware-issue-on-X-Gene-based-m400.patch + +# http://www.spinics.net/lists/linux-tegra/msg26029.html +Patch304: usb-phy-tegra-Add-38.4MHz-clock-table-entry.patch +# http://patchwork.ozlabs.org/patch/587554/ +Patch305: ARM-tegra-usb-no-reset.patch # https://patchwork.kernel.org/project/linux-mmc/list/?submitter=71861 -Patch305: arm-sdhci-esdhc-imx-fixes.patch - -# Fix accepted for 5.3 https://patchwork.kernel.org/patch/10992783/ -# Patch306: arm64-dts-rockchip-Update-DWC3-modules-on-RK3399-SoCs.patch - -# RHBZ Bug 1576593 - work around while vendor investigates -Patch307: arm-make-highpte-not-expert.patch - -# Raspberry Pi bits -# Patch330: ARM-cpufreq-support-for-Raspberry-Pi.patch +Patch306: arm-sdhci-esdhc-imx-fixes.patch # Tegra bits -Patch340: arm64-tegra-jetson-tx1-fixes.patch +Patch320: arm64-tegra-jetson-tx1-fixes.patch # https://www.spinics.net/lists/linux-tegra/msg43110.html -Patch341: arm64-tegra-Jetson-TX2-Allow-bootloader-to-configure.patch - -# QCom ACPI device support pieces +Patch321: arm64-tegra-Jetson-TX2-Allow-bootloader-to-configure.patch # 400 - IBM (ppc/s390x) patches From cf82a100d1e32240b0c4266cbc57c7839d233f48 Mon Sep 17 00:00:00 2001 From: Laura Abbott Date: Mon, 26 Aug 2019 08:08:12 -0400 Subject: [PATCH 2/3] Disable debugging options. --- kernel.spec | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/kernel.spec b/kernel.spec index e94f8e79d..333c9deb7 100644 --- a/kernel.spec +++ b/kernel.spec @@ -124,7 +124,7 @@ Summary: The Linux kernel # Set debugbuildsenabled to 1 for production (build separate debug kernels) # and 0 for rawhide (all kernels are debug kernels). # See also 'make debug' and 'make release'. -%define debugbuildsenabled 0 +%define debugbuildsenabled 1 # Kernel headers are being split out into a separate package %if 0%{?fedora} @@ -1809,6 +1809,9 @@ fi # # %changelog +* Mon Aug 26 2019 Laura Abbott +- Disable debugging options. + * Fri Aug 23 2019 Laura Abbott - 5.3.0-0.rc5.git2.1 - Linux v5.3-rc5-224-gdd469a456047 From 2fdc962749f67d7398efae07ced05753101de759 Mon Sep 17 00:00:00 2001 From: Laura Abbott Date: Mon, 26 Aug 2019 08:33:15 -0400 Subject: [PATCH 3/3] Linux v5.3-rc6 --- kernel.spec | 7 +++++-- sources | 3 +-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/kernel.spec b/kernel.spec index 333c9deb7..e7bd96641 100644 --- a/kernel.spec +++ b/kernel.spec @@ -69,9 +69,9 @@ Summary: The Linux kernel # The next upstream release sublevel (base_sublevel+1) %define upstream_sublevel %(echo $((%{base_sublevel} + 1))) # The rc snapshot level -%global rcrev 5 +%global rcrev 6 # The git snapshot level -%define gitrev 2 +%define gitrev 0 # Set rpm version accordingly %define rpmversion 5.%{upstream_sublevel}.0 %endif @@ -1809,6 +1809,9 @@ fi # # %changelog +* Mon Aug 26 2019 Laura Abbott - 5.3.0-0.rc6.git0.1 +- Linux v5.3-rc6 + * Mon Aug 26 2019 Laura Abbott - Disable debugging options. diff --git a/sources b/sources index 16be900fa..a5fbd914c 100644 --- a/sources +++ b/sources @@ -1,3 +1,2 @@ SHA512 (linux-5.2.tar.xz) = 5a28f8a34c4e0470617f5638b7112e6252109b78f23b1eed484a228530970c7ef5c130d6e5a09cf25ea2f6a0329602dcc1ec66ce893182e15b27d99bd228789c -SHA512 (patch-5.3-rc5.xz) = 9309bbcfd7f46924b983d0376a1d6b7ab0049121dffe80576d3604c3588370961bb14c3d6d45fc1ec71426cf24921f947ab893c306b6832387630f3711879623 -SHA512 (patch-5.3-rc5-git2.xz) = 9fd37c9c0e99fe55cd46f47fc31a515c8f7f900935776c5ef5b43619975b42e8a66c62a7403bf3af2d13a23343e3ed1489bb37d93212510b7f72577e3f3c0b13 +SHA512 (patch-5.3-rc6.xz) = 67863e79064488873309ac99b8691d3e9afa230900532675c8b8699768b2eba21409aceb0925dfc7e8a2403aed2b3de3d3fcd3c9fde08435cd4e4a643dc79a70