minor IrDA cleanup, add fix for Pine64 boot already in 4.14
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arm64-Revert-allwinner-a64-pine64-Use-dcdc1-regulato.patch
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41
arm64-Revert-allwinner-a64-pine64-Use-dcdc1-regulato.patch
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From 90e388ca5d8bbee022f9ed5fc24137b31579fa6e Mon Sep 17 00:00:00 2001
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From: Peter Robinson <pbrobinson@gmail.com>
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Date: Wed, 22 Nov 2017 15:52:36 +0000
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Subject: [PATCH] Revert "arm64: allwinner: a64: pine64: Use dcdc1 regulator
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for mmc0"
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This reverts commit 3f241bfa60bdc9c4fde63fa6664a8ce00fd668c6.
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 9 ++++++++-
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1 file changed, 8 insertions(+), 1 deletion(-)
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
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index d06e34b5d192..caf8b6fbe5e3 100644
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
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@@ -61,6 +61,13 @@
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chosen {
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stdout-path = "serial0:115200n8";
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};
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+
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+ reg_vcc3v3: vcc3v3 {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc3v3";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ };
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};
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&ehci0 {
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@@ -84,7 +91,7 @@
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&mmc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins>;
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- vmmc-supply = <®_dcdc1>;
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+ vmmc-supply = <®_vcc3v3>;
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cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
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cd-inverted;
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disable-wp;
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--
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2.14.3
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1
configs/base-generic/CONFIG_IR_SIR
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1
configs/base-generic/CONFIG_IR_SIR
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@ -0,0 +1 @@
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# CONFIG_IR_SIR is not set
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@ -2492,6 +2492,7 @@ CONFIG_IR_SANYO_DECODER=m
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CONFIG_IR_SERIAL=m
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CONFIG_IR_SERIAL_TRANSMITTER=y
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CONFIG_IR_SHARP_DECODER=m
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# CONFIG_IR_SIR is not set
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CONFIG_IR_SONY_DECODER=m
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CONFIG_IR_SPI=m
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CONFIG_IR_STREAMZAP=m
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@ -2475,6 +2475,7 @@ CONFIG_IR_SANYO_DECODER=m
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CONFIG_IR_SERIAL=m
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CONFIG_IR_SERIAL_TRANSMITTER=y
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CONFIG_IR_SHARP_DECODER=m
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# CONFIG_IR_SIR is not set
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CONFIG_IR_SONY_DECODER=m
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CONFIG_IR_SPI=m
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CONFIG_IR_STREAMZAP=m
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@ -2646,6 +2646,7 @@ CONFIG_IR_SANYO_DECODER=m
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CONFIG_IR_SERIAL=m
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CONFIG_IR_SERIAL_TRANSMITTER=y
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CONFIG_IR_SHARP_DECODER=m
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# CONFIG_IR_SIR is not set
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CONFIG_IR_SONY_DECODER=m
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CONFIG_IR_SPI=m
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CONFIG_IR_STREAMZAP=m
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@ -2514,6 +2514,7 @@ CONFIG_IR_SANYO_DECODER=m
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CONFIG_IR_SERIAL=m
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CONFIG_IR_SERIAL_TRANSMITTER=y
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CONFIG_IR_SHARP_DECODER=m
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# CONFIG_IR_SIR is not set
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CONFIG_IR_SONY_DECODER=m
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CONFIG_IR_SPI=m
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CONFIG_IR_STREAMZAP=m
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@ -2497,6 +2497,7 @@ CONFIG_IR_SANYO_DECODER=m
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CONFIG_IR_SERIAL=m
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CONFIG_IR_SERIAL_TRANSMITTER=y
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CONFIG_IR_SHARP_DECODER=m
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# CONFIG_IR_SIR is not set
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CONFIG_IR_SONY_DECODER=m
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CONFIG_IR_SPI=m
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CONFIG_IR_STREAMZAP=m
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@ -2629,6 +2629,7 @@ CONFIG_IR_SANYO_DECODER=m
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CONFIG_IR_SERIAL=m
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CONFIG_IR_SERIAL_TRANSMITTER=y
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CONFIG_IR_SHARP_DECODER=m
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# CONFIG_IR_SIR is not set
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CONFIG_IR_SONY_DECODER=m
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CONFIG_IR_SPI=m
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CONFIG_IR_STREAMZAP=m
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@ -2383,6 +2383,7 @@ CONFIG_IR_SANYO_DECODER=m
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CONFIG_IR_SERIAL=m
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CONFIG_IR_SERIAL_TRANSMITTER=y
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CONFIG_IR_SHARP_DECODER=m
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# CONFIG_IR_SIR is not set
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CONFIG_IR_SONY_DECODER=m
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CONFIG_IR_SPI=m
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CONFIG_IR_STREAMZAP=m
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@ -2401,6 +2401,7 @@ CONFIG_IR_SANYO_DECODER=m
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CONFIG_IR_SERIAL=m
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CONFIG_IR_SERIAL_TRANSMITTER=y
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CONFIG_IR_SHARP_DECODER=m
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# CONFIG_IR_SIR is not set
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CONFIG_IR_SONY_DECODER=m
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CONFIG_IR_SPI=m
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CONFIG_IR_STREAMZAP=m
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@ -2401,6 +2401,7 @@ CONFIG_IR_SANYO_DECODER=m
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CONFIG_IR_SERIAL=m
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CONFIG_IR_SERIAL_TRANSMITTER=y
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CONFIG_IR_SHARP_DECODER=m
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# CONFIG_IR_SIR is not set
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CONFIG_IR_SONY_DECODER=m
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CONFIG_IR_SPI=m
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CONFIG_IR_STREAMZAP=m
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@ -2383,6 +2383,7 @@ CONFIG_IR_SANYO_DECODER=m
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CONFIG_IR_SERIAL=m
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CONFIG_IR_SERIAL_TRANSMITTER=y
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CONFIG_IR_SHARP_DECODER=m
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# CONFIG_IR_SIR is not set
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CONFIG_IR_SONY_DECODER=m
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CONFIG_IR_SPI=m
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CONFIG_IR_STREAMZAP=m
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@ -2250,6 +2250,7 @@ CONFIG_IR_SANYO_DECODER=m
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CONFIG_IR_SERIAL=m
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CONFIG_IR_SERIAL_TRANSMITTER=y
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CONFIG_IR_SHARP_DECODER=m
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# CONFIG_IR_SIR is not set
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CONFIG_IR_SONY_DECODER=m
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CONFIG_IR_SPI=m
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CONFIG_IR_STREAMZAP=m
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@ -2232,6 +2232,7 @@ CONFIG_IR_SANYO_DECODER=m
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CONFIG_IR_SERIAL=m
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CONFIG_IR_SERIAL_TRANSMITTER=y
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CONFIG_IR_SHARP_DECODER=m
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# CONFIG_IR_SIR is not set
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CONFIG_IR_SONY_DECODER=m
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CONFIG_IR_SPI=m
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CONFIG_IR_STREAMZAP=m
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@ -2195,6 +2195,7 @@ CONFIG_IR_SANYO_DECODER=m
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CONFIG_IR_SERIAL=m
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CONFIG_IR_SERIAL_TRANSMITTER=y
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CONFIG_IR_SHARP_DECODER=m
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# CONFIG_IR_SIR is not set
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CONFIG_IR_SONY_DECODER=m
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CONFIG_IR_SPI=m
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CONFIG_IR_STREAMZAP=m
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@ -2177,6 +2177,7 @@ CONFIG_IR_SANYO_DECODER=m
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CONFIG_IR_SERIAL=m
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CONFIG_IR_SERIAL_TRANSMITTER=y
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CONFIG_IR_SHARP_DECODER=m
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# CONFIG_IR_SIR is not set
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CONFIG_IR_SONY_DECODER=m
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CONFIG_IR_SPI=m
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CONFIG_IR_STREAMZAP=m
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@ -2146,6 +2146,7 @@ CONFIG_IR_SANYO_DECODER=m
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CONFIG_IR_SERIAL=m
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CONFIG_IR_SERIAL_TRANSMITTER=y
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CONFIG_IR_SHARP_DECODER=m
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# CONFIG_IR_SIR is not set
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CONFIG_IR_SONY_DECODER=m
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CONFIG_IR_SPI=m
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CONFIG_IR_STREAMZAP=m
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@ -2128,6 +2128,7 @@ CONFIG_IR_SANYO_DECODER=m
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CONFIG_IR_SERIAL=m
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CONFIG_IR_SERIAL_TRANSMITTER=y
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CONFIG_IR_SHARP_DECODER=m
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# CONFIG_IR_SIR is not set
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CONFIG_IR_SONY_DECODER=m
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CONFIG_IR_SPI=m
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CONFIG_IR_STREAMZAP=m
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@ -2457,6 +2457,7 @@ CONFIG_IR_SANYO_DECODER=m
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CONFIG_IR_SERIAL=m
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CONFIG_IR_SERIAL_TRANSMITTER=y
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CONFIG_IR_SHARP_DECODER=m
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# CONFIG_IR_SIR is not set
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CONFIG_IR_SONY_DECODER=m
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CONFIG_IR_SPI=m
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CONFIG_IR_STREAMZAP=m
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@ -2439,6 +2439,7 @@ CONFIG_IR_SANYO_DECODER=m
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CONFIG_IR_SERIAL=m
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CONFIG_IR_SERIAL_TRANSMITTER=y
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CONFIG_IR_SHARP_DECODER=m
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# CONFIG_IR_SIR is not set
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CONFIG_IR_SONY_DECODER=m
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CONFIG_IR_SPI=m
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CONFIG_IR_STREAMZAP=m
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@ -591,6 +591,8 @@ Patch305: arm-imx6-hummingboard2.patch
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Patch306: arm64-Add-option-of-13-for-FORCE_MAX_ZONEORDER.patch
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Patch307: arm64-Revert-allwinner-a64-pine64-Use-dcdc1-regulato.patch
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# https://patchwork.kernel.org/patch/9820417/
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Patch310: qcom-msm89xx-fixes.patch
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