minor IrDA cleanup, add fix for Pine64 boot already in 4.14

This commit is contained in:
Peter Robinson 2017-12-06 04:33:38 +00:00
parent 9e9be214f5
commit bd6ba47fb1
21 changed files with 62 additions and 0 deletions

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@ -0,0 +1,41 @@
From 90e388ca5d8bbee022f9ed5fc24137b31579fa6e Mon Sep 17 00:00:00 2001
From: Peter Robinson <pbrobinson@gmail.com>
Date: Wed, 22 Nov 2017 15:52:36 +0000
Subject: [PATCH] Revert "arm64: allwinner: a64: pine64: Use dcdc1 regulator
for mmc0"
This reverts commit 3f241bfa60bdc9c4fde63fa6664a8ce00fd668c6.
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index d06e34b5d192..caf8b6fbe5e3 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -61,6 +61,13 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
};
&ehci0 {
@@ -84,7 +91,7 @@
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
- vmmc-supply = <&reg_dcdc1>;
+ vmmc-supply = <&reg_vcc3v3>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
disable-wp;
--
2.14.3

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@ -0,0 +1 @@
# CONFIG_IR_SIR is not set

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@ -2492,6 +2492,7 @@ CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_SHARP_DECODER=m
# CONFIG_IR_SIR is not set
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_SPI=m
CONFIG_IR_STREAMZAP=m

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@ -2475,6 +2475,7 @@ CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_SHARP_DECODER=m
# CONFIG_IR_SIR is not set
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_SPI=m
CONFIG_IR_STREAMZAP=m

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@ -2646,6 +2646,7 @@ CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_SHARP_DECODER=m
# CONFIG_IR_SIR is not set
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_SPI=m
CONFIG_IR_STREAMZAP=m

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@ -2514,6 +2514,7 @@ CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_SHARP_DECODER=m
# CONFIG_IR_SIR is not set
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_SPI=m
CONFIG_IR_STREAMZAP=m

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@ -2497,6 +2497,7 @@ CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_SHARP_DECODER=m
# CONFIG_IR_SIR is not set
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_SPI=m
CONFIG_IR_STREAMZAP=m

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@ -2629,6 +2629,7 @@ CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_SHARP_DECODER=m
# CONFIG_IR_SIR is not set
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_SPI=m
CONFIG_IR_STREAMZAP=m

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@ -2383,6 +2383,7 @@ CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_SHARP_DECODER=m
# CONFIG_IR_SIR is not set
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_SPI=m
CONFIG_IR_STREAMZAP=m

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@ -2401,6 +2401,7 @@ CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_SHARP_DECODER=m
# CONFIG_IR_SIR is not set
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_SPI=m
CONFIG_IR_STREAMZAP=m

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@ -2401,6 +2401,7 @@ CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_SHARP_DECODER=m
# CONFIG_IR_SIR is not set
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_SPI=m
CONFIG_IR_STREAMZAP=m

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@ -2383,6 +2383,7 @@ CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_SHARP_DECODER=m
# CONFIG_IR_SIR is not set
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_SPI=m
CONFIG_IR_STREAMZAP=m

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@ -2250,6 +2250,7 @@ CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_SHARP_DECODER=m
# CONFIG_IR_SIR is not set
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_SPI=m
CONFIG_IR_STREAMZAP=m

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@ -2232,6 +2232,7 @@ CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_SHARP_DECODER=m
# CONFIG_IR_SIR is not set
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_SPI=m
CONFIG_IR_STREAMZAP=m

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@ -2195,6 +2195,7 @@ CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_SHARP_DECODER=m
# CONFIG_IR_SIR is not set
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_SPI=m
CONFIG_IR_STREAMZAP=m

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@ -2177,6 +2177,7 @@ CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_SHARP_DECODER=m
# CONFIG_IR_SIR is not set
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_SPI=m
CONFIG_IR_STREAMZAP=m

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@ -2146,6 +2146,7 @@ CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_SHARP_DECODER=m
# CONFIG_IR_SIR is not set
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_SPI=m
CONFIG_IR_STREAMZAP=m

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@ -2128,6 +2128,7 @@ CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_SHARP_DECODER=m
# CONFIG_IR_SIR is not set
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_SPI=m
CONFIG_IR_STREAMZAP=m

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@ -2457,6 +2457,7 @@ CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_SHARP_DECODER=m
# CONFIG_IR_SIR is not set
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_SPI=m
CONFIG_IR_STREAMZAP=m

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@ -2439,6 +2439,7 @@ CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_SHARP_DECODER=m
# CONFIG_IR_SIR is not set
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_SPI=m
CONFIG_IR_STREAMZAP=m

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@ -591,6 +591,8 @@ Patch305: arm-imx6-hummingboard2.patch
Patch306: arm64-Add-option-of-13-for-FORCE_MAX_ZONEORDER.patch
Patch307: arm64-Revert-allwinner-a64-pine64-Use-dcdc1-regulato.patch
# https://patchwork.kernel.org/patch/9820417/
Patch310: qcom-msm89xx-fixes.patch