diff --git a/kernel-riscv64-debug-fedora.config b/kernel-riscv64-debug-fedora.config index bb740bf8f..71b7dcb8a 100644 --- a/kernel-riscv64-debug-fedora.config +++ b/kernel-riscv64-debug-fedora.config @@ -119,6 +119,7 @@ CONFIG_AD7292=m CONFIG_AD7293=m # CONFIG_AD7298 is not set # CONFIG_AD7303 is not set +# CONFIG_AD7380 is not set CONFIG_AD74115=m CONFIG_AD74413R=m # CONFIG_AD7476 is not set @@ -192,7 +193,7 @@ CONFIG_ADXL372_I2C=m CONFIG_ADXL372_SPI=m CONFIG_ADXRS290=m # CONFIG_ADXRS450 is not set -# CONFIG_AF8133J is not set +CONFIG_AF8133J=m # CONFIG_AFE4403 is not set # CONFIG_AFE4404 is not set CONFIG_AFFS_FS=m @@ -317,7 +318,6 @@ CONFIG_ARM_CMN=m # CONFIG_ARM_MHU is not set # CONFIG_ARM_MHU_V2 is not set # CONFIG_ARM_MHU_V3 is not set -CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y CONFIG_ARM_PTDUMP_DEBUGFS=y # CONFIG_ARM_SCMI_TRANSPORT_MAILBOX is not set # CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set @@ -470,6 +470,7 @@ CONFIG_BACKLIGHT_KTD253=m # CONFIG_BACKLIGHT_KTD2801 is not set CONFIG_BACKLIGHT_KTZ8866=m CONFIG_BACKLIGHT_LED=m +# CONFIG_BACKLIGHT_LM3509 is not set # CONFIG_BACKLIGHT_LM3630A is not set # CONFIG_BACKLIGHT_LM3639 is not set CONFIG_BACKLIGHT_LP855X=m @@ -505,6 +506,7 @@ CONFIG_BATTERY_CW2015=m # CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_MAX1720X is not set # CONFIG_BATTERY_MAX1721X is not set CONFIG_BATTERY_RT5033=m CONFIG_BATTERY_SAMSUNG_SDI=y @@ -889,6 +891,7 @@ CONFIG_CHARGER_BQ2515X=m CONFIG_CHARGER_BQ256XX=m # CONFIG_CHARGER_BQ25890 is not set # CONFIG_CHARGER_BQ25980 is not set +CONFIG_CHARGER_CROS_CONTROL=m CONFIG_CHARGER_CROS_PCHG=m # CONFIG_CHARGER_CROS_USBPD is not set # CONFIG_CHARGER_DETECTOR_MAX14656 is not set @@ -957,6 +960,7 @@ CONFIG_CLK_KUNIT_TEST=m CONFIG_CLK_SIFIVE_PRCI=y CONFIG_CLK_SIFIVE=y CONFIG_CLK_SOPHGO_CV1800=y +CONFIG_CLK_SOPHGO_SG2042_PLL=y # CONFIG_CLK_SP810 is not set CONFIG_CLK_STARFIVE_JH7100_AUDIO=m CONFIG_CLK_STARFIVE_JH7100=y @@ -972,6 +976,7 @@ CONFIG_CLK_STARFIVE_JH71X0=y # CONFIG_CLK_SUNXI_PRCM_SUN6I is not set # CONFIG_CLK_SUNXI_PRCM_SUN8I is not set # CONFIG_CLK_SUNXI_PRCM_SUN9I is not set +CONFIG_CLK_THEAD_TH1520_AP=y CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100 CONFIG_CLS_U32_MARK=y CONFIG_CLS_U32_PERF=y @@ -998,6 +1003,8 @@ CONFIG_CODA_FS=m CONFIG_COMMAND_LINE_SIZE=4096 CONFIG_COMMON_CLK_AXG_AUDIO=y CONFIG_COMMON_CLK_AXI_CLKGEN=m +CONFIG_COMMON_CLK_C3_PERIPHERALS=y +CONFIG_COMMON_CLK_C3_PLL=y # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CDCE925 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set @@ -1025,6 +1032,7 @@ CONFIG_COMPAT_32BIT_TIME=y # CONFIG_COMPAT_BRK is not set # CONFIG_COMPAT is not set # CONFIG_COMPILE_TEST is not set +# CONFIG_COMPRESSED_INSTALL is not set CONFIG_CONFIGFS_FS=y CONFIG_CONNECTOR=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 @@ -1266,6 +1274,7 @@ CONFIG_CXL_PMEM=m CONFIG_CXL_PMU=m # CONFIG_CXL_REGION_INVALIDATION_TEST is not set CONFIG_CXL_REGION=y +# CONFIG_CZNIC_PLATFORMS is not set CONFIG_DA280=m CONFIG_DA311=m CONFIG_DA9063_WATCHDOG=m @@ -1382,6 +1391,7 @@ CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 # CONFIG_DEFAULT_SECURITY_DAC is not set CONFIG_DEFAULT_SECURITY_SELINUX=y # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +CONFIG_DELL_PC=m CONFIG_DETECT_HUNG_TASK=y CONFIG_DEV_DAX_CXL=m CONFIG_DEV_DAX_HMEM=m @@ -1460,6 +1470,7 @@ CONFIG_DM_UNSTRIPED=m CONFIG_DM_VDO=m CONFIG_DM_VERITY_FEC=y CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_WRITECACHE=m @@ -1493,6 +1504,7 @@ CONFIG_DRM_AMDGPU=m CONFIG_DRM_AMDGPU_SI=y CONFIG_DRM_AMDGPU_USERPTR=y # CONFIG_DRM_AMDGPU_WERROR is not set +# CONFIG_DRM_AMD_ISP is not set CONFIG_DRM_AMD_SECURE_DISPLAY=y CONFIG_DRM_ANALOGIX_ANX6345=m CONFIG_DRM_ANALOGIX_ANX7625=m @@ -1532,6 +1544,7 @@ CONFIG_DRM_I2C_CH7006=m # CONFIG_DRM_I2C_NXP_TDA9950 is not set # CONFIG_DRM_I2C_NXP_TDA998X is not set CONFIG_DRM_I2C_SIL164=m +# CONFIG_DRM_I915_REPLAY_GPU_HANGS_API is not set # CONFIG_DRM_IMX_LCDIF is not set CONFIG_DRM_ITE_IT6505=m # CONFIG_DRM_ITE_IT66121 is not set @@ -1572,11 +1585,13 @@ CONFIG_DRM_PANEL_DSI_CM=m CONFIG_DRM_PANEL_ELIDA_KD35T133=m CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m +# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set # CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set CONFIG_DRM_PANEL_ILITEK_ILI9882T=m CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m @@ -1592,6 +1607,7 @@ CONFIG_DRM_PANEL_JDI_R63452=m # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_LG_SW43408 is not set +# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set # CONFIG_DRM_PANEL_LVDS is not set CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966=m CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m @@ -1887,6 +1903,7 @@ CONFIG_ENCRYPTED_KEYS=y # CONFIG_ENCX24J600 is not set CONFIG_ENERGY_MODEL=y CONFIG_ENIC=m +# CONFIG_ENS160 is not set CONFIG_ENVELOPE_DETECTOR=m CONFIG_EPIC100=m CONFIG_EPOLL=y @@ -2015,6 +2032,7 @@ CONFIG_FB_EFI=y # CONFIG_FB_METRONOME is not set CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_NEOMAGIC is not set +# CONFIG_FBNIC is not set # CONFIG_FB_NVIDIA is not set # CONFIG_FB_OF is not set # CONFIG_FB_OPENCORES is not set @@ -2054,7 +2072,9 @@ CONFIG_FILE_LOCKING=y # CONFIG_FIND_BIT_BENCHMARK is not set # CONFIG_FIPS_SIGNATURE_SELFTEST is not set # CONFIG_FIREWIRE is not set +CONFIG_FIREWIRE_KUNIT_OHCI_SERDES_TEST=m CONFIG_FIREWIRE_KUNIT_PACKET_SERDES_TEST=m +CONFIG_FIREWIRE_KUNIT_SELF_ID_SEQUENCE_HELPER_TEST=m # CONFIG_FIREWIRE_NOSY is not set # CONFIG_FIRMWARE_EDID is not set # CONFIG_FIRMWARE_MEMMAP is not set @@ -2111,6 +2131,7 @@ CONFIG_FS_ENCRYPTION=y # CONFIG_FSL_ENETC is not set # CONFIG_FSL_ENETC_MDIO is not set # CONFIG_FSL_ENETC_VF is not set +# CONFIG_FSL_IFC is not set # CONFIG_FSL_PQ_MDIO is not set # CONFIG_FSL_QDMA is not set # CONFIG_FSL_RCPM is not set @@ -2255,6 +2276,7 @@ CONFIG_GPIO_PCI_IDIO_16=m # CONFIG_GPIO_SCH311X is not set CONFIG_GPIO_SIFIVE=y CONFIG_GPIO_SIM=m +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set CONFIG_GPIO_SYSCON=m # CONFIG_GPIO_SYSFS is not set # CONFIG_GPIO_TPIC2810 is not set @@ -2262,6 +2284,7 @@ CONFIG_GPIO_TPS65219=m # CONFIG_GPIO_TS4900 is not set # CONFIG_GPIO_VIPERBOARD is not set CONFIG_GPIO_VIRTIO=m +# CONFIG_GPIO_VIRTUSER is not set # CONFIG_GPIO_WATCHDOG is not set # CONFIG_GPIO_WINBOND is not set CONFIG_GPIO_WM8994=m @@ -2608,6 +2631,7 @@ CONFIG_ICPLUS_PHY=m # CONFIG_IDLE_INJECT is not set CONFIG_IDLE_PAGE_TRACKING=y CONFIG_IDPF=m +# CONFIG_IDPF_SINGLEQ is not set CONFIG_IEEE802154_6LOWPAN=m CONFIG_IEEE802154_ADF7242=m # CONFIG_IEEE802154_AT86RF230_DEBUGFS is not set @@ -2836,6 +2860,7 @@ CONFIG_INTEL_IDXD=m # CONFIG_INTEL_ISHTP_ECLITE is not set # CONFIG_INTEL_LDMA is not set # CONFIG_INTEL_MEI_PXP is not set +# CONFIG_INTEL_PLR_TPMI is not set # CONFIG_INTEL_PMT_CLASS is not set # CONFIG_INTEL_PMT_CRASHLOG is not set # CONFIG_INTEL_PMT_TELEMETRY is not set @@ -3166,6 +3191,7 @@ CONFIG_KASAN=y CONFIG_KDB_CONTINUE_CATASTROPHIC=0 CONFIG_KDB_DEFAULT_ENABLE=0x0 CONFIG_KDB_KEYBOARD=y +# CONFIG_KEBA_CP500 is not set # CONFIG_KERNEL_BZIP2 is not set CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_LZ4 is not set @@ -3264,6 +3290,7 @@ CONFIG_L2TP=m CONFIG_L2TP_V3=y CONFIG_LAN743X=m CONFIG_LAN966X_DCB=y +# CONFIG_LAN966X_OIC is not set CONFIG_LAN966X_SWITCH=m # CONFIG_LAPB is not set CONFIG_LATENCYTOP=y @@ -3303,6 +3330,7 @@ CONFIG_LEDS_CLASS_MULTICOLOR=m CONFIG_LEDS_CLASS=y CONFIG_LEDS_CLEVO_MAIL=m CONFIG_LEDS_CR0014114=m +CONFIG_LEDS_CROS_EC=m # CONFIG_LEDS_DAC124S085 is not set # CONFIG_LEDS_EL15203000 is not set CONFIG_LEDS_GPIO=m @@ -3345,6 +3373,7 @@ CONFIG_LEDS_REGULATOR=m # CONFIG_LEDS_RT8515 is not set # CONFIG_LEDS_SGM3140 is not set # CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_SY7802 is not set CONFIG_LEDS_SYSCON=y # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TI_LMU_COMMON is not set @@ -3358,6 +3387,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m +# CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set CONFIG_LEDS_TRIGGER_MTD=y CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_ONESHOT=m @@ -3492,6 +3522,7 @@ CONFIG_MANTIS_CORE=m CONFIG_MARVELL_10G_PHY=m CONFIG_MARVELL_88Q2XXX_PHY=m CONFIG_MARVELL_88X2222_PHY=m +# CONFIG_MARVELL_CN10K_DPI is not set CONFIG_MARVELL_PHY=m # CONFIG_MATOM is not set # CONFIG_MAX1027 is not set @@ -3610,11 +3641,13 @@ CONFIG_MEGARAID_SAS=m CONFIG_MELLANOX_PLATFORM=y # CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_MEMCG_SWAP=y +# CONFIG_MEMCG_V1 is not set CONFIG_MEMCG=y CONFIG_MEMCPY_KUNIT_TEST=m CONFIG_MEMCPY_SLOW_KUNIT_TEST=y CONFIG_MEMORY_FAILURE=y # CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE is not set +CONFIG_MEMORY_HOTPLUG=y # CONFIG_MEMORY is not set # CONFIG_MEMSTICK_DEBUG is not set CONFIG_MEMSTICK_JMICRON_38X=m @@ -3631,6 +3664,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM886_PMIC is not set # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_ARIZONA_I2C is not set @@ -3647,6 +3681,8 @@ CONFIG_MFD_AXP20X=y CONFIG_MFD_BD9571MWV=m CONFIG_MFD_CORE=y # CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_CS40L50_I2C is not set +# CONFIG_MFD_CS40L50_SPI is not set CONFIG_MFD_CS42L43_I2C=m CONFIG_MFD_CS42L43_SDW=m # CONFIG_MFD_CS5535 is not set @@ -3710,6 +3746,7 @@ CONFIG_MFD_MAX77714=m # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD957XMUF is not set +# CONFIG_MFD_ROHM_BD96801 is not set CONFIG_MFD_RSMU_I2C=m CONFIG_MFD_RSMU_SPI=m CONFIG_MFD_RT4831=m @@ -4199,6 +4236,7 @@ CONFIG_NET_DSA_TAG_RTL8_4=m # CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set CONFIG_NET_DSA_TAG_SJA1105=m CONFIG_NET_DSA_TAG_TRAILER=m +# CONFIG_NET_DSA_TAG_VSC73XX_8021Q is not set CONFIG_NET_DSA_TAG_XRS700X=m # CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set # CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set @@ -4303,8 +4341,10 @@ CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER=y +CONFIG_NET_FLOW_LIMIT=y CONFIG_NET_FOU_IP_TUNNELS=y CONFIG_NET_FOU=m +# CONFIG_NETFS_DEBUG is not set CONFIG_NETFS_STATS=y CONFIG_NETFS_SUPPORT=m CONFIG_NET_HANDSHAKE_KUNIT_TEST=m @@ -4411,6 +4451,7 @@ CONFIG_NET_VENDOR_INTEL=y CONFIG_NET_VENDOR_LITEX=y CONFIG_NET_VENDOR_MARVELL=y CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_NET_VENDOR_META=y CONFIG_NET_VENDOR_MICREL=y CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_NET_VENDOR_MICROSEMI is not set @@ -4715,6 +4756,7 @@ CONFIG_NVME_MULTIPATH=y CONFIG_NVMEM=y CONFIG_NVME_RDMA=m CONFIG_NVME_TARGET_AUTH=y +# CONFIG_NVME_TARGET_DEBUGFS is not set CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_LOOP=m @@ -4738,6 +4780,7 @@ CONFIG_OCFS2_FS_O2CB=m # CONFIG_OCFS2_FS_STATS is not set CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m CONFIG_OCTEON_EP=m +# CONFIG_OCTEONEP_VDPA is not set CONFIG_OCTEON_EP_VF=m CONFIG_OF_FPGA_REGION=m CONFIG_OF_GPIO=y @@ -4893,6 +4936,7 @@ CONFIG_PCI_PASID=y CONFIG_PCIPCWATCHDOG=m CONFIG_PCI_PF_STUB=m CONFIG_PCI_PRI=y +CONFIG_PCI_PWRCTL_PWRSEQ=m CONFIG_PCI_QUIRKS=y # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set CONFIG_PCI_STUB=y @@ -4947,6 +4991,7 @@ CONFIG_PHY_RTK_RTD_USB3PHY=m # CONFIG_PHY_SAMSUNG_USB2 is not set # CONFIG_PHYS_RAM_BASE_FIXED is not set CONFIG_PHY_STARFIVE_JH7110_DPHY_RX=m +CONFIG_PHY_STARFIVE_JH7110_DPHY_TX=m CONFIG_PHY_STARFIVE_JH7110_PCIE=m CONFIG_PHY_STARFIVE_JH7110_USB=m # CONFIG_PHY_TUSB1210 is not set @@ -5041,6 +5086,8 @@ CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_RESET_TPS65086=y # CONFIG_POWER_RESET_VEXPRESS is not set CONFIG_POWER_RESET=y +CONFIG_POWER_SEQUENCING=m +CONFIG_POWER_SEQUENCING_QCOM_WCN=m # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y CONFIG_POWER_SUPPLY=y @@ -5144,10 +5191,12 @@ CONFIG_PTP_DFL_TOD=m # CONFIG_PVPANIC_PCI is not set CONFIG_PVPANIC=y # CONFIG_PWM_ATMEL_TCB is not set +# CONFIG_PWM_AXI_PWMGEN is not set # CONFIG_PWM_CLK is not set # CONFIG_PWM_DEBUG is not set CONFIG_PWM_DWC=m # CONFIG_PWM_FSL_FTM is not set +CONFIG_PWM_GPIO=m CONFIG_PWM_HIBVT=m # CONFIG_PWM_MICROCHIP_CORE is not set CONFIG_PWM_OMAP_DMTIMER=m @@ -5175,6 +5224,7 @@ CONFIG_QCA83XX_PHY=m # CONFIG_QCOM_LMH is not set # CONFIG_QCOM_OCMEM is not set CONFIG_QCOM_PBS=m +# CONFIG_QCOM_PD_MAPPER is not set # CONFIG_QCOM_PMIC_GLINK is not set # CONFIG_QCOM_PMIC_PDCHARGER_ULOG is not set # CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set @@ -5224,6 +5274,7 @@ CONFIG_RADIO_WL1273=m CONFIG_RAID_ATTRS=m CONFIG_RANDOM32_SELFTEST=y CONFIG_RANDOMIZE_BASE=y +# CONFIG_RANDOMIZE_IDENTITY_BASE is not set CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y CONFIG_RANDOMIZE_KSTACK_OFFSET=y CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa @@ -5411,7 +5462,8 @@ CONFIG_RESOURCE_KUNIT_TEST=m CONFIG_RFKILL_GPIO=m CONFIG_RFKILL_INPUT=y CONFIG_RFKILL=m -# CONFIG_RH_DISABLE_DEPRECATED is not set +CONFIG_RFS_ACCEL=y +# CONFIG_RHEL_DIFFERENCES is not set CONFIG_RICHTEK_RTQ6056=m CONFIG_RING_BUFFER_BENCHMARK=m # CONFIG_RING_BUFFER_STARTUP_TEST is not set @@ -5431,10 +5483,14 @@ CONFIG_RISCV_ISA_FALLBACK=y CONFIG_RISCV_ISA_SVNAPOT=y CONFIG_RISCV_ISA_SVPBMT=y CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y +CONFIG_RISCV_ISA_VENDOR_EXT_ANDES=y CONFIG_RISCV_ISA_V_PREEMPTIVE=y CONFIG_RISCV_ISA_V_UCOPY_THRESHOLD=768 CONFIG_RISCV_ISA_V=y +CONFIG_RISCV_ISA_ZAWRS=y +CONFIG_RISCV_ISA_ZBA=y CONFIG_RISCV_ISA_ZBB=y +CONFIG_RISCV_ISA_ZBC=y CONFIG_RISCV_ISA_ZICBOM=y CONFIG_RISCV_ISA_ZICBOZ=y CONFIG_RISCV_MISALIGNED=y @@ -5485,6 +5541,7 @@ CONFIG_RPMSG_TTY=m CONFIG_RPMSG_VIRTIO=m CONFIG_RPMSG_WWAN_CTRL=m CONFIG_RPR0521=m +CONFIG_RPS=y CONFIG_RSEQ=y CONFIG_RSI_91X=m CONFIG_RSI_COEX=y @@ -5620,8 +5677,9 @@ CONFIG_RTL8180=m CONFIG_RTL8187=m CONFIG_RTL8188EE=m CONFIG_RTL8192CE=m -CONFIG_RTL8192CU=m +# CONFIG_RTL8192CU is not set CONFIG_RTL8192DE=m +# CONFIG_RTL8192DU is not set CONFIG_RTL8192EE=m CONFIG_RTL8192E=m CONFIG_RTL8192SE=m @@ -5640,6 +5698,7 @@ CONFIG_RTLLIB=m CONFIG_RTLWIFI_DEBUG=y CONFIG_RTLWIFI=m # CONFIG_RTS5208 is not set +# CONFIG_RTSN is not set CONFIG_RTW88_8723CS=m CONFIG_RTW88_8723DE=m CONFIG_RTW88_8723DS=m @@ -5666,6 +5725,7 @@ CONFIG_RTW89_DEBUGMSG=y CONFIG_RTW89=m # CONFIG_RUNTIME_KERNEL_TESTING_MENU is not set CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_RUST is not set CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PANIC=y @@ -5908,6 +5968,7 @@ CONFIG_SENSORS_BPA_RS600=m CONFIG_SENSORS_CHIPCAP2=m CONFIG_SENSORS_CORSAIR_CPRO=m CONFIG_SENSORS_CORSAIR_PSU=m +CONFIG_SENSORS_CROS_EC=m CONFIG_SENSORS_DELTA_AHE50DC_FAN=m CONFIG_SENSORS_DME1737=m CONFIG_SENSORS_DPS920AB=m @@ -6023,10 +6084,14 @@ CONFIG_SENSORS_MCP3021=m CONFIG_SENSORS_MLXREG_FAN=m # CONFIG_SENSORS_MP2856 is not set CONFIG_SENSORS_MP2888=m +# CONFIG_SENSORS_MP2891 is not set CONFIG_SENSORS_MP2975=m CONFIG_SENSORS_MP2975_REGULATOR=y +# CONFIG_SENSORS_MP2993 is not set CONFIG_SENSORS_MP5023=m +# CONFIG_SENSORS_MP5920 is not set # CONFIG_SENSORS_MP5990 is not set +# CONFIG_SENSORS_MP9941 is not set CONFIG_SENSORS_MPQ7932=m CONFIG_SENSORS_MPQ7932_REGULATOR=y CONFIG_SENSORS_MPQ8785=m @@ -6073,6 +6138,7 @@ CONFIG_SENSORS_SIS5595=m CONFIG_SENSORS_SMSC47B397=m CONFIG_SENSORS_SMSC47M192=m CONFIG_SENSORS_SMSC47M1=m +# CONFIG_SENSORS_SPD5118 is not set # CONFIG_SENSORS_STPDDC60 is not set # CONFIG_SENSORS_STTS751 is not set CONFIG_SENSORS_SURFACE_FAN=m @@ -6224,6 +6290,7 @@ CONFIG_SKGE_GENESIS=y CONFIG_SKGE=m # CONFIG_SKY2_DEBUG is not set CONFIG_SKY2=m +CONFIG_SLAB_BUCKETS=y CONFIG_SLAB_FREELIST_HARDENED=y # CONFIG_SLAB_FREELIST_RANDOM is not set # CONFIG_SLAB_MERGE_DEFAULT is not set @@ -6332,6 +6399,7 @@ CONFIG_SND_HDA_CODEC_CONEXANT=m CONFIG_SND_HDA_CODEC_CS8409=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_HDA_CODEC_REALTEK=m +# CONFIG_SND_HDA_CODEC_SENARYTECH is not set CONFIG_SND_HDA_CODEC_SI3054=m CONFIG_SND_HDA_CODEC_SIGMATEL=m CONFIG_SND_HDA_CODEC_VIA=m @@ -6443,6 +6511,7 @@ CONFIG_SND_SOC_ADI=m # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4619 is not set # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set CONFIG_SND_SOC_AK5558=m @@ -6505,6 +6574,7 @@ CONFIG_SND_SOC_CS42L83=m CONFIG_SND_SOC_CS43130=m # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS530X_I2C is not set # CONFIG_SND_SOC_CS53L30 is not set CONFIG_SND_SOC_CS_AMP_LIB_TEST=m CONFIG_SND_SOC_CX2072X=m @@ -6513,6 +6583,7 @@ CONFIG_SND_SOC_DA7213=m CONFIG_SND_SOC_DMIC=m CONFIG_SND_SOC_ES7134=m # CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8311 is not set # CONFIG_SND_SOC_ES8316 is not set CONFIG_SND_SOC_ES8326=m CONFIG_SND_SOC_ES8328_I2C=m @@ -6684,6 +6755,7 @@ CONFIG_SND_SOC_RT1017_SDCA_SDW=m # CONFIG_SND_SOC_RT1308_SDW is not set # CONFIG_SND_SOC_RT1316_SDW is not set CONFIG_SND_SOC_RT1318_SDW=m +# CONFIG_SND_SOC_RT1320_SDW is not set # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set CONFIG_SND_SOC_RT5640=m @@ -6823,6 +6895,7 @@ CONFIG_SND_SOC_TSCS42XX=m # CONFIG_SND_SOC_UDA1334 is not set CONFIG_SND_SOC_UTILS_KUNIT_TEST=m # CONFIG_SND_SOC_WCD9335 is not set +# CONFIG_SND_SOC_WCD937X_SDW is not set # CONFIG_SND_SOC_WCD938X_SDW is not set CONFIG_SND_SOC_WCD939X_SDW=m # CONFIG_SND_SOC_WM8510 is not set @@ -6946,6 +7019,7 @@ CONFIG_SPI_AX88796C=m # CONFIG_SPI_CADENCE is not set CONFIG_SPI_CADENCE_QUADSPI=m # CONFIG_SPI_CADENCE_XSPI is not set +# CONFIG_SPI_CH341 is not set # CONFIG_SPI_CS42L43 is not set # CONFIG_SPI_DEBUG is not set # CONFIG_SPI_DESIGNWARE is not set @@ -7027,6 +7101,7 @@ CONFIG_STAGING_MEDIA=y CONFIG_STAGING=y CONFIG_STANDALONE=y CONFIG_STARFIVE_JH8100_INTC=y +# CONFIG_STARFIVE_STARLINK_CACHE is not set # CONFIG_STARFIVE_STARLINK_PMU is not set CONFIG_STARFIVE_WATCHDOG=y # CONFIG_STATIC_CALL_SELFTEST is not set @@ -7186,6 +7261,7 @@ CONFIG_TCP_MD5SIG=y CONFIG_TDX_GUEST_DRIVER=m CONFIG_TEE=m CONFIG_TEHUTI=m +# CONFIG_TEHUTI_TN40 is not set CONFIG_TELCLOCK=m CONFIG_TERANETICS_PHY=m # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set @@ -7267,6 +7343,7 @@ CONFIG_TI_ADC128S052=m # CONFIG_TI_ADC161S626 is not set CONFIG_TI_ADS1015=m CONFIG_TI_ADS1100=m +# CONFIG_TI_ADS1119 is not set # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS1298 is not set CONFIG_TI_ADS131E08=m @@ -7934,6 +8011,7 @@ CONFIG_USB_YUREX=m # CONFIG_USB_ZERO is not set CONFIG_USB_ZR364XX=m # CONFIG_USELIB is not set +CONFIG_USERCOPY_KUNIT_TEST=m # CONFIG_USER_DECRYPTED_DATA is not set # CONFIG_USER_EVENTS is not set CONFIG_USERFAULTFD=y @@ -7959,6 +8037,7 @@ CONFIG_VDPA_SIM=m CONFIG_VDPA_SIM_NET=m CONFIG_VDPA_USER=m CONFIG_VEML6030=m +# CONFIG_VEML6040 is not set # CONFIG_VEML6070 is not set # CONFIG_VEML6075 is not set CONFIG_VETH=m @@ -8045,6 +8124,7 @@ CONFIG_VIDEO_DW9714=m CONFIG_VIDEO_DW9719=m CONFIG_VIDEO_DW9768=m CONFIG_VIDEO_DW9807_VCM=m +# CONFIG_VIDEO_E5010_JPEG_ENC is not set CONFIG_VIDEO_EM28XX_ALSA=m CONFIG_VIDEO_EM28XX_DVB=m CONFIG_VIDEO_EM28XX=m @@ -8054,6 +8134,8 @@ CONFIG_VIDEO_ET8EK8=m CONFIG_VIDEO_FB_IVTV=m # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set CONFIG_VIDEO_GC0308=m +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set CONFIG_VIDEO_GC2145=m CONFIG_VIDEO_GO7007_LOADER=m CONFIG_VIDEO_GO7007=m @@ -8072,6 +8154,7 @@ CONFIG_VIDEO_IMX214=m CONFIG_VIDEO_IMX219=m CONFIG_VIDEO_IMX258=m CONFIG_VIDEO_IMX274=m +CONFIG_VIDEO_IMX283=m CONFIG_VIDEO_IMX290=m CONFIG_VIDEO_IMX296=m CONFIG_VIDEO_IMX319=m @@ -8091,6 +8174,8 @@ CONFIG_VIDEO_LM3646=m CONFIG_VIDEO_M52790=m # CONFIG_VIDEO_MAX9286 is not set # CONFIG_VIDEO_MAX96712 is not set +CONFIG_VIDEO_MAX96714=m +CONFIG_VIDEO_MAX96717=m # CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set # CONFIG_VIDEO_MGB4 is not set # CONFIG_VIDEO_ML86V7667 is not set @@ -8143,6 +8228,7 @@ CONFIG_VIDEO_OV9734=m CONFIG_VIDEO_PVRUSB2_DVB=y CONFIG_VIDEO_PVRUSB2=m CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_RASPBERRYPI_PISP_BE=m CONFIG_VIDEO_RDACM20=m # CONFIG_VIDEO_RDACM21 is not set CONFIG_VIDEO_RJ54N1=m @@ -8208,6 +8294,7 @@ CONFIG_VIDEO_UPD64083=m CONFIG_VIDEO_USBTV=m CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VGXY61 is not set CONFIG_VIDEO_VICODEC=m CONFIG_VIDEO_VIM2M=m CONFIG_VIDEO_VIMC=m diff --git a/kernel-riscv64-fedora.config b/kernel-riscv64-fedora.config index 38c394ffc..aef111b73 100644 --- a/kernel-riscv64-fedora.config +++ b/kernel-riscv64-fedora.config @@ -119,6 +119,7 @@ CONFIG_AD7292=m CONFIG_AD7293=m # CONFIG_AD7298 is not set # CONFIG_AD7303 is not set +# CONFIG_AD7380 is not set CONFIG_AD74115=m CONFIG_AD74413R=m # CONFIG_AD7476 is not set @@ -192,7 +193,7 @@ CONFIG_ADXL372_I2C=m CONFIG_ADXL372_SPI=m CONFIG_ADXRS290=m # CONFIG_ADXRS450 is not set -# CONFIG_AF8133J is not set +CONFIG_AF8133J=m # CONFIG_AFE4403 is not set # CONFIG_AFE4404 is not set CONFIG_AFFS_FS=m @@ -317,7 +318,6 @@ CONFIG_ARM_CMN=m # CONFIG_ARM_MHU is not set # CONFIG_ARM_MHU_V2 is not set # CONFIG_ARM_MHU_V3 is not set -CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y # CONFIG_ARM_SCMI_TRANSPORT_MAILBOX is not set # CONFIG_ARM_SCMI_TRANSPORT_SMC is not set # CONFIG_ARM_SCMI_TRANSPORT_VIRTIO is not set @@ -468,6 +468,7 @@ CONFIG_BACKLIGHT_KTD253=m # CONFIG_BACKLIGHT_KTD2801 is not set CONFIG_BACKLIGHT_KTZ8866=m CONFIG_BACKLIGHT_LED=m +# CONFIG_BACKLIGHT_LM3509 is not set # CONFIG_BACKLIGHT_LM3630A is not set # CONFIG_BACKLIGHT_LM3639 is not set CONFIG_BACKLIGHT_LP855X=m @@ -503,6 +504,7 @@ CONFIG_BATTERY_CW2015=m # CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_MAX1720X is not set # CONFIG_BATTERY_MAX1721X is not set CONFIG_BATTERY_RT5033=m CONFIG_BATTERY_SAMSUNG_SDI=y @@ -887,6 +889,7 @@ CONFIG_CHARGER_BQ2515X=m CONFIG_CHARGER_BQ256XX=m # CONFIG_CHARGER_BQ25890 is not set # CONFIG_CHARGER_BQ25980 is not set +CONFIG_CHARGER_CROS_CONTROL=m CONFIG_CHARGER_CROS_PCHG=m # CONFIG_CHARGER_CROS_USBPD is not set # CONFIG_CHARGER_DETECTOR_MAX14656 is not set @@ -955,6 +958,7 @@ CONFIG_CLK_KUNIT_TEST=m CONFIG_CLK_SIFIVE_PRCI=y CONFIG_CLK_SIFIVE=y CONFIG_CLK_SOPHGO_CV1800=y +CONFIG_CLK_SOPHGO_SG2042_PLL=y # CONFIG_CLK_SP810 is not set CONFIG_CLK_STARFIVE_JH7100_AUDIO=m CONFIG_CLK_STARFIVE_JH7100=y @@ -970,6 +974,7 @@ CONFIG_CLK_STARFIVE_JH71X0=y # CONFIG_CLK_SUNXI_PRCM_SUN6I is not set # CONFIG_CLK_SUNXI_PRCM_SUN8I is not set # CONFIG_CLK_SUNXI_PRCM_SUN9I is not set +CONFIG_CLK_THEAD_TH1520_AP=y CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100 CONFIG_CLS_U32_MARK=y CONFIG_CLS_U32_PERF=y @@ -996,6 +1001,8 @@ CONFIG_CODA_FS=m CONFIG_COMMAND_LINE_SIZE=4096 CONFIG_COMMON_CLK_AXG_AUDIO=y CONFIG_COMMON_CLK_AXI_CLKGEN=m +CONFIG_COMMON_CLK_C3_PERIPHERALS=y +CONFIG_COMMON_CLK_C3_PLL=y # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CDCE925 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set @@ -1023,6 +1030,7 @@ CONFIG_COMPAT_32BIT_TIME=y # CONFIG_COMPAT_BRK is not set # CONFIG_COMPAT is not set # CONFIG_COMPILE_TEST is not set +# CONFIG_COMPRESSED_INSTALL is not set CONFIG_CONFIGFS_FS=y CONFIG_CONNECTOR=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 @@ -1264,6 +1272,7 @@ CONFIG_CXL_PMEM=m CONFIG_CXL_PMU=m # CONFIG_CXL_REGION_INVALIDATION_TEST is not set CONFIG_CXL_REGION=y +# CONFIG_CZNIC_PLATFORMS is not set CONFIG_DA280=m CONFIG_DA311=m CONFIG_DA9063_WATCHDOG=m @@ -1372,6 +1381,7 @@ CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 # CONFIG_DEFAULT_SECURITY_DAC is not set CONFIG_DEFAULT_SECURITY_SELINUX=y # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +CONFIG_DELL_PC=m # CONFIG_DETECT_HUNG_TASK is not set CONFIG_DEV_DAX_CXL=m CONFIG_DEV_DAX_HMEM=m @@ -1449,6 +1459,7 @@ CONFIG_DM_UNSTRIPED=m CONFIG_DM_VDO=m CONFIG_DM_VERITY_FEC=y CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_WRITECACHE=m @@ -1482,6 +1493,7 @@ CONFIG_DRM_AMDGPU=m CONFIG_DRM_AMDGPU_SI=y CONFIG_DRM_AMDGPU_USERPTR=y # CONFIG_DRM_AMDGPU_WERROR is not set +# CONFIG_DRM_AMD_ISP is not set CONFIG_DRM_AMD_SECURE_DISPLAY=y CONFIG_DRM_ANALOGIX_ANX6345=m CONFIG_DRM_ANALOGIX_ANX7625=m @@ -1521,6 +1533,7 @@ CONFIG_DRM_I2C_CH7006=m # CONFIG_DRM_I2C_NXP_TDA9950 is not set # CONFIG_DRM_I2C_NXP_TDA998X is not set CONFIG_DRM_I2C_SIL164=m +# CONFIG_DRM_I915_REPLAY_GPU_HANGS_API is not set # CONFIG_DRM_IMX_LCDIF is not set CONFIG_DRM_ITE_IT6505=m # CONFIG_DRM_ITE_IT66121 is not set @@ -1561,11 +1574,13 @@ CONFIG_DRM_PANEL_DSI_CM=m CONFIG_DRM_PANEL_ELIDA_KD35T133=m CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m +# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set # CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set CONFIG_DRM_PANEL_ILITEK_ILI9882T=m CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m @@ -1581,6 +1596,7 @@ CONFIG_DRM_PANEL_JDI_R63452=m # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_LG_SW43408 is not set +# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set # CONFIG_DRM_PANEL_LVDS is not set CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966=m CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m @@ -1876,6 +1892,7 @@ CONFIG_ENCRYPTED_KEYS=y # CONFIG_ENCX24J600 is not set CONFIG_ENERGY_MODEL=y CONFIG_ENIC=m +# CONFIG_ENS160 is not set CONFIG_ENVELOPE_DETECTOR=m CONFIG_EPIC100=m CONFIG_EPOLL=y @@ -1996,6 +2013,7 @@ CONFIG_FB_EFI=y # CONFIG_FB_METRONOME is not set CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_NEOMAGIC is not set +# CONFIG_FBNIC is not set # CONFIG_FB_NVIDIA is not set # CONFIG_FB_OF is not set # CONFIG_FB_OPENCORES is not set @@ -2035,7 +2053,9 @@ CONFIG_FILE_LOCKING=y # CONFIG_FIND_BIT_BENCHMARK is not set # CONFIG_FIPS_SIGNATURE_SELFTEST is not set # CONFIG_FIREWIRE is not set +CONFIG_FIREWIRE_KUNIT_OHCI_SERDES_TEST=m CONFIG_FIREWIRE_KUNIT_PACKET_SERDES_TEST=m +CONFIG_FIREWIRE_KUNIT_SELF_ID_SEQUENCE_HELPER_TEST=m # CONFIG_FIREWIRE_NOSY is not set # CONFIG_FIRMWARE_EDID is not set # CONFIG_FIRMWARE_MEMMAP is not set @@ -2092,6 +2112,7 @@ CONFIG_FS_ENCRYPTION=y # CONFIG_FSL_ENETC is not set # CONFIG_FSL_ENETC_MDIO is not set # CONFIG_FSL_ENETC_VF is not set +# CONFIG_FSL_IFC is not set # CONFIG_FSL_PQ_MDIO is not set # CONFIG_FSL_QDMA is not set # CONFIG_FSL_RCPM is not set @@ -2236,6 +2257,7 @@ CONFIG_GPIO_PCI_IDIO_16=m # CONFIG_GPIO_SCH311X is not set CONFIG_GPIO_SIFIVE=y CONFIG_GPIO_SIM=m +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set CONFIG_GPIO_SYSCON=m # CONFIG_GPIO_SYSFS is not set # CONFIG_GPIO_TPIC2810 is not set @@ -2243,6 +2265,7 @@ CONFIG_GPIO_TPS65219=m # CONFIG_GPIO_TS4900 is not set # CONFIG_GPIO_VIPERBOARD is not set CONFIG_GPIO_VIRTIO=m +# CONFIG_GPIO_VIRTUSER is not set # CONFIG_GPIO_WATCHDOG is not set # CONFIG_GPIO_WINBOND is not set CONFIG_GPIO_WM8994=m @@ -2588,6 +2611,7 @@ CONFIG_ICPLUS_PHY=m # CONFIG_IDLE_INJECT is not set CONFIG_IDLE_PAGE_TRACKING=y CONFIG_IDPF=m +# CONFIG_IDPF_SINGLEQ is not set CONFIG_IEEE802154_6LOWPAN=m CONFIG_IEEE802154_ADF7242=m # CONFIG_IEEE802154_AT86RF230_DEBUGFS is not set @@ -2816,6 +2840,7 @@ CONFIG_INTEL_IDXD=m # CONFIG_INTEL_ISHTP_ECLITE is not set # CONFIG_INTEL_LDMA is not set # CONFIG_INTEL_MEI_PXP is not set +# CONFIG_INTEL_PLR_TPMI is not set # CONFIG_INTEL_PMT_CLASS is not set # CONFIG_INTEL_PMT_CRASHLOG is not set # CONFIG_INTEL_PMT_TELEMETRY is not set @@ -3140,6 +3165,7 @@ CONFIG_KALLSYMS=y # CONFIG_KCOV is not set # CONFIG_KCSAN is not set CONFIG_KDB_CONTINUE_CATASTROPHIC=0 +# CONFIG_KEBA_CP500 is not set # CONFIG_KERNEL_BZIP2 is not set CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_LZ4 is not set @@ -3238,6 +3264,7 @@ CONFIG_L2TP=m CONFIG_L2TP_V3=y CONFIG_LAN743X=m CONFIG_LAN966X_DCB=y +# CONFIG_LAN966X_OIC is not set CONFIG_LAN966X_SWITCH=m # CONFIG_LAPB is not set CONFIG_LATENCYTOP=y @@ -3277,6 +3304,7 @@ CONFIG_LEDS_CLASS_MULTICOLOR=m CONFIG_LEDS_CLASS=y CONFIG_LEDS_CLEVO_MAIL=m CONFIG_LEDS_CR0014114=m +CONFIG_LEDS_CROS_EC=m # CONFIG_LEDS_DAC124S085 is not set # CONFIG_LEDS_EL15203000 is not set CONFIG_LEDS_GPIO=m @@ -3319,6 +3347,7 @@ CONFIG_LEDS_REGULATOR=m # CONFIG_LEDS_RT8515 is not set # CONFIG_LEDS_SGM3140 is not set # CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_SY7802 is not set CONFIG_LEDS_SYSCON=y # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TI_LMU_COMMON is not set @@ -3332,6 +3361,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m +# CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set CONFIG_LEDS_TRIGGER_MTD=y CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_ONESHOT=m @@ -3466,6 +3496,7 @@ CONFIG_MANTIS_CORE=m CONFIG_MARVELL_10G_PHY=m CONFIG_MARVELL_88Q2XXX_PHY=m CONFIG_MARVELL_88X2222_PHY=m +# CONFIG_MARVELL_CN10K_DPI is not set CONFIG_MARVELL_PHY=m # CONFIG_MATOM is not set # CONFIG_MAX1027 is not set @@ -3583,11 +3614,13 @@ CONFIG_MEGARAID_SAS=m CONFIG_MELLANOX_PLATFORM=y # CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_MEMCG_SWAP=y +# CONFIG_MEMCG_V1 is not set CONFIG_MEMCG=y CONFIG_MEMCPY_KUNIT_TEST=m CONFIG_MEMCPY_SLOW_KUNIT_TEST=y CONFIG_MEMORY_FAILURE=y # CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE is not set +CONFIG_MEMORY_HOTPLUG=y # CONFIG_MEMORY is not set # CONFIG_MEMSTICK_DEBUG is not set CONFIG_MEMSTICK_JMICRON_38X=m @@ -3604,6 +3637,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM886_PMIC is not set # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_ARIZONA_I2C is not set @@ -3620,6 +3654,8 @@ CONFIG_MFD_AXP20X=y CONFIG_MFD_BD9571MWV=m CONFIG_MFD_CORE=y # CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_CS40L50_I2C is not set +# CONFIG_MFD_CS40L50_SPI is not set CONFIG_MFD_CS42L43_I2C=m CONFIG_MFD_CS42L43_SDW=m # CONFIG_MFD_CS5535 is not set @@ -3683,6 +3719,7 @@ CONFIG_MFD_MAX77714=m # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD957XMUF is not set +# CONFIG_MFD_ROHM_BD96801 is not set CONFIG_MFD_RSMU_I2C=m CONFIG_MFD_RSMU_SPI=m CONFIG_MFD_RT4831=m @@ -4171,6 +4208,7 @@ CONFIG_NET_DSA_TAG_RTL8_4=m # CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set CONFIG_NET_DSA_TAG_SJA1105=m CONFIG_NET_DSA_TAG_TRAILER=m +# CONFIG_NET_DSA_TAG_VSC73XX_8021Q is not set CONFIG_NET_DSA_TAG_XRS700X=m # CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set # CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set @@ -4275,8 +4313,10 @@ CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER=y +CONFIG_NET_FLOW_LIMIT=y CONFIG_NET_FOU_IP_TUNNELS=y CONFIG_NET_FOU=m +# CONFIG_NETFS_DEBUG is not set CONFIG_NETFS_STATS=y CONFIG_NETFS_SUPPORT=m CONFIG_NET_HANDSHAKE_KUNIT_TEST=m @@ -4383,6 +4423,7 @@ CONFIG_NET_VENDOR_INTEL=y CONFIG_NET_VENDOR_LITEX=y CONFIG_NET_VENDOR_MARVELL=y CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_NET_VENDOR_META=y CONFIG_NET_VENDOR_MICREL=y CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_NET_VENDOR_MICROSEMI is not set @@ -4687,6 +4728,7 @@ CONFIG_NVME_MULTIPATH=y CONFIG_NVMEM=y CONFIG_NVME_RDMA=m CONFIG_NVME_TARGET_AUTH=y +# CONFIG_NVME_TARGET_DEBUGFS is not set CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_LOOP=m @@ -4710,6 +4752,7 @@ CONFIG_OCFS2_FS_O2CB=m # CONFIG_OCFS2_FS_STATS is not set CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m CONFIG_OCTEON_EP=m +# CONFIG_OCTEONEP_VDPA is not set CONFIG_OCTEON_EP_VF=m CONFIG_OF_FPGA_REGION=m CONFIG_OF_GPIO=y @@ -4864,6 +4907,7 @@ CONFIG_PCI_PASID=y CONFIG_PCIPCWATCHDOG=m CONFIG_PCI_PF_STUB=m CONFIG_PCI_PRI=y +CONFIG_PCI_PWRCTL_PWRSEQ=m CONFIG_PCI_QUIRKS=y # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set CONFIG_PCI_STUB=y @@ -4918,6 +4962,7 @@ CONFIG_PHY_RTK_RTD_USB3PHY=m # CONFIG_PHY_SAMSUNG_USB2 is not set # CONFIG_PHYS_RAM_BASE_FIXED is not set CONFIG_PHY_STARFIVE_JH7110_DPHY_RX=m +CONFIG_PHY_STARFIVE_JH7110_DPHY_TX=m CONFIG_PHY_STARFIVE_JH7110_PCIE=m CONFIG_PHY_STARFIVE_JH7110_USB=m # CONFIG_PHY_TUSB1210 is not set @@ -5012,6 +5057,8 @@ CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_RESET_TPS65086=y # CONFIG_POWER_RESET_VEXPRESS is not set CONFIG_POWER_RESET=y +CONFIG_POWER_SEQUENCING=m +CONFIG_POWER_SEQUENCING_QCOM_WCN=m # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y CONFIG_POWER_SUPPLY=y @@ -5115,10 +5162,12 @@ CONFIG_PTP_DFL_TOD=m # CONFIG_PVPANIC_PCI is not set CONFIG_PVPANIC=y # CONFIG_PWM_ATMEL_TCB is not set +# CONFIG_PWM_AXI_PWMGEN is not set # CONFIG_PWM_CLK is not set # CONFIG_PWM_DEBUG is not set CONFIG_PWM_DWC=m # CONFIG_PWM_FSL_FTM is not set +CONFIG_PWM_GPIO=m CONFIG_PWM_HIBVT=m # CONFIG_PWM_MICROCHIP_CORE is not set CONFIG_PWM_OMAP_DMTIMER=m @@ -5146,6 +5195,7 @@ CONFIG_QCA83XX_PHY=m # CONFIG_QCOM_LMH is not set # CONFIG_QCOM_OCMEM is not set CONFIG_QCOM_PBS=m +# CONFIG_QCOM_PD_MAPPER is not set # CONFIG_QCOM_PMIC_GLINK is not set # CONFIG_QCOM_PMIC_PDCHARGER_ULOG is not set # CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set @@ -5195,6 +5245,7 @@ CONFIG_RADIO_WL1273=m CONFIG_RAID_ATTRS=m # CONFIG_RANDOM32_SELFTEST is not set CONFIG_RANDOMIZE_BASE=y +# CONFIG_RANDOMIZE_IDENTITY_BASE is not set CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y CONFIG_RANDOMIZE_KSTACK_OFFSET=y CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa @@ -5382,7 +5433,8 @@ CONFIG_RESOURCE_KUNIT_TEST=m CONFIG_RFKILL_GPIO=m CONFIG_RFKILL_INPUT=y CONFIG_RFKILL=m -# CONFIG_RH_DISABLE_DEPRECATED is not set +CONFIG_RFS_ACCEL=y +# CONFIG_RHEL_DIFFERENCES is not set CONFIG_RICHTEK_RTQ6056=m CONFIG_RING_BUFFER_BENCHMARK=m # CONFIG_RING_BUFFER_STARTUP_TEST is not set @@ -5402,10 +5454,14 @@ CONFIG_RISCV_ISA_FALLBACK=y CONFIG_RISCV_ISA_SVNAPOT=y CONFIG_RISCV_ISA_SVPBMT=y CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y +CONFIG_RISCV_ISA_VENDOR_EXT_ANDES=y CONFIG_RISCV_ISA_V_PREEMPTIVE=y CONFIG_RISCV_ISA_V_UCOPY_THRESHOLD=768 CONFIG_RISCV_ISA_V=y +CONFIG_RISCV_ISA_ZAWRS=y +CONFIG_RISCV_ISA_ZBA=y CONFIG_RISCV_ISA_ZBB=y +CONFIG_RISCV_ISA_ZBC=y CONFIG_RISCV_ISA_ZICBOM=y CONFIG_RISCV_ISA_ZICBOZ=y CONFIG_RISCV_MISALIGNED=y @@ -5456,6 +5512,7 @@ CONFIG_RPMSG_TTY=m CONFIG_RPMSG_VIRTIO=m CONFIG_RPMSG_WWAN_CTRL=m CONFIG_RPR0521=m +CONFIG_RPS=y CONFIG_RSEQ=y CONFIG_RSI_91X=m CONFIG_RSI_COEX=y @@ -5591,8 +5648,9 @@ CONFIG_RTL8180=m CONFIG_RTL8187=m CONFIG_RTL8188EE=m CONFIG_RTL8192CE=m -CONFIG_RTL8192CU=m +# CONFIG_RTL8192CU is not set CONFIG_RTL8192DE=m +# CONFIG_RTL8192DU is not set CONFIG_RTL8192EE=m CONFIG_RTL8192E=m CONFIG_RTL8192SE=m @@ -5611,6 +5669,7 @@ CONFIG_RTLLIB=m # CONFIG_RTLWIFI_DEBUG is not set CONFIG_RTLWIFI=m # CONFIG_RTS5208 is not set +# CONFIG_RTSN is not set CONFIG_RTW88_8723CS=m CONFIG_RTW88_8723DE=m CONFIG_RTW88_8723DS=m @@ -5637,6 +5696,7 @@ CONFIG_RTW89_8922AE=m CONFIG_RTW89=m # CONFIG_RUNTIME_KERNEL_TESTING_MENU is not set CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_RUST is not set CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PANIC=y @@ -5879,6 +5939,7 @@ CONFIG_SENSORS_BPA_RS600=m CONFIG_SENSORS_CHIPCAP2=m CONFIG_SENSORS_CORSAIR_CPRO=m CONFIG_SENSORS_CORSAIR_PSU=m +CONFIG_SENSORS_CROS_EC=m CONFIG_SENSORS_DELTA_AHE50DC_FAN=m CONFIG_SENSORS_DME1737=m CONFIG_SENSORS_DPS920AB=m @@ -5994,10 +6055,14 @@ CONFIG_SENSORS_MCP3021=m CONFIG_SENSORS_MLXREG_FAN=m # CONFIG_SENSORS_MP2856 is not set CONFIG_SENSORS_MP2888=m +# CONFIG_SENSORS_MP2891 is not set CONFIG_SENSORS_MP2975=m CONFIG_SENSORS_MP2975_REGULATOR=y +# CONFIG_SENSORS_MP2993 is not set CONFIG_SENSORS_MP5023=m +# CONFIG_SENSORS_MP5920 is not set # CONFIG_SENSORS_MP5990 is not set +# CONFIG_SENSORS_MP9941 is not set CONFIG_SENSORS_MPQ7932=m CONFIG_SENSORS_MPQ7932_REGULATOR=y CONFIG_SENSORS_MPQ8785=m @@ -6044,6 +6109,7 @@ CONFIG_SENSORS_SIS5595=m CONFIG_SENSORS_SMSC47B397=m CONFIG_SENSORS_SMSC47M192=m CONFIG_SENSORS_SMSC47M1=m +# CONFIG_SENSORS_SPD5118 is not set # CONFIG_SENSORS_STPDDC60 is not set # CONFIG_SENSORS_STTS751 is not set CONFIG_SENSORS_SURFACE_FAN=m @@ -6195,6 +6261,7 @@ CONFIG_SKGE_GENESIS=y CONFIG_SKGE=m # CONFIG_SKY2_DEBUG is not set CONFIG_SKY2=m +CONFIG_SLAB_BUCKETS=y CONFIG_SLAB_FREELIST_HARDENED=y # CONFIG_SLAB_FREELIST_RANDOM is not set # CONFIG_SLAB_MERGE_DEFAULT is not set @@ -6303,6 +6370,7 @@ CONFIG_SND_HDA_CODEC_CONEXANT=m CONFIG_SND_HDA_CODEC_CS8409=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_HDA_CODEC_REALTEK=m +# CONFIG_SND_HDA_CODEC_SENARYTECH is not set CONFIG_SND_HDA_CODEC_SI3054=m CONFIG_SND_HDA_CODEC_SIGMATEL=m CONFIG_SND_HDA_CODEC_VIA=m @@ -6413,6 +6481,7 @@ CONFIG_SND_SOC_ADI=m # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4619 is not set # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set CONFIG_SND_SOC_AK5558=m @@ -6475,6 +6544,7 @@ CONFIG_SND_SOC_CS42L83=m CONFIG_SND_SOC_CS43130=m # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS530X_I2C is not set # CONFIG_SND_SOC_CS53L30 is not set CONFIG_SND_SOC_CS_AMP_LIB_TEST=m CONFIG_SND_SOC_CX2072X=m @@ -6483,6 +6553,7 @@ CONFIG_SND_SOC_DA7213=m CONFIG_SND_SOC_DMIC=m CONFIG_SND_SOC_ES7134=m # CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8311 is not set # CONFIG_SND_SOC_ES8316 is not set CONFIG_SND_SOC_ES8326=m CONFIG_SND_SOC_ES8328_I2C=m @@ -6654,6 +6725,7 @@ CONFIG_SND_SOC_RT1017_SDCA_SDW=m # CONFIG_SND_SOC_RT1308_SDW is not set # CONFIG_SND_SOC_RT1316_SDW is not set CONFIG_SND_SOC_RT1318_SDW=m +# CONFIG_SND_SOC_RT1320_SDW is not set # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set CONFIG_SND_SOC_RT5640=m @@ -6792,6 +6864,7 @@ CONFIG_SND_SOC_TSCS42XX=m # CONFIG_SND_SOC_UDA1334 is not set CONFIG_SND_SOC_UTILS_KUNIT_TEST=m # CONFIG_SND_SOC_WCD9335 is not set +# CONFIG_SND_SOC_WCD937X_SDW is not set # CONFIG_SND_SOC_WCD938X_SDW is not set CONFIG_SND_SOC_WCD939X_SDW=m # CONFIG_SND_SOC_WM8510 is not set @@ -6915,6 +6988,7 @@ CONFIG_SPI_AX88796C=m # CONFIG_SPI_CADENCE is not set CONFIG_SPI_CADENCE_QUADSPI=m # CONFIG_SPI_CADENCE_XSPI is not set +# CONFIG_SPI_CH341 is not set # CONFIG_SPI_CS42L43 is not set # CONFIG_SPI_DEBUG is not set # CONFIG_SPI_DESIGNWARE is not set @@ -6996,6 +7070,7 @@ CONFIG_STAGING_MEDIA=y CONFIG_STAGING=y CONFIG_STANDALONE=y CONFIG_STARFIVE_JH8100_INTC=y +# CONFIG_STARFIVE_STARLINK_CACHE is not set # CONFIG_STARFIVE_STARLINK_PMU is not set CONFIG_STARFIVE_WATCHDOG=y # CONFIG_STATIC_CALL_SELFTEST is not set @@ -7155,6 +7230,7 @@ CONFIG_TCP_MD5SIG=y CONFIG_TDX_GUEST_DRIVER=m CONFIG_TEE=m CONFIG_TEHUTI=m +# CONFIG_TEHUTI_TN40 is not set CONFIG_TELCLOCK=m CONFIG_TERANETICS_PHY=m # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set @@ -7236,6 +7312,7 @@ CONFIG_TI_ADC128S052=m # CONFIG_TI_ADC161S626 is not set CONFIG_TI_ADS1015=m CONFIG_TI_ADS1100=m +# CONFIG_TI_ADS1119 is not set # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS1298 is not set CONFIG_TI_ADS131E08=m @@ -7903,6 +7980,7 @@ CONFIG_USB_YUREX=m # CONFIG_USB_ZERO is not set CONFIG_USB_ZR364XX=m # CONFIG_USELIB is not set +CONFIG_USERCOPY_KUNIT_TEST=m # CONFIG_USER_DECRYPTED_DATA is not set # CONFIG_USER_EVENTS is not set CONFIG_USERFAULTFD=y @@ -7928,6 +8006,7 @@ CONFIG_VDPA_SIM=m CONFIG_VDPA_SIM_NET=m CONFIG_VDPA_USER=m CONFIG_VEML6030=m +# CONFIG_VEML6040 is not set # CONFIG_VEML6070 is not set # CONFIG_VEML6075 is not set CONFIG_VETH=m @@ -8014,6 +8093,7 @@ CONFIG_VIDEO_DW9714=m CONFIG_VIDEO_DW9719=m CONFIG_VIDEO_DW9768=m CONFIG_VIDEO_DW9807_VCM=m +# CONFIG_VIDEO_E5010_JPEG_ENC is not set CONFIG_VIDEO_EM28XX_ALSA=m CONFIG_VIDEO_EM28XX_DVB=m CONFIG_VIDEO_EM28XX=m @@ -8023,6 +8103,8 @@ CONFIG_VIDEO_ET8EK8=m CONFIG_VIDEO_FB_IVTV=m # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set CONFIG_VIDEO_GC0308=m +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set CONFIG_VIDEO_GC2145=m CONFIG_VIDEO_GO7007_LOADER=m CONFIG_VIDEO_GO7007=m @@ -8041,6 +8123,7 @@ CONFIG_VIDEO_IMX214=m CONFIG_VIDEO_IMX219=m CONFIG_VIDEO_IMX258=m CONFIG_VIDEO_IMX274=m +CONFIG_VIDEO_IMX283=m CONFIG_VIDEO_IMX290=m CONFIG_VIDEO_IMX296=m CONFIG_VIDEO_IMX319=m @@ -8060,6 +8143,8 @@ CONFIG_VIDEO_LM3646=m CONFIG_VIDEO_M52790=m # CONFIG_VIDEO_MAX9286 is not set # CONFIG_VIDEO_MAX96712 is not set +CONFIG_VIDEO_MAX96714=m +CONFIG_VIDEO_MAX96717=m # CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set # CONFIG_VIDEO_MGB4 is not set # CONFIG_VIDEO_ML86V7667 is not set @@ -8112,6 +8197,7 @@ CONFIG_VIDEO_OV9734=m CONFIG_VIDEO_PVRUSB2_DVB=y CONFIG_VIDEO_PVRUSB2=m CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_RASPBERRYPI_PISP_BE=m CONFIG_VIDEO_RDACM20=m # CONFIG_VIDEO_RDACM21 is not set CONFIG_VIDEO_RJ54N1=m @@ -8177,6 +8263,7 @@ CONFIG_VIDEO_UPD64083=m CONFIG_VIDEO_USBTV=m CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VGXY61 is not set CONFIG_VIDEO_VICODEC=m CONFIG_VIDEO_VIM2M=m CONFIG_VIDEO_VIMC=m diff --git a/linux-kernel-test.patch b/linux-kernel-test.patch index c453676ae..e69de29bb 100644 --- a/linux-kernel-test.patch +++ b/linux-kernel-test.patch @@ -1,7859 +0,0 @@ -From patchwork Thu Mar 28 09:18:14 2024 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Minda Chen -X-Patchwork-Id: 13608233 -X-Patchwork-Delegate: kw@linux.com -Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn - (mail-sh0chn02on2114.outbound.protection.partner.outlook.cn - [139.219.146.114]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) 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-X-OriginatorOrg: starfivetech.com -X-MS-Exchange-CrossTenant-Network-Message-Id: - bfc79af4-ca3e-4708-7233-08dc4f081152 -X-MS-Exchange-CrossTenant-AuthSource: - SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn -X-MS-Exchange-CrossTenant-AuthAs: Internal -X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Mar 2024 09:18:44.9798 - (UTC) -X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted -X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c -X-MS-Exchange-CrossTenant-MailboxType: HOSTED -X-MS-Exchange-CrossTenant-UserPrincipalName: - MpVczu0QHOn5pV2f8B+naM/HZXehpWcgNJpmmGbFb7SzhldRoQGSdpAf1bFoHdA47TUslqXcps6Phmc+fZUOgiIWFX9OSnuG4cEN5dgqdCI= -X-MS-Exchange-Transport-CrossTenantHeadersStamped: SHXPR01MB0496 - -Add PLDA XpressRICH PCIe host common properties dt-binding doc. -PolarFire PCIe host using PLDA IP. Move common properties from Microchip -PolarFire PCIe host to PLDA files. - -Signed-off-by: Minda Chen -Reviewed-by: Hal Feng -Reviewed-by: Conor Dooley -Reviewed-by: Rob Herring -Tested-by: John Clark ---- - .../bindings/pci/microchip,pcie-host.yaml | 55 +------------- - .../pci/plda,xpressrich3-axi-common.yaml | 75 +++++++++++++++++++ - MAINTAINERS | 6 ++ - 3 files changed, 82 insertions(+), 54 deletions(-) - create mode 100644 Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml - -diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml -index 5d7aec5f54e71..612633ba59e2c 100644 ---- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml -+++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml -@@ -10,21 +10,13 @@ maintainers: - - Daire McNamara - - allOf: -- - $ref: /schemas/pci/pci-host-bridge.yaml# -+ - $ref: plda,xpressrich3-axi-common.yaml# - - $ref: /schemas/interrupt-controller/msi-controller.yaml# - - properties: - compatible: - const: microchip,pcie-host-1.0 # PolarFire - -- reg: -- maxItems: 2 -- -- reg-names: -- items: -- - const: cfg -- - const: apb -- - clocks: - description: - Fabric Interface Controllers, FICs, are the interface between the FPGA -@@ -52,18 +44,6 @@ properties: - items: - pattern: '^fic[0-3]$' - -- interrupts: -- minItems: 1 -- items: -- - description: PCIe host controller -- - description: builtin MSI controller -- -- interrupt-names: -- minItems: 1 -- items: -- - const: pcie -- - const: msi -- - ranges: - minItems: 1 - maxItems: 3 -@@ -72,39 +52,6 @@ properties: - minItems: 1 - maxItems: 6 - -- msi-controller: -- description: Identifies the node as an MSI controller. -- -- msi-parent: -- description: MSI controller the device is capable of using. -- -- interrupt-controller: -- type: object -- properties: -- '#address-cells': -- const: 0 -- -- '#interrupt-cells': -- const: 1 -- -- interrupt-controller: true -- -- required: -- - '#address-cells' -- - '#interrupt-cells' -- - interrupt-controller -- -- additionalProperties: false -- --required: -- - reg -- - reg-names -- - "#interrupt-cells" -- - interrupts -- - interrupt-map-mask -- - interrupt-map -- - msi-controller -- - unevaluatedProperties: false - - examples: -diff --git a/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml b/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml -new file mode 100644 -index 000000000000..31bb17b11e58 ---- /dev/null -+++ b/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml -@@ -0,0 +1,75 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/pci/plda,xpressrich3-axi-common.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: PLDA XpressRICH PCIe host common properties -+ -+maintainers: -+ - Daire McNamara -+ - Kevin Xie -+ -+description: -+ Generic PLDA XpressRICH PCIe host common properties. -+ -+allOf: -+ - $ref: /schemas/pci/pci-bus.yaml# -+ -+properties: -+ reg: -+ maxItems: 2 -+ -+ reg-names: -+ items: -+ - const: cfg -+ - const: apb -+ -+ interrupts: -+ minItems: 1 -+ items: -+ - description: PCIe host controller -+ - description: builtin MSI controller -+ -+ interrupt-names: -+ minItems: 1 -+ items: -+ - const: pcie -+ - const: msi -+ -+ msi-controller: -+ description: Identifies the node as an MSI controller. -+ -+ msi-parent: -+ description: MSI controller the device is capable of using. -+ -+ interrupt-controller: -+ type: object -+ properties: -+ '#address-cells': -+ const: 0 -+ -+ '#interrupt-cells': -+ const: 1 -+ -+ interrupt-controller: true -+ -+ required: -+ - '#address-cells' -+ - '#interrupt-cells' -+ - interrupt-controller -+ -+ additionalProperties: false -+ -+required: -+ - reg -+ - reg-names -+ - interrupts -+ - msi-controller -+ - "#interrupt-cells" -+ - interrupt-map-mask -+ - interrupt-map -+ -+additionalProperties: true -+ -+... -diff --git a/MAINTAINERS b/MAINTAINERS -index aa3b947fb080..06278f1db13f 100644 ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -16946,6 +16946,12 @@ S: Maintained - F: Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt - F: drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c - -+PCI DRIVER FOR PLDA PCIE IP -+M: Daire McNamara -+L: linux-pci@vger.kernel.org -+S: Maintained -+F: Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml -+ - PCI DRIVER FOR RENESAS R-CAR - M: Marek Vasut - M: Yoshihiro Shimoda - -From patchwork Thu Mar 28 09:18:15 2024 -Content-Type: text/plain; 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Prepare for refactoring the codes. - -Signed-off-by: Minda Chen -Reviewed-by: Conor Dooley ---- - MAINTAINERS | 4 ++-- - drivers/pci/controller/Kconfig | 9 +-------- - drivers/pci/controller/Makefile | 2 +- - drivers/pci/controller/plda/Kconfig | 14 ++++++++++++++ - drivers/pci/controller/plda/Makefile | 2 ++ - .../controller/{ => plda}/pcie-microchip-host.c | 2 +- - 6 files changed, 21 insertions(+), 12 deletions(-) - create mode 100644 drivers/pci/controller/plda/Kconfig - create mode 100644 drivers/pci/controller/plda/Makefile - rename drivers/pci/controller/{ => plda}/pcie-microchip-host.c (99%) - -diff --git a/MAINTAINERS b/MAINTAINERS -index 06278f1db13f..dd158cc7b009 100644 ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -17183,7 +17183,7 @@ M: Daire McNamara - L: linux-pci@vger.kernel.org - S: Supported - F: Documentation/devicetree/bindings/pci/microchip* --F: drivers/pci/controller/*microchip* -+F: drivers/pci/controller/plda/*microchip* - - PCIE DRIVER FOR QUALCOMM MSM - M: Manivannan Sadhasivam -@@ -18963,7 +18963,7 @@ F: drivers/clk/microchip/clk-mpfs*.c - F: drivers/firmware/microchip/mpfs-auto-update.c - F: drivers/i2c/busses/i2c-microchip-corei2c.c - F: drivers/mailbox/mailbox-mpfs.c --F: drivers/pci/controller/pcie-microchip-host.c -+F: drivers/pci/controller/plda/pcie-microchip-host.c - F: drivers/pwm/pwm-microchip-core.c - F: drivers/reset/reset-mpfs.c - F: drivers/rtc/rtc-mpfs.c -diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig -index e534c02ee34f..4d2c188f5835 100644 ---- a/drivers/pci/controller/Kconfig -+++ b/drivers/pci/controller/Kconfig -@@ -215,14 +215,6 @@ config PCIE_MT7621 - help - This selects a driver for the MediaTek MT7621 PCIe Controller. - --config PCIE_MICROCHIP_HOST -- tristate "Microchip AXI PCIe controller" -- depends on PCI_MSI && OF -- select PCI_HOST_COMMON -- help -- Say Y here if you want kernel to support the Microchip AXI PCIe -- Host Bridge driver. -- - config PCI_HYPERV_INTERFACE - tristate "Microsoft Hyper-V PCI Interface" - depends on ((X86 && X86_64) || ARM64) && HYPERV && PCI_MSI -@@ -356,4 +348,5 @@ config PCIE_XILINX_CPM - source "drivers/pci/controller/cadence/Kconfig" - source "drivers/pci/controller/dwc/Kconfig" - source "drivers/pci/controller/mobiveil/Kconfig" -+source "drivers/pci/controller/plda/Kconfig" - endmenu -diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile -index f2b19e6174af..038ccbd9e3ba 100644 ---- a/drivers/pci/controller/Makefile -+++ b/drivers/pci/controller/Makefile -@@ -33,7 +33,6 @@ obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o - obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o - obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o - obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o --obj-$(CONFIG_PCIE_MICROCHIP_HOST) += pcie-microchip-host.o - obj-$(CONFIG_VMD) += vmd.o - obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o - obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o -@@ -44,6 +43,7 @@ obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o - # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW - obj-y += dwc/ - obj-y += mobiveil/ -+obj-y += plda/ - - - # The following drivers are for devices that use the generic ACPI -diff --git a/drivers/pci/controller/plda/Kconfig b/drivers/pci/controller/plda/Kconfig -new file mode 100644 -index 000000000000..5cb3be4fc98c ---- /dev/null -+++ b/drivers/pci/controller/plda/Kconfig -@@ -0,0 +1,14 @@ -+# SPDX-License-Identifier: GPL-2.0 -+ -+menu "PLDA-based PCIe controllers" -+ depends on PCI -+ -+config PCIE_MICROCHIP_HOST -+ tristate "Microchip AXI PCIe controller" -+ depends on PCI_MSI && OF -+ select PCI_HOST_COMMON -+ help -+ Say Y here if you want kernel to support the Microchip AXI PCIe -+ Host Bridge driver. -+ -+endmenu -diff --git a/drivers/pci/controller/plda/Makefile b/drivers/pci/controller/plda/Makefile -new file mode 100644 -index 000000000000..e1a265cbf91c ---- /dev/null -+++ b/drivers/pci/controller/plda/Makefile -@@ -0,0 +1,2 @@ -+# SPDX-License-Identifier: GPL-2.0 -+obj-$(CONFIG_PCIE_MICROCHIP_HOST) += pcie-microchip-host.o -diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c -similarity index 99% -rename from drivers/pci/controller/pcie-microchip-host.c -rename to drivers/pci/controller/plda/pcie-microchip-host.c -index 137fb8570ba2..cb09a8137e25 100644 ---- a/drivers/pci/controller/pcie-microchip-host.c -+++ b/drivers/pci/controller/plda/pcie-microchip-host.c -@@ -18,7 +18,7 @@ - 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(2406:e500:c311:1f::21) with Microsoft SMTP Server (version=TLS1_2, - cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7409.32; Thu, 28 Mar - 2024 09:18:47 +0000 -Received: from SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn - ([fe80::c738:9e6b:f92e:8bb9]) by - SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn ([fe80::c738:9e6b:f92e:8bb9%6]) - with mapi id 15.20.7409.031; Thu, 28 Mar 2024 09:18:47 +0000 -From: Minda Chen -To: Lorenzo Pieralisi , - Conor Dooley , - =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , - Rob Herring , Bjorn Helgaas , - Thomas Gleixner , - Daire McNamara , - Emil Renner Berthing , - Krzysztof Kozlowski -Cc: devicetree@vger.kernel.org, - linux-kernel@vger.kernel.org, - linux-riscv@lists.infradead.org, - linux-pci@vger.kernel.org, - Paul Walmsley , - Palmer Dabbelt , - Albert Ou , - Philipp Zabel , - Mason Huo , - Leyfoon Tan , - Kevin Xie , - Minda Chen -Subject: [PATCH v16 03/22] PCI: microchip: Move PLDA IP register macros to - pcie-plda.h -Date: Thu, 28 Mar 2024 17:18:16 +0800 -Message-Id: <20240328091835.14797-4-minda.chen@starfivetech.com> -X-Mailer: git-send-email 2.17.1 -In-Reply-To: <20240328091835.14797-1-minda.chen@starfivetech.com> -References: <20240328091835.14797-1-minda.chen@starfivetech.com> -X-ClientProxiedBy: NT0PR01CA0020.CHNPR01.prod.partner.outlook.cn - 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20346f6f-0279-46c2-581a-08dc4f081280 -X-MS-Exchange-CrossTenant-AuthSource: - SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn -X-MS-Exchange-CrossTenant-AuthAs: Internal -X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Mar 2024 09:18:46.9632 - (UTC) -X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted -X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c -X-MS-Exchange-CrossTenant-MailboxType: HOSTED -X-MS-Exchange-CrossTenant-UserPrincipalName: - rXUgtRani3aIcYJmLkQUjdkUYL4knuHV27DXp5nOrPiHirO8Z11a5kvnQZGyZxSu1FlpfFcF8VpMiCXD8H6hokaFG/iBLeAlK9O+5Tjz5ug= -X-MS-Exchange-Transport-CrossTenantHeadersStamped: SHXPR01MB0496 - -Move PLDA PCIe host controller IP registers macros to pcie-plda.h, -including bridge registers and PLDA IRQ event number. - -Signed-off-by: Minda Chen -Reviewed-by: Conor Dooley ---- - MAINTAINERS | 1 + - .../pci/controller/plda/pcie-microchip-host.c | 108 +++--------------- - drivers/pci/controller/plda/pcie-plda.h | 108 ++++++++++++++++++ - 3 files changed, 125 insertions(+), 92 deletions(-) - create mode 100644 drivers/pci/controller/plda/pcie-plda.h - -diff --git a/MAINTAINERS b/MAINTAINERS -index dd158cc7b009..1fa4d61291f9 100644 ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -16951,6 +16951,7 @@ M: Daire McNamara - L: linux-pci@vger.kernel.org - S: Maintained - F: Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml -+F: drivers/pci/controller/plda/pcie-plda.h - - PCI DRIVER FOR RENESAS R-CAR - M: Marek Vasut -diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c -index cb09a8137e25..d9030d550482 100644 ---- a/drivers/pci/controller/plda/pcie-microchip-host.c -+++ b/drivers/pci/controller/plda/pcie-microchip-host.c -@@ -19,6 +19,7 @@ - #include - - #include "../../pci.h" -+#include "pcie-plda.h" - - /* Number of MSI IRQs */ - #define MC_MAX_NUM_MSI_IRQS 32 -@@ -30,84 +31,6 @@ - #define MC_PCIE_BRIDGE_ADDR (MC_PCIE1_BRIDGE_ADDR) - #define MC_PCIE_CTRL_ADDR (MC_PCIE1_CTRL_ADDR) - --/* PCIe Bridge Phy Regs */ --#define PCIE_PCI_IRQ_DW0 0xa8 --#define MSIX_CAP_MASK BIT(31) --#define NUM_MSI_MSGS_MASK GENMASK(6, 4) --#define NUM_MSI_MSGS_SHIFT 4 -- --#define IMASK_LOCAL 0x180 --#define DMA_END_ENGINE_0_MASK 0x00000000u --#define DMA_END_ENGINE_0_SHIFT 0 --#define DMA_END_ENGINE_1_MASK 0x00000000u --#define DMA_END_ENGINE_1_SHIFT 1 --#define DMA_ERROR_ENGINE_0_MASK 0x00000100u --#define DMA_ERROR_ENGINE_0_SHIFT 8 --#define DMA_ERROR_ENGINE_1_MASK 0x00000200u --#define DMA_ERROR_ENGINE_1_SHIFT 9 --#define A_ATR_EVT_POST_ERR_MASK 0x00010000u --#define A_ATR_EVT_POST_ERR_SHIFT 16 --#define A_ATR_EVT_FETCH_ERR_MASK 0x00020000u --#define A_ATR_EVT_FETCH_ERR_SHIFT 17 --#define A_ATR_EVT_DISCARD_ERR_MASK 0x00040000u --#define A_ATR_EVT_DISCARD_ERR_SHIFT 18 --#define A_ATR_EVT_DOORBELL_MASK 0x00000000u --#define A_ATR_EVT_DOORBELL_SHIFT 19 --#define P_ATR_EVT_POST_ERR_MASK 0x00100000u --#define P_ATR_EVT_POST_ERR_SHIFT 20 --#define P_ATR_EVT_FETCH_ERR_MASK 0x00200000u --#define P_ATR_EVT_FETCH_ERR_SHIFT 21 --#define P_ATR_EVT_DISCARD_ERR_MASK 0x00400000u --#define P_ATR_EVT_DISCARD_ERR_SHIFT 22 --#define P_ATR_EVT_DOORBELL_MASK 0x00000000u --#define P_ATR_EVT_DOORBELL_SHIFT 23 --#define PM_MSI_INT_INTA_MASK 0x01000000u --#define PM_MSI_INT_INTA_SHIFT 24 --#define PM_MSI_INT_INTB_MASK 0x02000000u --#define PM_MSI_INT_INTB_SHIFT 25 --#define PM_MSI_INT_INTC_MASK 0x04000000u --#define PM_MSI_INT_INTC_SHIFT 26 --#define PM_MSI_INT_INTD_MASK 0x08000000u --#define PM_MSI_INT_INTD_SHIFT 27 --#define PM_MSI_INT_INTX_MASK 0x0f000000u --#define PM_MSI_INT_INTX_SHIFT 24 --#define PM_MSI_INT_MSI_MASK 0x10000000u --#define PM_MSI_INT_MSI_SHIFT 28 --#define PM_MSI_INT_AER_EVT_MASK 0x20000000u --#define PM_MSI_INT_AER_EVT_SHIFT 29 --#define PM_MSI_INT_EVENTS_MASK 0x40000000u --#define PM_MSI_INT_EVENTS_SHIFT 30 --#define PM_MSI_INT_SYS_ERR_MASK 0x80000000u --#define PM_MSI_INT_SYS_ERR_SHIFT 31 --#define NUM_LOCAL_EVENTS 15 --#define ISTATUS_LOCAL 0x184 --#define IMASK_HOST 0x188 --#define ISTATUS_HOST 0x18c --#define IMSI_ADDR 0x190 --#define ISTATUS_MSI 0x194 -- --/* PCIe Master table init defines */ --#define ATR0_PCIE_WIN0_SRCADDR_PARAM 0x600u --#define ATR0_PCIE_ATR_SIZE 0x25 --#define ATR0_PCIE_ATR_SIZE_SHIFT 1 --#define ATR0_PCIE_WIN0_SRC_ADDR 0x604u --#define ATR0_PCIE_WIN0_TRSL_ADDR_LSB 0x608u --#define ATR0_PCIE_WIN0_TRSL_ADDR_UDW 0x60cu --#define ATR0_PCIE_WIN0_TRSL_PARAM 0x610u -- --/* PCIe AXI slave table init defines */ --#define ATR0_AXI4_SLV0_SRCADDR_PARAM 0x800u --#define ATR_SIZE_SHIFT 1 --#define ATR_IMPL_ENABLE 1 --#define ATR0_AXI4_SLV0_SRC_ADDR 0x804u --#define ATR0_AXI4_SLV0_TRSL_ADDR_LSB 0x808u --#define ATR0_AXI4_SLV0_TRSL_ADDR_UDW 0x80cu --#define ATR0_AXI4_SLV0_TRSL_PARAM 0x810u --#define PCIE_TX_RX_INTERFACE 0x00000000u --#define PCIE_CONFIG_INTERFACE 0x00000001u -- --#define ATR_ENTRY_SIZE 32 -- - /* PCIe Controller Phy Regs */ - #define SEC_ERROR_EVENT_CNT 0x20 - #define DED_ERROR_EVENT_CNT 0x24 -@@ -179,20 +102,21 @@ - #define EVENT_LOCAL_DMA_END_ENGINE_1 12 - #define EVENT_LOCAL_DMA_ERROR_ENGINE_0 13 - #define EVENT_LOCAL_DMA_ERROR_ENGINE_1 14 --#define EVENT_LOCAL_A_ATR_EVT_POST_ERR 15 --#define EVENT_LOCAL_A_ATR_EVT_FETCH_ERR 16 --#define EVENT_LOCAL_A_ATR_EVT_DISCARD_ERR 17 --#define EVENT_LOCAL_A_ATR_EVT_DOORBELL 18 --#define EVENT_LOCAL_P_ATR_EVT_POST_ERR 19 --#define EVENT_LOCAL_P_ATR_EVT_FETCH_ERR 20 --#define EVENT_LOCAL_P_ATR_EVT_DISCARD_ERR 21 --#define EVENT_LOCAL_P_ATR_EVT_DOORBELL 22 --#define EVENT_LOCAL_PM_MSI_INT_INTX 23 --#define EVENT_LOCAL_PM_MSI_INT_MSI 24 --#define EVENT_LOCAL_PM_MSI_INT_AER_EVT 25 --#define EVENT_LOCAL_PM_MSI_INT_EVENTS 26 --#define EVENT_LOCAL_PM_MSI_INT_SYS_ERR 27 --#define NUM_EVENTS 28 -+#define NUM_MC_EVENTS 15 -+#define EVENT_LOCAL_A_ATR_EVT_POST_ERR (NUM_MC_EVENTS + PLDA_AXI_POST_ERR) -+#define EVENT_LOCAL_A_ATR_EVT_FETCH_ERR (NUM_MC_EVENTS + PLDA_AXI_FETCH_ERR) -+#define EVENT_LOCAL_A_ATR_EVT_DISCARD_ERR (NUM_MC_EVENTS + PLDA_AXI_DISCARD_ERR) -+#define EVENT_LOCAL_A_ATR_EVT_DOORBELL (NUM_MC_EVENTS + PLDA_AXI_DOORBELL) -+#define EVENT_LOCAL_P_ATR_EVT_POST_ERR (NUM_MC_EVENTS + PLDA_PCIE_POST_ERR) -+#define EVENT_LOCAL_P_ATR_EVT_FETCH_ERR (NUM_MC_EVENTS + PLDA_PCIE_FETCH_ERR) -+#define EVENT_LOCAL_P_ATR_EVT_DISCARD_ERR (NUM_MC_EVENTS + PLDA_PCIE_DISCARD_ERR) -+#define EVENT_LOCAL_P_ATR_EVT_DOORBELL (NUM_MC_EVENTS + PLDA_PCIE_DOORBELL) -+#define EVENT_LOCAL_PM_MSI_INT_INTX (NUM_MC_EVENTS + PLDA_INTX) -+#define EVENT_LOCAL_PM_MSI_INT_MSI (NUM_MC_EVENTS + PLDA_MSI) -+#define EVENT_LOCAL_PM_MSI_INT_AER_EVT (NUM_MC_EVENTS + PLDA_AER_EVENT) -+#define EVENT_LOCAL_PM_MSI_INT_EVENTS (NUM_MC_EVENTS + PLDA_MISC_EVENTS) -+#define EVENT_LOCAL_PM_MSI_INT_SYS_ERR (NUM_MC_EVENTS + PLDA_SYS_ERR) -+#define NUM_EVENTS (NUM_MC_EVENTS + PLDA_INT_EVENT_NUM) - - #define PCIE_EVENT_CAUSE(x, s) \ - [EVENT_PCIE_ ## x] = { __stringify(x), s } -diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h -new file mode 100644 -index 000000000000..65e0f3b72184 ---- /dev/null -+++ b/drivers/pci/controller/plda/pcie-plda.h -@@ -0,0 +1,108 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * PLDA PCIe host controller driver -+ */ -+ -+#ifndef _PCIE_PLDA_H -+#define _PCIE_PLDA_H -+ -+/* PCIe Bridge Phy Regs */ -+#define PCIE_PCI_IRQ_DW0 0xa8 -+#define MSIX_CAP_MASK BIT(31) -+#define NUM_MSI_MSGS_MASK GENMASK(6, 4) -+#define NUM_MSI_MSGS_SHIFT 4 -+ -+#define IMASK_LOCAL 0x180 -+#define DMA_END_ENGINE_0_MASK 0x00000000u -+#define DMA_END_ENGINE_0_SHIFT 0 -+#define DMA_END_ENGINE_1_MASK 0x00000000u -+#define DMA_END_ENGINE_1_SHIFT 1 -+#define DMA_ERROR_ENGINE_0_MASK 0x00000100u -+#define DMA_ERROR_ENGINE_0_SHIFT 8 -+#define DMA_ERROR_ENGINE_1_MASK 0x00000200u -+#define DMA_ERROR_ENGINE_1_SHIFT 9 -+#define A_ATR_EVT_POST_ERR_MASK 0x00010000u -+#define A_ATR_EVT_POST_ERR_SHIFT 16 -+#define A_ATR_EVT_FETCH_ERR_MASK 0x00020000u -+#define A_ATR_EVT_FETCH_ERR_SHIFT 17 -+#define A_ATR_EVT_DISCARD_ERR_MASK 0x00040000u -+#define A_ATR_EVT_DISCARD_ERR_SHIFT 18 -+#define A_ATR_EVT_DOORBELL_MASK 0x00000000u -+#define A_ATR_EVT_DOORBELL_SHIFT 19 -+#define P_ATR_EVT_POST_ERR_MASK 0x00100000u -+#define P_ATR_EVT_POST_ERR_SHIFT 20 -+#define P_ATR_EVT_FETCH_ERR_MASK 0x00200000u -+#define P_ATR_EVT_FETCH_ERR_SHIFT 21 -+#define P_ATR_EVT_DISCARD_ERR_MASK 0x00400000u -+#define P_ATR_EVT_DISCARD_ERR_SHIFT 22 -+#define P_ATR_EVT_DOORBELL_MASK 0x00000000u -+#define P_ATR_EVT_DOORBELL_SHIFT 23 -+#define PM_MSI_INT_INTA_MASK 0x01000000u -+#define PM_MSI_INT_INTA_SHIFT 24 -+#define PM_MSI_INT_INTB_MASK 0x02000000u -+#define PM_MSI_INT_INTB_SHIFT 25 -+#define PM_MSI_INT_INTC_MASK 0x04000000u -+#define PM_MSI_INT_INTC_SHIFT 26 -+#define PM_MSI_INT_INTD_MASK 0x08000000u -+#define PM_MSI_INT_INTD_SHIFT 27 -+#define PM_MSI_INT_INTX_MASK 0x0f000000u -+#define PM_MSI_INT_INTX_SHIFT 24 -+#define PM_MSI_INT_MSI_MASK 0x10000000u -+#define PM_MSI_INT_MSI_SHIFT 28 -+#define PM_MSI_INT_AER_EVT_MASK 0x20000000u -+#define PM_MSI_INT_AER_EVT_SHIFT 29 -+#define PM_MSI_INT_EVENTS_MASK 0x40000000u -+#define PM_MSI_INT_EVENTS_SHIFT 30 -+#define PM_MSI_INT_SYS_ERR_MASK 0x80000000u -+#define PM_MSI_INT_SYS_ERR_SHIFT 31 -+#define NUM_LOCAL_EVENTS 15 -+#define ISTATUS_LOCAL 0x184 -+#define IMASK_HOST 0x188 -+#define ISTATUS_HOST 0x18c -+#define IMSI_ADDR 0x190 -+#define ISTATUS_MSI 0x194 -+ -+/* PCIe Master table init defines */ -+#define ATR0_PCIE_WIN0_SRCADDR_PARAM 0x600u -+#define ATR0_PCIE_ATR_SIZE 0x25 -+#define ATR0_PCIE_ATR_SIZE_SHIFT 1 -+#define ATR0_PCIE_WIN0_SRC_ADDR 0x604u -+#define ATR0_PCIE_WIN0_TRSL_ADDR_LSB 0x608u -+#define ATR0_PCIE_WIN0_TRSL_ADDR_UDW 0x60cu -+#define ATR0_PCIE_WIN0_TRSL_PARAM 0x610u -+ -+/* PCIe AXI slave table init defines */ -+#define ATR0_AXI4_SLV0_SRCADDR_PARAM 0x800u -+#define ATR_SIZE_SHIFT 1 -+#define ATR_IMPL_ENABLE 1 -+#define ATR0_AXI4_SLV0_SRC_ADDR 0x804u -+#define ATR0_AXI4_SLV0_TRSL_ADDR_LSB 0x808u -+#define ATR0_AXI4_SLV0_TRSL_ADDR_UDW 0x80cu -+#define ATR0_AXI4_SLV0_TRSL_PARAM 0x810u -+#define PCIE_TX_RX_INTERFACE 0x00000000u -+#define PCIE_CONFIG_INTERFACE 0x00000001u -+ -+#define ATR_ENTRY_SIZE 32 -+ -+enum plda_int_event { -+ PLDA_AXI_POST_ERR, -+ PLDA_AXI_FETCH_ERR, -+ PLDA_AXI_DISCARD_ERR, -+ PLDA_AXI_DOORBELL, -+ PLDA_PCIE_POST_ERR, -+ PLDA_PCIE_FETCH_ERR, -+ PLDA_PCIE_DISCARD_ERR, -+ PLDA_PCIE_DOORBELL, -+ PLDA_INTX, -+ PLDA_MSI, -+ PLDA_AER_EVENT, -+ PLDA_MISC_EVENTS, -+ PLDA_SYS_ERR, -+ PLDA_INT_EVENT_NUM -+}; -+ -+#define PLDA_NUM_DMA_EVENTS 16 -+ -+#define PLDA_MAX_EVENT_NUM (PLDA_NUM_DMA_EVENTS + PLDA_INT_EVENT_NUM) -+ -+#endif - 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1531236a-9d19-4211-6dec-08dc4f081319 -X-MS-Exchange-CrossTenant-AuthSource: - SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn -X-MS-Exchange-CrossTenant-AuthAs: Internal -X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Mar 2024 09:18:47.9642 - (UTC) -X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted -X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c -X-MS-Exchange-CrossTenant-MailboxType: HOSTED -X-MS-Exchange-CrossTenant-UserPrincipalName: - Gf84FnfnzkpyIrmswrcBLts8mO6yyTzHR5G5q0UeeXUlZmKrreFUeANWOiyHY/Shg2WF9+71H/72+xy0qF8RrBkmZyzGro8SDmBLfJ5X/Vg= -X-MS-Exchange-Transport-CrossTenantHeadersStamped: SHXPR01MB0496 - -Bridge address base is common PLDA field, add this to struct mc_pcie -first. - -INTx and MSI interrupt code will be changed to common code, so get -the bridge base address from port->bridge_addr instead of -axi_base_addr. axi_base_addr is Microchip its own data. - -Signed-off-by: Minda Chen -Reviewed-by: Conor Dooley ---- - .../pci/controller/plda/pcie-microchip-host.c | 23 ++++++++----------- - 1 file changed, 9 insertions(+), 14 deletions(-) - -diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c -index d9030d550482..c55ede80a6d0 100644 ---- a/drivers/pci/controller/plda/pcie-microchip-host.c -+++ b/drivers/pci/controller/plda/pcie-microchip-host.c -@@ -195,6 +195,7 @@ struct mc_pcie { - struct irq_domain *event_domain; - raw_spinlock_t lock; - struct mc_msi msi; -+ void __iomem *bridge_addr; - }; - - struct cause { -@@ -339,8 +340,7 @@ static void mc_handle_msi(struct irq_desc *desc) - struct irq_chip *chip = irq_desc_get_chip(desc); - struct device *dev = port->dev; - struct mc_msi *msi = &port->msi; -- void __iomem *bridge_base_addr = -- port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; -+ void __iomem *bridge_base_addr = port->bridge_addr; - unsigned long status; - u32 bit; - int ret; -@@ -365,8 +365,7 @@ static void mc_handle_msi(struct irq_desc *desc) - static void mc_msi_bottom_irq_ack(struct irq_data *data) - { - struct mc_pcie *port = irq_data_get_irq_chip_data(data); -- void __iomem *bridge_base_addr = -- port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; -+ void __iomem *bridge_base_addr = port->bridge_addr; - u32 bitpos = data->hwirq; - - writel_relaxed(BIT(bitpos), bridge_base_addr + ISTATUS_MSI); -@@ -488,8 +487,7 @@ static void mc_handle_intx(struct irq_desc *desc) - struct mc_pcie *port = irq_desc_get_handler_data(desc); - struct irq_chip *chip = irq_desc_get_chip(desc); - struct device *dev = port->dev; -- void __iomem *bridge_base_addr = -- port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; -+ void __iomem *bridge_base_addr = port->bridge_addr; - unsigned long status; - u32 bit; - int ret; -@@ -514,8 +512,7 @@ static void mc_handle_intx(struct irq_desc *desc) - static void mc_ack_intx_irq(struct irq_data *data) - { - struct mc_pcie *port = irq_data_get_irq_chip_data(data); -- void __iomem *bridge_base_addr = -- port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; -+ void __iomem *bridge_base_addr = port->bridge_addr; - u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); - - writel_relaxed(mask, bridge_base_addr + ISTATUS_LOCAL); -@@ -524,8 +521,7 @@ static void mc_ack_intx_irq(struct irq_data *data) - static void mc_mask_intx_irq(struct irq_data *data) - { - struct mc_pcie *port = irq_data_get_irq_chip_data(data); -- void __iomem *bridge_base_addr = -- port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; -+ void __iomem *bridge_base_addr = port->bridge_addr; - unsigned long flags; - u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); - u32 val; -@@ -540,8 +536,7 @@ static void mc_mask_intx_irq(struct irq_data *data) - static void mc_unmask_intx_irq(struct irq_data *data) - { - struct mc_pcie *port = irq_data_get_irq_chip_data(data); -- void __iomem *bridge_base_addr = -- port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; -+ void __iomem *bridge_base_addr = port->bridge_addr; - unsigned long flags; - u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); - u32 val; -@@ -896,8 +891,7 @@ static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, - static int mc_pcie_setup_windows(struct platform_device *pdev, - struct mc_pcie *port) - { -- void __iomem *bridge_base_addr = -- port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; -+ void __iomem *bridge_base_addr = port->bridge_addr; - struct pci_host_bridge *bridge = platform_get_drvdata(pdev); - struct resource_entry *entry; - u64 pci_addr; -@@ -1081,6 +1075,7 @@ static int mc_host_probe(struct platform_device *pdev) - mc_disable_interrupts(port); - - bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; -+ port->bridge_addr = bridge_base_addr; - - /* Allow enabling MSI by disabling MSI-X */ - val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0); - -From patchwork Thu Mar 28 09:18:18 2024 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Minda Chen -X-Patchwork-Id: 13608298 -X-Patchwork-Delegate: kw@linux.com -Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn - (mail-sh0chn02on2115.outbound.protection.partner.outlook.cn - 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eba31e99-6978-415f-fb01-08dc4f0813af -X-MS-Exchange-CrossTenant-AuthSource: - SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn -X-MS-Exchange-CrossTenant-AuthAs: Internal -X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Mar 2024 09:18:48.9461 - (UTC) -X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted -X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c -X-MS-Exchange-CrossTenant-MailboxType: HOSTED -X-MS-Exchange-CrossTenant-UserPrincipalName: - nNq1Or/I3qVHZE2RveNgOoPfuW6SGIKlgPlcbo0AgSFDIN2m6Y1bCJDSFU8OAPECWSvScZJN7/mlx4/acenCddD9pMkXaym3rFeUQtWP7Zc= -X-MS-Exchange-Transport-CrossTenantHeadersStamped: SHXPR01MB0496 - -Add PLDA PCIe related data structures by rename data structure name from -mc_* to plda_*. - -axi_base_addr is stayed in struct mc_pcie since it's microchip its own -data. - -The event interrupt code is still using struct mc_pcie because the event -interrupt code can not be re-used. - -Signed-off-by: Minda Chen -Reviewed-by: Conor Dooley ---- - .../pci/controller/plda/pcie-microchip-host.c | 96 ++++++++++--------- - 1 file changed, 53 insertions(+), 43 deletions(-) - -diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c -index c55ede80a6d0..df0736f688ce 100644 ---- a/drivers/pci/controller/plda/pcie-microchip-host.c -+++ b/drivers/pci/controller/plda/pcie-microchip-host.c -@@ -22,7 +22,7 @@ - #include "pcie-plda.h" - - /* Number of MSI IRQs */ --#define MC_MAX_NUM_MSI_IRQS 32 -+#define PLDA_MAX_NUM_MSI_IRQS 32 - - /* PCIe Bridge Phy and Controller Phy offsets */ - #define MC_PCIE1_BRIDGE_ADDR 0x00008000u -@@ -179,25 +179,29 @@ struct event_map { - u32 event_bit; - }; - --struct mc_msi { -+struct plda_msi { - struct mutex lock; /* Protect used bitmap */ - struct irq_domain *msi_domain; - struct irq_domain *dev_domain; - u32 num_vectors; - u64 vector_phy; -- DECLARE_BITMAP(used, MC_MAX_NUM_MSI_IRQS); -+ DECLARE_BITMAP(used, PLDA_MAX_NUM_MSI_IRQS); - }; - --struct mc_pcie { -- void __iomem *axi_base_addr; -+struct plda_pcie_rp { - struct device *dev; - struct irq_domain *intx_domain; - struct irq_domain *event_domain; - raw_spinlock_t lock; -- struct mc_msi msi; -+ struct plda_msi msi; - void __iomem *bridge_addr; - }; - -+struct mc_pcie { -+ struct plda_pcie_rp plda; -+ void __iomem *axi_base_addr; -+}; -+ - struct cause { - const char *sym; - const char *str; -@@ -313,7 +317,7 @@ static struct mc_pcie *port; - - static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *ecam) - { -- struct mc_msi *msi = &port->msi; -+ struct plda_msi *msi = &port->plda.msi; - u16 reg; - u8 queue_size; - -@@ -336,10 +340,10 @@ static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *ecam) - - static void mc_handle_msi(struct irq_desc *desc) - { -- struct mc_pcie *port = irq_desc_get_handler_data(desc); -+ struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); - struct irq_chip *chip = irq_desc_get_chip(desc); - struct device *dev = port->dev; -- struct mc_msi *msi = &port->msi; -+ struct plda_msi *msi = &port->msi; - void __iomem *bridge_base_addr = port->bridge_addr; - unsigned long status; - u32 bit; -@@ -364,7 +368,7 @@ static void mc_handle_msi(struct irq_desc *desc) - - static void mc_msi_bottom_irq_ack(struct irq_data *data) - { -- struct mc_pcie *port = irq_data_get_irq_chip_data(data); -+ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); - void __iomem *bridge_base_addr = port->bridge_addr; - u32 bitpos = data->hwirq; - -@@ -373,7 +377,7 @@ static void mc_msi_bottom_irq_ack(struct irq_data *data) - - static void mc_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) - { -- struct mc_pcie *port = irq_data_get_irq_chip_data(data); -+ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); - phys_addr_t addr = port->msi.vector_phy; - - msg->address_lo = lower_32_bits(addr); -@@ -400,8 +404,8 @@ static struct irq_chip mc_msi_bottom_irq_chip = { - static int mc_irq_msi_domain_alloc(struct irq_domain *domain, unsigned int virq, - unsigned int nr_irqs, void *args) - { -- struct mc_pcie *port = domain->host_data; -- struct mc_msi *msi = &port->msi; -+ struct plda_pcie_rp *port = domain->host_data; -+ struct plda_msi *msi = &port->msi; - unsigned long bit; - - mutex_lock(&msi->lock); -@@ -425,8 +429,8 @@ static void mc_irq_msi_domain_free(struct irq_domain *domain, unsigned int virq, - unsigned int nr_irqs) - { - struct irq_data *d = irq_domain_get_irq_data(domain, virq); -- struct mc_pcie *port = irq_data_get_irq_chip_data(d); -- struct mc_msi *msi = &port->msi; -+ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(d); -+ struct plda_msi *msi = &port->msi; - - mutex_lock(&msi->lock); - -@@ -456,11 +460,11 @@ static struct msi_domain_info mc_msi_domain_info = { - .chip = &mc_msi_irq_chip, - }; - --static int mc_allocate_msi_domains(struct mc_pcie *port) -+static int mc_allocate_msi_domains(struct plda_pcie_rp *port) - { - struct device *dev = port->dev; - struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); -- struct mc_msi *msi = &port->msi; -+ struct plda_msi *msi = &port->msi; - - mutex_init(&port->msi.lock); - -@@ -484,7 +488,7 @@ static int mc_allocate_msi_domains(struct mc_pcie *port) - - static void mc_handle_intx(struct irq_desc *desc) - { -- struct mc_pcie *port = irq_desc_get_handler_data(desc); -+ struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); - struct irq_chip *chip = irq_desc_get_chip(desc); - struct device *dev = port->dev; - void __iomem *bridge_base_addr = port->bridge_addr; -@@ -511,7 +515,7 @@ static void mc_handle_intx(struct irq_desc *desc) - - static void mc_ack_intx_irq(struct irq_data *data) - { -- struct mc_pcie *port = irq_data_get_irq_chip_data(data); -+ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); - void __iomem *bridge_base_addr = port->bridge_addr; - u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); - -@@ -520,7 +524,7 @@ static void mc_ack_intx_irq(struct irq_data *data) - - static void mc_mask_intx_irq(struct irq_data *data) - { -- struct mc_pcie *port = irq_data_get_irq_chip_data(data); -+ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); - void __iomem *bridge_base_addr = port->bridge_addr; - unsigned long flags; - u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); -@@ -535,7 +539,7 @@ static void mc_mask_intx_irq(struct irq_data *data) - - static void mc_unmask_intx_irq(struct irq_data *data) - { -- struct mc_pcie *port = irq_data_get_irq_chip_data(data); -+ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); - void __iomem *bridge_base_addr = port->bridge_addr; - unsigned long flags; - u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); -@@ -625,21 +629,22 @@ static u32 local_events(struct mc_pcie *port) - return val; - } - --static u32 get_events(struct mc_pcie *port) -+static u32 get_events(struct plda_pcie_rp *port) - { -+ struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda); - u32 events = 0; - -- events |= pcie_events(port); -- events |= sec_errors(port); -- events |= ded_errors(port); -- events |= local_events(port); -+ events |= pcie_events(mc_port); -+ events |= sec_errors(mc_port); -+ events |= ded_errors(mc_port); -+ events |= local_events(mc_port); - - return events; - } - - static irqreturn_t mc_event_handler(int irq, void *dev_id) - { -- struct mc_pcie *port = dev_id; -+ struct plda_pcie_rp *port = dev_id; - struct device *dev = port->dev; - struct irq_data *data; - -@@ -655,7 +660,7 @@ static irqreturn_t mc_event_handler(int irq, void *dev_id) - - static void mc_handle_event(struct irq_desc *desc) - { -- struct mc_pcie *port = irq_desc_get_handler_data(desc); -+ struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); - unsigned long events; - u32 bit; - struct irq_chip *chip = irq_desc_get_chip(desc); -@@ -672,12 +677,13 @@ static void mc_handle_event(struct irq_desc *desc) - - static void mc_ack_event_irq(struct irq_data *data) - { -- struct mc_pcie *port = irq_data_get_irq_chip_data(data); -+ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); -+ struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda); - u32 event = data->hwirq; - void __iomem *addr; - u32 mask; - -- addr = port->axi_base_addr + event_descs[event].base + -+ addr = mc_port->axi_base_addr + event_descs[event].base + - event_descs[event].offset; - mask = event_descs[event].mask; - mask |= event_descs[event].enb_mask; -@@ -687,13 +693,14 @@ static void mc_ack_event_irq(struct irq_data *data) - - static void mc_mask_event_irq(struct irq_data *data) - { -- struct mc_pcie *port = irq_data_get_irq_chip_data(data); -+ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); -+ struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda); - u32 event = data->hwirq; - void __iomem *addr; - u32 mask; - u32 val; - -- addr = port->axi_base_addr + event_descs[event].base + -+ addr = mc_port->axi_base_addr + event_descs[event].base + - event_descs[event].mask_offset; - mask = event_descs[event].mask; - if (event_descs[event].enb_mask) { -@@ -717,13 +724,14 @@ static void mc_mask_event_irq(struct irq_data *data) - - static void mc_unmask_event_irq(struct irq_data *data) - { -- struct mc_pcie *port = irq_data_get_irq_chip_data(data); -+ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); -+ struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda); - u32 event = data->hwirq; - void __iomem *addr; - u32 mask; - u32 val; - -- addr = port->axi_base_addr + event_descs[event].base + -+ addr = mc_port->axi_base_addr + event_descs[event].base + - event_descs[event].mask_offset; - mask = event_descs[event].mask; - -@@ -811,7 +819,7 @@ static int mc_pcie_init_clks(struct device *dev) - return 0; - } - --static int mc_pcie_init_irq_domains(struct mc_pcie *port) -+static int mc_pcie_init_irq_domains(struct plda_pcie_rp *port) - { - struct device *dev = port->dev; - struct device_node *node = dev->of_node; -@@ -889,7 +897,7 @@ static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, - } - - static int mc_pcie_setup_windows(struct platform_device *pdev, -- struct mc_pcie *port) -+ struct plda_pcie_rp *port) - { - void __iomem *bridge_base_addr = port->bridge_addr; - struct pci_host_bridge *bridge = platform_get_drvdata(pdev); -@@ -970,7 +978,7 @@ static void mc_disable_interrupts(struct mc_pcie *port) - writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST); - } - --static int mc_init_interrupts(struct platform_device *pdev, struct mc_pcie *port) -+static int mc_init_interrupts(struct platform_device *pdev, struct plda_pcie_rp *port) - { - struct device *dev = &pdev->dev; - int irq; -@@ -1043,12 +1051,12 @@ static int mc_platform_init(struct pci_config_window *cfg) - mc_pcie_enable_msi(port, cfg->win); - - /* Configure non-config space outbound ranges */ -- ret = mc_pcie_setup_windows(pdev, port); -+ ret = mc_pcie_setup_windows(pdev, &port->plda); - if (ret) - return ret; - - /* Address translation is up; safe to enable interrupts */ -- ret = mc_init_interrupts(pdev, port); -+ ret = mc_init_interrupts(pdev, &port->plda); - if (ret) - return ret; - -@@ -1059,6 +1067,7 @@ static int mc_host_probe(struct platform_device *pdev) - { - struct device *dev = &pdev->dev; - void __iomem *bridge_base_addr; -+ struct plda_pcie_rp *plda; - int ret; - u32 val; - -@@ -1066,7 +1075,8 @@ static int mc_host_probe(struct platform_device *pdev) - if (!port) - return -ENOMEM; - -- port->dev = dev; -+ plda = &port->plda; -+ plda->dev = dev; - - port->axi_base_addr = devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(port->axi_base_addr)) -@@ -1075,7 +1085,7 @@ static int mc_host_probe(struct platform_device *pdev) - mc_disable_interrupts(port); - - bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; -- port->bridge_addr = bridge_base_addr; -+ plda->bridge_addr = bridge_base_addr; - - /* Allow enabling MSI by disabling MSI-X */ - val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0); -@@ -1087,10 +1097,10 @@ static int mc_host_probe(struct platform_device *pdev) - val &= NUM_MSI_MSGS_MASK; - val >>= NUM_MSI_MSGS_SHIFT; - -- port->msi.num_vectors = 1 << val; -+ plda->msi.num_vectors = 1 << val; - - /* Pick vector address from design */ -- port->msi.vector_phy = readl_relaxed(bridge_base_addr + IMSI_ADDR); -+ plda->msi.vector_phy = readl_relaxed(bridge_base_addr + IMSI_ADDR); - - ret = mc_pcie_init_clks(dev); - if (ret) { - -From patchwork Thu Mar 28 09:18:19 2024 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Minda Chen -X-Patchwork-Id: 13608242 -X-Patchwork-Delegate: kw@linux.com -Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn - 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1a4f727a-0627-446f-de7b-08dc4f081445 -X-MS-Exchange-CrossTenant-AuthSource: - SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn -X-MS-Exchange-CrossTenant-AuthAs: Internal -X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Mar 2024 09:18:49.9299 - (UTC) -X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted -X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c -X-MS-Exchange-CrossTenant-MailboxType: HOSTED -X-MS-Exchange-CrossTenant-UserPrincipalName: - LCHQ2sJHbI/lT7eo2ROwhPuuYZ+Sxfs29NJD+imxzLfPJMh+gkZZJnHXBaiI++zLXXOxQAyJa0ojj/it/a8ib8kjDUGET09inyxbr8o65Zk= -X-MS-Exchange-Transport-CrossTenantHeadersStamped: SHXPR01MB0496 - -Move the common data structures definition to head file becauce these two -data structures can be re-used. - -Signed-off-by: Minda Chen -Reviewed-by: Conor Dooley ---- - .../pci/controller/plda/pcie-microchip-host.c | 20 ------------------ - drivers/pci/controller/plda/pcie-plda.h | 21 +++++++++++++++++++ - 2 files changed, 21 insertions(+), 20 deletions(-) - -diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c -index df0736f688ce..a554a56cc0e8 100644 ---- a/drivers/pci/controller/plda/pcie-microchip-host.c -+++ b/drivers/pci/controller/plda/pcie-microchip-host.c -@@ -21,9 +21,6 @@ - #include "../../pci.h" - #include "pcie-plda.h" - --/* Number of MSI IRQs */ --#define PLDA_MAX_NUM_MSI_IRQS 32 -- - /* PCIe Bridge Phy and Controller Phy offsets */ - #define MC_PCIE1_BRIDGE_ADDR 0x00008000u - #define MC_PCIE1_CTRL_ADDR 0x0000a000u -@@ -179,23 +176,6 @@ struct event_map { - u32 event_bit; - }; - --struct plda_msi { -- struct mutex lock; /* Protect used bitmap */ -- struct irq_domain *msi_domain; -- struct irq_domain *dev_domain; -- u32 num_vectors; -- u64 vector_phy; -- DECLARE_BITMAP(used, PLDA_MAX_NUM_MSI_IRQS); --}; -- --struct plda_pcie_rp { -- struct device *dev; -- struct irq_domain *intx_domain; -- struct irq_domain *event_domain; -- raw_spinlock_t lock; -- struct plda_msi msi; -- void __iomem *bridge_addr; --}; - - struct mc_pcie { - struct plda_pcie_rp plda; -diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h -index 65e0f3b72184..9ca66916c609 100644 ---- a/drivers/pci/controller/plda/pcie-plda.h -+++ b/drivers/pci/controller/plda/pcie-plda.h -@@ -6,6 +6,9 @@ - #ifndef _PCIE_PLDA_H - #define _PCIE_PLDA_H - -+/* Number of MSI IRQs */ -+#define PLDA_MAX_NUM_MSI_IRQS 32 -+ - /* PCIe Bridge Phy Regs */ - #define PCIE_PCI_IRQ_DW0 0xa8 - #define MSIX_CAP_MASK BIT(31) -@@ -105,4 +108,22 @@ enum plda_int_event { - - #define PLDA_MAX_EVENT_NUM (PLDA_NUM_DMA_EVENTS + PLDA_INT_EVENT_NUM) - -+struct plda_msi { -+ struct mutex lock; /* Protect used bitmap */ -+ struct irq_domain *msi_domain; -+ struct irq_domain *dev_domain; -+ u32 num_vectors; -+ u64 vector_phy; -+ DECLARE_BITMAP(used, PLDA_MAX_NUM_MSI_IRQS); -+}; -+ -+struct plda_pcie_rp { -+ struct device *dev; -+ struct irq_domain *intx_domain; -+ struct irq_domain *event_domain; -+ raw_spinlock_t lock; -+ struct plda_msi msi; -+ void __iomem *bridge_addr; -+}; -+ - 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c89e9911-47ac-4aad-3f8f-08dc4f0814dc -X-MS-Exchange-CrossTenant-AuthSource: - SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn -X-MS-Exchange-CrossTenant-AuthAs: Internal -X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Mar 2024 09:18:50.9253 - (UTC) -X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted -X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c -X-MS-Exchange-CrossTenant-MailboxType: HOSTED -X-MS-Exchange-CrossTenant-UserPrincipalName: - cPw+Mao2oxql5095ghqm4WH43F0BWhE9+b1csmwiC7m/5Vrcv+0SjFghlMXqrmJ01YEP43JpArLGqCQQ4mc33hzDNeIVqdf7v9voIyQp4tI= -X-MS-Exchange-Transport-CrossTenantHeadersStamped: SHXPR01MB0496 - -Rename two setup functions to plda prefix. Prepare to re-use these two -setup functions. - -Since two setup functions names are similar, rename mc_pcie_setup_windows() -to plda_pcie_setup_iomems(). - -Signed-off-by: Minda Chen -Reviewed-by: Conor Dooley ---- - .../pci/controller/plda/pcie-microchip-host.c | 24 +++++++++---------- - 1 file changed, 12 insertions(+), 12 deletions(-) - -diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c -index a554a56cc0e8..9b367927cd32 100644 ---- a/drivers/pci/controller/plda/pcie-microchip-host.c -+++ b/drivers/pci/controller/plda/pcie-microchip-host.c -@@ -838,9 +838,9 @@ static int mc_pcie_init_irq_domains(struct plda_pcie_rp *port) - return mc_allocate_msi_domains(port); - } - --static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, -- phys_addr_t axi_addr, phys_addr_t pci_addr, -- size_t size) -+static void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, -+ phys_addr_t axi_addr, phys_addr_t pci_addr, -+ size_t size) - { - u32 atr_sz = ilog2(size) - 1; - u32 val; -@@ -876,8 +876,8 @@ static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, - writel(0, bridge_base_addr + ATR0_PCIE_WIN0_SRC_ADDR); - } - --static int mc_pcie_setup_windows(struct platform_device *pdev, -- struct plda_pcie_rp *port) -+static int plda_pcie_setup_iomems(struct platform_device *pdev, -+ struct plda_pcie_rp *port) - { - void __iomem *bridge_base_addr = port->bridge_addr; - struct pci_host_bridge *bridge = platform_get_drvdata(pdev); -@@ -888,9 +888,9 @@ static int mc_pcie_setup_windows(struct platform_device *pdev, - resource_list_for_each_entry(entry, &bridge->windows) { - if (resource_type(entry->res) == IORESOURCE_MEM) { - pci_addr = entry->res->start - entry->offset; -- mc_pcie_setup_window(bridge_base_addr, index, -- entry->res->start, pci_addr, -- resource_size(entry->res)); -+ plda_pcie_setup_window(bridge_base_addr, index, -+ entry->res->start, pci_addr, -+ resource_size(entry->res)); - index++; - } - } -@@ -1023,15 +1023,15 @@ static int mc_platform_init(struct pci_config_window *cfg) - int ret; - - /* Configure address translation table 0 for PCIe config space */ -- mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start, -- cfg->res.start, -- resource_size(&cfg->res)); -+ plda_pcie_setup_window(bridge_base_addr, 0, cfg->res.start, -+ cfg->res.start, -+ resource_size(&cfg->res)); - - /* Need some fixups in config space */ - mc_pcie_enable_msi(port, cfg->win); - - /* Configure non-config space outbound ranges */ -- ret = mc_pcie_setup_windows(pdev, &port->plda); -+ ret = plda_pcie_setup_iomems(pdev, &port->plda); - if (ret) - return ret; - - -From patchwork Thu Mar 28 09:18:21 2024 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Minda Chen -X-Patchwork-Id: 13608235 -X-Patchwork-Delegate: kw@linux.com -Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn - (mail-sh0chn02on2111.outbound.protection.partner.outlook.cn - [139.219.146.111]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60E4662172; 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Thu, 28 Mar 2024 09:18:51 +0000 -From: Minda Chen -To: Lorenzo Pieralisi , - Conor Dooley , - =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , - Rob Herring , Bjorn Helgaas , - Thomas Gleixner , - Daire McNamara , - Emil Renner Berthing , - Krzysztof Kozlowski -Cc: devicetree@vger.kernel.org, - linux-kernel@vger.kernel.org, - linux-riscv@lists.infradead.org, - linux-pci@vger.kernel.org, - Paul Walmsley , - Palmer Dabbelt , - Albert Ou , - Philipp Zabel , - Mason Huo , - Leyfoon Tan , - Kevin Xie , - Minda Chen -Subject: [PATCH v16 08/22] PCI: microchip: Change the argument of - plda_pcie_setup_iomems() -Date: Thu, 28 Mar 2024 17:18:21 +0800 -Message-Id: <20240328091835.14797-9-minda.chen@starfivetech.com> -X-Mailer: git-send-email 2.17.1 -In-Reply-To: <20240328091835.14797-1-minda.chen@starfivetech.com> -References: <20240328091835.14797-1-minda.chen@starfivetech.com> -X-ClientProxiedBy: NT0PR01CA0020.CHNPR01.prod.partner.outlook.cn - (2406:e500:c510:c::16) To SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn - (2406:e500:c311:25::15) -Precedence: bulk -X-Mailing-List: linux-pci@vger.kernel.org -List-Id: -List-Subscribe: -List-Unsubscribe: -MIME-Version: 1.0 -X-MS-PublicTrafficType: Email -X-MS-TrafficTypeDiagnostic: SHXPR01MB0863:EE_|SHXPR01MB0526:EE_ -X-MS-Office365-Filtering-Correlation-Id: a799fe66-961b-4faf-0bdc-08dc4f081574 -X-MS-Exchange-SenderADCheck: 1 -X-Microsoft-Antispam: BCL:0; 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- } - --static int plda_pcie_setup_iomems(struct platform_device *pdev, -+static int plda_pcie_setup_iomems(struct pci_host_bridge *bridge, - struct plda_pcie_rp *port) - { - void __iomem *bridge_base_addr = port->bridge_addr; -- struct pci_host_bridge *bridge = platform_get_drvdata(pdev); - struct resource_entry *entry; - u64 pci_addr; - u32 index = 1; -@@ -1018,6 +1017,7 @@ static int mc_platform_init(struct pci_config_window *cfg) - { - struct device *dev = cfg->parent; - struct platform_device *pdev = to_platform_device(dev); -+ struct pci_host_bridge *bridge = platform_get_drvdata(pdev); - void __iomem *bridge_base_addr = - port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; - int ret; -@@ -1031,7 +1031,7 @@ static int mc_platform_init(struct pci_config_window *cfg) - mc_pcie_enable_msi(port, cfg->win); - - /* Configure non-config space outbound ranges */ -- ret = plda_pcie_setup_iomems(pdev, &port->plda); -+ ret = plda_pcie_setup_iomems(bridge, &port->plda); - if (ret) - return ret; - - -From patchwork Thu Mar 28 09:18:22 2024 -Content-Type: text/plain; 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So these two functions -can be re-used. - -Signed-off-by: Minda Chen -Reviewed-by: Conor Dooley ---- - MAINTAINERS | 1 + - drivers/pci/controller/plda/Kconfig | 4 + - drivers/pci/controller/plda/Makefile | 1 + - .../pci/controller/plda/pcie-microchip-host.c | 59 --------------- - drivers/pci/controller/plda/pcie-plda-host.c | 73 +++++++++++++++++++ - drivers/pci/controller/plda/pcie-plda.h | 5 ++ - 6 files changed, 84 insertions(+), 59 deletions(-) - create mode 100644 drivers/pci/controller/plda/pcie-plda-host.c - -diff --git a/MAINTAINERS b/MAINTAINERS -index 1fa4d61291f9..d85d9db38efa 100644 ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -16951,6 +16951,7 @@ M: Daire McNamara - L: linux-pci@vger.kernel.org - S: Maintained - F: Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml -+F: drivers/pci/controller/plda/pcie-plda-host.c - F: drivers/pci/controller/plda/pcie-plda.h - - PCI DRIVER FOR RENESAS R-CAR -diff --git a/drivers/pci/controller/plda/Kconfig b/drivers/pci/controller/plda/Kconfig -index 5cb3be4fc98c..e54a82ee94f5 100644 ---- a/drivers/pci/controller/plda/Kconfig -+++ b/drivers/pci/controller/plda/Kconfig -@@ -3,10 +3,14 @@ - menu "PLDA-based PCIe controllers" - depends on PCI - -+config PCIE_PLDA_HOST -+ bool -+ - config PCIE_MICROCHIP_HOST - tristate "Microchip AXI PCIe controller" - depends on PCI_MSI && OF - select PCI_HOST_COMMON -+ select PCIE_PLDA_HOST - help - Say Y here if you want kernel to support the Microchip AXI PCIe - Host Bridge driver. -diff --git a/drivers/pci/controller/plda/Makefile b/drivers/pci/controller/plda/Makefile -index e1a265cbf91c..4340ab007f44 100644 ---- a/drivers/pci/controller/plda/Makefile -+++ b/drivers/pci/controller/plda/Makefile -@@ -1,2 +1,3 @@ - # SPDX-License-Identifier: GPL-2.0 -+obj-$(CONFIG_PCIE_PLDA_HOST) += pcie-plda-host.o - obj-$(CONFIG_PCIE_MICROCHIP_HOST) += pcie-microchip-host.o -diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c -index 805870aed61d..573ad31c578a 100644 ---- a/drivers/pci/controller/plda/pcie-microchip-host.c -+++ b/drivers/pci/controller/plda/pcie-microchip-host.c -@@ -838,65 +838,6 @@ static int mc_pcie_init_irq_domains(struct plda_pcie_rp *port) - return mc_allocate_msi_domains(port); - } - --static void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, -- phys_addr_t axi_addr, phys_addr_t pci_addr, -- size_t size) --{ -- u32 atr_sz = ilog2(size) - 1; -- u32 val; -- -- if (index == 0) -- val = PCIE_CONFIG_INTERFACE; -- else -- val = PCIE_TX_RX_INTERFACE; -- -- writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + -- ATR0_AXI4_SLV0_TRSL_PARAM); -- -- val = lower_32_bits(axi_addr) | (atr_sz << ATR_SIZE_SHIFT) | -- ATR_IMPL_ENABLE; -- writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + -- ATR0_AXI4_SLV0_SRCADDR_PARAM); -- -- val = upper_32_bits(axi_addr); -- writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + -- ATR0_AXI4_SLV0_SRC_ADDR); -- -- val = lower_32_bits(pci_addr); -- writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + -- ATR0_AXI4_SLV0_TRSL_ADDR_LSB); -- -- val = upper_32_bits(pci_addr); -- writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + -- ATR0_AXI4_SLV0_TRSL_ADDR_UDW); -- -- val = readl(bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); -- val |= (ATR0_PCIE_ATR_SIZE << ATR0_PCIE_ATR_SIZE_SHIFT); -- writel(val, bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); -- writel(0, bridge_base_addr + ATR0_PCIE_WIN0_SRC_ADDR); --} -- --static int plda_pcie_setup_iomems(struct pci_host_bridge *bridge, -- struct plda_pcie_rp *port) --{ -- void __iomem *bridge_base_addr = port->bridge_addr; -- struct resource_entry *entry; -- u64 pci_addr; -- u32 index = 1; -- -- resource_list_for_each_entry(entry, &bridge->windows) { -- if (resource_type(entry->res) == IORESOURCE_MEM) { -- pci_addr = entry->res->start - entry->offset; -- plda_pcie_setup_window(bridge_base_addr, index, -- entry->res->start, pci_addr, -- resource_size(entry->res)); -- index++; -- } -- } -- -- return 0; --} -- - static inline void mc_clear_secs(struct mc_pcie *port) - { - void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; -diff --git a/drivers/pci/controller/plda/pcie-plda-host.c b/drivers/pci/controller/plda/pcie-plda-host.c -new file mode 100644 -index 000000000000..05ea68baebfb ---- /dev/null -+++ b/drivers/pci/controller/plda/pcie-plda-host.c -@@ -0,0 +1,73 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * PLDA PCIe XpressRich host controller driver -+ * -+ * Copyright (C) 2023 Microchip Co. Ltd -+ * -+ * Author: Daire McNamara -+ */ -+ -+#include -+ -+#include "pcie-plda.h" -+ -+void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, -+ phys_addr_t axi_addr, phys_addr_t pci_addr, -+ size_t size) -+{ -+ u32 atr_sz = ilog2(size) - 1; -+ u32 val; -+ -+ if (index == 0) -+ val = PCIE_CONFIG_INTERFACE; -+ else -+ val = PCIE_TX_RX_INTERFACE; -+ -+ writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + -+ ATR0_AXI4_SLV0_TRSL_PARAM); -+ -+ val = lower_32_bits(axi_addr) | (atr_sz << ATR_SIZE_SHIFT) | -+ ATR_IMPL_ENABLE; -+ writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + -+ ATR0_AXI4_SLV0_SRCADDR_PARAM); -+ -+ val = upper_32_bits(axi_addr); -+ writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + -+ ATR0_AXI4_SLV0_SRC_ADDR); -+ -+ val = lower_32_bits(pci_addr); -+ writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + -+ ATR0_AXI4_SLV0_TRSL_ADDR_LSB); -+ -+ val = upper_32_bits(pci_addr); -+ writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + -+ ATR0_AXI4_SLV0_TRSL_ADDR_UDW); -+ -+ val = readl(bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); -+ val |= (ATR0_PCIE_ATR_SIZE << ATR0_PCIE_ATR_SIZE_SHIFT); -+ writel(val, bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); -+ writel(0, bridge_base_addr + ATR0_PCIE_WIN0_SRC_ADDR); -+} -+EXPORT_SYMBOL_GPL(plda_pcie_setup_window); -+ -+int plda_pcie_setup_iomems(struct pci_host_bridge *bridge, -+ struct plda_pcie_rp *port) -+{ -+ void __iomem *bridge_base_addr = port->bridge_addr; -+ struct resource_entry *entry; -+ u64 pci_addr; -+ u32 index = 1; -+ -+ resource_list_for_each_entry(entry, &bridge->windows) { -+ if (resource_type(entry->res) == IORESOURCE_MEM) { -+ pci_addr = entry->res->start - entry->offset; -+ plda_pcie_setup_window(bridge_base_addr, index, -+ entry->res->start, pci_addr, -+ resource_size(entry->res)); -+ index++; -+ } -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(plda_pcie_setup_iomems); -diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h -index 9ca66916c609..e277a5452b5d 100644 ---- a/drivers/pci/controller/plda/pcie-plda.h -+++ b/drivers/pci/controller/plda/pcie-plda.h -@@ -126,4 +126,9 @@ struct plda_pcie_rp { - void __iomem *bridge_addr; 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- } - --static void mc_handle_msi(struct irq_desc *desc) -+static void plda_handle_msi(struct irq_desc *desc) - { - struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); - struct irq_chip *chip = irq_desc_get_chip(desc); -@@ -346,7 +346,7 @@ static void mc_handle_msi(struct irq_desc *desc) - chained_irq_exit(chip, desc); - } - --static void mc_msi_bottom_irq_ack(struct irq_data *data) -+static void plda_msi_bottom_irq_ack(struct irq_data *data) - { - struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); - void __iomem *bridge_base_addr = port->bridge_addr; -@@ -355,7 +355,7 @@ static void mc_msi_bottom_irq_ack(struct irq_data *data) - writel_relaxed(BIT(bitpos), bridge_base_addr + ISTATUS_MSI); - } - --static void mc_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) -+static void plda_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) - { - struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); - phys_addr_t addr = port->msi.vector_phy; -@@ -368,21 +368,23 @@ static void mc_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) - (int)data->hwirq, msg->address_hi, msg->address_lo); - } - --static int mc_msi_set_affinity(struct irq_data *irq_data, -- const struct cpumask *mask, bool force) -+static int plda_msi_set_affinity(struct irq_data *irq_data, -+ const struct cpumask *mask, bool force) - { - return -EINVAL; - } - --static struct irq_chip mc_msi_bottom_irq_chip = { -- .name = "Microchip MSI", -- .irq_ack = mc_msi_bottom_irq_ack, -- .irq_compose_msi_msg = mc_compose_msi_msg, -- .irq_set_affinity = mc_msi_set_affinity, -+static struct irq_chip plda_msi_bottom_irq_chip = { -+ .name = "PLDA MSI", -+ .irq_ack = plda_msi_bottom_irq_ack, -+ .irq_compose_msi_msg = plda_compose_msi_msg, -+ .irq_set_affinity = plda_msi_set_affinity, - }; - --static int mc_irq_msi_domain_alloc(struct irq_domain *domain, unsigned int virq, -- unsigned int nr_irqs, void *args) -+static int plda_irq_msi_domain_alloc(struct irq_domain *domain, -+ unsigned int virq, -+ unsigned int nr_irqs, -+ void *args) - { - struct plda_pcie_rp *port = domain->host_data; - struct plda_msi *msi = &port->msi; -@@ -397,7 +399,7 @@ static int mc_irq_msi_domain_alloc(struct irq_domain *domain, unsigned int virq, - - set_bit(bit, msi->used); - -- irq_domain_set_info(domain, virq, bit, &mc_msi_bottom_irq_chip, -+ irq_domain_set_info(domain, virq, bit, &plda_msi_bottom_irq_chip, - domain->host_data, handle_edge_irq, NULL, NULL); - - mutex_unlock(&msi->lock); -@@ -405,8 +407,9 @@ static int mc_irq_msi_domain_alloc(struct irq_domain *domain, unsigned int virq, - return 0; - } - --static void mc_irq_msi_domain_free(struct irq_domain *domain, unsigned int virq, -- unsigned int nr_irqs) -+static void plda_irq_msi_domain_free(struct irq_domain *domain, -+ unsigned int virq, -+ unsigned int nr_irqs) - { - struct irq_data *d = irq_domain_get_irq_data(domain, virq); - struct plda_pcie_rp *port = irq_data_get_irq_chip_data(d); -@@ -423,24 +426,24 @@ static void mc_irq_msi_domain_free(struct irq_domain *domain, unsigned int virq, - } - - static const struct irq_domain_ops msi_domain_ops = { -- .alloc = mc_irq_msi_domain_alloc, -- .free = mc_irq_msi_domain_free, -+ .alloc = plda_irq_msi_domain_alloc, -+ .free = plda_irq_msi_domain_free, - }; - --static struct irq_chip mc_msi_irq_chip = { -- .name = "Microchip PCIe MSI", -+static struct irq_chip plda_msi_irq_chip = { -+ .name = "PLDA PCIe MSI", - .irq_ack = irq_chip_ack_parent, - .irq_mask = pci_msi_mask_irq, - .irq_unmask = pci_msi_unmask_irq, - }; - --static struct msi_domain_info mc_msi_domain_info = { -+static struct msi_domain_info plda_msi_domain_info = { - .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | - MSI_FLAG_PCI_MSIX), -- .chip = &mc_msi_irq_chip, -+ .chip = &plda_msi_irq_chip, - }; - --static int mc_allocate_msi_domains(struct plda_pcie_rp *port) -+static int plda_allocate_msi_domains(struct plda_pcie_rp *port) - { - struct device *dev = port->dev; - struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); -@@ -455,7 +458,8 @@ static int mc_allocate_msi_domains(struct plda_pcie_rp *port) - return -ENOMEM; - } - -- msi->msi_domain = pci_msi_create_irq_domain(fwnode, &mc_msi_domain_info, -+ msi->msi_domain = pci_msi_create_irq_domain(fwnode, -+ &plda_msi_domain_info, - msi->dev_domain); - if (!msi->msi_domain) { - dev_err(dev, "failed to create MSI domain\n"); -@@ -466,7 +470,7 @@ static int mc_allocate_msi_domains(struct plda_pcie_rp *port) - return 0; - } - --static void mc_handle_intx(struct irq_desc *desc) -+static void plda_handle_intx(struct irq_desc *desc) - { - struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); - struct irq_chip *chip = irq_desc_get_chip(desc); -@@ -493,7 +497,7 @@ static void mc_handle_intx(struct irq_desc *desc) - chained_irq_exit(chip, desc); - } - --static void mc_ack_intx_irq(struct irq_data *data) -+static void plda_ack_intx_irq(struct irq_data *data) - { - struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); - void __iomem *bridge_base_addr = port->bridge_addr; -@@ -502,7 +506,7 @@ static void mc_ack_intx_irq(struct irq_data *data) - writel_relaxed(mask, bridge_base_addr + ISTATUS_LOCAL); - } - --static void mc_mask_intx_irq(struct irq_data *data) -+static void plda_mask_intx_irq(struct irq_data *data) - { - struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); - void __iomem *bridge_base_addr = port->bridge_addr; -@@ -517,7 +521,7 @@ static void mc_mask_intx_irq(struct irq_data *data) - raw_spin_unlock_irqrestore(&port->lock, flags); - } - --static void mc_unmask_intx_irq(struct irq_data *data) -+static void plda_unmask_intx_irq(struct irq_data *data) - { - struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); - void __iomem *bridge_base_addr = port->bridge_addr; -@@ -532,24 +536,24 @@ static void mc_unmask_intx_irq(struct irq_data *data) - raw_spin_unlock_irqrestore(&port->lock, flags); - } - --static struct irq_chip mc_intx_irq_chip = { -- .name = "Microchip PCIe INTx", -- .irq_ack = mc_ack_intx_irq, -- .irq_mask = mc_mask_intx_irq, -- .irq_unmask = mc_unmask_intx_irq, -+static struct irq_chip plda_intx_irq_chip = { -+ .name = "PLDA PCIe INTx", -+ .irq_ack = plda_ack_intx_irq, -+ .irq_mask = plda_mask_intx_irq, -+ .irq_unmask = plda_unmask_intx_irq, - }; - --static int mc_pcie_intx_map(struct irq_domain *domain, unsigned int irq, -- irq_hw_number_t hwirq) -+static int plda_pcie_intx_map(struct irq_domain *domain, unsigned int irq, -+ irq_hw_number_t hwirq) - { -- irq_set_chip_and_handler(irq, &mc_intx_irq_chip, handle_level_irq); -+ irq_set_chip_and_handler(irq, &plda_intx_irq_chip, handle_level_irq); - irq_set_chip_data(irq, domain->host_data); - - return 0; - } - - static const struct irq_domain_ops intx_domain_ops = { -- .map = mc_pcie_intx_map, -+ .map = plda_pcie_intx_map, - }; - - static inline u32 reg_to_event(u32 reg, struct event_map field) -@@ -609,7 +613,7 @@ static u32 local_events(struct mc_pcie *port) - return val; - } - --static u32 get_events(struct plda_pcie_rp *port) -+static u32 mc_get_events(struct plda_pcie_rp *port) - { - struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda); - u32 events = 0; -@@ -638,7 +642,7 @@ static irqreturn_t mc_event_handler(int irq, void *dev_id) - return IRQ_HANDLED; - } - --static void mc_handle_event(struct irq_desc *desc) -+static void plda_handle_event(struct irq_desc *desc) - { - struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); - unsigned long events; -@@ -647,7 +651,7 @@ static void mc_handle_event(struct irq_desc *desc) - - chained_irq_enter(chip, desc); - -- events = get_events(port); -+ events = mc_get_events(port); - - for_each_set_bit(bit, &events, NUM_EVENTS) - generic_handle_domain_irq(port->event_domain, bit); -@@ -741,8 +745,8 @@ static struct irq_chip mc_event_irq_chip = { - .irq_unmask = mc_unmask_event_irq, - }; - --static int mc_pcie_event_map(struct irq_domain *domain, unsigned int irq, -- irq_hw_number_t hwirq) -+static int plda_pcie_event_map(struct irq_domain *domain, unsigned int irq, -+ irq_hw_number_t hwirq) - { - irq_set_chip_and_handler(irq, &mc_event_irq_chip, handle_level_irq); - irq_set_chip_data(irq, domain->host_data); -@@ -750,8 +754,8 @@ static int mc_pcie_event_map(struct irq_domain *domain, unsigned int irq, - return 0; - } - --static const struct irq_domain_ops event_domain_ops = { -- .map = mc_pcie_event_map, -+static const struct irq_domain_ops plda_event_domain_ops = { -+ .map = plda_pcie_event_map, - }; - - static inline void mc_pcie_deinit_clk(void *data) -@@ -799,7 +803,7 @@ static int mc_pcie_init_clks(struct device *dev) - return 0; - } - --static int mc_pcie_init_irq_domains(struct plda_pcie_rp *port) -+static int plda_pcie_init_irq_domains(struct plda_pcie_rp *port) - { - struct device *dev = port->dev; - struct device_node *node = dev->of_node; -@@ -813,7 +817,8 @@ static int mc_pcie_init_irq_domains(struct plda_pcie_rp *port) - } - - port->event_domain = irq_domain_add_linear(pcie_intc_node, NUM_EVENTS, -- &event_domain_ops, port); -+ &plda_event_domain_ops, -+ port); - if (!port->event_domain) { - dev_err(dev, "failed to get event domain\n"); - of_node_put(pcie_intc_node); -@@ -835,7 +840,7 @@ static int mc_pcie_init_irq_domains(struct plda_pcie_rp *port) - of_node_put(pcie_intc_node); - raw_spin_lock_init(&port->lock); - -- return mc_allocate_msi_domains(port); -+ return plda_allocate_msi_domains(port); - } - - static inline void mc_clear_secs(struct mc_pcie *port) -@@ -898,14 +903,14 @@ static void mc_disable_interrupts(struct mc_pcie *port) - writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST); - } - --static int mc_init_interrupts(struct platform_device *pdev, struct plda_pcie_rp *port) -+static int plda_init_interrupts(struct platform_device *pdev, struct plda_pcie_rp *port) - { - struct device *dev = &pdev->dev; - int irq; - int i, intx_irq, msi_irq, event_irq; - int ret; - -- ret = mc_pcie_init_irq_domains(port); -+ ret = plda_pcie_init_irq_domains(port); - if (ret) { - dev_err(dev, "failed creating IRQ domains\n"); - return ret; -@@ -938,7 +943,7 @@ static int mc_init_interrupts(struct platform_device *pdev, struct plda_pcie_rp - } - - /* Plug the INTx chained handler */ -- irq_set_chained_handler_and_data(intx_irq, mc_handle_intx, port); -+ irq_set_chained_handler_and_data(intx_irq, plda_handle_intx, port); - - msi_irq = irq_create_mapping(port->event_domain, - EVENT_LOCAL_PM_MSI_INT_MSI); -@@ -946,10 +951,10 @@ static int mc_init_interrupts(struct platform_device *pdev, struct plda_pcie_rp - return -ENXIO; - - /* Plug the MSI chained handler */ -- irq_set_chained_handler_and_data(msi_irq, mc_handle_msi, port); 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Thu, 28 Mar 2024 09:18:55 +0000 -From: Minda Chen -To: Lorenzo Pieralisi , - Conor Dooley , - =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , - Rob Herring , Bjorn Helgaas , - Thomas Gleixner , - Daire McNamara , - Emil Renner Berthing , - Krzysztof Kozlowski -Cc: devicetree@vger.kernel.org, - linux-kernel@vger.kernel.org, - linux-riscv@lists.infradead.org, - linux-pci@vger.kernel.org, - Paul Walmsley , - Palmer Dabbelt , - Albert Ou , - Philipp Zabel , - Mason Huo , - Leyfoon Tan , - Kevin Xie , - Minda Chen -Subject: [PATCH v16 11/22] PCI: microchip: Add num_events field to struct - plda_pcie_rp -Date: Thu, 28 Mar 2024 17:18:24 +0800 -Message-Id: <20240328091835.14797-12-minda.chen@starfivetech.com> -X-Mailer: git-send-email 2.17.1 -In-Reply-To: <20240328091835.14797-1-minda.chen@starfivetech.com> -References: <20240328091835.14797-1-minda.chen@starfivetech.com> -X-ClientProxiedBy: NT0PR01CA0020.CHNPR01.prod.partner.outlook.cn - (2406:e500:c510:c::16) To SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn - (2406:e500:c311:25::15) -Precedence: bulk -X-Mailing-List: linux-pci@vger.kernel.org -List-Id: -List-Subscribe: -List-Unsubscribe: -MIME-Version: 1.0 -X-MS-PublicTrafficType: Email -X-MS-TrafficTypeDiagnostic: SHXPR01MB0863:EE_|SHXPR01MB0559:EE_ -X-MS-Office365-Filtering-Correlation-Id: c27c3db2-0005-4c53-be14-08dc4f08174a -X-MS-Exchange-SenderADCheck: 1 -X-Microsoft-Antispam: BCL:0; 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In order to share -interrupt processing code, add a variable that defines the number of -events so that it can be set per-platform instead of hardcoding it. - -Signed-off-by: Minda Chen -Reviewed-by: Conor Dooley ---- - drivers/pci/controller/plda/pcie-microchip-host.c | 8 +++++--- - drivers/pci/controller/plda/pcie-plda.h | 1 + - 2 files changed, 6 insertions(+), 3 deletions(-) - -diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c -index 18bc352db389..0a5cd8b214cd 100644 ---- a/drivers/pci/controller/plda/pcie-microchip-host.c -+++ b/drivers/pci/controller/plda/pcie-microchip-host.c -@@ -653,7 +653,7 @@ static void plda_handle_event(struct irq_desc *desc) - - events = mc_get_events(port); - -- for_each_set_bit(bit, &events, NUM_EVENTS) -+ for_each_set_bit(bit, &events, port->num_events) - generic_handle_domain_irq(port->event_domain, bit); - - chained_irq_exit(chip, desc); -@@ -816,7 +816,8 @@ static int plda_pcie_init_irq_domains(struct plda_pcie_rp *port) - return -EINVAL; - } - -- port->event_domain = irq_domain_add_linear(pcie_intc_node, NUM_EVENTS, -+ port->event_domain = irq_domain_add_linear(pcie_intc_node, -+ port->num_events, - &plda_event_domain_ops, - port); - if (!port->event_domain) { -@@ -920,7 +921,7 @@ static int plda_init_interrupts(struct platform_device *pdev, struct plda_pcie_r - if (irq < 0) - return -ENODEV; - -- for (i = 0; i < NUM_EVENTS; i++) { -+ for (i = 0; i < port->num_events; i++) { - event_irq = irq_create_mapping(port->event_domain, i); - if (!event_irq) { - dev_err(dev, "failed to map hwirq %d\n", i); -@@ -1012,6 +1013,7 @@ static int mc_host_probe(struct platform_device *pdev) - - bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; - plda->bridge_addr = bridge_base_addr; -+ plda->num_events = NUM_EVENTS; - - /* Allow enabling MSI by disabling MSI-X */ - val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0); -diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h -index e277a5452b5d..f7e900b395f8 100644 ---- a/drivers/pci/controller/plda/pcie-plda.h -+++ b/drivers/pci/controller/plda/pcie-plda.h -@@ -124,6 +124,7 @@ struct plda_pcie_rp { - raw_spinlock_t lock; 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Microchip Polarfire PCIe add some PCIe interrupts base on -PLDA interrupt controller. - -Microchip Polarfire PCIe additional intrerrupts: -(defined in drivers/pci/controller/plda/pcie-microchip-host.c) -EVENT_PCIE_L2_EXIT -EVENT_PCIE_HOTRST_EXIT -EVENT_PCIE_DLUP_EXIT -EVENT_SEC_TX_RAM_SEC_ERR -EVENT_SEC_RX_RAM_SEC_ERR -.... - -Both code of request interrupts and mc_event_handler() contain -additional interrupts symbol names, these can not be re-used. So add a -new plda_event_handler() functions, which implements PLDA interrupt -defalt handler, add request_event_irq() callback function to compat -Microchip Polorfire PCIe additional interrupts. - -Signed-off-by: Minda Chen -Acked-by: Conor Dooley ---- - .../pci/controller/plda/pcie-microchip-host.c | 31 ++++++++++++++++--- - drivers/pci/controller/plda/pcie-plda.h | 5 +++ - 2 files changed, 32 insertions(+), 4 deletions(-) - -diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c -index 0a5cd8b214cd..bf5ce33ee275 100644 ---- a/drivers/pci/controller/plda/pcie-microchip-host.c -+++ b/drivers/pci/controller/plda/pcie-microchip-host.c -@@ -642,6 +642,11 @@ static irqreturn_t mc_event_handler(int irq, void *dev_id) - return IRQ_HANDLED; - } - -+static irqreturn_t plda_event_handler(int irq, void *dev_id) -+{ -+ return IRQ_HANDLED; -+} -+ - static void plda_handle_event(struct irq_desc *desc) - { - struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); -@@ -803,6 +808,17 @@ static int mc_pcie_init_clks(struct device *dev) - return 0; - } - -+static int mc_request_event_irq(struct plda_pcie_rp *plda, int event_irq, -+ int event) -+{ -+ return devm_request_irq(plda->dev, event_irq, mc_event_handler, -+ 0, event_cause[event].sym, plda); -+} -+ -+static const struct plda_event mc_event = { -+ .request_event_irq = mc_request_event_irq, -+}; -+ - static int plda_pcie_init_irq_domains(struct plda_pcie_rp *port) - { - struct device *dev = port->dev; -@@ -904,7 +920,9 @@ static void mc_disable_interrupts(struct mc_pcie *port) - writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST); - } - --static int plda_init_interrupts(struct platform_device *pdev, struct plda_pcie_rp *port) -+static int plda_init_interrupts(struct platform_device *pdev, -+ struct plda_pcie_rp *port, -+ const struct plda_event *event) - { - struct device *dev = &pdev->dev; - int irq; -@@ -928,8 +946,13 @@ static int plda_init_interrupts(struct platform_device *pdev, struct plda_pcie_r - return -ENXIO; - } - -- ret = devm_request_irq(dev, event_irq, mc_event_handler, -- 0, event_cause[i].sym, port); -+ if (event->request_event_irq) -+ ret = event->request_event_irq(port, event_irq, i); -+ else -+ ret = devm_request_irq(dev, event_irq, -+ plda_event_handler, -+ 0, NULL, port); -+ - if (ret) { - dev_err(dev, "failed to request IRQ %d\n", event_irq); - return ret; -@@ -983,7 +1006,7 @@ static int mc_platform_init(struct pci_config_window *cfg) - return ret; - - /* Address translation is up; safe to enable interrupts */ -- ret = plda_init_interrupts(pdev, &port->plda); -+ ret = plda_init_interrupts(pdev, &port->plda, &mc_event); - if (ret) - return ret; - -diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h -index f7e900b395f8..935686bba837 100644 ---- a/drivers/pci/controller/plda/pcie-plda.h -+++ b/drivers/pci/controller/plda/pcie-plda.h -@@ -127,6 +127,11 @@ struct plda_pcie_rp { - int num_events; - }; - -+struct plda_event { -+ int (*request_event_irq)(struct plda_pcie_rp *pcie, -+ int event_irq, int event); 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- - static int plda_pcie_init_irq_domains(struct plda_pcie_rp *port) -@@ -960,7 +962,7 @@ static int plda_init_interrupts(struct platform_device *pdev, - } - - intx_irq = irq_create_mapping(port->event_domain, -- EVENT_LOCAL_PM_MSI_INT_INTX); -+ event->intx_event); - if (!intx_irq) { - dev_err(dev, "failed to map INTx interrupt\n"); - return -ENXIO; -@@ -970,7 +972,7 @@ static int plda_init_interrupts(struct platform_device *pdev, - irq_set_chained_handler_and_data(intx_irq, plda_handle_intx, port); - - msi_irq = irq_create_mapping(port->event_domain, -- EVENT_LOCAL_PM_MSI_INT_MSI); -+ event->msi_event); - if (!msi_irq) - return -ENXIO; - -diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h -index 935686bba837..89172ce18237 100644 ---- a/drivers/pci/controller/plda/pcie-plda.h -+++ b/drivers/pci/controller/plda/pcie-plda.h -@@ -130,6 +130,8 @@ struct plda_pcie_rp { - struct plda_event { - int (*request_event_irq)(struct plda_pcie_rp *pcie, - int event_irq, int event); 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- } - -+static u32 plda_get_events(struct plda_pcie_rp *port) -+{ -+ u32 events, val, origin; -+ -+ origin = readl_relaxed(port->bridge_addr + ISTATUS_LOCAL); -+ -+ /* MSI event and sys events */ -+ val = (origin & SYS_AND_MSI_MASK) >> PM_MSI_INT_MSI_SHIFT; -+ events = val << (PM_MSI_INT_MSI_SHIFT - PCI_NUM_INTX + 1); -+ -+ /* INTx events */ -+ if (origin & PM_MSI_INT_INTX_MASK) -+ events |= BIT(PM_MSI_INT_INTX_SHIFT); -+ -+ /* remains are same with register */ -+ events |= origin & GENMASK(P_ATR_EVT_DOORBELL_SHIFT, 0); -+ -+ return events; -+} -+ - static irqreturn_t mc_event_handler(int irq, void *dev_id) - { - struct plda_pcie_rp *port = dev_id; -@@ -656,7 +676,7 @@ static void plda_handle_event(struct irq_desc *desc) - - chained_irq_enter(chip, desc); - -- events = mc_get_events(port); -+ events = port->event_ops->get_events(port); - - for_each_set_bit(bit, &events, port->num_events) - generic_handle_domain_irq(port->event_domain, bit); -@@ -750,6 +770,10 @@ static struct irq_chip mc_event_irq_chip = { - .irq_unmask = mc_unmask_event_irq, - }; - -+static const struct plda_event_ops plda_event_ops = { -+ .get_events = plda_get_events, -+}; -+ - static int plda_pcie_event_map(struct irq_domain *domain, unsigned int irq, - irq_hw_number_t hwirq) - { -@@ -815,6 +839,10 @@ static int mc_request_event_irq(struct plda_pcie_rp *plda, int event_irq, - 0, event_cause[event].sym, plda); - } - -+static const struct plda_event_ops mc_event_ops = { -+ .get_events = mc_get_events, -+}; -+ - static const struct plda_event mc_event = { - .request_event_irq = mc_request_event_irq, - .intx_event = EVENT_LOCAL_PM_MSI_INT_INTX, -@@ -931,6 +959,9 @@ static int plda_init_interrupts(struct platform_device *pdev, - int i, intx_irq, msi_irq, event_irq; - int ret; - -+ if (!port->event_ops) -+ port->event_ops = &plda_event_ops; -+ - ret = plda_pcie_init_irq_domains(port); - if (ret) { - dev_err(dev, "failed creating IRQ domains\n"); -@@ -1007,6 +1038,8 @@ static int mc_platform_init(struct pci_config_window *cfg) - if (ret) - return ret; - -+ port->plda.event_ops = &mc_event_ops; -+ - /* Address translation is up; safe to enable interrupts */ - ret = plda_init_interrupts(pdev, &port->plda, &mc_event); - if (ret) -diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h -index 89172ce18237..e0e5e7cc8434 100644 ---- a/drivers/pci/controller/plda/pcie-plda.h -+++ b/drivers/pci/controller/plda/pcie-plda.h -@@ -58,6 +58,7 @@ - #define PM_MSI_INT_EVENTS_SHIFT 30 - #define PM_MSI_INT_SYS_ERR_MASK 0x80000000u - #define PM_MSI_INT_SYS_ERR_SHIFT 31 -+#define SYS_AND_MSI_MASK GENMASK(31, 28) - #define NUM_LOCAL_EVENTS 15 - #define ISTATUS_LOCAL 0x184 - #define IMASK_HOST 0x188 -@@ -108,6 +109,36 @@ enum plda_int_event { - - #define PLDA_MAX_EVENT_NUM (PLDA_NUM_DMA_EVENTS + PLDA_INT_EVENT_NUM) - -+/* -+ * PLDA interrupt register -+ * -+ * 31 27 23 15 7 0 -+ * +--+--+--+-+------+-+-+-+-+-+-+-+-+-----------+-----------+ -+ * |12|11|10|9| intx |7|6|5|4|3|2|1|0| DMA error | DMA end | -+ * +--+--+--+-+------+-+-+-+-+-+-+-+-+-----------+-----------+ -+ * bit 0-7 DMA interrupt end : reserved for vendor implement -+ * bit 8-15 DMA error : reserved for vendor implement -+ * 0: AXI post error (PLDA_AXI_POST_ERR) -+ * 1: AXI fetch error (PLDA_AXI_FETCH_ERR) -+ * 2: AXI discard error (PLDA_AXI_DISCARD_ERR) -+ * 3: AXI doorbell (PLDA_PCIE_DOORBELL) -+ * 4: PCIe post error (PLDA_PCIE_POST_ERR) -+ * 5: PCIe fetch error (PLDA_PCIE_FETCH_ERR) -+ * 6: PCIe discard error (PLDA_PCIE_DISCARD_ERR) -+ * 7: PCIe doorbell (PLDA_PCIE_DOORBELL) -+ * 8: 4 INTx interruts (PLDA_INTX) -+ * 9: MSI interrupt (PLDA_MSI) -+ * 10: AER event (PLDA_AER_EVENT) -+ * 11: PM/LTR/Hotplug (PLDA_MISC_EVENTS) -+ * 12: System error (PLDA_SYS_ERR) -+ */ -+ -+struct plda_pcie_rp; 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The interrupt irqchip ops includes -ack/mask/unmask interrupt ops, which will write correct registers. -Microchip Polarfire PCIe additional interrupts require to write Polarfire -SoC self-defined registers. So Microchip PCIe event irqchip ops can not -be re-used. - -Microchip Polarfire PCIe additional intrerrupts: -(defined in drivers/pci/controller/plda/pcie-microchip-host.c) -EVENT_PCIE_L2_EXIT -EVENT_PCIE_HOTRST_EXIT -EVENT_PCIE_DLUP_EXIT -EVENT_SEC_TX_RAM_SEC_ERR -EVENT_SEC_RX_RAM_SEC_ERR -.... - -To support PLDA its own event IRQ process, implements PLDA irqchip ops and -add event irqchip field to struct pcie_plda_rp. - -Signed-off-by: Minda Chen -Acked-by: Conor Dooley ---- - .../pci/controller/plda/pcie-microchip-host.c | 66 ++++++++++++++++++- - drivers/pci/controller/plda/pcie-plda.h | 34 +++++----- - 2 files changed, 84 insertions(+), 16 deletions(-) - -diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c -index b3df373a2141..beaf5c27da84 100644 ---- a/drivers/pci/controller/plda/pcie-microchip-host.c -+++ b/drivers/pci/controller/plda/pcie-microchip-host.c -@@ -770,6 +770,64 @@ static struct irq_chip mc_event_irq_chip = { - .irq_unmask = mc_unmask_event_irq, - }; - -+static u32 plda_hwirq_to_mask(int hwirq) -+{ -+ u32 mask; -+ -+ /* hwirq 23 - 0 are the same with register */ -+ if (hwirq < EVENT_PM_MSI_INT_INTX) -+ mask = BIT(hwirq); -+ else if (hwirq == EVENT_PM_MSI_INT_INTX) -+ mask = PM_MSI_INT_INTX_MASK; -+ else -+ mask = BIT(hwirq + PCI_NUM_INTX - 1); -+ -+ return mask; -+} -+ -+static void plda_ack_event_irq(struct irq_data *data) -+{ -+ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); -+ -+ writel_relaxed(plda_hwirq_to_mask(data->hwirq), -+ port->bridge_addr + ISTATUS_LOCAL); -+} -+ -+static void plda_mask_event_irq(struct irq_data *data) -+{ -+ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); -+ u32 mask, val; -+ -+ mask = plda_hwirq_to_mask(data->hwirq); -+ -+ raw_spin_lock(&port->lock); -+ val = readl_relaxed(port->bridge_addr + IMASK_LOCAL); -+ val &= ~mask; -+ writel_relaxed(val, port->bridge_addr + IMASK_LOCAL); -+ raw_spin_unlock(&port->lock); -+} -+ -+static void plda_unmask_event_irq(struct irq_data *data) -+{ -+ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); -+ u32 mask, val; -+ -+ mask = plda_hwirq_to_mask(data->hwirq); -+ -+ raw_spin_lock(&port->lock); -+ val = readl_relaxed(port->bridge_addr + IMASK_LOCAL); -+ val |= mask; -+ writel_relaxed(val, port->bridge_addr + IMASK_LOCAL); -+ raw_spin_unlock(&port->lock); -+} -+ -+static struct irq_chip plda_event_irq_chip = { -+ .name = "PLDA PCIe EVENT", -+ .irq_ack = plda_ack_event_irq, -+ .irq_mask = plda_mask_event_irq, -+ .irq_unmask = plda_unmask_event_irq, -+}; -+ - static const struct plda_event_ops plda_event_ops = { - .get_events = plda_get_events, - }; -@@ -777,7 +835,9 @@ static const struct plda_event_ops plda_event_ops = { - static int plda_pcie_event_map(struct irq_domain *domain, unsigned int irq, - irq_hw_number_t hwirq) - { -- irq_set_chip_and_handler(irq, &mc_event_irq_chip, handle_level_irq); -+ struct plda_pcie_rp *port = (void *)domain->host_data; -+ -+ irq_set_chip_and_handler(irq, port->event_irq_chip, handle_level_irq); - irq_set_chip_data(irq, domain->host_data); - - return 0; -@@ -962,6 +1022,9 @@ static int plda_init_interrupts(struct platform_device *pdev, - if (!port->event_ops) - port->event_ops = &plda_event_ops; - -+ if (!port->event_irq_chip) -+ port->event_irq_chip = &plda_event_irq_chip; -+ - ret = plda_pcie_init_irq_domains(port); - if (ret) { - dev_err(dev, "failed creating IRQ domains\n"); -@@ -1039,6 +1102,7 @@ static int mc_platform_init(struct pci_config_window *cfg) - return ret; - - port->plda.event_ops = &mc_event_ops; -+ port->plda.event_irq_chip = &mc_event_irq_chip; - - /* Address translation is up; safe to enable interrupts */ - ret = plda_init_interrupts(pdev, &port->plda, &mc_event); -diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h -index e0e5e7cc8434..0e5157eb3a32 100644 ---- a/drivers/pci/controller/plda/pcie-plda.h -+++ b/drivers/pci/controller/plda/pcie-plda.h -@@ -107,6 +107,8 @@ enum plda_int_event { - - #define PLDA_NUM_DMA_EVENTS 16 - -+#define EVENT_PM_MSI_INT_INTX (PLDA_NUM_DMA_EVENTS + PLDA_INTX) -+#define EVENT_PM_MSI_INT_MSI (PLDA_NUM_DMA_EVENTS + PLDA_MSI) - #define PLDA_MAX_EVENT_NUM (PLDA_NUM_DMA_EVENTS + PLDA_INT_EVENT_NUM) - - /* -@@ -116,21 +118,22 @@ enum plda_int_event { - * +--+--+--+-+------+-+-+-+-+-+-+-+-+-----------+-----------+ - * |12|11|10|9| intx |7|6|5|4|3|2|1|0| DMA error | DMA end | - * +--+--+--+-+------+-+-+-+-+-+-+-+-+-----------+-----------+ -- * bit 0-7 DMA interrupt end : reserved for vendor implement -- * bit 8-15 DMA error : reserved for vendor implement -- * 0: AXI post error (PLDA_AXI_POST_ERR) -- * 1: AXI fetch error (PLDA_AXI_FETCH_ERR) -- * 2: AXI discard error (PLDA_AXI_DISCARD_ERR) -- * 3: AXI doorbell (PLDA_PCIE_DOORBELL) -- * 4: PCIe post error (PLDA_PCIE_POST_ERR) -- * 5: PCIe fetch error (PLDA_PCIE_FETCH_ERR) -- * 6: PCIe discard error (PLDA_PCIE_DISCARD_ERR) -- * 7: PCIe doorbell (PLDA_PCIE_DOORBELL) -- * 8: 4 INTx interruts (PLDA_INTX) -- * 9: MSI interrupt (PLDA_MSI) -- * 10: AER event (PLDA_AER_EVENT) -- * 11: PM/LTR/Hotplug (PLDA_MISC_EVENTS) -- * 12: System error (PLDA_SYS_ERR) -+ * event bit -+ * 0-7 (0-7) DMA interrupt end : reserved for vendor implement -+ * 8-15 (8-15) DMA error : reserved for vendor implement -+ * 16 (16) AXI post error (PLDA_AXI_POST_ERR) -+ * 17 (17) AXI fetch error (PLDA_AXI_FETCH_ERR) -+ * 18 (18) AXI discard error (PLDA_AXI_DISCARD_ERR) -+ * 19 (19) AXI doorbell (PLDA_PCIE_DOORBELL) -+ * 20 (20) PCIe post error (PLDA_PCIE_POST_ERR) -+ * 21 (21) PCIe fetch error (PLDA_PCIE_FETCH_ERR) -+ * 22 (22) PCIe discard error (PLDA_PCIE_DISCARD_ERR) -+ * 23 (23) PCIe doorbell (PLDA_PCIE_DOORBELL) -+ * 24 (27-24) INTx interruts (PLDA_INTX) -+ * 25 (28): MSI interrupt (PLDA_MSI) -+ * 26 (29): AER event (PLDA_AER_EVENT) -+ * 27 (30): PM/LTR/Hotplug (PLDA_MISC_EVENTS) -+ * 28 (31): System error (PLDA_SYS_ERR) - */ - - struct plda_pcie_rp; -@@ -155,6 +158,7 @@ struct plda_pcie_rp { - raw_spinlock_t lock; - struct plda_msi msi; - const struct plda_event_ops *event_ops; -+ const struct irq_chip *event_irq_chip; - void __iomem *bridge_addr; - int num_events; - }; - -From patchwork Thu Mar 28 09:18:29 2024 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Minda Chen -X-Patchwork-Id: 13608246 -X-Patchwork-Delegate: kw@linux.com -Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn - (mail-sh0chn02on2136.outbound.protection.partner.outlook.cn - [139.219.146.136]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by smtp.subspace.kernel.org (Postfix) with ESMTPS id 858A27E574; - Thu, 28 Mar 2024 09:19:10 +0000 (UTC) -Authentication-Results: smtp.subspace.kernel.org; - arc=fail smtp.client-ip=139.219.146.136 -ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; - t=1711617553; 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- } - --static void plda_handle_msi(struct irq_desc *desc) --{ -- struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); -- struct irq_chip *chip = irq_desc_get_chip(desc); -- struct device *dev = port->dev; -- struct plda_msi *msi = &port->msi; -- void __iomem *bridge_base_addr = port->bridge_addr; -- unsigned long status; -- u32 bit; -- int ret; -- -- chained_irq_enter(chip, desc); -- -- status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); -- if (status & PM_MSI_INT_MSI_MASK) { -- writel_relaxed(status & PM_MSI_INT_MSI_MASK, bridge_base_addr + ISTATUS_LOCAL); -- status = readl_relaxed(bridge_base_addr + ISTATUS_MSI); -- for_each_set_bit(bit, &status, msi->num_vectors) { -- ret = generic_handle_domain_irq(msi->dev_domain, bit); -- if (ret) -- dev_err_ratelimited(dev, "bad MSI IRQ %d\n", -- bit); -- } -- } -- -- chained_irq_exit(chip, desc); --} -- --static void plda_msi_bottom_irq_ack(struct irq_data *data) --{ -- struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); -- void __iomem *bridge_base_addr = port->bridge_addr; -- u32 bitpos = data->hwirq; -- -- writel_relaxed(BIT(bitpos), bridge_base_addr + ISTATUS_MSI); --} -- --static void plda_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) --{ -- struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); -- phys_addr_t addr = port->msi.vector_phy; -- -- msg->address_lo = lower_32_bits(addr); -- msg->address_hi = upper_32_bits(addr); -- msg->data = data->hwirq; -- -- dev_dbg(port->dev, "msi#%x address_hi %#x address_lo %#x\n", -- (int)data->hwirq, msg->address_hi, msg->address_lo); --} -- --static int plda_msi_set_affinity(struct irq_data *irq_data, -- const struct cpumask *mask, bool force) --{ -- return -EINVAL; --} -- --static struct irq_chip plda_msi_bottom_irq_chip = { -- .name = "PLDA MSI", -- .irq_ack = plda_msi_bottom_irq_ack, -- .irq_compose_msi_msg = plda_compose_msi_msg, -- .irq_set_affinity = plda_msi_set_affinity, --}; -- --static int plda_irq_msi_domain_alloc(struct irq_domain *domain, -- unsigned int virq, -- unsigned int nr_irqs, -- void *args) --{ -- struct plda_pcie_rp *port = domain->host_data; -- struct plda_msi *msi = &port->msi; -- unsigned long bit; -- -- mutex_lock(&msi->lock); -- bit = find_first_zero_bit(msi->used, msi->num_vectors); -- if (bit >= msi->num_vectors) { -- mutex_unlock(&msi->lock); -- return -ENOSPC; -- } -- -- set_bit(bit, msi->used); -- -- irq_domain_set_info(domain, virq, bit, &plda_msi_bottom_irq_chip, -- domain->host_data, handle_edge_irq, NULL, NULL); -- -- mutex_unlock(&msi->lock); -- -- return 0; --} -- --static void plda_irq_msi_domain_free(struct irq_domain *domain, -- unsigned int virq, -- unsigned int nr_irqs) --{ -- struct irq_data *d = irq_domain_get_irq_data(domain, virq); -- struct plda_pcie_rp *port = irq_data_get_irq_chip_data(d); -- struct plda_msi *msi = &port->msi; -- -- mutex_lock(&msi->lock); -- -- if (test_bit(d->hwirq, msi->used)) -- __clear_bit(d->hwirq, msi->used); -- else -- dev_err(port->dev, "trying to free unused MSI%lu\n", d->hwirq); -- -- mutex_unlock(&msi->lock); --} -- --static const struct irq_domain_ops msi_domain_ops = { -- .alloc = plda_irq_msi_domain_alloc, -- .free = plda_irq_msi_domain_free, --}; -- --static struct irq_chip plda_msi_irq_chip = { -- .name = "PLDA PCIe MSI", -- .irq_ack = irq_chip_ack_parent, -- .irq_mask = pci_msi_mask_irq, -- .irq_unmask = pci_msi_unmask_irq, --}; -- --static struct msi_domain_info plda_msi_domain_info = { -- .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | -- MSI_FLAG_PCI_MSIX), -- .chip = &plda_msi_irq_chip, --}; -- --static int plda_allocate_msi_domains(struct plda_pcie_rp *port) --{ -- struct device *dev = port->dev; -- struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); -- struct plda_msi *msi = &port->msi; -- -- mutex_init(&port->msi.lock); -- -- msi->dev_domain = irq_domain_add_linear(NULL, msi->num_vectors, -- &msi_domain_ops, port); -- if (!msi->dev_domain) { -- dev_err(dev, "failed to create IRQ domain\n"); -- return -ENOMEM; -- } -- -- msi->msi_domain = pci_msi_create_irq_domain(fwnode, -- &plda_msi_domain_info, -- msi->dev_domain); -- if (!msi->msi_domain) { -- dev_err(dev, "failed to create MSI domain\n"); -- irq_domain_remove(msi->dev_domain); -- return -ENOMEM; -- } -- -- return 0; --} -- --static void plda_handle_intx(struct irq_desc *desc) --{ -- struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); -- struct irq_chip *chip = irq_desc_get_chip(desc); -- struct device *dev = port->dev; -- void __iomem *bridge_base_addr = port->bridge_addr; -- unsigned long status; -- u32 bit; -- int ret; -- -- chained_irq_enter(chip, desc); -- -- status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); -- if (status & PM_MSI_INT_INTX_MASK) { -- status &= PM_MSI_INT_INTX_MASK; -- status >>= PM_MSI_INT_INTX_SHIFT; -- for_each_set_bit(bit, &status, PCI_NUM_INTX) { -- ret = generic_handle_domain_irq(port->intx_domain, bit); -- if (ret) -- dev_err_ratelimited(dev, "bad INTx IRQ %d\n", -- bit); -- } -- } -- -- chained_irq_exit(chip, desc); --} -- --static void plda_ack_intx_irq(struct irq_data *data) --{ -- struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); -- void __iomem *bridge_base_addr = port->bridge_addr; -- u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); -- -- writel_relaxed(mask, bridge_base_addr + ISTATUS_LOCAL); --} -- --static void plda_mask_intx_irq(struct irq_data *data) --{ -- struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); -- void __iomem *bridge_base_addr = port->bridge_addr; -- unsigned long flags; -- u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); -- u32 val; -- -- raw_spin_lock_irqsave(&port->lock, flags); -- val = readl_relaxed(bridge_base_addr + IMASK_LOCAL); -- val &= ~mask; -- writel_relaxed(val, bridge_base_addr + IMASK_LOCAL); -- raw_spin_unlock_irqrestore(&port->lock, flags); --} -- --static void plda_unmask_intx_irq(struct irq_data *data) --{ -- struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); -- void __iomem *bridge_base_addr = port->bridge_addr; -- unsigned long flags; -- u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); -- u32 val; -- -- raw_spin_lock_irqsave(&port->lock, flags); -- val = readl_relaxed(bridge_base_addr + IMASK_LOCAL); -- val |= mask; -- writel_relaxed(val, bridge_base_addr + IMASK_LOCAL); -- raw_spin_unlock_irqrestore(&port->lock, flags); --} -- --static struct irq_chip plda_intx_irq_chip = { -- .name = "PLDA PCIe INTx", -- .irq_ack = plda_ack_intx_irq, -- .irq_mask = plda_mask_intx_irq, -- .irq_unmask = plda_unmask_intx_irq, --}; -- --static int plda_pcie_intx_map(struct irq_domain *domain, unsigned int irq, -- irq_hw_number_t hwirq) --{ -- irq_set_chip_and_handler(irq, &plda_intx_irq_chip, handle_level_irq); -- irq_set_chip_data(irq, domain->host_data); -- -- return 0; --} -- --static const struct irq_domain_ops intx_domain_ops = { -- .map = plda_pcie_intx_map, --}; -- - static inline u32 reg_to_event(u32 reg, struct event_map field) - { - return (reg & field.reg_mask) ? BIT(field.event_bit) : 0; -@@ -626,26 +388,6 @@ static u32 mc_get_events(struct plda_pcie_rp *port) - return events; - } - --static u32 plda_get_events(struct plda_pcie_rp *port) --{ -- u32 events, val, origin; -- -- origin = readl_relaxed(port->bridge_addr + ISTATUS_LOCAL); -- -- /* MSI event and sys events */ -- val = (origin & SYS_AND_MSI_MASK) >> PM_MSI_INT_MSI_SHIFT; -- events = val << (PM_MSI_INT_MSI_SHIFT - PCI_NUM_INTX + 1); -- -- /* INTx events */ -- if (origin & PM_MSI_INT_INTX_MASK) -- events |= BIT(PM_MSI_INT_INTX_SHIFT); -- -- /* remains are same with register */ -- events |= origin & GENMASK(P_ATR_EVT_DOORBELL_SHIFT, 0); -- -- return events; --} -- - static irqreturn_t mc_event_handler(int irq, void *dev_id) - { - struct plda_pcie_rp *port = dev_id; -@@ -662,28 +404,6 @@ static irqreturn_t mc_event_handler(int irq, void *dev_id) - return IRQ_HANDLED; - } - --static irqreturn_t plda_event_handler(int irq, void *dev_id) --{ -- return IRQ_HANDLED; --} -- --static void plda_handle_event(struct irq_desc *desc) --{ -- struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); -- unsigned long events; -- u32 bit; -- struct irq_chip *chip = irq_desc_get_chip(desc); -- -- chained_irq_enter(chip, desc); -- -- events = port->event_ops->get_events(port); -- -- for_each_set_bit(bit, &events, port->num_events) -- generic_handle_domain_irq(port->event_domain, bit); -- -- chained_irq_exit(chip, desc); --} -- - static void mc_ack_event_irq(struct irq_data *data) - { - struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); -@@ -770,83 +490,6 @@ static struct irq_chip mc_event_irq_chip = { - .irq_unmask = mc_unmask_event_irq, - }; - --static u32 plda_hwirq_to_mask(int hwirq) --{ -- u32 mask; -- -- /* hwirq 23 - 0 are the same with register */ -- if (hwirq < EVENT_PM_MSI_INT_INTX) -- mask = BIT(hwirq); -- else if (hwirq == EVENT_PM_MSI_INT_INTX) -- mask = PM_MSI_INT_INTX_MASK; -- else -- mask = BIT(hwirq + PCI_NUM_INTX - 1); -- -- return mask; --} -- --static void plda_ack_event_irq(struct irq_data *data) --{ -- struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); -- -- writel_relaxed(plda_hwirq_to_mask(data->hwirq), -- port->bridge_addr + ISTATUS_LOCAL); --} -- --static void plda_mask_event_irq(struct irq_data *data) --{ -- struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); -- u32 mask, val; -- -- mask = plda_hwirq_to_mask(data->hwirq); -- -- raw_spin_lock(&port->lock); -- val = readl_relaxed(port->bridge_addr + IMASK_LOCAL); -- val &= ~mask; -- writel_relaxed(val, port->bridge_addr + IMASK_LOCAL); -- raw_spin_unlock(&port->lock); --} -- --static void plda_unmask_event_irq(struct irq_data *data) --{ -- struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); -- u32 mask, val; -- -- mask = plda_hwirq_to_mask(data->hwirq); -- -- raw_spin_lock(&port->lock); -- val = readl_relaxed(port->bridge_addr + IMASK_LOCAL); -- val |= mask; -- writel_relaxed(val, port->bridge_addr + IMASK_LOCAL); -- raw_spin_unlock(&port->lock); --} -- --static struct irq_chip plda_event_irq_chip = { -- .name = "PLDA PCIe EVENT", -- .irq_ack = plda_ack_event_irq, -- .irq_mask = plda_mask_event_irq, -- .irq_unmask = plda_unmask_event_irq, --}; -- --static const struct plda_event_ops plda_event_ops = { -- .get_events = plda_get_events, --}; -- --static int plda_pcie_event_map(struct irq_domain *domain, unsigned int irq, -- irq_hw_number_t hwirq) --{ -- struct plda_pcie_rp *port = (void *)domain->host_data; -- -- irq_set_chip_and_handler(irq, port->event_irq_chip, handle_level_irq); -- irq_set_chip_data(irq, domain->host_data); -- -- return 0; --} -- --static const struct irq_domain_ops plda_event_domain_ops = { -- .map = plda_pcie_event_map, --}; -- - static inline void mc_pcie_deinit_clk(void *data) - { - struct clk *clk = data; -@@ -909,47 +552,6 @@ static const struct plda_event mc_event = { - .msi_event = EVENT_LOCAL_PM_MSI_INT_MSI, - }; - --static int plda_pcie_init_irq_domains(struct plda_pcie_rp *port) --{ -- struct device *dev = port->dev; -- struct device_node *node = dev->of_node; -- struct device_node *pcie_intc_node; -- -- /* Setup INTx */ -- pcie_intc_node = of_get_next_child(node, NULL); -- if (!pcie_intc_node) { -- dev_err(dev, "failed to find PCIe Intc node\n"); -- return -EINVAL; -- } -- -- port->event_domain = irq_domain_add_linear(pcie_intc_node, -- port->num_events, -- &plda_event_domain_ops, -- port); -- if (!port->event_domain) { -- dev_err(dev, "failed to get event domain\n"); -- of_node_put(pcie_intc_node); -- return -ENOMEM; -- } -- -- irq_domain_update_bus_token(port->event_domain, DOMAIN_BUS_NEXUS); -- -- port->intx_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, -- &intx_domain_ops, port); -- if (!port->intx_domain) { -- dev_err(dev, "failed to get an INTx IRQ domain\n"); -- of_node_put(pcie_intc_node); -- return -ENOMEM; -- } -- -- irq_domain_update_bus_token(port->intx_domain, DOMAIN_BUS_WIRED); -- -- of_node_put(pcie_intc_node); -- raw_spin_lock_init(&port->lock); -- -- return plda_allocate_msi_domains(port); --} -- - static inline void mc_clear_secs(struct mc_pcie *port) - { - void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; -@@ -1010,75 +612,6 @@ static void mc_disable_interrupts(struct mc_pcie *port) - writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST); - } - --static int plda_init_interrupts(struct platform_device *pdev, -- struct plda_pcie_rp *port, -- const struct plda_event *event) --{ -- struct device *dev = &pdev->dev; -- int irq; -- int i, intx_irq, msi_irq, event_irq; -- int ret; -- -- if (!port->event_ops) -- port->event_ops = &plda_event_ops; -- -- if (!port->event_irq_chip) -- port->event_irq_chip = &plda_event_irq_chip; -- -- ret = plda_pcie_init_irq_domains(port); -- if (ret) { -- dev_err(dev, "failed creating IRQ domains\n"); -- return ret; -- } -- -- irq = platform_get_irq(pdev, 0); -- if (irq < 0) -- return -ENODEV; -- -- for (i = 0; i < port->num_events; i++) { -- event_irq = irq_create_mapping(port->event_domain, i); -- if (!event_irq) { -- dev_err(dev, "failed to map hwirq %d\n", i); -- return -ENXIO; -- } -- -- if (event->request_event_irq) -- ret = event->request_event_irq(port, event_irq, i); -- else -- ret = devm_request_irq(dev, event_irq, -- plda_event_handler, -- 0, NULL, port); -- -- if (ret) { -- dev_err(dev, "failed to request IRQ %d\n", event_irq); -- return ret; -- } -- } -- -- intx_irq = irq_create_mapping(port->event_domain, -- event->intx_event); -- if (!intx_irq) { -- dev_err(dev, "failed to map INTx interrupt\n"); -- return -ENXIO; -- } -- -- /* Plug the INTx chained handler */ -- irq_set_chained_handler_and_data(intx_irq, plda_handle_intx, port); -- -- msi_irq = irq_create_mapping(port->event_domain, -- event->msi_event); -- if (!msi_irq) -- return -ENXIO; -- -- /* Plug the MSI chained handler */ -- irq_set_chained_handler_and_data(msi_irq, plda_handle_msi, port); -- -- /* Plug the main event chained handler */ -- irq_set_chained_handler_and_data(irq, plda_handle_event, port); -- -- return 0; --} -- - static int mc_platform_init(struct pci_config_window *cfg) - { - struct device *dev = cfg->parent; -diff --git a/drivers/pci/controller/plda/pcie-plda-host.c b/drivers/pci/controller/plda/pcie-plda-host.c -index 05ea68baebfb..98c51e594efe 100644 ---- a/drivers/pci/controller/plda/pcie-plda-host.c -+++ b/drivers/pci/controller/plda/pcie-plda-host.c -@@ -7,10 +7,483 @@ - * Author: Daire McNamara - */ - -+#include -+#include -+#include -+#include - #include - - #include "pcie-plda.h" - -+static void plda_handle_msi(struct irq_desc *desc) -+{ -+ struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); -+ struct irq_chip *chip = irq_desc_get_chip(desc); -+ struct device *dev = port->dev; -+ struct plda_msi *msi = &port->msi; -+ void __iomem *bridge_base_addr = port->bridge_addr; -+ unsigned long status; -+ u32 bit; -+ int ret; -+ -+ chained_irq_enter(chip, desc); -+ -+ status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); -+ if (status & PM_MSI_INT_MSI_MASK) { -+ writel_relaxed(status & PM_MSI_INT_MSI_MASK, -+ bridge_base_addr + ISTATUS_LOCAL); -+ status = readl_relaxed(bridge_base_addr + ISTATUS_MSI); -+ for_each_set_bit(bit, &status, msi->num_vectors) { -+ ret = generic_handle_domain_irq(msi->dev_domain, bit); -+ if (ret) -+ dev_err_ratelimited(dev, "bad MSI IRQ %d\n", -+ bit); -+ } -+ } -+ -+ chained_irq_exit(chip, desc); -+} -+ -+static void plda_msi_bottom_irq_ack(struct irq_data *data) -+{ -+ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); -+ void __iomem *bridge_base_addr = port->bridge_addr; -+ u32 bitpos = data->hwirq; -+ -+ writel_relaxed(BIT(bitpos), bridge_base_addr + ISTATUS_MSI); -+} -+ -+static void plda_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) -+{ -+ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); -+ phys_addr_t addr = port->msi.vector_phy; -+ -+ msg->address_lo = lower_32_bits(addr); -+ msg->address_hi = upper_32_bits(addr); -+ msg->data = data->hwirq; -+ -+ dev_dbg(port->dev, "msi#%x address_hi %#x address_lo %#x\n", -+ (int)data->hwirq, msg->address_hi, msg->address_lo); -+} -+ -+static int plda_msi_set_affinity(struct irq_data *irq_data, -+ const struct cpumask *mask, bool force) -+{ -+ return -EINVAL; -+} -+ -+static struct irq_chip plda_msi_bottom_irq_chip = { -+ .name = "PLDA MSI", -+ .irq_ack = plda_msi_bottom_irq_ack, -+ .irq_compose_msi_msg = plda_compose_msi_msg, -+ .irq_set_affinity = plda_msi_set_affinity, -+}; -+ -+static int plda_irq_msi_domain_alloc(struct irq_domain *domain, -+ unsigned int virq, -+ unsigned int nr_irqs, -+ void *args) -+{ -+ struct plda_pcie_rp *port = domain->host_data; -+ struct plda_msi *msi = &port->msi; -+ unsigned long bit; -+ -+ mutex_lock(&msi->lock); -+ bit = find_first_zero_bit(msi->used, msi->num_vectors); -+ if (bit >= msi->num_vectors) { -+ mutex_unlock(&msi->lock); -+ return -ENOSPC; -+ } -+ -+ set_bit(bit, msi->used); -+ -+ irq_domain_set_info(domain, virq, bit, &plda_msi_bottom_irq_chip, -+ domain->host_data, handle_edge_irq, NULL, NULL); -+ -+ mutex_unlock(&msi->lock); -+ -+ return 0; -+} -+ -+static void plda_irq_msi_domain_free(struct irq_domain *domain, -+ unsigned int virq, -+ unsigned int nr_irqs) -+{ -+ struct irq_data *d = irq_domain_get_irq_data(domain, virq); -+ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(d); -+ struct plda_msi *msi = &port->msi; -+ -+ mutex_lock(&msi->lock); -+ -+ if (test_bit(d->hwirq, msi->used)) -+ __clear_bit(d->hwirq, msi->used); -+ else -+ dev_err(port->dev, "trying to free unused MSI%lu\n", d->hwirq); -+ -+ mutex_unlock(&msi->lock); -+} -+ -+static const struct irq_domain_ops msi_domain_ops = { -+ .alloc = plda_irq_msi_domain_alloc, -+ .free = plda_irq_msi_domain_free, -+}; -+ -+static struct irq_chip plda_msi_irq_chip = { -+ .name = "PLDA PCIe MSI", -+ .irq_ack = irq_chip_ack_parent, -+ .irq_mask = pci_msi_mask_irq, -+ .irq_unmask = pci_msi_unmask_irq, -+}; -+ -+static struct msi_domain_info plda_msi_domain_info = { -+ .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | -+ MSI_FLAG_PCI_MSIX), -+ .chip = &plda_msi_irq_chip, -+}; -+ -+static int plda_allocate_msi_domains(struct plda_pcie_rp *port) -+{ -+ struct device *dev = port->dev; -+ struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); -+ struct plda_msi *msi = &port->msi; -+ -+ mutex_init(&port->msi.lock); -+ -+ msi->dev_domain = irq_domain_add_linear(NULL, msi->num_vectors, -+ &msi_domain_ops, port); -+ if (!msi->dev_domain) { -+ dev_err(dev, "failed to create IRQ domain\n"); -+ return -ENOMEM; -+ } -+ -+ msi->msi_domain = pci_msi_create_irq_domain(fwnode, -+ &plda_msi_domain_info, -+ msi->dev_domain); -+ if (!msi->msi_domain) { -+ dev_err(dev, "failed to create MSI domain\n"); -+ irq_domain_remove(msi->dev_domain); -+ return -ENOMEM; -+ } -+ -+ return 0; -+} -+ -+static void plda_handle_intx(struct irq_desc *desc) -+{ -+ struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); -+ struct irq_chip *chip = irq_desc_get_chip(desc); -+ struct device *dev = port->dev; -+ void __iomem *bridge_base_addr = port->bridge_addr; -+ unsigned long status; -+ u32 bit; -+ int ret; -+ -+ chained_irq_enter(chip, desc); -+ -+ status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); -+ if (status & PM_MSI_INT_INTX_MASK) { -+ status &= PM_MSI_INT_INTX_MASK; -+ status >>= PM_MSI_INT_INTX_SHIFT; -+ for_each_set_bit(bit, &status, PCI_NUM_INTX) { -+ ret = generic_handle_domain_irq(port->intx_domain, bit); -+ if (ret) -+ dev_err_ratelimited(dev, "bad INTx IRQ %d\n", -+ bit); -+ } -+ } -+ -+ chained_irq_exit(chip, desc); -+} -+ -+static void plda_ack_intx_irq(struct irq_data *data) -+{ -+ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); -+ void __iomem *bridge_base_addr = port->bridge_addr; -+ u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); -+ -+ writel_relaxed(mask, bridge_base_addr + ISTATUS_LOCAL); -+} -+ -+static void plda_mask_intx_irq(struct irq_data *data) -+{ -+ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); -+ void __iomem *bridge_base_addr = port->bridge_addr; -+ unsigned long flags; -+ u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); -+ u32 val; -+ -+ raw_spin_lock_irqsave(&port->lock, flags); -+ val = readl_relaxed(bridge_base_addr + IMASK_LOCAL); -+ val &= ~mask; -+ writel_relaxed(val, bridge_base_addr + IMASK_LOCAL); -+ raw_spin_unlock_irqrestore(&port->lock, flags); -+} -+ -+static void plda_unmask_intx_irq(struct irq_data *data) -+{ -+ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); -+ void __iomem *bridge_base_addr = port->bridge_addr; -+ unsigned long flags; -+ u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); -+ u32 val; -+ -+ raw_spin_lock_irqsave(&port->lock, flags); -+ val = readl_relaxed(bridge_base_addr + IMASK_LOCAL); -+ val |= mask; -+ writel_relaxed(val, bridge_base_addr + IMASK_LOCAL); -+ raw_spin_unlock_irqrestore(&port->lock, flags); -+} -+ -+static struct irq_chip plda_intx_irq_chip = { -+ .name = "PLDA PCIe INTx", -+ .irq_ack = plda_ack_intx_irq, -+ .irq_mask = plda_mask_intx_irq, -+ .irq_unmask = plda_unmask_intx_irq, -+}; -+ -+static int plda_pcie_intx_map(struct irq_domain *domain, unsigned int irq, -+ irq_hw_number_t hwirq) -+{ -+ irq_set_chip_and_handler(irq, &plda_intx_irq_chip, handle_level_irq); -+ irq_set_chip_data(irq, domain->host_data); -+ -+ return 0; -+} -+ -+static const struct irq_domain_ops intx_domain_ops = { -+ .map = plda_pcie_intx_map, -+}; -+ -+static u32 plda_get_events(struct plda_pcie_rp *port) -+{ -+ u32 events, val, origin; -+ -+ origin = readl_relaxed(port->bridge_addr + ISTATUS_LOCAL); -+ -+ /* MSI event and sys events */ -+ val = (origin & SYS_AND_MSI_MASK) >> PM_MSI_INT_MSI_SHIFT; -+ events = val << (PM_MSI_INT_MSI_SHIFT - PCI_NUM_INTX + 1); -+ -+ /* INTx events */ -+ if (origin & PM_MSI_INT_INTX_MASK) -+ events |= BIT(PM_MSI_INT_INTX_SHIFT); -+ -+ /* remains are same with register */ -+ events |= origin & GENMASK(P_ATR_EVT_DOORBELL_SHIFT, 0); -+ -+ return events; -+} -+ -+static irqreturn_t plda_event_handler(int irq, void *dev_id) -+{ -+ return IRQ_HANDLED; -+} -+ -+static void plda_handle_event(struct irq_desc *desc) -+{ -+ struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); -+ unsigned long events; -+ u32 bit; -+ struct irq_chip *chip = irq_desc_get_chip(desc); -+ -+ chained_irq_enter(chip, desc); -+ -+ events = port->event_ops->get_events(port); -+ -+ for_each_set_bit(bit, &events, port->num_events) -+ generic_handle_domain_irq(port->event_domain, bit); -+ -+ chained_irq_exit(chip, desc); -+} -+ -+static u32 plda_hwirq_to_mask(int hwirq) -+{ -+ u32 mask; -+ -+ /* hwirq 23 - 0 are the same with register */ -+ if (hwirq < EVENT_PM_MSI_INT_INTX) -+ mask = BIT(hwirq); -+ else if (hwirq == EVENT_PM_MSI_INT_INTX) -+ mask = PM_MSI_INT_INTX_MASK; -+ else -+ mask = BIT(hwirq + PCI_NUM_INTX - 1); -+ -+ return mask; -+} -+ -+static void plda_ack_event_irq(struct irq_data *data) -+{ -+ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); -+ -+ writel_relaxed(plda_hwirq_to_mask(data->hwirq), -+ port->bridge_addr + ISTATUS_LOCAL); -+} -+ -+static void plda_mask_event_irq(struct irq_data *data) -+{ -+ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); -+ u32 mask, val; -+ -+ mask = plda_hwirq_to_mask(data->hwirq); -+ -+ raw_spin_lock(&port->lock); -+ val = readl_relaxed(port->bridge_addr + IMASK_LOCAL); -+ val &= ~mask; -+ writel_relaxed(val, port->bridge_addr + IMASK_LOCAL); -+ raw_spin_unlock(&port->lock); -+} -+ -+static void plda_unmask_event_irq(struct irq_data *data) -+{ -+ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); -+ u32 mask, val; -+ -+ mask = plda_hwirq_to_mask(data->hwirq); -+ -+ raw_spin_lock(&port->lock); -+ val = readl_relaxed(port->bridge_addr + IMASK_LOCAL); -+ val |= mask; -+ writel_relaxed(val, port->bridge_addr + IMASK_LOCAL); -+ raw_spin_unlock(&port->lock); -+} -+ -+static struct irq_chip plda_event_irq_chip = { -+ .name = "PLDA PCIe EVENT", -+ .irq_ack = plda_ack_event_irq, -+ .irq_mask = plda_mask_event_irq, -+ .irq_unmask = plda_unmask_event_irq, -+}; -+ -+static const struct plda_event_ops plda_event_ops = { -+ .get_events = plda_get_events, -+}; -+ -+static int plda_pcie_event_map(struct irq_domain *domain, unsigned int irq, -+ irq_hw_number_t hwirq) -+{ -+ struct plda_pcie_rp *port = (void *)domain->host_data; -+ -+ irq_set_chip_and_handler(irq, port->event_irq_chip, handle_level_irq); -+ irq_set_chip_data(irq, domain->host_data); -+ -+ return 0; -+} -+ -+static const struct irq_domain_ops plda_event_domain_ops = { -+ .map = plda_pcie_event_map, -+}; -+ -+static int plda_pcie_init_irq_domains(struct plda_pcie_rp *port) -+{ -+ struct device *dev = port->dev; -+ struct device_node *node = dev->of_node; -+ struct device_node *pcie_intc_node; -+ -+ /* Setup INTx */ -+ pcie_intc_node = of_get_next_child(node, NULL); -+ if (!pcie_intc_node) { -+ dev_err(dev, "failed to find PCIe Intc node\n"); -+ return -EINVAL; -+ } -+ -+ port->event_domain = irq_domain_add_linear(pcie_intc_node, -+ port->num_events, -+ &plda_event_domain_ops, -+ port); -+ if (!port->event_domain) { -+ dev_err(dev, "failed to get event domain\n"); -+ of_node_put(pcie_intc_node); -+ return -ENOMEM; -+ } -+ -+ irq_domain_update_bus_token(port->event_domain, DOMAIN_BUS_NEXUS); -+ -+ port->intx_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, -+ &intx_domain_ops, port); -+ if (!port->intx_domain) { -+ dev_err(dev, "failed to get an INTx IRQ domain\n"); -+ of_node_put(pcie_intc_node); -+ return -ENOMEM; -+ } -+ -+ irq_domain_update_bus_token(port->intx_domain, DOMAIN_BUS_WIRED); -+ -+ of_node_put(pcie_intc_node); -+ raw_spin_lock_init(&port->lock); -+ -+ return plda_allocate_msi_domains(port); -+} -+ -+int plda_init_interrupts(struct platform_device *pdev, -+ struct plda_pcie_rp *port, -+ const struct plda_event *event) -+{ -+ struct device *dev = &pdev->dev; -+ int irq; -+ int i, intx_irq, msi_irq, event_irq; -+ int ret; -+ -+ if (!port->event_ops) -+ port->event_ops = &plda_event_ops; -+ -+ if (!port->event_irq_chip) -+ port->event_irq_chip = &plda_event_irq_chip; -+ -+ ret = plda_pcie_init_irq_domains(port); -+ if (ret) { -+ dev_err(dev, "failed creating IRQ domains\n"); -+ return ret; -+ } -+ -+ irq = platform_get_irq(pdev, 0); -+ if (irq < 0) -+ return -ENODEV; -+ -+ for (i = 0; i < port->num_events; i++) { -+ event_irq = irq_create_mapping(port->event_domain, i); -+ if (!event_irq) { -+ dev_err(dev, "failed to map hwirq %d\n", i); -+ return -ENXIO; -+ } -+ -+ if (event->request_event_irq) -+ ret = event->request_event_irq(port, event_irq, i); -+ else -+ ret = devm_request_irq(dev, event_irq, -+ plda_event_handler, -+ 0, NULL, port); -+ -+ if (ret) { -+ dev_err(dev, "failed to request IRQ %d\n", event_irq); -+ return ret; -+ } -+ } -+ -+ intx_irq = irq_create_mapping(port->event_domain, -+ event->intx_event); -+ if (!intx_irq) { -+ dev_err(dev, "failed to map INTx interrupt\n"); -+ return -ENXIO; -+ } -+ -+ /* Plug the INTx chained handler */ -+ irq_set_chained_handler_and_data(intx_irq, plda_handle_intx, port); -+ -+ msi_irq = irq_create_mapping(port->event_domain, -+ event->msi_event); -+ if (!msi_irq) -+ return -ENXIO; -+ -+ /* Plug the MSI chained handler */ -+ irq_set_chained_handler_and_data(msi_irq, plda_handle_msi, port); -+ -+ /* Plug the main event chained handler */ -+ irq_set_chained_handler_and_data(irq, plda_handle_event, port); -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(plda_init_interrupts); -+ - void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, - phys_addr_t axi_addr, phys_addr_t pci_addr, - size_t size) -diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h -index 0e5157eb3a32..eb9e6f304985 100644 ---- a/drivers/pci/controller/plda/pcie-plda.h -+++ b/drivers/pci/controller/plda/pcie-plda.h -@@ -170,6 +170,9 @@ struct plda_event { - int msi_event; - }; - -+int plda_init_interrupts(struct platform_device *pdev, -+ struct plda_pcie_rp *port, -+ const struct plda_event *event); - void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, - phys_addr_t axi_addr, phys_addr_t pci_addr, - size_t size); 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So add a bitmap field to mask the non- -implemented interrupts. - -Signed-off-by: Minda Chen ---- - drivers/pci/controller/plda/pcie-microchip-host.c | 1 + - drivers/pci/controller/plda/pcie-plda-host.c | 6 ++++-- - drivers/pci/controller/plda/pcie-plda.h | 1 + - 3 files changed, 6 insertions(+), 2 deletions(-) - -diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c -index 105964306b71..48f60a04b740 100644 ---- a/drivers/pci/controller/plda/pcie-microchip-host.c -+++ b/drivers/pci/controller/plda/pcie-microchip-host.c -@@ -636,6 +636,7 @@ static int mc_platform_init(struct pci_config_window *cfg) - - port->plda.event_ops = &mc_event_ops; - port->plda.event_irq_chip = &mc_event_irq_chip; -+ port->plda.events_bitmap = GENMASK(NUM_EVENTS - 1, 0); - - /* Address translation is up; safe to enable interrupts */ - ret = plda_init_interrupts(pdev, &port->plda, &mc_event); -diff --git a/drivers/pci/controller/plda/pcie-plda-host.c b/drivers/pci/controller/plda/pcie-plda-host.c -index 98c51e594efe..a040e7e5492f 100644 ---- a/drivers/pci/controller/plda/pcie-plda-host.c -+++ b/drivers/pci/controller/plda/pcie-plda-host.c -@@ -290,6 +290,7 @@ static void plda_handle_event(struct irq_desc *desc) - - events = port->event_ops->get_events(port); - -+ events &= port->events_bitmap; - for_each_set_bit(bit, &events, port->num_events) - generic_handle_domain_irq(port->event_domain, bit); - -@@ -420,8 +421,9 @@ int plda_init_interrupts(struct platform_device *pdev, - { - struct device *dev = &pdev->dev; - int irq; -- int i, intx_irq, msi_irq, event_irq; -+ int intx_irq, msi_irq, event_irq; - int ret; -+ u32 i; - - if (!port->event_ops) - port->event_ops = &plda_event_ops; -@@ -439,7 +441,7 @@ int plda_init_interrupts(struct platform_device *pdev, - if (irq < 0) - return -ENODEV; - -- for (i = 0; i < port->num_events; i++) { -+ for_each_set_bit(i, &port->events_bitmap, port->num_events) { - event_irq = irq_create_mapping(port->event_domain, i); - if (!event_irq) { - dev_err(dev, "failed to map hwirq %d\n", i); -diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h -index eb9e6f304985..c3d8c141e44d 100644 ---- a/drivers/pci/controller/plda/pcie-plda.h -+++ b/drivers/pci/controller/plda/pcie-plda.h -@@ -160,6 +160,7 @@ struct plda_pcie_rp { - const struct plda_event_ops *event_ops; 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So vendor can use it to init PLDA PCIe host core. - -Signed-off-by: Minda Chen -Reviewed-by: Mason Huo ---- - drivers/pci/controller/plda/pcie-plda-host.c | 131 +++++++++++++++++-- - drivers/pci/controller/plda/pcie-plda.h | 22 ++++ - 2 files changed, 139 insertions(+), 14 deletions(-) - -diff --git a/drivers/pci/controller/plda/pcie-plda-host.c b/drivers/pci/controller/plda/pcie-plda-host.c -index a040e7e5492f..a18923d7cea6 100644 ---- a/drivers/pci/controller/plda/pcie-plda-host.c -+++ b/drivers/pci/controller/plda/pcie-plda-host.c -@@ -3,6 +3,7 @@ - * PLDA PCIe XpressRich host controller driver - * - * Copyright (C) 2023 Microchip Co. Ltd -+ * StarFive Co. Ltd - * - * Author: Daire McNamara - */ -@@ -15,6 +16,15 @@ - - #include "pcie-plda.h" - -+void __iomem *plda_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, -+ int where) -+{ -+ struct plda_pcie_rp *pcie = bus->sysdata; -+ -+ return pcie->config_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); -+} -+EXPORT_SYMBOL_GPL(plda_pcie_map_bus); -+ - static void plda_handle_msi(struct irq_desc *desc) - { - struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); -@@ -420,9 +430,7 @@ int plda_init_interrupts(struct platform_device *pdev, - const struct plda_event *event) - { - struct device *dev = &pdev->dev; -- int irq; -- int intx_irq, msi_irq, event_irq; -- int ret; -+ int event_irq, ret; - u32 i; - - if (!port->event_ops) -@@ -437,8 +445,8 @@ int plda_init_interrupts(struct platform_device *pdev, - return ret; - } - -- irq = platform_get_irq(pdev, 0); -- if (irq < 0) -+ port->irq = platform_get_irq(pdev, 0); -+ if (port->irq < 0) - return -ENODEV; - - for_each_set_bit(i, &port->events_bitmap, port->num_events) { -@@ -461,26 +469,26 @@ int plda_init_interrupts(struct platform_device *pdev, - } - } - -- intx_irq = irq_create_mapping(port->event_domain, -- event->intx_event); -- if (!intx_irq) { -+ port->intx_irq = irq_create_mapping(port->event_domain, -+ event->intx_event); -+ if (!port->intx_irq) { - dev_err(dev, "failed to map INTx interrupt\n"); - return -ENXIO; - } - - /* Plug the INTx chained handler */ -- irq_set_chained_handler_and_data(intx_irq, plda_handle_intx, port); -+ irq_set_chained_handler_and_data(port->intx_irq, plda_handle_intx, port); - -- msi_irq = irq_create_mapping(port->event_domain, -- event->msi_event); -- if (!msi_irq) -+ port->msi_irq = irq_create_mapping(port->event_domain, -+ event->msi_event); -+ if (!port->msi_irq) - return -ENXIO; - - /* Plug the MSI chained handler */ -- irq_set_chained_handler_and_data(msi_irq, plda_handle_msi, port); -+ irq_set_chained_handler_and_data(port->msi_irq, plda_handle_msi, port); - - /* Plug the main event chained handler */ -- irq_set_chained_handler_and_data(irq, plda_handle_event, port); -+ irq_set_chained_handler_and_data(port->irq, plda_handle_event, port); - - return 0; - } -@@ -546,3 +554,98 @@ int plda_pcie_setup_iomems(struct pci_host_bridge *bridge, - return 0; - } - EXPORT_SYMBOL_GPL(plda_pcie_setup_iomems); -+ -+static void plda_pcie_irq_domain_deinit(struct plda_pcie_rp *pcie) -+{ -+ irq_set_chained_handler_and_data(pcie->irq, NULL, NULL); -+ irq_set_chained_handler_and_data(pcie->msi_irq, NULL, NULL); -+ irq_set_chained_handler_and_data(pcie->intx_irq, NULL, NULL); -+ -+ irq_domain_remove(pcie->msi.msi_domain); -+ irq_domain_remove(pcie->msi.dev_domain); -+ -+ irq_domain_remove(pcie->intx_domain); -+ irq_domain_remove(pcie->event_domain); -+} -+ -+int plda_pcie_host_init(struct plda_pcie_rp *port, struct pci_ops *ops, -+ const struct plda_event *plda_event) -+{ -+ struct device *dev = port->dev; -+ struct pci_host_bridge *bridge; -+ struct platform_device *pdev = to_platform_device(dev); -+ struct resource *cfg_res; -+ int ret; -+ -+ pdev = to_platform_device(dev); -+ -+ port->bridge_addr = -+ devm_platform_ioremap_resource_byname(pdev, "apb"); -+ -+ if (IS_ERR(port->bridge_addr)) -+ return dev_err_probe(dev, PTR_ERR(port->bridge_addr), -+ "failed to map reg memory\n"); -+ -+ cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); -+ if (!cfg_res) -+ return dev_err_probe(dev, -ENODEV, -+ "failed to get config memory\n"); -+ -+ port->config_base = devm_ioremap_resource(dev, cfg_res); -+ if (IS_ERR(port->config_base)) -+ return dev_err_probe(dev, PTR_ERR(port->config_base), -+ "failed to map config memory\n"); -+ -+ bridge = devm_pci_alloc_host_bridge(dev, 0); -+ if (!bridge) -+ return dev_err_probe(dev, -ENOMEM, -+ "failed to alloc bridge\n"); -+ -+ if (port->host_ops && port->host_ops->host_init) { -+ ret = port->host_ops->host_init(port); -+ if (ret) -+ return ret; -+ } -+ -+ port->bridge = bridge; -+ plda_pcie_setup_window(port->bridge_addr, 0, cfg_res->start, 0, -+ resource_size(cfg_res)); -+ plda_pcie_setup_iomems(bridge, port); -+ plda_set_default_msi(&port->msi); -+ ret = plda_init_interrupts(pdev, port, plda_event); -+ if (ret) -+ goto err_host; -+ -+ /* Set default bus ops */ -+ bridge->ops = ops; -+ bridge->sysdata = port; -+ -+ ret = pci_host_probe(bridge); -+ if (ret < 0) { -+ dev_err_probe(dev, ret, "failed to probe pci host\n"); -+ goto err_probe; -+ } -+ -+ return ret; -+ -+err_probe: -+ plda_pcie_irq_domain_deinit(port); -+err_host: -+ if (port->host_ops && port->host_ops->host_deinit) -+ port->host_ops->host_deinit(port); -+ -+ return ret; -+} -+EXPORT_SYMBOL_GPL(plda_pcie_host_init); -+ -+void plda_pcie_host_deinit(struct plda_pcie_rp *port) -+{ -+ pci_stop_root_bus(port->bridge->bus); -+ pci_remove_root_bus(port->bridge->bus); -+ -+ plda_pcie_irq_domain_deinit(port); -+ -+ if (port->host_ops && port->host_ops->host_deinit) -+ port->host_ops->host_deinit(port); -+} -+EXPORT_SYMBOL_GPL(plda_pcie_host_deinit); -diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h -index c3d8c141e44d..52f4cacf7917 100644 ---- a/drivers/pci/controller/plda/pcie-plda.h -+++ b/drivers/pci/controller/plda/pcie-plda.h -@@ -142,6 +142,11 @@ struct plda_event_ops { - u32 (*get_events)(struct plda_pcie_rp *pcie); - }; - -+struct plda_pcie_host_ops { -+ int (*host_init)(struct plda_pcie_rp *pcie); -+ void (*host_deinit)(struct plda_pcie_rp *pcie); -+}; -+ - struct plda_msi { - struct mutex lock; /* Protect used bitmap */ - struct irq_domain *msi_domain; -@@ -153,14 +158,20 @@ struct plda_msi { - - struct plda_pcie_rp { - struct device *dev; -+ struct pci_host_bridge *bridge; - struct irq_domain *intx_domain; - struct irq_domain *event_domain; - raw_spinlock_t lock; - struct plda_msi msi; - const struct plda_event_ops *event_ops; - const struct irq_chip *event_irq_chip; -+ const struct plda_pcie_host_ops *host_ops; - void __iomem *bridge_addr; -+ void __iomem *config_base; - unsigned long events_bitmap; -+ int irq; -+ int msi_irq; -+ int intx_irq; - int num_events; - }; - -@@ -171,6 +182,8 @@ struct plda_event { - int msi_event; - }; - -+void __iomem *plda_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, -+ int where); - int plda_init_interrupts(struct platform_device *pdev, - struct plda_pcie_rp *port, - const struct plda_event *event); -@@ -179,4 +192,13 @@ void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, - size_t size); - int plda_pcie_setup_iomems(struct pci_host_bridge *bridge, - struct plda_pcie_rp *port); -+int plda_pcie_host_init(struct plda_pcie_rp *port, struct pci_ops *ops, -+ const struct plda_event *plda_event); -+void plda_pcie_host_deinit(struct plda_pcie_rp *pcie); -+ -+static inline void plda_set_default_msi(struct plda_msi *msi) -+{ -+ msi->vector_phy = IMSI_ADDR; -+ msi->num_vectors = PLDA_MAX_NUM_MSI_IRQS; -+} - #endif - -From patchwork Thu Mar 28 09:18:32 2024 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Minda Chen -X-Patchwork-Id: 13608249 -X-Patchwork-Delegate: kw@linux.com -Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn - (mail-sh0chn02on2091.outbound.protection.partner.outlook.cn [139.219.146.91]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4772C7F7C7; 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Thu, 28 Mar 2024 09:19:03 +0000 -From: Minda Chen -To: Lorenzo Pieralisi , - Conor Dooley , - =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , - Rob Herring , Bjorn Helgaas , - Thomas Gleixner , - Daire McNamara , - Emil Renner Berthing , - Krzysztof Kozlowski -Cc: devicetree@vger.kernel.org, - linux-kernel@vger.kernel.org, - linux-riscv@lists.infradead.org, - linux-pci@vger.kernel.org, - Paul Walmsley , - Palmer Dabbelt , - Albert Ou , - Philipp Zabel , - Mason Huo , - Leyfoon Tan , - Kevin Xie , - Minda Chen -Subject: [PATCH v16 19/22] dt-bindings: PCI: Add StarFive JH7110 PCIe - controller -Date: Thu, 28 Mar 2024 17:18:32 +0800 -Message-Id: <20240328091835.14797-20-minda.chen@starfivetech.com> -X-Mailer: git-send-email 2.17.1 -In-Reply-To: <20240328091835.14797-1-minda.chen@starfivetech.com> -References: <20240328091835.14797-1-minda.chen@starfivetech.com> -X-ClientProxiedBy: NT0PR01CA0020.CHNPR01.prod.partner.outlook.cn - (2406:e500:c510:c::16) To SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn - (2406:e500:c311:25::15) -Precedence: bulk -X-Mailing-List: linux-pci@vger.kernel.org -List-Id: -List-Subscribe: -List-Unsubscribe: -MIME-Version: 1.0 -X-MS-PublicTrafficType: Email -X-MS-TrafficTypeDiagnostic: SHXPR01MB0863:EE_|SHXPR01MB0559:EE_ -X-MS-Office365-Filtering-Correlation-Id: 191e3b49-1114-4f7b-7186-08dc4f081c14 -X-MS-Exchange-SenderADCheck: 1 -X-Microsoft-Antispam: BCL:0; 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JH7110 using PLDA -XpressRICH PCIe host controller IP. - -Signed-off-by: Minda Chen -Reviewed-by: Hal Feng -Reviewed-by: Conor Dooley -Reviewed-by: Rob Herring -Acked-by: Kevin Xie ---- - .../bindings/pci/starfive,jh7110-pcie.yaml | 120 ++++++++++++++++++ - MAINTAINERS | 6 + - 2 files changed, 126 insertions(+) - create mode 100644 Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml - -diff --git a/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml -new file mode 100644 -index 000000000000..67151aaa3948 ---- /dev/null -+++ b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml -@@ -0,0 +1,120 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/pci/starfive,jh7110-pcie.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: StarFive JH7110 PCIe host controller -+ -+maintainers: -+ - Kevin Xie -+ -+allOf: -+ - $ref: plda,xpressrich3-axi-common.yaml# -+ -+properties: -+ compatible: -+ const: starfive,jh7110-pcie -+ -+ clocks: -+ items: -+ - description: NOC bus clock -+ - description: Transport layer clock -+ - description: AXI MST0 clock -+ - description: APB clock -+ -+ clock-names: -+ items: -+ - const: noc -+ - const: tl -+ - const: axi_mst0 -+ - const: apb -+ -+ resets: -+ items: -+ - description: AXI MST0 reset -+ - description: AXI SLAVE0 reset -+ - description: AXI SLAVE reset -+ - description: PCIE BRIDGE reset -+ - description: PCIE CORE reset -+ - description: PCIE APB reset -+ -+ reset-names: -+ items: -+ - const: mst0 -+ - const: slv0 -+ - const: slv -+ - const: brg -+ - const: core -+ - const: apb -+ -+ starfive,stg-syscon: -+ $ref: /schemas/types.yaml#/definitions/phandle-array -+ description: -+ The phandle to System Register Controller syscon node. -+ -+ perst-gpios: -+ description: GPIO controlled connection to PERST# signal -+ maxItems: 1 -+ -+ phys: -+ description: -+ Specified PHY is attached to PCIe controller. -+ maxItems: 1 -+ -+required: -+ - clocks -+ - resets -+ - starfive,stg-syscon -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ #include -+ soc { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ pcie@940000000 { -+ compatible = "starfive,jh7110-pcie"; -+ reg = <0x9 0x40000000 0x0 0x10000000>, -+ <0x0 0x2b000000 0x0 0x1000000>; -+ reg-names = "cfg", "apb"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ device_type = "pci"; -+ ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, -+ <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; -+ starfive,stg-syscon = <&stg_syscon>; -+ bus-range = <0x0 0xff>; -+ interrupt-parent = <&plic>; -+ interrupts = <56>; -+ interrupt-map-mask = <0x0 0x0 0x0 0x7>; -+ interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>, -+ <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>, -+ <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>, -+ <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>; -+ msi-controller; -+ clocks = <&syscrg 86>, -+ <&stgcrg 10>, -+ <&stgcrg 8>, -+ <&stgcrg 9>; -+ clock-names = "noc", "tl", "axi_mst0", "apb"; -+ resets = <&stgcrg 11>, -+ <&stgcrg 12>, -+ <&stgcrg 13>, -+ <&stgcrg 14>, -+ <&stgcrg 15>, -+ <&stgcrg 16>; -+ perst-gpios = <&gpios 26 GPIO_ACTIVE_LOW>; -+ phys = <&pciephy0>; -+ -+ pcie_intc0: interrupt-controller { -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ }; -diff --git a/MAINTAINERS b/MAINTAINERS -index d85d9db38efa..3772f6893818 100644 ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -17215,6 +17215,12 @@ L: linux-pci@vger.kernel.org - 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fa28561d-cd0b-4b65-0e69-08dc4f081cae -X-MS-Exchange-CrossTenant-AuthSource: - SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn -X-MS-Exchange-CrossTenant-AuthAs: Internal -X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Mar 2024 09:19:04.0399 - (UTC) -X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted -X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c -X-MS-Exchange-CrossTenant-MailboxType: HOSTED -X-MS-Exchange-CrossTenant-UserPrincipalName: - mT4IaNHihzqZr0YFm7I6Ika7qeEmUX436O01daXl8Gp2CfWjkcuftyDn4T131NAc2yCrrJGB9Pt0sFC1cV872YXiRJNroRpOJne4u0A2JC8= -X-MS-Exchange-Transport-CrossTenantHeadersStamped: SHXPR01MB0559 - -From: Kevin Xie - -Add the PCIE_RESET_CONFIG_DEVICE_WAIT_MS macro to define the minimum -waiting time between exit from a conventional reset and sending the -first configuration request to the device. - -As described in PCI base specification r6.0, section 6.6.1 , there are two different use cases of the value: - - - "With a Downstream Port that does not support Link speeds greater - than 5.0 GT/s, software must wait a minimum of 100 ms following exit - from a Conventional Reset before sending a Configuration Request to - the device immediately below that Port." - - - "With a Downstream Port that supports Link speeds greater than - 5.0 GT/s, software must wait a minimum of 100 ms after Link training - completes before sending a Configuration Request to the device - immediately below that Port." - -Signed-off-by: Kevin Xie -Reviewed-by: Mason Huo -Acked-by: Bjorn Helgaas ---- - drivers/pci/pci.h | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - -diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h -index 17fed1846847..6fa59d6aa063 100644 ---- a/drivers/pci/pci.h -+++ b/drivers/pci/pci.h -@@ -22,6 +22,22 @@ - */ - #define PCIE_PME_TO_L2_TIMEOUT_US 10000 - -+/* -+ * As described in PCI base specification r6.0, section 6.6.1 , there are two different use cases of the value: -+ * -+ * - "With a Downstream Port that does not support Link speeds greater -+ * than 5.0 GT/s, software must wait a minimum of 100 ms following exit -+ * from a Conventional Reset before sending a Configuration Request to -+ * the device immediately below that Port." -+ * -+ * - "With a Downstream Port that supports Link speeds greater than -+ * 5.0 GT/s, software must wait a minimum of 100 ms after Link training -+ * completes before sending a Configuration Request to the device -+ * immediately below that Port." -+ */ -+#define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 100 -+ - extern const unsigned char pcie_link_speed[]; - extern bool pci_early_dump; - - -From patchwork Thu Mar 28 09:18:34 2024 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Minda Chen -X-Patchwork-Id: 13608252 -X-Patchwork-Delegate: kw@linux.com -Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn - (mail-sh0chn02on2091.outbound.protection.partner.outlook.cn [139.219.146.91]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by smtp.subspace.kernel.org (Postfix) with ESMTPS id D11B88002F; - Thu, 28 Mar 2024 09:19:17 +0000 (UTC) -Authentication-Results: smtp.subspace.kernel.org; - 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b869200f-e1b4-49d4-d121-08dc4f081d49 -X-MS-Exchange-CrossTenant-AuthSource: - SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn -X-MS-Exchange-CrossTenant-AuthAs: Internal -X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Mar 2024 09:19:05.0868 - (UTC) -X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted -X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c -X-MS-Exchange-CrossTenant-MailboxType: HOSTED -X-MS-Exchange-CrossTenant-UserPrincipalName: - dl89eCWLs7SXIywp4zQUPyticVVXHOKdm6AReyuHd71RlNLVCxm3NzZiARQdQjprlocEuuYIhLL/kPJLtacqERArUTUeJ0KYMkrp6UGeurE= -X-MS-Exchange-Transport-CrossTenantHeadersStamped: SHXPR01MB0559 - -Add StarFive JH7110 SoC PCIe controller platform driver code, JH7110 -with PLDA host PCIe core. - -Signed-off-by: Minda Chen -Co-developed-by: Kevin Xie -Reviewed-by: Mason Huo ---- - MAINTAINERS | 1 + - drivers/pci/controller/plda/Kconfig | 12 + - drivers/pci/controller/plda/Makefile | 1 + - drivers/pci/controller/plda/pcie-plda.h | 71 ++- - drivers/pci/controller/plda/pcie-starfive.c | 488 ++++++++++++++++++++ - 5 files changed, 572 insertions(+), 1 deletion(-) - create mode 100644 drivers/pci/controller/plda/pcie-starfive.c - -diff --git a/MAINTAINERS b/MAINTAINERS -index 3772f6893818..de85d6d1b92c 100644 ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -17220,6 +17220,7 @@ M: Kevin Xie - L: linux-pci@vger.kernel.org - S: Maintained - F: Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml -+F: drivers/pci/controller/plda/pcie-starfive.c - - PCIE ENDPOINT DRIVER FOR QUALCOMM - M: Manivannan Sadhasivam -diff --git a/drivers/pci/controller/plda/Kconfig b/drivers/pci/controller/plda/Kconfig -index e54a82ee94f5..c0e14146d7e4 100644 ---- a/drivers/pci/controller/plda/Kconfig -+++ b/drivers/pci/controller/plda/Kconfig -@@ -15,4 +15,16 @@ config PCIE_MICROCHIP_HOST - Say Y here if you want kernel to support the Microchip AXI PCIe - Host Bridge driver. - -+config PCIE_STARFIVE_HOST -+ tristate "StarFive PCIe host controller" -+ depends on PCI_MSI && OF -+ depends on ARCH_STARFIVE || COMPILE_TEST -+ select PCIE_PLDA_HOST -+ help -+ Say Y here if you want to support the StarFive PCIe controller in -+ host mode. StarFive PCIe controller uses PLDA PCIe core. -+ -+ If you choose to build this driver as module it will be dynamically -+ linked and module will be called pcie-starfive.ko. -+ - endmenu -diff --git a/drivers/pci/controller/plda/Makefile b/drivers/pci/controller/plda/Makefile -index 4340ab007f44..0ac6851bed48 100644 ---- a/drivers/pci/controller/plda/Makefile -+++ b/drivers/pci/controller/plda/Makefile -@@ -1,3 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0 - obj-$(CONFIG_PCIE_PLDA_HOST) += pcie-plda-host.o - obj-$(CONFIG_PCIE_MICROCHIP_HOST) += pcie-microchip-host.o -+obj-$(CONFIG_PCIE_STARFIVE_HOST) += pcie-starfive.o -diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h -index 52f4cacf7917..0e7dc0d8e5ba 100644 ---- a/drivers/pci/controller/plda/pcie-plda.h -+++ b/drivers/pci/controller/plda/pcie-plda.h -@@ -10,10 +10,20 @@ - #define PLDA_MAX_NUM_MSI_IRQS 32 - - /* PCIe Bridge Phy Regs */ -+#define GEN_SETTINGS 0x80 -+#define RP_ENABLE 1 -+#define PCIE_PCI_IDS_DW1 0x9c -+#define IDS_CLASS_CODE_SHIFT 16 -+#define REVISION_ID_MASK GENMASK(7, 0) -+#define CLASS_CODE_ID_MASK GENMASK(31, 8) - #define PCIE_PCI_IRQ_DW0 0xa8 - #define MSIX_CAP_MASK BIT(31) - #define NUM_MSI_MSGS_MASK GENMASK(6, 4) - #define NUM_MSI_MSGS_SHIFT 4 -+#define PCI_MISC 0xb4 -+#define PHY_FUNCTION_DIS BIT(15) -+#define PCIE_WINROM 0xfc -+#define PREF_MEM_WIN_64_SUPPORT BIT(3) - - #define IMASK_LOCAL 0x180 - #define DMA_END_ENGINE_0_MASK 0x00000000u -@@ -65,6 +75,8 @@ - #define ISTATUS_HOST 0x18c - #define IMSI_ADDR 0x190 - #define ISTATUS_MSI 0x194 -+#define PMSG_SUPPORT_RX 0x3f0 -+#define PMSG_LTR_SUPPORT BIT(2) - - /* PCIe Master table init defines */ - #define ATR0_PCIE_WIN0_SRCADDR_PARAM 0x600u -@@ -86,6 +98,8 @@ - #define PCIE_TX_RX_INTERFACE 0x00000000u - #define PCIE_CONFIG_INTERFACE 0x00000001u - -+#define CONFIG_SPACE_ADDR_OFFSET 0x1000u -+ - #define ATR_ENTRY_SIZE 32 - - enum plda_int_event { -@@ -201,4 +215,59 @@ static inline void plda_set_default_msi(struct plda_msi *msi) - msi->vector_phy = IMSI_ADDR; - msi->num_vectors = PLDA_MAX_NUM_MSI_IRQS; - } --#endif -+ -+static inline void plda_pcie_enable_root_port(struct plda_pcie_rp *plda) -+{ -+ u32 value; -+ -+ value = readl_relaxed(plda->bridge_addr + GEN_SETTINGS); -+ value |= RP_ENABLE; -+ writel_relaxed(value, plda->bridge_addr + GEN_SETTINGS); -+} -+ -+static inline void plda_pcie_set_standard_class(struct plda_pcie_rp *plda) -+{ -+ u32 value; -+ -+ /* set class code and reserve revision id */ -+ value = readl_relaxed(plda->bridge_addr + PCIE_PCI_IDS_DW1); -+ value &= REVISION_ID_MASK; -+ value |= (PCI_CLASS_BRIDGE_PCI << IDS_CLASS_CODE_SHIFT); -+ writel_relaxed(value, plda->bridge_addr + PCIE_PCI_IDS_DW1); -+} -+ -+static inline void plda_pcie_set_pref_win_64bit(struct plda_pcie_rp *plda) -+{ -+ u32 value; -+ -+ value = readl_relaxed(plda->bridge_addr + PCIE_WINROM); -+ value |= PREF_MEM_WIN_64_SUPPORT; -+ writel_relaxed(value, plda->bridge_addr + PCIE_WINROM); -+} -+ -+static inline void plda_pcie_disable_ltr(struct plda_pcie_rp *plda) -+{ -+ u32 value; -+ -+ value = readl_relaxed(plda->bridge_addr + PMSG_SUPPORT_RX); -+ value &= ~PMSG_LTR_SUPPORT; -+ writel_relaxed(value, plda->bridge_addr + PMSG_SUPPORT_RX); -+} -+ -+static inline void plda_pcie_disable_func(struct plda_pcie_rp *plda) -+{ -+ u32 value; -+ -+ value = readl_relaxed(plda->bridge_addr + PCI_MISC); -+ value |= PHY_FUNCTION_DIS; -+ writel_relaxed(value, plda->bridge_addr + PCI_MISC); -+} -+ -+static inline void plda_pcie_write_rc_bar(struct plda_pcie_rp *plda, u64 val) -+{ -+ void __iomem *addr = plda->bridge_addr + CONFIG_SPACE_ADDR_OFFSET; -+ -+ writel_relaxed(lower_32_bits(val), addr + PCI_BASE_ADDRESS_0); -+ writel_relaxed(upper_32_bits(val), addr + PCI_BASE_ADDRESS_1); -+} -+#endif /* _PCIE_PLDA_H */ -diff --git a/drivers/pci/controller/plda/pcie-starfive.c b/drivers/pci/controller/plda/pcie-starfive.c -new file mode 100644 -index 000000000000..c9933ecf6833 ---- /dev/null -+++ b/drivers/pci/controller/plda/pcie-starfive.c -@@ -0,0 +1,488 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * PCIe host controller driver for StarFive JH7110 Soc. -+ * -+ * Copyright (C) 2023 StarFive Technology Co., Ltd. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "../../pci.h" -+ -+#include "pcie-plda.h" -+ -+#define PCIE_FUNC_NUM 4 -+ -+/* system control */ -+#define STG_SYSCON_PCIE0_BASE 0x48 -+#define STG_SYSCON_PCIE1_BASE 0x1f8 -+ -+#define STG_SYSCON_AR_OFFSET 0x78 -+#define STG_SYSCON_AXI4_SLVL_AR_MASK GENMASK(22, 8) -+#define STG_SYSCON_AXI4_SLVL_PHY_AR(x) FIELD_PREP(GENMASK(20, 17), x) -+#define STG_SYSCON_AW_OFFSET 0x7c -+#define STG_SYSCON_AXI4_SLVL_AW_MASK GENMASK(14, 0) -+#define STG_SYSCON_AXI4_SLVL_PHY_AW(x) FIELD_PREP(GENMASK(12, 9), x) -+#define STG_SYSCON_CLKREQ BIT(22) -+#define STG_SYSCON_CKREF_SRC_MASK GENMASK(19, 18) -+#define STG_SYSCON_RP_NEP_OFFSET 0xe8 -+#define STG_SYSCON_K_RP_NEP BIT(8) -+#define STG_SYSCON_LNKSTA_OFFSET 0x170 -+#define DATA_LINK_ACTIVE BIT(5) -+ -+/* Parameters for the waiting for link up routine */ -+#define LINK_WAIT_MAX_RETRIES 10 -+#define LINK_WAIT_USLEEP_MIN 90000 -+#define LINK_WAIT_USLEEP_MAX 100000 -+ -+struct starfive_jh7110_pcie { -+ struct plda_pcie_rp plda; -+ struct reset_control *resets; -+ struct clk_bulk_data *clks; -+ struct regmap *reg_syscon; -+ struct gpio_desc *power_gpio; -+ struct gpio_desc *reset_gpio; -+ struct phy *phy; -+ -+ unsigned int stg_pcie_base; -+ int num_clks; -+}; -+ -+/* -+ * JH7110 PCIe port BAR0/1 can be configured as 64-bit prefetchable memory -+ * space. PCIe read and write requests targeting BAR0/1 are routed to so called -+ * 'Bridge Configuration space' in PLDA IP datasheet, which contains the bridge -+ * internal registers, such as interrupt, DMA and ATU registers... -+ * JH7110 can access the Bridge Configuration space by local bus, and don`t -+ * want the bridge internal registers accessed by the DMA from EP devices. -+ * Thus, they are unimplemented and should be hidden here. -+ */ -+static bool starfive_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn, -+ int offset) -+{ -+ if (pci_is_root_bus(bus) && !devfn && -+ (offset == PCI_BASE_ADDRESS_0 || offset == PCI_BASE_ADDRESS_1)) -+ return true; -+ -+ return false; -+} -+ -+static int starfive_pcie_config_write(struct pci_bus *bus, unsigned int devfn, -+ int where, int size, u32 value) -+{ -+ if (starfive_pcie_hide_rc_bar(bus, devfn, where)) -+ return PCIBIOS_SUCCESSFUL; -+ -+ return pci_generic_config_write(bus, devfn, where, size, value); -+} -+ -+static int starfive_pcie_config_read(struct pci_bus *bus, unsigned int devfn, -+ int where, int size, u32 *value) -+{ -+ if (starfive_pcie_hide_rc_bar(bus, devfn, where)) { -+ *value = 0; -+ return PCIBIOS_SUCCESSFUL; -+ } -+ -+ return pci_generic_config_read(bus, devfn, where, size, value); -+} -+ -+static int starfive_pcie_parse_dt(struct starfive_jh7110_pcie *pcie, -+ struct device *dev) -+{ -+ int domain_nr; -+ -+ pcie->num_clks = devm_clk_bulk_get_all(dev, &pcie->clks); -+ if (pcie->num_clks < 0) -+ return dev_err_probe(dev, pcie->num_clks, -+ "failed to get pcie clocks\n"); -+ -+ pcie->resets = devm_reset_control_array_get_exclusive(dev); -+ if (IS_ERR(pcie->resets)) -+ return dev_err_probe(dev, PTR_ERR(pcie->resets), -+ "failed to get pcie resets"); -+ -+ pcie->reg_syscon = -+ syscon_regmap_lookup_by_phandle(dev->of_node, -+ "starfive,stg-syscon"); -+ -+ if (IS_ERR(pcie->reg_syscon)) -+ return dev_err_probe(dev, PTR_ERR(pcie->reg_syscon), -+ "failed to parse starfive,stg-syscon\n"); -+ -+ pcie->phy = devm_phy_optional_get(dev, NULL); -+ if (IS_ERR(pcie->phy)) -+ return dev_err_probe(dev, PTR_ERR(pcie->phy), -+ "failed to get pcie phy\n"); -+ -+ /* -+ * The PCIe domain numbers are set to be static in JH7110 DTS. -+ * As the STG system controller defines different bases in PCIe RP0 & -+ * RP1, we use them to identify which controller is doing the hardware -+ * initialization. -+ */ -+ domain_nr = of_get_pci_domain_nr(dev->of_node); -+ -+ if (domain_nr < 0 || domain_nr > 1) -+ return dev_err_probe(dev, -ENODEV, -+ "failed to get valid pcie domain\n"); -+ -+ if (domain_nr == 0) -+ pcie->stg_pcie_base = STG_SYSCON_PCIE0_BASE; -+ else -+ pcie->stg_pcie_base = STG_SYSCON_PCIE1_BASE; -+ -+ pcie->reset_gpio = devm_gpiod_get_optional(dev, "perst", -+ GPIOD_OUT_HIGH); -+ if (IS_ERR(pcie->reset_gpio)) -+ return dev_err_probe(dev, PTR_ERR(pcie->reset_gpio), -+ "failed to get perst-gpio\n"); -+ -+ pcie->power_gpio = devm_gpiod_get_optional(dev, "enable", -+ GPIOD_OUT_LOW); -+ if (IS_ERR(pcie->power_gpio)) -+ return dev_err_probe(dev, PTR_ERR(pcie->power_gpio), -+ "failed to get power-gpio\n"); -+ -+ return 0; -+} -+ -+static struct pci_ops starfive_pcie_ops = { -+ .map_bus = plda_pcie_map_bus, -+ .read = starfive_pcie_config_read, -+ .write = starfive_pcie_config_write, -+}; -+ -+static int starfive_pcie_clk_rst_init(struct starfive_jh7110_pcie *pcie) -+{ -+ struct device *dev = pcie->plda.dev; -+ int ret; -+ -+ ret = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); -+ if (ret) -+ return dev_err_probe(dev, ret, "failed to enable clocks\n"); -+ -+ ret = reset_control_deassert(pcie->resets); -+ if (ret) { -+ clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); -+ dev_err_probe(dev, ret, "failed to deassert resets\n"); -+ } -+ -+ return ret; -+} -+ -+static void starfive_pcie_clk_rst_deinit(struct starfive_jh7110_pcie *pcie) -+{ -+ reset_control_assert(pcie->resets); -+ clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); -+} -+ -+static bool starfive_pcie_link_up(struct plda_pcie_rp *plda) -+{ -+ struct starfive_jh7110_pcie *pcie = -+ container_of(plda, struct starfive_jh7110_pcie, plda); -+ int ret; -+ u32 stg_reg_val; -+ -+ ret = regmap_read(pcie->reg_syscon, -+ pcie->stg_pcie_base + STG_SYSCON_LNKSTA_OFFSET, -+ &stg_reg_val); -+ if (ret) { -+ dev_err(pcie->plda.dev, "failed to read link status\n"); -+ return false; -+ } -+ -+ return !!(stg_reg_val & DATA_LINK_ACTIVE); -+} -+ -+static int starfive_pcie_host_wait_for_link(struct starfive_jh7110_pcie *pcie) -+{ -+ int retries; -+ -+ /* Check if the link is up or not */ -+ for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { -+ if (starfive_pcie_link_up(&pcie->plda)) { -+ dev_info(pcie->plda.dev, "port link up\n"); -+ return 0; -+ } -+ usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); -+ } -+ -+ return -ETIMEDOUT; -+} -+ -+static int starfive_pcie_enable_phy(struct device *dev, -+ struct starfive_jh7110_pcie *pcie) -+{ -+ int ret; -+ -+ if (!pcie->phy) -+ return 0; -+ -+ ret = phy_init(pcie->phy); -+ if (ret) -+ return dev_err_probe(dev, ret, -+ "failed to initialize pcie phy\n"); -+ -+ ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE); -+ if (ret) { -+ dev_err_probe(dev, ret, "failed to set pcie mode\n"); -+ goto err_phy_on; -+ } -+ -+ ret = phy_power_on(pcie->phy); -+ if (ret) { -+ dev_err_probe(dev, ret, "failed to power on pcie phy\n"); -+ goto err_phy_on; -+ } -+ -+ return 0; -+ -+err_phy_on: -+ phy_exit(pcie->phy); -+ return ret; -+} -+ -+static void starfive_pcie_disable_phy(struct starfive_jh7110_pcie *pcie) -+{ -+ phy_power_off(pcie->phy); -+ phy_exit(pcie->phy); -+} -+ -+static void starfive_pcie_host_deinit(struct plda_pcie_rp *plda) -+{ -+ struct starfive_jh7110_pcie *pcie = -+ container_of(plda, struct starfive_jh7110_pcie, plda); -+ -+ starfive_pcie_clk_rst_deinit(pcie); -+ if (pcie->power_gpio) -+ gpiod_set_value_cansleep(pcie->power_gpio, 0); -+ starfive_pcie_disable_phy(pcie); -+} -+ -+static int starfive_pcie_host_init(struct plda_pcie_rp *plda) -+{ -+ struct starfive_jh7110_pcie *pcie = -+ container_of(plda, struct starfive_jh7110_pcie, plda); -+ struct device *dev = plda->dev; -+ int ret; -+ int i; -+ -+ ret = starfive_pcie_enable_phy(dev, pcie); -+ if (ret) -+ return ret; -+ -+ regmap_update_bits(pcie->reg_syscon, -+ pcie->stg_pcie_base + STG_SYSCON_RP_NEP_OFFSET, -+ STG_SYSCON_K_RP_NEP, STG_SYSCON_K_RP_NEP); -+ -+ regmap_update_bits(pcie->reg_syscon, -+ pcie->stg_pcie_base + STG_SYSCON_AW_OFFSET, -+ STG_SYSCON_CKREF_SRC_MASK, -+ FIELD_PREP(STG_SYSCON_CKREF_SRC_MASK, 2)); -+ -+ regmap_update_bits(pcie->reg_syscon, -+ pcie->stg_pcie_base + STG_SYSCON_AW_OFFSET, -+ STG_SYSCON_CLKREQ, STG_SYSCON_CLKREQ); -+ -+ ret = starfive_pcie_clk_rst_init(pcie); -+ if (ret) -+ return ret; -+ -+ if (pcie->power_gpio) -+ gpiod_set_value_cansleep(pcie->power_gpio, 1); -+ -+ if (pcie->reset_gpio) -+ gpiod_set_value_cansleep(pcie->reset_gpio, 1); -+ -+ /* Disable physical functions except #0 */ -+ for (i = 1; i < PCIE_FUNC_NUM; i++) { -+ regmap_update_bits(pcie->reg_syscon, -+ pcie->stg_pcie_base + STG_SYSCON_AR_OFFSET, -+ STG_SYSCON_AXI4_SLVL_AR_MASK, -+ STG_SYSCON_AXI4_SLVL_PHY_AR(i)); -+ -+ regmap_update_bits(pcie->reg_syscon, -+ pcie->stg_pcie_base + STG_SYSCON_AW_OFFSET, -+ STG_SYSCON_AXI4_SLVL_AW_MASK, -+ STG_SYSCON_AXI4_SLVL_PHY_AW(i)); -+ -+ plda_pcie_disable_func(plda); -+ } -+ -+ regmap_update_bits(pcie->reg_syscon, -+ pcie->stg_pcie_base + STG_SYSCON_AR_OFFSET, -+ STG_SYSCON_AXI4_SLVL_AR_MASK, 0); -+ regmap_update_bits(pcie->reg_syscon, -+ pcie->stg_pcie_base + STG_SYSCON_AW_OFFSET, -+ STG_SYSCON_AXI4_SLVL_AW_MASK, 0); -+ -+ plda_pcie_enable_root_port(plda); -+ plda_pcie_write_rc_bar(plda, 0); -+ -+ /* PCIe PCI Standard Configuration Identification Settings. */ -+ plda_pcie_set_standard_class(plda); -+ -+ /* -+ * The LTR message receiving is enabled by the register "PCIe Message -+ * Reception" as default, but the forward id & addr are uninitialized. -+ * If we do not disable LTR message forwarding here, or set a legal -+ * forwarding address, the kernel will get stuck. -+ * To workaround, disable the LTR message forwarding here before using -+ * this feature. -+ */ -+ plda_pcie_disable_ltr(plda); -+ -+ /* -+ * Enable the prefetchable memory window 64-bit addressing in JH7110. -+ * The 64-bits prefetchable address translation configurations in ATU -+ * can be work after enable the register setting below. -+ */ -+ plda_pcie_set_pref_win_64bit(plda); -+ -+ /* -+ * Ensure that PERST has been asserted for at least 100 ms, -+ * the sleep value is T_PVPERL from PCIe CEM spec r2.0 (Table 2-4) -+ */ -+ msleep(100); -+ if (pcie->reset_gpio) -+ gpiod_set_value_cansleep(pcie->reset_gpio, 0); -+ -+ /* -+ * With a Downstream Port (<=5GT/s), software must wait a minimum -+ * of 100ms following exit from a conventional reset before -+ * sending a configuration request to the device. -+ */ -+ msleep(PCIE_RESET_CONFIG_DEVICE_WAIT_MS); -+ -+ if (starfive_pcie_host_wait_for_link(pcie)) -+ dev_info(dev, "port link down\n"); -+ -+ return 0; -+} -+ -+static const struct plda_pcie_host_ops sf_host_ops = { -+ .host_init = starfive_pcie_host_init, -+ .host_deinit = starfive_pcie_host_deinit, -+}; -+ -+static const struct plda_event stf_pcie_event = { -+ .intx_event = EVENT_PM_MSI_INT_INTX, -+ .msi_event = EVENT_PM_MSI_INT_MSI -+}; -+ -+static int starfive_pcie_probe(struct platform_device *pdev) -+{ -+ struct starfive_jh7110_pcie *pcie; -+ struct device *dev = &pdev->dev; -+ struct plda_pcie_rp *plda; -+ int ret; -+ -+ pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); -+ if (!pcie) -+ return -ENOMEM; -+ -+ plda = &pcie->plda; -+ plda->dev = dev; -+ -+ ret = starfive_pcie_parse_dt(pcie, dev); -+ if (ret) -+ return ret; -+ -+ plda->host_ops = &sf_host_ops; -+ plda->num_events = PLDA_MAX_EVENT_NUM; -+ /* mask doorbell event */ -+ plda->events_bitmap = GENMASK(PLDA_INT_EVENT_NUM - 1, 0) -+ & ~BIT(PLDA_AXI_DOORBELL) -+ & ~BIT(PLDA_PCIE_DOORBELL); -+ plda->events_bitmap <<= PLDA_NUM_DMA_EVENTS; -+ ret = plda_pcie_host_init(&pcie->plda, &starfive_pcie_ops, -+ &stf_pcie_event); -+ if (ret) -+ return ret; -+ -+ pm_runtime_enable(&pdev->dev); -+ pm_runtime_get_sync(&pdev->dev); -+ platform_set_drvdata(pdev, pcie); -+ -+ return 0; -+} -+ -+static void starfive_pcie_remove(struct platform_device *pdev) -+{ -+ struct starfive_jh7110_pcie *pcie = platform_get_drvdata(pdev); -+ -+ pm_runtime_put(&pdev->dev); -+ pm_runtime_disable(&pdev->dev); -+ plda_pcie_host_deinit(&pcie->plda); -+ platform_set_drvdata(pdev, NULL); -+} -+ -+static int starfive_pcie_suspend_noirq(struct device *dev) -+{ -+ struct starfive_jh7110_pcie *pcie = dev_get_drvdata(dev); -+ -+ clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); -+ starfive_pcie_disable_phy(pcie); -+ -+ return 0; -+} -+ -+static int starfive_pcie_resume_noirq(struct device *dev) -+{ -+ struct starfive_jh7110_pcie *pcie = dev_get_drvdata(dev); -+ int ret; -+ -+ ret = starfive_pcie_enable_phy(dev, pcie); -+ if (ret) -+ return ret; -+ -+ ret = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); -+ if (ret) { -+ dev_err(dev, "failed to enable clocks\n"); -+ starfive_pcie_disable_phy(pcie); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static const struct dev_pm_ops starfive_pcie_pm_ops = { -+ NOIRQ_SYSTEM_SLEEP_PM_OPS(starfive_pcie_suspend_noirq, -+ starfive_pcie_resume_noirq) -+}; -+ -+static const struct of_device_id starfive_pcie_of_match[] = { -+ { .compatible = "starfive,jh7110-pcie", }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, starfive_pcie_of_match); -+ -+static struct platform_driver starfive_pcie_driver = { -+ .driver = { -+ .name = "pcie-starfive", -+ .of_match_table = of_match_ptr(starfive_pcie_of_match), -+ .pm = pm_sleep_ptr(&starfive_pcie_pm_ops), -+ }, -+ .probe = starfive_pcie_probe, -+ .remove_new = starfive_pcie_remove, -+}; -+module_platform_driver(starfive_pcie_driver); -+ -+MODULE_DESCRIPTION("StarFive JH7110 PCIe host driver"); -+MODULE_LICENSE("GPL v2"); - -From 2904244a8c46bdd0fee181df693a495f4628a575 Mon Sep 17 00:00:00 2001 -From: Minda Chen -Date: Fri, 21 Jun 2024 16:22:31 +0800 -Subject: riscv: dts: starfive: add PCIe dts configuration for JH7110 - -Add PCIe dts configuraion for JH7110 SoC platform. The Star64 only has -one exposed PCIe port, so only the Mars and VisionFive 2 get two -enabled. - -Signed-off-by: Minda Chen -Reviewed-by: Hal Feng -[conor: squash in star64's single exposed port] -Signed-off-by: Conor Dooley ---- - arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 62 ++++++++++++++++ - arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts | 7 ++ - .../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 8 ++ - arch/riscv/boot/dts/starfive/jh7110.dtsi | 86 ++++++++++++++++++++++ - 5 files changed, 167 insertions(+) - -(limited to 'arch/riscv/boot/dts/starfive') - -diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi -index 37b4c294ffcc53..20bc8c03b8215c 100644 ---- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi -+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi -@@ -294,6 +294,20 @@ - status = "okay"; - }; - -+&pcie0 { -+ perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; -+ phys = <&pciephy0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie0_pins>; -+}; -+ -+&pcie1 { -+ perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>; -+ phys = <&pciephy1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie1_pins>; -+}; -+ - &pwmdac { - pinctrl-names = "default"; - pinctrl-0 = <&pwmdac_pins>; -@@ -473,6 +487,54 @@ - }; - }; - -+ pcie0_pins: pcie0-0 { -+ clkreq-pins { -+ pinmux = ; -+ bias-pull-down; -+ drive-strength = <2>; -+ input-enable; -+ input-schmitt-disable; -+ slew-rate = <0>; -+ }; -+ -+ wake-pins { -+ pinmux = ; -+ bias-pull-up; -+ drive-strength = <2>; -+ input-enable; -+ input-schmitt-disable; -+ slew-rate = <0>; -+ }; -+ }; -+ -+ pcie1_pins: pcie1-0 { -+ clkreq-pins { -+ pinmux = ; -+ bias-pull-down; -+ drive-strength = <2>; -+ input-enable; -+ input-schmitt-disable; -+ slew-rate = <0>; -+ }; -+ -+ wake-pins { -+ pinmux = ; -+ bias-pull-up; -+ drive-strength = <2>; -+ input-enable; -+ input-schmitt-disable; -+ slew-rate = <0>; -+ }; -+ }; -+ - pwmdac_pins: pwmdac-0 { - pwmdac-pins { - pinmux = ; - }; - -+&pcie0 { -+ status = "okay"; -+}; -+ -+&pcie1 { -+ status = "okay"; -+}; - - &phy0 { - motorcomm,tx-clk-adj-enabled; -diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi -index 9d70f21c86fc6e..18f38fc790a4d1 100644 ---- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi -+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi -@@ -32,3 +32,11 @@ - &mmc0 { - non-removable; - }; -+ -+&pcie0 { -+ status = "okay"; -+}; -+ -+&pcie1 { -+ status = "okay"; -+}; -diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi -index 18047195c600bd..5ac70759e0ab9e 100644 ---- a/arch/riscv/boot/dts/starfive/jh7110.dtsi -+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi -@@ -1214,5 +1214,91 @@ - #reset-cells = <1>; - power-domains = <&pwrc JH7110_PD_VOUT>; - }; -+ -+ pcie0: pcie@940000000 { -+ compatible = "starfive,jh7110-pcie"; -+ reg = <0x9 0x40000000 0x0 0x1000000>, -+ <0x0 0x2b000000 0x0 0x100000>; -+ reg-names = "cfg", "apb"; -+ linux,pci-domain = <0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, -+ <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; -+ interrupts = <56>; -+ interrupt-map-mask = <0x0 0x0 0x0 0x7>; -+ interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>, -+ <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>, -+ <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>, -+ <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>; -+ msi-controller; -+ device_type = "pci"; -+ starfive,stg-syscon = <&stg_syscon>; -+ bus-range = <0x0 0xff>; -+ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, -+ <&stgcrg JH7110_STGCLK_PCIE0_TL>, -+ <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>, -+ <&stgcrg JH7110_STGCLK_PCIE0_APB>; -+ clock-names = "noc", "tl", "axi_mst0", "apb"; -+ resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>, -+ <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>, -+ <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>, -+ <&stgcrg JH7110_STGRST_PCIE0_BRG>, -+ <&stgcrg JH7110_STGRST_PCIE0_CORE>, -+ <&stgcrg JH7110_STGRST_PCIE0_APB>; -+ reset-names = "mst0", "slv0", "slv", "brg", -+ "core", "apb"; -+ status = "disabled"; -+ -+ pcie_intc0: interrupt-controller { -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ -+ pcie1: pcie@9c0000000 { -+ compatible = "starfive,jh7110-pcie"; -+ reg = <0x9 0xc0000000 0x0 0x1000000>, -+ <0x0 0x2c000000 0x0 0x100000>; -+ reg-names = "cfg", "apb"; -+ linux,pci-domain = <1>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>, -+ <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>; -+ interrupts = <57>; -+ interrupt-map-mask = <0x0 0x0 0x0 0x7>; -+ interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>, -+ <0x0 0x0 0x0 0x2 &pcie_intc1 0x2>, -+ <0x0 0x0 0x0 0x3 &pcie_intc1 0x3>, -+ <0x0 0x0 0x0 0x4 &pcie_intc1 0x4>; -+ msi-controller; -+ device_type = "pci"; -+ starfive,stg-syscon = <&stg_syscon>; -+ bus-range = <0x0 0xff>; -+ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, -+ <&stgcrg JH7110_STGCLK_PCIE1_TL>, -+ <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>, -+ <&stgcrg JH7110_STGCLK_PCIE1_APB>; -+ clock-names = "noc", "tl", "axi_mst0", "apb"; -+ resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>, -+ <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>, -+ <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>, -+ <&stgcrg JH7110_STGRST_PCIE1_BRG>, -+ <&stgcrg JH7110_STGRST_PCIE1_CORE>, -+ <&stgcrg JH7110_STGRST_PCIE1_APB>; -+ reset-names = "mst0", "slv0", "slv", "brg", -+ "core", "apb"; -+ status = "disabled"; -+ -+ pcie_intc1: interrupt-controller { -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; - }; - }; --- -cgit 1.2.3-korg - -From patchwork Tue Feb 27 10:35:21 2024 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Minda Chen -X-Patchwork-Id: 13573530 -Return-Path: - -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -Received: from bombadil.infradead.org (bombadil.infradead.org - [198.137.202.133]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by smtp.lore.kernel.org (Postfix) with ESMTPS id 13397C54798 - for ; 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Tue, 27 Feb 2024 10:35:52 +0000 -From: Minda Chen -To: Conor Dooley , - =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , - Rob Herring , Bjorn Helgaas , - Lorenzo Pieralisi , - Thomas Gleixner , - Daire McNamara , - Emil Renner Berthing , - Krzysztof Kozlowski -Cc: devicetree@vger.kernel.org, - linux-kernel@vger.kernel.org, - linux-riscv@lists.infradead.org, - linux-pci@vger.kernel.org, - Paul Walmsley , - Palmer Dabbelt , - Albert Ou , - Philipp Zabel , - Mason Huo , - Leyfoon Tan , - Kevin Xie , - Minda Chen -Subject: [PATCH v15,RESEND 22/23] PCI: starfive: Offload the NVMe timeout - workaround to host drivers. -Date: Tue, 27 Feb 2024 18:35:21 +0800 -Message-Id: <20240227103522.80915-23-minda.chen@starfivetech.com> -X-Mailer: git-send-email 2.17.1 -In-Reply-To: <20240227103522.80915-1-minda.chen@starfivetech.com> -References: <20240227103522.80915-1-minda.chen@starfivetech.com> -X-ClientProxiedBy: NT0PR01CA0003.CHNPR01.prod.partner.outlook.cn - (2406:e500:c510::15) To SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn - (2406:e500:c311:25::15) -MIME-Version: 1.0 -X-MS-PublicTrafficType: Email -X-MS-TrafficTypeDiagnostic: SHXPR01MB0863:EE_ -X-MS-Office365-Filtering-Correlation-Id: e8c49661-21f3-486e-017e-08dc377fdef2 -X-MS-Exchange-SenderADCheck: 1 -X-Microsoft-Antispam: BCL:0; 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If the -NVMe completion update later than the MSI, an NVMe IRQ handle will miss. - -As a workaround, we will wait a while before going to the generic -handle here. - -Verified with NVMe SSD, USB SSD, R8169 NIC. -The performance are stable and even higher after this patch. - -Signed-off-by: Kevin Xie -Signed-off-by: Minda Chen ---- - drivers/pci/controller/plda/pcie-plda-host.c | 12 ++++++++++++ - drivers/pci/controller/plda/pcie-plda.h | 1 + - drivers/pci/controller/plda/pcie-starfive.c | 1 + - 3 files changed, 14 insertions(+) - -diff --git a/drivers/pci/controller/plda/pcie-plda-host.c b/drivers/pci/controller/plda/pcie-plda-host.c -index a18923d7cea6..9e077ddf45c0 100644 ---- a/drivers/pci/controller/plda/pcie-plda-host.c -+++ b/drivers/pci/controller/plda/pcie-plda-host.c -@@ -13,6 +13,7 @@ - #include - #include - #include -+#include - - #include "pcie-plda.h" - -@@ -44,6 +45,17 @@ static void plda_handle_msi(struct irq_desc *desc) - bridge_base_addr + ISTATUS_LOCAL); - status = readl_relaxed(bridge_base_addr + ISTATUS_MSI); - for_each_set_bit(bit, &status, msi->num_vectors) { -+ /* -+ * As the Starfive JH7110 hardware can't keep two -+ * inbound post write in order all the time, such as -+ * MSI messages and NVMe completions. -+ * If the NVMe completion update later than the MSI, -+ * an NVMe IRQ handle will miss. -+ * As a workaround, we will wait a while before -+ * going to the generic handle here. -+ */ -+ if (port->msi_quirk_delay_us) -+ udelay(port->msi_quirk_delay_us); - ret = generic_handle_domain_irq(msi->dev_domain, bit); - if (ret) - dev_err_ratelimited(dev, "bad MSI IRQ %d\n", -diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h -index 04e385758a2f..feccf285dfe8 100644 ---- a/drivers/pci/controller/plda/pcie-plda.h -+++ b/drivers/pci/controller/plda/pcie-plda.h -@@ -186,6 +186,7 @@ struct plda_pcie_rp { - int msi_irq; - int intx_irq; - int num_events; -+ u16 msi_quirk_delay_us; - }; - - struct plda_event { -diff --git a/drivers/pci/controller/plda/pcie-starfive.c b/drivers/pci/controller/plda/pcie-starfive.c -index 9bb9f0e29565..5cfc30572b7f 100644 ---- a/drivers/pci/controller/plda/pcie-starfive.c -+++ b/drivers/pci/controller/plda/pcie-starfive.c -@@ -391,6 +391,7 @@ static int starfive_pcie_probe(struct platform_device *pdev) - - plda->host_ops = &sf_host_ops; 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In the function, the cpu_root clock -should be operated by saving its current parent and setting a new safe -parent (osc clock) before setting the PLL0 clock rate. After setting PLL0 -rate, it should be switched back to the original parent clock. - -Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC") -Signed-off-by: Xingyu Wu -Reviewed-by: Emil Renner Berthing ---- - .../clk/starfive/clk-starfive-jh7110-sys.c | 31 ++++++++++++++++++- - drivers/clk/starfive/clk-starfive-jh71x0.h | 2 ++ - 2 files changed, 32 insertions(+), 1 deletion(-) - -diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c -index 8f5e5abfa178..dafa3ae71751 100644 ---- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c -+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c -@@ -385,6 +385,32 @@ int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv, - } - EXPORT_SYMBOL_GPL(jh7110_reset_controller_register); - -+/* -+ * This clock notifier is called when the rate of PLL0 clock is to be changed. -+ * The cpu_root clock should save the curent parent clock and swicth its parent -+ * clock to osc before PLL0 rate will be changed. Then swicth its parent clock -+ * back after the PLL0 rate is completed. -+ */ -+static int jh7110_pll0_clk_notifier_cb(struct notifier_block *nb, -+ unsigned long action, void *data) -+{ -+ struct jh71x0_clk_priv *priv = container_of(nb, struct jh71x0_clk_priv, pll_clk_nb); -+ struct clk *cpu_root = priv->reg[JH7110_SYSCLK_CPU_ROOT].hw.clk; -+ int ret = 0; -+ -+ if (action == PRE_RATE_CHANGE) { -+ struct clk *osc = clk_get(priv->dev, "osc"); -+ -+ priv->original_clk = clk_get_parent(cpu_root); -+ ret = clk_set_parent(cpu_root, osc); -+ clk_put(osc); -+ } else if (action == POST_RATE_CHANGE) { -+ ret = clk_set_parent(cpu_root, priv->original_clk); -+ } -+ -+ return notifier_from_errno(ret); -+} -+ - static int __init jh7110_syscrg_probe(struct platform_device *pdev) - { - struct jh71x0_clk_priv *priv; -@@ -413,7 +439,10 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev) - if (IS_ERR(priv->pll[0])) - return PTR_ERR(priv->pll[0]); - } else { -- clk_put(pllclk); -+ priv->pll_clk_nb.notifier_call = jh7110_pll0_clk_notifier_cb; -+ ret = clk_notifier_register(pllclk, &priv->pll_clk_nb); -+ if (ret) -+ return ret; - priv->pll[0] = NULL; - } - -diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.h b/drivers/clk/starfive/clk-starfive-jh71x0.h -index 23e052fc1549..e3f441393e48 100644 ---- a/drivers/clk/starfive/clk-starfive-jh71x0.h -+++ b/drivers/clk/starfive/clk-starfive-jh71x0.h -@@ -114,6 +114,8 @@ struct jh71x0_clk_priv { - spinlock_t rmw_lock; - struct device *dev; - void __iomem *base; -+ struct clk *original_clk; -+ struct notifier_block pll_clk_nb; - struct clk_hw *pll[3]; - struct jh71x0_clk reg[]; - }; - -From patchwork Tue May 7 06:53:19 2024 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Xingyu Wu -X-Patchwork-Id: 13656352 -Received: from CHN02-BJS-obe.outbound.protection.partner.outlook.cn - (mail-bjschn02on2097.outbound.protection.partner.outlook.cn [139.219.17.97]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C3E413BAEF; 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- }; - -+&syscrg { -+ assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>, -+ <&pllclk JH7110_PLLCLK_PLL0_OUT>; -+ assigned-clock-rates = <500000000>, <1500000000>; -+}; -+ - &sysgpio { - i2c0_pins: i2c0-0 { - i2c-pins {