Sync 2 skylake i915 bug-fix patches with latest upstream version
This commit is contained in:
Hans de Goede
parent
7178b87593
commit
b4f8089833
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@ -1,43 +0,0 @@
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From 89b9366047f51fcef7f7e36f2b351a98326c8656 Mon Sep 17 00:00:00 2001
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From: Hans de Goede <hdegoede@redhat.com>
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Date: Tue, 12 Jul 2016 22:40:01 +0200
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Subject: [PATCH] Revert "ALSA: hda - remove controller dependency on i915
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power well for SKL"
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This reverts commit 03b135cebc47d75ea2dc346770374ab741966955.
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---
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sound/pci/hda/hda_intel.c | 4 +++-
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sound/pci/hda/patch_hdmi.c | 2 +-
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2 files changed, 4 insertions(+), 2 deletions(-)
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diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
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index e320c44..290d60f 100644
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--- a/sound/pci/hda/hda_intel.c
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+++ b/sound/pci/hda/hda_intel.c
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@@ -361,7 +361,9 @@ enum {
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#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
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((pci)->device == 0x0c0c) || \
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((pci)->device == 0x0d0c) || \
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- ((pci)->device == 0x160c))
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+ ((pci)->device == 0x160c) || \
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+ ((pci)->device == 0xa170) || \
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+ ((pci)->device == 0x9d70))
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#define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170)
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#define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70)
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diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c
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index d0d5ad8..9203da1 100644
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--- a/sound/pci/hda/patch_hdmi.c
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+++ b/sound/pci/hda/patch_hdmi.c
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@@ -2379,7 +2379,7 @@ static int patch_i915_hsw_hdmi(struct hda_codec *codec)
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/* For Haswell/Broadwell, the controller is also in the power well and
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* can cover the codec power request, and so need not set this flag.
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*/
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- if (!is_haswell(codec) && !is_broadwell(codec))
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+ if (!is_haswell(codec) && !is_broadwell(codec) && !is_skylake(codec))
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codec->core.link_power_control = 1;
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codec->patch_ops.set_power_state = haswell_set_power_state;
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--
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2.7.4
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@ -0,0 +1,64 @@
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From 74f829a6e44fe217b6161f8935524fc807be0648 Mon Sep 17 00:00:00 2001
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From: Chris Wilson <chris@chris-wilson.co.uk>
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Date: Sat, 9 Jul 2016 11:01:20 +0100
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Subject: [PATCH] drm/i915: Acquire audio powerwell for HD-Audio registers
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On Haswell/Broadwell, the HD-Audio block is inside the HDMI/display
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power well and so the sna-hda audio codec acquires the display power
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well while it is operational. However, Skylake separates the powerwells
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again, but yet we still need the audio powerwell to setup the registers.
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(But then the hardware uses those registers even while powered off???)
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v2: Grab both rpm wakelock and audio wakelock
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Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96214
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Fixes: 03b135cebc47 "ALSA: hda - remove dependency on i915 power well for SKL")
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Cc: Libin Yang <libin.yang@intel.com>
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Cc: Takashi Iwai <tiwai@suse.de>
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Cc: Marius Vlad <marius.c.vlad@intel.com>
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---
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drivers/gpu/drm/i915/intel_audio.c | 6 ++++++
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1 file changed, 6 insertions(+)
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diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
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index 5d5f6bc10e85..948a7a52e3f8 100644
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--- a/drivers/gpu/drm/i915/intel_audio.c
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+++ b/drivers/gpu/drm/i915/intel_audio.c
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@@ -600,6 +600,8 @@ static void i915_audio_component_codec_wake_override(struct device *dev,
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if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv))
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return;
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+ i915_audio_component_get_power(dev);
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+
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/*
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* Enable/disable generating the codec wake signal, overriding the
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* internal logic to generate the codec wake to controller.
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@@ -615,6 +617,8 @@ static void i915_audio_component_codec_wake_override(struct device *dev,
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I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
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usleep_range(1000, 1500);
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}
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+
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+ i915_audio_component_put_power(dev);
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}
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/* Get CDCLK in kHz */
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@@ -648,6 +652,7 @@ static int i915_audio_component_sync_audio_rate(struct device *dev,
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!IS_HASWELL(dev_priv))
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return 0;
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+ i915_audio_component_get_power(dev);
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mutex_lock(&dev_priv->av_mutex);
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/* 1. get the pipe */
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intel_encoder = dev_priv->dig_port_map[port];
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@@ -698,6 +703,7 @@ static int i915_audio_component_sync_audio_rate(struct device *dev,
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unlock:
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mutex_unlock(&dev_priv->av_mutex);
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+ i915_audio_component_put_power(dev);
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return err;
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}
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--
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2.8.1
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@ -1,230 +0,0 @@
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From 5fc9d375bac02e054fcaaf14a06bebc6c7118008 Mon Sep 17 00:00:00 2001
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From: "cpaul@redhat.com" <cpaul@redhat.com>
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Date: Tue, 12 Jul 2016 13:36:03 -0400
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Subject: [PATCH] drm/i915/skl: Add support for the SAGV, fix underrun hangs
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Since the watermark calculations for Skylake are still broken, we're apt
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to hitting underruns very easily under multi-monitor configurations.
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While it would be lovely if this was fixed, it's not. Another problem
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that's been coming from this however, is the mysterious issue of
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underruns causing full system hangs. An easy way to reproduce this with
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a skylake system:
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- Get a laptop with a skylake GPU, and hook up two external monitors to
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it
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- Move the cursor from the built-in LCD to one of the external displays
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as quickly as you can
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- You'll get a few pipe underruns, and eventually the entire system will
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just freeze.
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After doing a lot of investigation and reading through the bspec, I
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found the existence of the SAGV, which is responsible for adjusting the
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system agent voltage and clock frequencies depending on how much power
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we need. According to the bspec:
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"The display engine access to system memory is blocked during the
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adjustment time. SAGV defaults to enabled. Software must use the
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GT-driver pcode mailbox to disable SAGV when the display engine is not
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able to tolerate the blocking time."
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The rest of the bspec goes on to explain that software can simply leave
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the SAGV enabled, and disable it when we use interlaced pipes/have more
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then one pipe active.
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Sure enough, with this patchset the system hangs resulting from pipe
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underruns on Skylake have completely vanished on my T460s. Additionally,
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the bspec mentions turning off the SAGV with more then one pipe enabled
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as a workaround for display underruns. While this patch doesn't entirely
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fix that, it looks like it does improve the situation a little bit so
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it's likely this is going to be required to make watermarks on Skylake
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fully functional.
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Changes since v2:
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- Really apply minor style nitpicks to patch this time
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Changes since v1:
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- Added comments about this probably being one of the requirements to
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fixing Skylake's watermark issues
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- Minor style nitpicks from Matt Roper
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- Disable these functions on Broxton, since it doesn't have an SAGV
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Cc: Matt Roper <matthew.d.roper@intel.com>
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Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
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Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
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Signed-off-by: Lyude <cpaul@redhat.com>
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Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
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---
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drivers/gpu/drm/i915/i915_drv.h | 2 +
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drivers/gpu/drm/i915/i915_reg.h | 5 ++
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drivers/gpu/drm/i915/intel_pm.c | 110 ++++++++++++++++++++++++++++++++++++++++
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3 files changed, 117 insertions(+)
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diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
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index 608f8e44f353..274b57ac1a91 100644
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--- a/drivers/gpu/drm/i915/i915_drv.h
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+++ b/drivers/gpu/drm/i915/i915_drv.h
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@@ -1942,6 +1942,8 @@ struct drm_i915_private {
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struct i915_suspend_saved_registers regfile;
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struct vlv_s0ix_state vlv_s0ix_state;
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+ bool skl_sagv_enabled;
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+
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struct {
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/*
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* Raw watermark latency values:
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diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
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index b407411e31ba..9472949e8442 100644
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--- a/drivers/gpu/drm/i915/i915_reg.h
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+++ b/drivers/gpu/drm/i915/i915_reg.h
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@@ -7094,6 +7094,11 @@ enum skl_disp_power_wells {
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#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
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#define DISPLAY_IPS_CONTROL 0x19
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#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
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+#define GEN9_PCODE_SAGV_CONTROL 0x21
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+#define GEN9_SAGV_DISABLE 0x0
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+#define GEN9_SAGV_LOW_FREQ 0x1
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+#define GEN9_SAGV_HIGH_FREQ 0x2
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+#define GEN9_SAGV_DYNAMIC_FREQ 0x3
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#define GEN6_PCODE_DATA _MMIO(0x138128)
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#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
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#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
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diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
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index f764d284e6a0..439a38b08760 100644
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--- a/drivers/gpu/drm/i915/intel_pm.c
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+++ b/drivers/gpu/drm/i915/intel_pm.c
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@@ -2847,6 +2847,109 @@ skl_wm_plane_id(const struct intel_plane *plane)
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}
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static void
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+skl_sagv_get_hw_state(struct drm_i915_private *dev_priv)
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+{
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+ u32 temp;
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+ int ret;
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+
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+ if (IS_BROXTON(dev_priv))
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+ return;
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+
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+ mutex_lock(&dev_priv->rps.hw_lock);
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+ ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL, &temp);
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+ mutex_unlock(&dev_priv->rps.hw_lock);
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+
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+ if (!ret) {
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+ dev_priv->skl_sagv_enabled = !!(temp & GEN9_SAGV_DYNAMIC_FREQ);
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+ } else {
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+ /*
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+ * If for some reason we can't access the SAGV state, follow
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+ * the bspec and assume it's enabled
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+ */
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+ DRM_ERROR("Failed to get SAGV state, assuming enabled\n");
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+ dev_priv->skl_sagv_enabled = true;
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+ }
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+}
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+
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+/*
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+ * SAGV dynamically adjusts the system agent voltage and clock frequencies
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+ * depending on power and performance requirements. The display engine access
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+ * to system memory is blocked during the adjustment time. Having this enabled
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+ * in multi-pipe configurations can cause issues (such as underruns causing
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+ * full system hangs), and the bspec also suggests that software disable it
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+ * when more then one pipe is enabled.
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+ */
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+static int
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+skl_enable_sagv(struct drm_i915_private *dev_priv)
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+{
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+ int ret;
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+
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+ if (IS_BROXTON(dev_priv))
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+ return 0;
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+ if (dev_priv->skl_sagv_enabled)
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+ return 0;
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+
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+ mutex_lock(&dev_priv->rps.hw_lock);
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+ DRM_DEBUG_KMS("Enabling the SAGV\n");
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+
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+ ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
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+ GEN9_SAGV_DYNAMIC_FREQ);
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+ if (!ret)
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+ dev_priv->skl_sagv_enabled = true;
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+ else
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+ DRM_ERROR("Failed to enable the SAGV\n");
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+
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+ /* We don't need to wait for SAGV when enabling */
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+ mutex_unlock(&dev_priv->rps.hw_lock);
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+ return ret;
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+}
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+
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+static int
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+skl_disable_sagv(struct drm_i915_private *dev_priv)
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+{
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+ int ret = 0;
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+ unsigned long timeout;
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+ u32 temp;
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+
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+ if (IS_BROXTON(dev_priv))
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+ return 0;
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+ if (!dev_priv->skl_sagv_enabled)
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+ return 0;
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+
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+ mutex_lock(&dev_priv->rps.hw_lock);
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+ DRM_DEBUG_KMS("Disabling the SAGV\n");
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+
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+ /* bspec says to keep retrying for at least 1 ms */
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+ timeout = jiffies + msecs_to_jiffies(1);
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+ do {
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+ ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
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+ GEN9_SAGV_DISABLE);
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+ if (ret) {
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+ DRM_ERROR("Failed to disable the SAGV\n");
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+ goto out;
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+ }
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+
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+ ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL,
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+ &temp);
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+ if (ret) {
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+ DRM_ERROR("Failed to check the status of the SAGV\n");
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+ goto out;
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+ }
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+ } while (!(temp & 0x1) && jiffies < timeout);
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+
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+ if (temp & 0x1) {
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+ dev_priv->skl_sagv_enabled = false;
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+ } else {
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+ ret = -1;
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+ DRM_ERROR("Request to disable SAGV timed out\n");
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+ }
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+
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+out:
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+ mutex_unlock(&dev_priv->rps.hw_lock);
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+ return ret;
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+}
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+
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+static void
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skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
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const struct intel_crtc_state *cstate,
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struct skl_ddb_entry *alloc, /* out */
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@@ -3525,6 +3628,11 @@ static void skl_write_wm_values(struct drm_i915_private *dev_priv,
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struct drm_device *dev = dev_priv->dev;
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struct intel_crtc *crtc;
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+ if (dev_priv->active_crtcs == 1)
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+ skl_enable_sagv(dev_priv);
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+ else
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+ skl_disable_sagv(dev_priv);
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+
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for_each_intel_crtc(dev, crtc) {
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int i, level, max_level = ilk_wm_max_level(dev);
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enum pipe pipe = crtc->pipe;
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@@ -4072,6 +4180,8 @@ void skl_wm_get_hw_state(struct drm_device *dev)
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skl_plane_relative_data_rate(cstate, pstate, 1);
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}
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}
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+
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+ skl_sagv_get_hw_state(dev_priv);
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}
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static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
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--
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2.7.4
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@ -631,8 +631,7 @@ Patch835: 0001-Work-around-for-addition-of-metag-def-but-not-reloca.patch
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# https://lists.fedoraproject.org/archives/list/kernel@lists.fedoraproject.org/message/A4YCP7OGMX6JLFT5V44H57GOMAQLC3M4/
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Patch837: drm-amdgpu-Disable-RPM-helpers-while-reprobing.patch
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Patch838: drm-i915-skl-Add-support-for-the-SAGV-fix-underrun-hangs.patch
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Patch839: Revert-ALSA-hda-remove-controller-dependency-on-i915.patch
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Patch838: drm-i915-Acquire-audio-powerwell-for-HD-Audio-regist.patch
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#CVE-2016-6136 rhbz 1353533 1353534
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Patch841: audit-fix-a-double-fetch-in-audit_log_single_execve_arg.patch
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@ -2175,6 +2174,10 @@ fi
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#
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#
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%changelog
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* Tue Aug 2 2016 Hans de Goede <jwrdegoede@fedoraproject.org>
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- Sync skylake hdaudio __unclaimed_reg WARN_ON fix with latest upstream version
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- Drop drm-i915-skl-Add-support-for-the-SAGV-fix-underrun-hangs.patch for now
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* Thu Jul 28 2016 Josh Boyer <jwboyer@fedoraproject.org>
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- CVE-2016-5412 powerpc: kvm: Infinite loop in HV mode (rhbz 1349916 1361040)
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