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Linux v4.16.4

This commit is contained in:
Jeremy Cline 2018-04-24 11:48:55 -04:00
parent 279f39904e
commit 83209239d1
No known key found for this signature in database
GPG Key ID: 9223308FA9B246DB
5 changed files with 6 additions and 157 deletions
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56
arm-clk-bcm2835-hdmi-fixes.patch
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@ -1,56 +0,0 @@
From patchwork Thu Feb 8 13:43:37 2018
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [3/4] clk: bcm2835: De-assert/assert PLL reset signal when appropriate
From: Boris Brezillon <boris.brezillon@bootlin.com>
X-Patchwork-Id: 10207157
Message-Id: <20180208134338.24590-3-boris.brezillon@bootlin.com>
To: Florian Fainelli <f.fainelli@gmail.com>, Ray Jui <rjui@broadcom.com>,
Scott Branden <sbranden@broadcom.com>,
bcm-kernel-feedback-list@broadcom.com,
Stephen Warren <swarren@wwwdotorg.org>,
Lee Jones <lee@kernel.org>, Eric Anholt <eric@anholt.net>,
linux-rpi-kernel@lists.infradead.org,
Mike Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>, linux-clk@vger.kernel.org
Cc: Boris Brezillon <boris.brezillon@bootlin.com>, stable@vger.kernel.org
Date: Thu, 8 Feb 2018 14:43:37 +0100
In order to enable a PLL, not only the PLL has to be powered up and
locked, but you also have to de-assert the reset signal. The last part
was missing. Add it so PLLs that were not enabled by the FW/bootloader
can be enabled from Linux.
Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks")
Cc: <stable@vger.kernel.org>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
---
drivers/clk/bcm/clk-bcm2835.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index a07f6451694a..6c5d4a8e426c 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -602,6 +602,9 @@ static void bcm2835_pll_off(struct clk_hw *hw)
const struct bcm2835_pll_data *data = pll->data;
spin_lock(&cprman->regs_lock);
+ cprman_write(cprman, data->a2w_ctrl_reg,
+ cprman_read(cprman, data->a2w_ctrl_reg) &
+ ~A2W_PLL_CTRL_PRST_DISABLE);
cprman_write(cprman, data->cm_ctrl_reg,
cprman_read(cprman, data->cm_ctrl_reg) |
CM_PLL_ANARST);
@@ -640,6 +643,10 @@ static int bcm2835_pll_on(struct clk_hw *hw)
cpu_relax();
}
+ cprman_write(cprman, data->a2w_ctrl_reg,
+ cprman_read(cprman, data->a2w_ctrl_reg) |
+ A2W_PLL_CTRL_PRST_DISABLE);
+
return 0;
}

43
bcm283x-clk-audio-fixes.patch
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@ -1,46 +1,3 @@
From aa964d59aab2cb04bc011ffd370822ac79f82a0b Mon Sep 17 00:00:00 2001
From: Boris Brezillon <boris.brezillon@bootlin.com>
Date: Wed, 7 Mar 2018 15:39:17 +0100
Subject: [PATCH] clk: bcm2835: De-assert/assert PLL reset signal when
appropriate
In order to enable a PLL, not only the PLL has to be powered up and
locked, but you also have to de-assert the reset signal. The last part
was missing. Add it so PLLs that were not enabled by the FW/bootloader
can be enabled from Linux.
Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks")
Cc: <stable@vger.kernel.org>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
---
drivers/clk/bcm/clk-bcm2835.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index a07f6451694a..6c5d4a8e426c 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -602,6 +602,9 @@ static void bcm2835_pll_off(struct clk_hw *hw)
const struct bcm2835_pll_data *data = pll->data;
spin_lock(&cprman->regs_lock);
+ cprman_write(cprman, data->a2w_ctrl_reg,
+ cprman_read(cprman, data->a2w_ctrl_reg) &
+ ~A2W_PLL_CTRL_PRST_DISABLE);
cprman_write(cprman, data->cm_ctrl_reg,
cprman_read(cprman, data->cm_ctrl_reg) |
CM_PLL_ANARST);
@@ -640,6 +643,10 @@ static int bcm2835_pll_on(struct clk_hw *hw)
cpu_relax();
}
+ cprman_write(cprman, data->a2w_ctrl_reg,
+ cprman_read(cprman, data->a2w_ctrl_reg) |
+ A2W_PLL_CTRL_PRST_DISABLE);
+
return 0;
}
From 1b6867ee05d84cc6ec23b5ec0b78684187d3190a Mon Sep 17 00:00:00 2001
From: Boris Brezillon <boris.brezillon@bootlin.com>
Date: Wed, 7 Mar 2018 15:41:14 +0100

7
kernel.spec
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@ -42,7 +42,7 @@ Summary: The Linux kernel
# For non-released -rc kernels, this will be appended after the rcX and
# gitX tags, so a 3 here would become part of release "0.rcX.gitX.3"
#
%global baserelease 301
%global baserelease 300
%global fedora_build %{baserelease}
# base_sublevel is the kernel version we're starting with and patching
@ -54,7 +54,7 @@ Summary: The Linux kernel
%if 0%{?released_kernel}
# Do we have a -stable update to apply?
%define stable_update 3
%define stable_update 4
# Set rpm version accordingly
%if 0%{?stable_update}
%define stablerev %{stable_update}
@ -1913,6 +1913,9 @@ fi
#
#
%changelog
* Tue Apr 24 2018 Jeremy Cline <jeremy@jcline.org> - 4.16.4-300
- Linux v4.16.4
* Sun Apr 22 2018 Peter Robinson <pbrobinson@fedoraproject.org> - 4.16.3-301
- Add quirk patch to fix X-Gene 1 console on HP m400/Mustang (RHBZ 1531140)
- Add fixes for Marvell a37xx EspressoBin

55
mvebu-a37xx-fixes.patch
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@ -60,61 +60,6 @@ index 750e5645dc85..f503fab1e268 100644
}
spin_unlock_irqrestore(&port->lock, flags);
From patchwork Wed Apr 4 14:44:44 2018
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: cpufreq: armada-37xx: Fix clock leak
From: Gregory CLEMENT <gregory.clement@bootlin.com>
X-Patchwork-Id: 10322649
Message-Id: <20180404144444.4142-1-gregory.clement@bootlin.com>
To: "Rafael J. Wysocki" <rjw@rjwysocki.net>,
Viresh Kumar <viresh.kumar@linaro.org>, linux-pm@vger.kernel.org
Cc: Andrew Lunn <andrew@lunn.ch>, Jason Cooper <jason@lakedaemon.net>,
Hua Jing <jinghua@marvell.com>,
Antoine Tenart <antoine.tenart@bootlin.com>,
Gregory CLEMENT <gregory.clement@bootlin.com>, stable@vger.kernel.org,
Maxime Chevallier <maxime.chevallier@bootlin.com>,
Nadav Haklai <nadavh@marvell.com>, Victor Gu <xigu@marvell.com>,
Neta Zur Hershkovits <neta@marvell.com>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
=?UTF-8?q?Miqu=C3=A8l=20Raynal?= <miquel.raynal@bootlin.com>,
Marcin Wojtas <mw@semihalf.com>, Wilson Ding <dingwei@marvell.com>,
linux-arm-kernel@lists.infradead.org,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Date: Wed, 4 Apr 2018 16:44:44 +0200
There was no clk_put() balancing the clk_get(). This commit fixes it.
Fixes: 92ce45fb875d ("cpufreq: Add DVFS support for Armada 37xx")
Cc: <stable@vger.kernel.org>
Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
---
drivers/cpufreq/armada-37xx-cpufreq.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/cpufreq/armada-37xx-cpufreq.c b/drivers/cpufreq/armada-37xx-cpufreq.c
index c6ebc88a7d8d..72a2975499db 100644
--- a/drivers/cpufreq/armada-37xx-cpufreq.c
+++ b/drivers/cpufreq/armada-37xx-cpufreq.c
@@ -202,6 +202,7 @@ static int __init armada37xx_cpufreq_driver_init(void)
cur_frequency = clk_get_rate(clk);
if (!cur_frequency) {
dev_err(cpu_dev, "Failed to get clock rate for CPU\n");
+ clk_put(clk);
return -EINVAL;
}
@@ -210,6 +211,7 @@ static int __init armada37xx_cpufreq_driver_init(void)
return -EINVAL;
armada37xx_cpufreq_dvfs_setup(nb_pm_base, clk, dvfs->divider);
+ clk_put(clk);
for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
load_lvl++) {
From patchwork Sun Mar 25 19:57:36 2018
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0

2
sources
View File

@ -1,2 +1,2 @@
SHA512 (linux-4.16.tar.xz) = ab47849314b177d0eec9dbf261f33972b0d89fb92fb0650130ffa7abc2f36c0fab2d06317dc1683c51a472a9a631573a9b1e7258d6281a2ee189897827f14662
SHA512 (patch-4.16.3.xz) = 7c7c2c090d7375a923524d88f86a714576321094de94bcfd78d467b78c3b933c2cdb4863db24b0091b28f78ae10a5d4e112c3d150998d552d29e737f043e5fa8
SHA512 (patch-4.16.4.xz) = caa9726e0c9ad4da4dbcebb6b47f08e6575d30f050e7d6087018fae932c0c706e9a03d4b703dd49bc46bc21df08b5c7dff37ac5bb6522d6a6ed3d3b10712e9eb