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add e1000e workaround for packet drop on 82579 at 100Mbps (rhbz 713315)

This commit is contained in:
Dave Jones 2011-10-11 11:12:15 -04:00
parent 71ac22df47
commit 7ba24c33e7
2 changed files with 68 additions and 0 deletions
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5
kernel.spec
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@ -602,6 +602,7 @@ Patch540: x86-pci-reduce-severity-of-host-bridge-window-conflict-warnings.patch
Patch610: hda_intel-prealloc-4mb-dmabuffer.patch
Patch700: linux-2.6-e1000-ich9-montevina.patch
Patch701: net-3-4-e1000e-workaround-for-packet-drop-on-82579-at-100Mbps.patch
Patch800: linux-2.6-crash-driver.patch
@ -1191,6 +1192,7 @@ ApplyPatch linux-2.6-crash-driver.patch
# Hack e1000e to work on Montevina SDV
ApplyPatch linux-2.6-e1000-ich9-montevina.patch
ApplyPatch net-3-4-e1000e-workaround-for-packet-drop-on-82579-at-100Mbps.patch
# crypto/
@ -1891,6 +1893,9 @@ fi
# and build.
%changelog
* Tue Oct 11 2011 Dave Jones <davej@redhat.com>
- add e1000e workaround for packet drop on 82579 at 100Mbps (rhbz 713315)
* Thu Oct 06 2011 Josh Boyer <jwboyer@redhat.com>
- Add patch to fix base frequency check for Ricoh e823 devices (rhbz 722509)

63
net-3-4-e1000e-workaround-for-packet-drop-on-82579-at-100Mbps.patch Normal file
View File

@ -0,0 +1,63 @@
http://patchwork.ozlabs.org/patch/109926/
From: Bruce Allan <bruce.w.allan@intel.com>
The MAC can drop short packets when the PHY detects noise on the line at
100Mbps due to a timing issue. Workaround the issue by increasing the PLL
counter so the PHY properly recognizes the synchronization pattern from the
MAC.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
---
drivers/net/e1000e/ich8lan.c | 19 ++++++++++++++-----
1 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c
index 7525e37..46a5277 100644
--- a/drivers/net/e1000e/ich8lan.c
+++ b/drivers/net/e1000e/ich8lan.c
@@ -137,8 +137,9 @@
#define HV_PM_CTRL PHY_REG(770, 17)
/* PHY Low Power Idle Control */
-#define I82579_LPI_CTRL PHY_REG(772, 20)
-#define I82579_LPI_CTRL_ENABLE_MASK 0x6000
+#define I82579_LPI_CTRL PHY_REG(772, 20)
+#define I82579_LPI_CTRL_ENABLE_MASK 0x6000
+#define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT 0x80
/* EMI Registers */
#define I82579_EMI_ADDR 0x10
@@ -1670,6 +1671,7 @@ static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
s32 ret_val = 0;
u16 status_reg = 0;
u32 mac_reg;
+ u16 phy_reg;
if (hw->mac.type != e1000_pch2lan)
goto out;
@@ -1684,12 +1686,19 @@ static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
mac_reg = er32(FEXTNVM4);
mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
- if (status_reg & HV_M_STATUS_SPEED_1000)
+ ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
+ if (ret_val)
+ goto out;
+
+ if (status_reg & HV_M_STATUS_SPEED_1000) {
mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
- else
+ phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
+ } else {
mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
-
+ phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
+ }
ew32(FEXTNVM4, mac_reg);
+ ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
}
out: