Remove obsolete patch (merged upstream)
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
This commit is contained in:
parent
09074c7b2c
commit
7a2b40f086
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@ -1,584 +0,0 @@
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From 8c904b6e4769270314d65b5f6fc2e514bbd34b50 Mon Sep 17 00:00:00 2001
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From: Fedora Kernel Team <kernel-team@fedoraproject.org>
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Date: Thu, 19 Dec 2019 19:34:50 +0000
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Subject: [PATCH] riscv: change CSR M/S defines to use "X" for prefix
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---
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arch/riscv/include/asm/csr.h | 70 +++++++++++++++----------------
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arch/riscv/include/asm/irqflags.h | 12 +++---
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arch/riscv/include/asm/ptrace.h | 2 +-
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arch/riscv/kernel/entry.S | 32 +++++++-------
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arch/riscv/kernel/fpu.S | 8 ++--
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arch/riscv/kernel/head.S | 14 +++----
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arch/riscv/kernel/irq.c | 6 +--
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arch/riscv/kernel/process.c | 4 +-
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arch/riscv/kernel/smp.c | 2 +-
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arch/riscv/kernel/traps.c | 6 +--
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arch/riscv/lib/uaccess.S | 12 +++---
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arch/riscv/mm/fault.c | 2 +-
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drivers/clocksource/timer-riscv.c | 8 ++--
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drivers/irqchip/irq-sifive-plic.c | 6 +--
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14 files changed, 92 insertions(+), 92 deletions(-)
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diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
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index 0a62d2d..21b323c 100644
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--- a/arch/riscv/include/asm/csr.h
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+++ b/arch/riscv/include/asm/csr.h
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@@ -103,45 +103,45 @@
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#define CSR_MHARTID 0xf14
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#ifdef CONFIG_RISCV_M_MODE
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-# define CSR_STATUS CSR_MSTATUS
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-# define CSR_IE CSR_MIE
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-# define CSR_TVEC CSR_MTVEC
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-# define CSR_SCRATCH CSR_MSCRATCH
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-# define CSR_EPC CSR_MEPC
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-# define CSR_CAUSE CSR_MCAUSE
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-# define CSR_TVAL CSR_MTVAL
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-# define CSR_IP CSR_MIP
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-
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-# define SR_IE SR_MIE
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-# define SR_PIE SR_MPIE
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-# define SR_PP SR_MPP
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-
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-# define IRQ_SOFT IRQ_M_SOFT
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-# define IRQ_TIMER IRQ_M_TIMER
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-# define IRQ_EXT IRQ_M_EXT
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+# define CSR_XSTATUS CSR_MSTATUS
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+# define CSR_XIE CSR_MIE
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+# define CSR_XTVEC CSR_MTVEC
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+# define CSR_XSCRATCH CSR_MSCRATCH
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+# define CSR_XEPC CSR_MEPC
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+# define CSR_XCAUSE CSR_MCAUSE
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+# define CSR_XTVAL CSR_MTVAL
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+# define CSR_XIP CSR_MIP
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+
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+# define SR_XIE SR_MIE
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+# define SR_XPIE SR_MPIE
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+# define SR_XPP SR_MPP
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+
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+# define IRQ_X_SOFT IRQ_M_SOFT
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+# define IRQ_X_TIMER IRQ_M_TIMER
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+# define IRQ_X_EXT IRQ_M_EXT
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#else /* CONFIG_RISCV_M_MODE */
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-# define CSR_STATUS CSR_SSTATUS
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-# define CSR_IE CSR_SIE
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-# define CSR_TVEC CSR_STVEC
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-# define CSR_SCRATCH CSR_SSCRATCH
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-# define CSR_EPC CSR_SEPC
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-# define CSR_CAUSE CSR_SCAUSE
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-# define CSR_TVAL CSR_STVAL
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-# define CSR_IP CSR_SIP
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-
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-# define SR_IE SR_SIE
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-# define SR_PIE SR_SPIE
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-# define SR_PP SR_SPP
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-
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-# define IRQ_SOFT IRQ_S_SOFT
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-# define IRQ_TIMER IRQ_S_TIMER
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-# define IRQ_EXT IRQ_S_EXT
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+# define CSR_XSTATUS CSR_SSTATUS
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+# define CSR_XIE CSR_SIE
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+# define CSR_XTVEC CSR_STVEC
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+# define CSR_XSCRATCH CSR_SSCRATCH
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+# define CSR_XEPC CSR_SEPC
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+# define CSR_XCAUSE CSR_SCAUSE
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+# define CSR_XTVAL CSR_STVAL
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+# define CSR_XIP CSR_SIP
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+
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+# define SR_XIE SR_SIE
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+# define SR_XPIE SR_SPIE
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+# define SR_XPP SR_SPP
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+
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+# define IRQ_X_SOFT IRQ_S_SOFT
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+# define IRQ_X_TIMER IRQ_S_TIMER
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+# define IRQ_X_EXT IRQ_S_EXT
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#endif /* CONFIG_RISCV_M_MODE */
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/* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */
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-#define IE_SIE (_AC(0x1, UL) << IRQ_SOFT)
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-#define IE_TIE (_AC(0x1, UL) << IRQ_TIMER)
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-#define IE_EIE (_AC(0x1, UL) << IRQ_EXT)
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+#define IE_SIE (_AC(0x1, UL) << IRQ_X_SOFT)
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+#define IE_TIE (_AC(0x1, UL) << IRQ_X_TIMER)
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+#define IE_EIE (_AC(0x1, UL) << IRQ_X_EXT)
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#ifndef __ASSEMBLY__
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diff --git a/arch/riscv/include/asm/irqflags.h b/arch/riscv/include/asm/irqflags.h
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index 08d4d6a..ba2828a 100644
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--- a/arch/riscv/include/asm/irqflags.h
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+++ b/arch/riscv/include/asm/irqflags.h
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@@ -13,31 +13,31 @@
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/* read interrupt enabled status */
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static inline unsigned long arch_local_save_flags(void)
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{
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- return csr_read(CSR_STATUS);
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+ return csr_read(CSR_XSTATUS);
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}
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/* unconditionally enable interrupts */
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static inline void arch_local_irq_enable(void)
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{
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- csr_set(CSR_STATUS, SR_IE);
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+ csr_set(CSR_XSTATUS, SR_XIE);
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}
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/* unconditionally disable interrupts */
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static inline void arch_local_irq_disable(void)
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{
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- csr_clear(CSR_STATUS, SR_IE);
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+ csr_clear(CSR_XSTATUS, SR_XIE);
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}
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/* get status and disable interrupts */
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static inline unsigned long arch_local_irq_save(void)
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{
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- return csr_read_clear(CSR_STATUS, SR_IE);
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+ return csr_read_clear(CSR_XSTATUS, SR_XIE);
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}
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/* test flags */
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static inline int arch_irqs_disabled_flags(unsigned long flags)
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{
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- return !(flags & SR_IE);
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+ return !(flags & SR_XIE);
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}
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/* test hardware interrupt enable bit */
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@@ -49,7 +49,7 @@ static inline int arch_irqs_disabled(void)
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/* set interrupt enabled status */
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static inline void arch_local_irq_restore(unsigned long flags)
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{
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- csr_set(CSR_STATUS, flags & SR_IE);
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+ csr_set(CSR_XSTATUS, flags & SR_XIE);
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}
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#endif /* _ASM_RISCV_IRQFLAGS_H */
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diff --git a/arch/riscv/include/asm/ptrace.h b/arch/riscv/include/asm/ptrace.h
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index ee49f80..507ed43 100644
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--- a/arch/riscv/include/asm/ptrace.h
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+++ b/arch/riscv/include/asm/ptrace.h
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@@ -58,7 +58,7 @@ struct pt_regs {
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#define REG_FMT "%08lx"
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#endif
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-#define user_mode(regs) (((regs)->status & SR_PP) == 0)
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+#define user_mode(regs) (((regs)->status & SR_XPP) == 0)
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/* Helpers for working with the instruction pointer */
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diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
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index e163b7b..03b3b59 100644
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--- a/arch/riscv/kernel/entry.S
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+++ b/arch/riscv/kernel/entry.S
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@@ -29,11 +29,11 @@
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* the kernel thread pointer. If we came from the kernel, the scratch
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* register will contain 0, and we should continue on the current TP.
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*/
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- csrrw tp, CSR_SCRATCH, tp
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+ csrrw tp, CSR_XSCRATCH, tp
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bnez tp, _save_context
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_restore_kernel_tpsp:
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- csrr tp, CSR_SCRATCH
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+ csrr tp, CSR_XSCRATCH
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REG_S sp, TASK_TI_KERNEL_SP(tp)
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_save_context:
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REG_S sp, TASK_TI_USER_SP(tp)
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@@ -79,11 +79,11 @@ _save_context:
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li t0, SR_SUM | SR_FS
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REG_L s0, TASK_TI_USER_SP(tp)
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- csrrc s1, CSR_STATUS, t0
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- csrr s2, CSR_EPC
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- csrr s3, CSR_TVAL
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- csrr s4, CSR_CAUSE
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- csrr s5, CSR_SCRATCH
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+ csrrc s1, CSR_XSTATUS, t0
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+ csrr s2, CSR_XEPC
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+ csrr s3, CSR_XTVAL
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+ csrr s4, CSR_XCAUSE
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+ csrr s5, CSR_XSCRATCH
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REG_S s0, PT_SP(sp)
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REG_S s1, PT_STATUS(sp)
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REG_S s2, PT_EPC(sp)
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@@ -118,8 +118,8 @@ _save_context:
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REG_L a2, PT_EPC(sp)
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REG_SC x0, a2, PT_EPC(sp)
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- csrw CSR_STATUS, a0
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- csrw CSR_EPC, a2
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+ csrw CSR_XSTATUS, a0
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+ csrw CSR_XEPC, a2
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REG_L x1, PT_RA(sp)
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REG_L x3, PT_GP(sp)
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@@ -166,7 +166,7 @@ ENTRY(handle_exception)
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* Set the scratch register to 0, so that if a recursive exception
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* occurs, the exception vector knows it came from the kernel
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*/
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- csrw CSR_SCRATCH, x0
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+ csrw CSR_XSCRATCH, x0
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/* Load the global pointer */
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.option push
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@@ -187,11 +187,11 @@ ENTRY(handle_exception)
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1:
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/*
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* Exceptions run with interrupts enabled or disabled depending on the
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- * state of SR_PIE in m/sstatus.
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+ * state of SR_XPIE in m/sstatus.
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*/
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- andi t0, s1, SR_PIE
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+ andi t0, s1, SR_XPIE
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beqz t0, 1f
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- csrs CSR_STATUS, SR_IE
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+ csrs CSR_XSTATUS, SR_XIE
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1:
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/* Handle syscalls */
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@@ -271,7 +271,7 @@ ret_from_syscall_rejected:
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ret_from_exception:
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REG_L s0, PT_STATUS(sp)
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- csrc CSR_STATUS, SR_IE
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+ csrc CSR_XSTATUS, SR_XIE
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#ifdef CONFIG_RISCV_M_MODE
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/* the MPP value is too large to be used as an immediate arg for addi */
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li t0, SR_MPP
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@@ -295,7 +295,7 @@ resume_userspace:
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* Save TP into the scratch register , so we can find the kernel data
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* structures again.
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*/
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- csrw CSR_SCRATCH, tp
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+ csrw CSR_XSCRATCH, tp
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restore_all:
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RESTORE_ALL
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@@ -323,7 +323,7 @@ work_pending:
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bnez s1, work_resched
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work_notifysig:
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/* Handle pending signals and notify-resume requests */
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- csrs CSR_STATUS, SR_IE /* Enable interrupts for do_notify_resume() */
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+ csrs CSR_XSTATUS, SR_XIE /* Enable interrupts for do_notify_resume() */
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move a0, sp /* pt_regs */
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move a1, s0 /* current_thread_info->flags */
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tail do_notify_resume
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diff --git a/arch/riscv/kernel/fpu.S b/arch/riscv/kernel/fpu.S
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index dd22054..1dade31 100644
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--- a/arch/riscv/kernel/fpu.S
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+++ b/arch/riscv/kernel/fpu.S
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@@ -23,7 +23,7 @@ ENTRY(__fstate_save)
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li a2, TASK_THREAD_F0
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add a0, a0, a2
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li t1, SR_FS
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- csrs CSR_STATUS, t1
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+ csrs CSR_XSTATUS, t1
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frcsr t0
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fsd f0, TASK_THREAD_F0_F0(a0)
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fsd f1, TASK_THREAD_F1_F0(a0)
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@@ -58,7 +58,7 @@ ENTRY(__fstate_save)
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fsd f30, TASK_THREAD_F30_F0(a0)
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fsd f31, TASK_THREAD_F31_F0(a0)
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sw t0, TASK_THREAD_FCSR_F0(a0)
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- csrc CSR_STATUS, t1
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+ csrc CSR_XSTATUS, t1
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ret
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ENDPROC(__fstate_save)
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@@ -67,7 +67,7 @@ ENTRY(__fstate_restore)
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add a0, a0, a2
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li t1, SR_FS
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lw t0, TASK_THREAD_FCSR_F0(a0)
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- csrs CSR_STATUS, t1
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+ csrs CSR_XSTATUS, t1
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fld f0, TASK_THREAD_F0_F0(a0)
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fld f1, TASK_THREAD_F1_F0(a0)
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fld f2, TASK_THREAD_F2_F0(a0)
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@@ -101,6 +101,6 @@ ENTRY(__fstate_restore)
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fld f30, TASK_THREAD_F30_F0(a0)
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fld f31, TASK_THREAD_F31_F0(a0)
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fscsr t0
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- csrc CSR_STATUS, t1
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+ csrc CSR_XSTATUS, t1
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ret
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ENDPROC(__fstate_restore)
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diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
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index 84a6f0a..71efbba 100644
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--- a/arch/riscv/kernel/head.S
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+++ b/arch/riscv/kernel/head.S
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@@ -48,8 +48,8 @@ ENTRY(_start)
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.global _start_kernel
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_start_kernel:
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/* Mask all interrupts */
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- csrw CSR_IE, zero
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- csrw CSR_IP, zero
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+ csrw CSR_XIE, zero
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+ csrw CSR_XIP, zero
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#ifdef CONFIG_RISCV_M_MODE
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/* flush the instruction cache */
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@@ -76,7 +76,7 @@ _start_kernel:
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* floating point in kernel space
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*/
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li t0, SR_FS
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- csrc CSR_STATUS, t0
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+ csrc CSR_XSTATUS, t0
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#ifdef CONFIG_SMP
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li t0, CONFIG_NR_CPUS
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@@ -134,7 +134,7 @@ relocate:
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/* Point stvec to virtual address of intruction after satp write */
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la a2, 1f
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add a2, a2, a1
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- csrw CSR_TVEC, a2
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+ csrw CSR_XTVEC, a2
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/* Compute satp for kernel page tables, but don't load it yet */
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srl a2, a0, PAGE_SHIFT
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@@ -156,7 +156,7 @@ relocate:
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1:
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/* Set trap vector to spin forever to help debug */
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la a0, .Lsecondary_park
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- csrw CSR_TVEC, a0
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+ csrw CSR_XTVEC, a0
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/* Reload the global pointer */
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.option push
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@@ -180,7 +180,7 @@ relocate:
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#ifdef CONFIG_SMP
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/* Set trap vector to spin forever to help debug */
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la a3, .Lsecondary_park
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- csrw CSR_TVEC, a3
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+ csrw CSR_XTVEC, a3
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slli a3, a0, LGREG
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la a1, __cpu_up_stack_pointer
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@@ -254,7 +254,7 @@ ENTRY(reset_regs)
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bnez t0, .Lreset_regs_done
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li t1, SR_FS
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- csrs CSR_STATUS, t1
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+ csrs CSR_XSTATUS, t1
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fmv.s.x f0, zero
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fmv.s.x f1, zero
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fmv.s.x f2, zero
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diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c
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index 3f07a91..cfbec2a 100644
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--- a/arch/riscv/kernel/irq.c
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+++ b/arch/riscv/kernel/irq.c
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@@ -23,11 +23,11 @@ asmlinkage __visible void __irq_entry do_IRQ(struct pt_regs *regs)
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irq_enter();
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switch (regs->cause & ~CAUSE_IRQ_FLAG) {
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- case IRQ_TIMER:
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+ case IRQ_X_TIMER:
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riscv_timer_interrupt();
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break;
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#ifdef CONFIG_SMP
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- case IRQ_SOFT:
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+ case IRQ_X_SOFT:
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/*
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* We only use software interrupts to pass IPIs, so if a non-SMP
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* system gets one, then we don't know what to do.
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@@ -35,7 +35,7 @@ asmlinkage __visible void __irq_entry do_IRQ(struct pt_regs *regs)
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riscv_software_interrupt();
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break;
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#endif
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- case IRQ_EXT:
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+ case IRQ_X_EXT:
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handle_arch_irq(regs);
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break;
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default:
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diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c
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index 95a3031..7d3ddb1 100644
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--- a/arch/riscv/kernel/process.c
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+++ b/arch/riscv/kernel/process.c
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@@ -65,7 +65,7 @@ void show_regs(struct pt_regs *regs)
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void start_thread(struct pt_regs *regs, unsigned long pc,
|
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unsigned long sp)
|
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{
|
||||
- regs->status = SR_PIE;
|
||||
+ regs->status = SR_XPIE;
|
||||
if (has_fpu) {
|
||||
regs->status |= SR_FS_INITIAL;
|
||||
/*
|
||||
@@ -111,7 +111,7 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
|
||||
memset(childregs, 0, sizeof(struct pt_regs));
|
||||
childregs->gp = gp;
|
||||
/* Supervisor/Machine, irqs on: */
|
||||
- childregs->status = SR_PP | SR_PIE;
|
||||
+ childregs->status = SR_XPP | SR_XPIE;
|
||||
|
||||
p->thread.ra = (unsigned long)ret_from_kernel_thread;
|
||||
p->thread.s[0] = usp; /* fn */
|
||||
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
|
||||
index eb878ab..1c95cfe 100644
|
||||
--- a/arch/riscv/kernel/smp.c
|
||||
+++ b/arch/riscv/kernel/smp.c
|
||||
@@ -116,7 +116,7 @@ static void send_ipi_single(int cpu, enum ipi_message_type op)
|
||||
static inline void clear_ipi(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_RISCV_SBI))
|
||||
- csr_clear(CSR_IP, IE_SIE);
|
||||
+ csr_clear(CSR_XIP, IE_SIE);
|
||||
else
|
||||
clint_clear_ipi(cpuid_to_hartid_map(smp_processor_id()));
|
||||
}
|
||||
diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
|
||||
index f4cad51..d8d7c4d 100644
|
||||
--- a/arch/riscv/kernel/traps.c
|
||||
+++ b/arch/riscv/kernel/traps.c
|
||||
@@ -153,9 +153,9 @@ void __init trap_init(void)
|
||||
* Set sup0 scratch register to 0, indicating to exception vector
|
||||
* that we are presently executing in the kernel
|
||||
*/
|
||||
- csr_write(CSR_SCRATCH, 0);
|
||||
+ csr_write(CSR_XSCRATCH, 0);
|
||||
/* Set the exception vector address */
|
||||
- csr_write(CSR_TVEC, &handle_exception);
|
||||
+ csr_write(CSR_XTVEC, &handle_exception);
|
||||
/* Enable all interrupts */
|
||||
- csr_write(CSR_IE, -1);
|
||||
+ csr_write(CSR_XIE, -1);
|
||||
}
|
||||
diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S
|
||||
index fecd656..f47a2ea 100644
|
||||
--- a/arch/riscv/lib/uaccess.S
|
||||
+++ b/arch/riscv/lib/uaccess.S
|
||||
@@ -18,7 +18,7 @@ ENTRY(__asm_copy_from_user)
|
||||
|
||||
/* Enable access to user memory */
|
||||
li t6, SR_SUM
|
||||
- csrs CSR_STATUS, t6
|
||||
+ csrs CSR_XSTATUS, t6
|
||||
|
||||
add a3, a1, a2
|
||||
/* Use word-oriented copy only if low-order bits match */
|
||||
@@ -47,7 +47,7 @@ ENTRY(__asm_copy_from_user)
|
||||
|
||||
3:
|
||||
/* Disable access to user memory */
|
||||
- csrc CSR_STATUS, t6
|
||||
+ csrc CSR_XSTATUS, t6
|
||||
li a0, 0
|
||||
ret
|
||||
4: /* Edge case: unalignment */
|
||||
@@ -72,7 +72,7 @@ ENTRY(__clear_user)
|
||||
|
||||
/* Enable access to user memory */
|
||||
li t6, SR_SUM
|
||||
- csrs CSR_STATUS, t6
|
||||
+ csrs CSR_XSTATUS, t6
|
||||
|
||||
add a3, a0, a1
|
||||
addi t0, a0, SZREG-1
|
||||
@@ -94,7 +94,7 @@ ENTRY(__clear_user)
|
||||
|
||||
3:
|
||||
/* Disable access to user memory */
|
||||
- csrc CSR_STATUS, t6
|
||||
+ csrc CSR_XSTATUS, t6
|
||||
li a0, 0
|
||||
ret
|
||||
4: /* Edge case: unalignment */
|
||||
@@ -114,11 +114,11 @@ ENDPROC(__clear_user)
|
||||
/* Fixup code for __copy_user(10) and __clear_user(11) */
|
||||
10:
|
||||
/* Disable access to user memory */
|
||||
- csrs CSR_STATUS, t6
|
||||
+ csrs CSR_XSTATUS, t6
|
||||
mv a0, a2
|
||||
ret
|
||||
11:
|
||||
- csrs CSR_STATUS, t6
|
||||
+ csrs CSR_XSTATUS, t6
|
||||
mv a0, a1
|
||||
ret
|
||||
.previous
|
||||
diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c
|
||||
index cf7248e..ede89cd 100644
|
||||
--- a/arch/riscv/mm/fault.c
|
||||
+++ b/arch/riscv/mm/fault.c
|
||||
@@ -53,7 +53,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs)
|
||||
goto vmalloc_fault;
|
||||
|
||||
/* Enable interrupts if they were enabled in the parent context. */
|
||||
- if (likely(regs->status & SR_PIE))
|
||||
+ if (likely(regs->status & SR_XPIE))
|
||||
local_irq_enable();
|
||||
|
||||
/*
|
||||
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
|
||||
index 4e54856..16ed374 100644
|
||||
--- a/drivers/clocksource/timer-riscv.c
|
||||
+++ b/drivers/clocksource/timer-riscv.c
|
||||
@@ -31,7 +31,7 @@ static inline void mmio_set_timer(u64 val)
|
||||
static int riscv_clock_next_event(unsigned long delta,
|
||||
struct clock_event_device *ce)
|
||||
{
|
||||
- csr_set(CSR_IE, IE_TIE);
|
||||
+ csr_set(CSR_XIE, IE_TIE);
|
||||
if (IS_ENABLED(CONFIG_RISCV_SBI))
|
||||
sbi_set_timer(get_cycles64() + delta);
|
||||
else
|
||||
@@ -76,13 +76,13 @@ static int riscv_timer_starting_cpu(unsigned int cpu)
|
||||
ce->cpumask = cpumask_of(cpu);
|
||||
clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
|
||||
|
||||
- csr_set(CSR_IE, IE_TIE);
|
||||
+ csr_set(CSR_XIE, IE_TIE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int riscv_timer_dying_cpu(unsigned int cpu)
|
||||
{
|
||||
- csr_clear(CSR_IE, IE_TIE);
|
||||
+ csr_clear(CSR_XIE, IE_TIE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -91,7 +91,7 @@ void riscv_timer_interrupt(void)
|
||||
{
|
||||
struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event);
|
||||
|
||||
- csr_clear(CSR_IE, IE_TIE);
|
||||
+ csr_clear(CSR_XIE, IE_TIE);
|
||||
evdev->event_handler(evdev);
|
||||
}
|
||||
|
||||
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
|
||||
index 8df547d..d75c12e 100644
|
||||
--- a/drivers/irqchip/irq-sifive-plic.c
|
||||
+++ b/drivers/irqchip/irq-sifive-plic.c
|
||||
@@ -181,7 +181,7 @@ static void plic_handle_irq(struct pt_regs *regs)
|
||||
|
||||
WARN_ON_ONCE(!handler->present);
|
||||
|
||||
- csr_clear(CSR_IE, IE_EIE);
|
||||
+ csr_clear(CSR_XIE, IE_EIE);
|
||||
while ((hwirq = readl(claim))) {
|
||||
int irq = irq_find_mapping(plic_irqdomain, hwirq);
|
||||
|
||||
@@ -191,7 +191,7 @@ static void plic_handle_irq(struct pt_regs *regs)
|
||||
else
|
||||
generic_handle_irq(irq);
|
||||
}
|
||||
- csr_set(CSR_IE, IE_EIE);
|
||||
+ csr_set(CSR_XIE, IE_EIE);
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -256,7 +256,7 @@ static int __init plic_init(struct device_node *node,
|
||||
* Skip contexts other than external interrupts for our
|
||||
* privilege level.
|
||||
*/
|
||||
- if (parent.args[0] != IRQ_EXT)
|
||||
+ if (parent.args[0] != IRQ_X_EXT)
|
||||
continue;
|
||||
|
||||
hartid = plic_find_hart_id(parent.np);
|
||||
--
|
||||
2.24.1
|
||||
|
|
@ -871,9 +871,6 @@ Patch526: libertas-Fix-two-buffer-overflows-at-parsing-bss-descriptor.patch
|
|||
# https://github.com/sifive/riscv-linux/commits/dev/paulw/cpufreq-dt-aloe-v5.3-rc4
|
||||
Patch570: 0002-SiFive-Unleashed-CPUFreq.patch
|
||||
|
||||
# https://patchwork.kernel.org/patch/11301459/
|
||||
Patch574: 0001-riscv-change-CSR-M-S-defines-to-use-X-for-prefix.patch
|
||||
|
||||
# END OF PATCH DEFINITIONS
|
||||
|
||||
%endif
|
||||
|
|
Loading…
Reference in New Issue