From 74be7cda280cddb83c0d09f8d269655de210235d Mon Sep 17 00:00:00 2001 From: David Abdurachmanov Date: Mon, 27 Jun 2022 14:19:57 +0300 Subject: [PATCH] Update riscv64 configs Signed-off-by: David Abdurachmanov --- kernel-riscv64-debug-fedora.config | 8 ++++++-- kernel-riscv64-fedora.config | 8 ++++++-- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/kernel-riscv64-debug-fedora.config b/kernel-riscv64-debug-fedora.config index 15c5d96cd..b0ab6f402 100644 --- a/kernel-riscv64-debug-fedora.config +++ b/kernel-riscv64-debug-fedora.config @@ -4168,8 +4168,8 @@ CONFIG_NLS_UTF8=m CONFIG_NLS=y # CONFIG_NOA1305 is not set CONFIG_NODES_SHIFT=2 -# CONFIG_NO_HZ_FULL is not set -CONFIG_NO_HZ_IDLE=y +CONFIG_NO_HZ_FULL=y +# CONFIG_NO_HZ_IDLE is not set CONFIG_NO_HZ=y CONFIG_NOP_USB_XCEIV=m CONFIG_NORTEL_HERMES=m @@ -4824,12 +4824,16 @@ CONFIG_RIONET_TX_SIZE=128 CONFIG_RISCV_BASE_PMU=y # CONFIG_RISCV_BOOT_SPINWAIT is not set CONFIG_RISCV_ERRATA_ALTERNATIVE=y +CONFIG_RISCV_INTC=y CONFIG_RISCV_ISA_C=y CONFIG_RISCV_PLIC=y CONFIG_RISCV_PMU_LEGACY=y CONFIG_RISCV_PMU_SBI=y CONFIG_RISCV_PMU=y +CONFIG_RISCV_SBI_CPUIDLE=y # CONFIG_RISCV_SBI_V01 is not set +CONFIG_RISCV_SBI=y +CONFIG_RISCV_TIMER=y CONFIG_RMI4_CORE=m CONFIG_RMI4_F03=y CONFIG_RMI4_F11=y diff --git a/kernel-riscv64-fedora.config b/kernel-riscv64-fedora.config index 91a5dbe5e..f984f71d0 100644 --- a/kernel-riscv64-fedora.config +++ b/kernel-riscv64-fedora.config @@ -4148,8 +4148,8 @@ CONFIG_NLS_UTF8=m CONFIG_NLS=y # CONFIG_NOA1305 is not set CONFIG_NODES_SHIFT=2 -# CONFIG_NO_HZ_FULL is not set -CONFIG_NO_HZ_IDLE=y +CONFIG_NO_HZ_FULL=y +# CONFIG_NO_HZ_IDLE is not set CONFIG_NO_HZ=y CONFIG_NOP_USB_XCEIV=m CONFIG_NORTEL_HERMES=m @@ -4803,12 +4803,16 @@ CONFIG_RIONET_TX_SIZE=128 CONFIG_RISCV_BASE_PMU=y # CONFIG_RISCV_BOOT_SPINWAIT is not set CONFIG_RISCV_ERRATA_ALTERNATIVE=y +CONFIG_RISCV_INTC=y CONFIG_RISCV_ISA_C=y CONFIG_RISCV_PLIC=y CONFIG_RISCV_PMU_LEGACY=y CONFIG_RISCV_PMU_SBI=y CONFIG_RISCV_PMU=y +CONFIG_RISCV_SBI_CPUIDLE=y # CONFIG_RISCV_SBI_V01 is not set +CONFIG_RISCV_SBI=y +CONFIG_RISCV_TIMER=y CONFIG_RMI4_CORE=m CONFIG_RMI4_F03=y CONFIG_RMI4_F11=y