Remove obsolete patches

The TLB issues might have been solved within OpenSBI.
Networking for SiFive has been merged into the final v5.3.

Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
This commit is contained in:
David Abdurachmanov 2019-09-20 10:10:47 +03:00
parent 576b1ae843
commit 6fe4640c1a
Signed by: davidlt
GPG Key ID: 8B7F1DA0E2C9FDBB
3 changed files with 0 additions and 150 deletions

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@ -1,61 +0,0 @@
From 0b2b2c260e4f6d088afe7940d036d154d3076ff5 Mon Sep 17 00:00:00 2001
From: Fedora Kernel Team <kernel-team@fedoraproject.org>
Date: Sun, 25 Aug 2019 06:57:36 +0000
Subject: [PATCH 1/2] SiFive Unleashed Ethernet
---
Documentation/devicetree/bindings/net/macb.txt | 4 ++--
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 9 +++++++++
drivers/net/ethernet/cadence/macb_main.c | 2 +-
3 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt
index 63c73fa..0b61a90 100644
--- a/Documentation/devicetree/bindings/net/macb.txt
+++ b/Documentation/devicetree/bindings/net/macb.txt
@@ -15,10 +15,10 @@ Required properties:
Use "atmel,sama5d4-gem" for the GEM IP (10/100) available on Atmel sama5d4 SoCs.
Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC.
Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC.
- Use "sifive,fu540-macb" for SiFive FU540-C000 SoC.
+ Use "sifive,fu540-c000-gem" for SiFive FU540-C000 SoC.
Or the generic form: "cdns,emac".
- reg: Address and length of the register set for the device
- For "sifive,fu540-macb", second range is required to specify the
+ For "sifive,fu540-c000-gem", second range is required to specify the
address and length of the registers for GEMGXL Management block.
- interrupts: Should contain macb interrupt
- phy-mode: See ethernet.txt file in the same directory.
diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
index 93d68cb..54fc701 100644
--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
@@ -85,3 +85,12 @@
reg = <0>;
};
};
+
+&eth0 {
+ status = "okay";
+ phy-mode = "gmii";
+ phy-handle = <&phy1>;
+ phy1: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
index 5ca17e6..35b59b5 100644
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -4154,7 +4154,7 @@ static const struct of_device_id macb_dt_ids[] = {
{ .compatible = "cdns,emac", .data = &emac_config },
{ .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
{ .compatible = "cdns,zynq-gem", .data = &zynq_config },
- { .compatible = "sifive,fu540-macb", .data = &fu540_c000_config },
+ { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, macb_dt_ids);
--
2.23.0

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@ -1,80 +0,0 @@
From e168a466bde2761439bfae6ba78d7321a9a3af58 Mon Sep 17 00:00:00 2001
From: Fedora Kernel Team <kernel-team@fedoraproject.org>
Date: Sun, 25 Aug 2019 09:04:31 +0000
Subject: [PATCH] riscv: optimize tlb flush path
diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h
index 4d9bbe8..d669d87 100644
--- a/arch/riscv/include/asm/tlbflush.h
+++ b/arch/riscv/include/asm/tlbflush.h
@@ -8,6 +8,7 @@
#define _ASM_RISCV_TLBFLUSH_H
#include <linux/mm_types.h>
+#include <linux/sched.h>
#include <asm/smp.h>
/*
@@ -42,20 +43,44 @@ static inline void flush_tlb_range(struct vm_area_struct *vma,
#include <asm/sbi.h>
-static inline void remote_sfence_vma(struct cpumask *cmask, unsigned long start,
- unsigned long size)
+static void __riscv_flush_tlb(struct cpumask *cmask, unsigned long start,
+ unsigned long size)
{
struct cpumask hmask;
+ unsigned int hartid;
+ unsigned int cpuid;
cpumask_clear(&hmask);
+
+ if (!cmask) {
+ riscv_cpuid_to_hartid_mask(cpu_online_mask, &hmask);
+ goto issue_sfence;
+ }
+
+ cpuid = get_cpu();
+ if (cpumask_test_cpu(cpuid, cmask)) {
+ /* Save trap cost by issuing a local tlb flush here */
+ if ((start == 0 && size == -1) || (size > PAGE_SIZE))
+ local_flush_tlb_all();
+ else if (size == PAGE_SIZE)
+ local_flush_tlb_page(start);
+ }
+ if (cpumask_any_but(cmask, cpuid) >= nr_cpu_ids)
+ goto done;
+
riscv_cpuid_to_hartid_mask(cmask, &hmask);
+ hartid = cpuid_to_hartid_map(cpuid);
+ cpumask_clear_cpu(hartid, &hmask);
+
+issue_sfence:
sbi_remote_sfence_vma(hmask.bits, start, size);
+done:
+ put_cpu();
}
-#define flush_tlb_all() sbi_remote_sfence_vma(NULL, 0, -1)
-
+#define flush_tlb_all() __riscv_flush_tlb(NULL, 0, -1)
#define flush_tlb_range(vma, start, end) \
- remote_sfence_vma(mm_cpumask((vma)->vm_mm), start, (end) - (start))
+ __riscv_flush_tlb(mm_cpumask((vma)->vm_mm), start, (end) - (start))
static inline void flush_tlb_page(struct vm_area_struct *vma,
unsigned long addr)
@@ -64,7 +89,7 @@ static inline void flush_tlb_page(struct vm_area_struct *vma,
}
#define flush_tlb_mm(mm) \
- remote_sfence_vma(mm_cpumask(mm), 0, -1)
+ __riscv_flush_tlb(mm_cpumask(mm), 0, -1)
#endif /* CONFIG_SMP */
--
2.23.0

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@ -594,20 +594,11 @@ Patch508: KEYS-Make-use-of-platform-keyring-for-module-signature.patch
# http://lists.infradead.org/pipermail/linux-riscv/2019-August/006235.html # http://lists.infradead.org/pipermail/linux-riscv/2019-August/006235.html
Patch550: 0001-riscv-add-SECCOMP-support.patch Patch550: 0001-riscv-add-SECCOMP-support.patch
# RISC-V SiFive Unleashed Ethernet driver
# Posted upstream, might land in 5.3
# https://patchwork.kernel.org/patch/11050003/
Patch551: 0001-SiFive-Unleashed-Ethernet.patch
# RISC-V SiFive Unleashed CPUFreq support # RISC-V SiFive Unleashed CPUFreq support
# WIP, private dev branch # WIP, private dev branch
# https://github.com/sifive/riscv-linux/commits/dev/paulw/cpufreq-dt-aloe-v5.3-rc4 # https://github.com/sifive/riscv-linux/commits/dev/paulw/cpufreq-dt-aloe-v5.3-rc4
Patch552: 0002-SiFive-Unleashed-CPUFreq.patch Patch552: 0002-SiFive-Unleashed-CPUFreq.patch
# RISC-V Fix TLB Flush issue
# Not upstreamed, but posted
Patch553: 0001-riscv-optimize-tlb-flush-path.patch
# END OF PATCH DEFINITIONS # END OF PATCH DEFINITIONS
%endif %endif