Remove obsolete patches
The TLB issues might have been solved within OpenSBI. Networking for SiFive has been merged into the final v5.3. Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
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8B7F1DA0E2C9FDBB
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@ -1,61 +0,0 @@
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From 0b2b2c260e4f6d088afe7940d036d154d3076ff5 Mon Sep 17 00:00:00 2001
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From: Fedora Kernel Team <kernel-team@fedoraproject.org>
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Date: Sun, 25 Aug 2019 06:57:36 +0000
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Subject: [PATCH 1/2] SiFive Unleashed Ethernet
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---
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Documentation/devicetree/bindings/net/macb.txt | 4 ++--
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arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 9 +++++++++
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drivers/net/ethernet/cadence/macb_main.c | 2 +-
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3 files changed, 12 insertions(+), 3 deletions(-)
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diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt
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index 63c73fa..0b61a90 100644
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--- a/Documentation/devicetree/bindings/net/macb.txt
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+++ b/Documentation/devicetree/bindings/net/macb.txt
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@@ -15,10 +15,10 @@ Required properties:
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Use "atmel,sama5d4-gem" for the GEM IP (10/100) available on Atmel sama5d4 SoCs.
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Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC.
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Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC.
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- Use "sifive,fu540-macb" for SiFive FU540-C000 SoC.
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+ Use "sifive,fu540-c000-gem" for SiFive FU540-C000 SoC.
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Or the generic form: "cdns,emac".
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- reg: Address and length of the register set for the device
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- For "sifive,fu540-macb", second range is required to specify the
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+ For "sifive,fu540-c000-gem", second range is required to specify the
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address and length of the registers for GEMGXL Management block.
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- interrupts: Should contain macb interrupt
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- phy-mode: See ethernet.txt file in the same directory.
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diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
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index 93d68cb..54fc701 100644
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--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
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+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
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@@ -85,3 +85,12 @@
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reg = <0>;
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};
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};
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+
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+ð0 {
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+ status = "okay";
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+ phy-mode = "gmii";
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+ phy-handle = <&phy1>;
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+ phy1: ethernet-phy@0 {
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+ reg = <0>;
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+ };
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+};
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diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
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index 5ca17e6..35b59b5 100644
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--- a/drivers/net/ethernet/cadence/macb_main.c
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+++ b/drivers/net/ethernet/cadence/macb_main.c
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@@ -4154,7 +4154,7 @@ static const struct of_device_id macb_dt_ids[] = {
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{ .compatible = "cdns,emac", .data = &emac_config },
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{ .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
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{ .compatible = "cdns,zynq-gem", .data = &zynq_config },
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- { .compatible = "sifive,fu540-macb", .data = &fu540_c000_config },
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+ { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, macb_dt_ids);
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--
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2.23.0
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@ -1,80 +0,0 @@
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From e168a466bde2761439bfae6ba78d7321a9a3af58 Mon Sep 17 00:00:00 2001
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From: Fedora Kernel Team <kernel-team@fedoraproject.org>
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Date: Sun, 25 Aug 2019 09:04:31 +0000
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Subject: [PATCH] riscv: optimize tlb flush path
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diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h
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index 4d9bbe8..d669d87 100644
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--- a/arch/riscv/include/asm/tlbflush.h
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+++ b/arch/riscv/include/asm/tlbflush.h
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@@ -8,6 +8,7 @@
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#define _ASM_RISCV_TLBFLUSH_H
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#include <linux/mm_types.h>
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+#include <linux/sched.h>
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#include <asm/smp.h>
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/*
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@@ -42,20 +43,44 @@ static inline void flush_tlb_range(struct vm_area_struct *vma,
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#include <asm/sbi.h>
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-static inline void remote_sfence_vma(struct cpumask *cmask, unsigned long start,
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- unsigned long size)
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+static void __riscv_flush_tlb(struct cpumask *cmask, unsigned long start,
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+ unsigned long size)
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{
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struct cpumask hmask;
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+ unsigned int hartid;
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+ unsigned int cpuid;
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cpumask_clear(&hmask);
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+
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+ if (!cmask) {
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+ riscv_cpuid_to_hartid_mask(cpu_online_mask, &hmask);
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+ goto issue_sfence;
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+ }
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+
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+ cpuid = get_cpu();
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+ if (cpumask_test_cpu(cpuid, cmask)) {
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+ /* Save trap cost by issuing a local tlb flush here */
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+ if ((start == 0 && size == -1) || (size > PAGE_SIZE))
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+ local_flush_tlb_all();
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+ else if (size == PAGE_SIZE)
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+ local_flush_tlb_page(start);
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+ }
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+ if (cpumask_any_but(cmask, cpuid) >= nr_cpu_ids)
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+ goto done;
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+
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riscv_cpuid_to_hartid_mask(cmask, &hmask);
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+ hartid = cpuid_to_hartid_map(cpuid);
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+ cpumask_clear_cpu(hartid, &hmask);
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+
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+issue_sfence:
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sbi_remote_sfence_vma(hmask.bits, start, size);
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+done:
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+ put_cpu();
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}
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-#define flush_tlb_all() sbi_remote_sfence_vma(NULL, 0, -1)
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-
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+#define flush_tlb_all() __riscv_flush_tlb(NULL, 0, -1)
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#define flush_tlb_range(vma, start, end) \
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- remote_sfence_vma(mm_cpumask((vma)->vm_mm), start, (end) - (start))
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+ __riscv_flush_tlb(mm_cpumask((vma)->vm_mm), start, (end) - (start))
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static inline void flush_tlb_page(struct vm_area_struct *vma,
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unsigned long addr)
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@@ -64,7 +89,7 @@ static inline void flush_tlb_page(struct vm_area_struct *vma,
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}
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#define flush_tlb_mm(mm) \
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- remote_sfence_vma(mm_cpumask(mm), 0, -1)
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+ __riscv_flush_tlb(mm_cpumask(mm), 0, -1)
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#endif /* CONFIG_SMP */
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--
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2.23.0
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@ -594,20 +594,11 @@ Patch508: KEYS-Make-use-of-platform-keyring-for-module-signature.patch
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# http://lists.infradead.org/pipermail/linux-riscv/2019-August/006235.html
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Patch550: 0001-riscv-add-SECCOMP-support.patch
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# RISC-V SiFive Unleashed Ethernet driver
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# Posted upstream, might land in 5.3
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# https://patchwork.kernel.org/patch/11050003/
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Patch551: 0001-SiFive-Unleashed-Ethernet.patch
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# RISC-V SiFive Unleashed CPUFreq support
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# WIP, private dev branch
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# https://github.com/sifive/riscv-linux/commits/dev/paulw/cpufreq-dt-aloe-v5.3-rc4
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Patch552: 0002-SiFive-Unleashed-CPUFreq.patch
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# RISC-V Fix TLB Flush issue
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# Not upstreamed, but posted
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Patch553: 0001-riscv-optimize-tlb-flush-path.patch
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# END OF PATCH DEFINITIONS
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%endif
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