Backport 3 upstream fixes to resolve radeon schedule IB errors (rhbz 855275)
This commit is contained in:
parent
78f006e1f1
commit
61d473f098
11
kernel.spec
11
kernel.spec
@ -54,7 +54,7 @@ Summary: The Linux kernel
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# For non-released -rc kernels, this will be appended after the rcX and
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# gitX tags, so a 3 here would become part of release "0.rcX.gitX.3"
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#
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%global baserelease 1
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%global baserelease 2
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%global fedora_build %{baserelease}
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# base_sublevel is the kernel version we're starting with and patching
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@ -725,6 +725,9 @@ Patch21230: SCSI-mvsas-Fix-oops-when-ata-commond-timeout.patch
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Patch21232: 8139cp-set-ring-address-after-enabling-C-mode.patch
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Patch21233: 8139cp-re-enable-interrupts-after-tx-timeout.patch
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#rhbz 855275
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Patch21235: radeon-evergreen-3.6.9-fixes.mbox
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# END OF PATCH DEFINITIONS
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%endif
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@ -1367,6 +1370,9 @@ ApplyPatch SCSI-mvsas-Fix-oops-when-ata-commond-timeout.patch
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ApplyPatch 8139cp-set-ring-address-after-enabling-C-mode.patch
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ApplyPatch 8139cp-re-enable-interrupts-after-tx-timeout.patch
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#rhbz 855275
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ApplyPatch radeon-evergreen-3.6.9-fixes.mbox
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# END OF PATCH APPLICATIONS
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%endif
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@ -2067,6 +2073,9 @@ fi
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# and build.
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%changelog
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* Mon Dec 03 2012 Josh Boyer <jwboyer@redhat.com> - 3.6.9-2
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- Backport 3 upstream fixes to resolve radeon schedule IB errors (rhbz 855275)
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* Mon Dec 03 2012 Josh Boyer <jwboyer@redhat.com> - 3.6.9-1
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- Linux v3.6.9
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376
radeon-evergreen-3.6.9-fixes.mbox
Normal file
376
radeon-evergreen-3.6.9-fixes.mbox
Normal file
@ -0,0 +1,376 @@
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From 8e502f50fdade16ab4540159218be5d81b678d11 Mon Sep 17 00:00:00 2001
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From: Alex Deucher <alexander.deucher@amd.com>
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Date: Mon, 3 Dec 2012 18:12:05 -0500
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Subject: [PATCH 1/3] drm/radeon/dce4+: don't use radeon_crtc for vblank
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callback
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Upstream commit 4a15903db02026728d0cf2755c6fabae16b8db6a
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This might be called before we've allocated the radeon_crtcs
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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---
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drivers/gpu/drm/radeon/evergreen.c | 20 ++++++++++++++++----
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1 file changed, 16 insertions(+), 4 deletions(-)
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diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
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index e93b80a..0c79d9e 100644
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--- a/drivers/gpu/drm/radeon/evergreen.c
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+++ b/drivers/gpu/drm/radeon/evergreen.c
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@@ -37,6 +37,16 @@
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#define EVERGREEN_PFP_UCODE_SIZE 1120
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#define EVERGREEN_PM4_UCODE_SIZE 1376
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+static const u32 crtc_offsets[6] =
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+{
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+ EVERGREEN_CRTC0_REGISTER_OFFSET,
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+ EVERGREEN_CRTC1_REGISTER_OFFSET,
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+ EVERGREEN_CRTC2_REGISTER_OFFSET,
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+ EVERGREEN_CRTC3_REGISTER_OFFSET,
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+ EVERGREEN_CRTC4_REGISTER_OFFSET,
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+ EVERGREEN_CRTC5_REGISTER_OFFSET
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+};
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+
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static void evergreen_gpu_init(struct radeon_device *rdev);
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void evergreen_fini(struct radeon_device *rdev);
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void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
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@@ -109,17 +119,19 @@ void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
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*/
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void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
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{
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- struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
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int i;
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- if (RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_MASTER_EN) {
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+ if (crtc >= rdev->num_crtc)
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+ return;
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+
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+ if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN) {
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for (i = 0; i < rdev->usec_timeout; i++) {
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- if (!(RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK))
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+ if (!(RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK))
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break;
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udelay(1);
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}
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for (i = 0; i < rdev->usec_timeout; i++) {
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- if (RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK)
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+ if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
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break;
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udelay(1);
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}
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--
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1.8.0
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From 027eb4090e4261a9b9f5cce47493657d12f2caf3 Mon Sep 17 00:00:00 2001
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From: Alex Deucher <alexander.deucher@amd.com>
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Date: Mon, 3 Dec 2012 18:15:21 -0500
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Subject: [PATCH 2/3] drm/radeon: properly handle mc_stop/mc_resume on
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evergreen+ (v2)
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Upstream commit 62444b7462a2b98bc78d68736c03a7c4e66ba7e2
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- Stop the displays from accessing the FB
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- Block CPU access
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- Turn off MC client access
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This should fix issues some users have seen, especially
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with UEFI, when changing the MC FB location that result
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in hangs or display corruption.
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v2: fix crtc enabled check noticed by Luca Tettamanti
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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---
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drivers/gpu/drm/radeon/evergreen.c | 169 +++++++++++++++------------------
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drivers/gpu/drm/radeon/evergreen_reg.h | 2 +
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drivers/gpu/drm/radeon/evergreend.h | 7 ++
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drivers/gpu/drm/radeon/radeon_asic.h | 1 +
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4 files changed, 88 insertions(+), 91 deletions(-)
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diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
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index 0c79d9e..10b34b8 100644
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--- a/drivers/gpu/drm/radeon/evergreen.c
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+++ b/drivers/gpu/drm/radeon/evergreen.c
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@@ -1241,116 +1241,103 @@ void evergreen_agp_enable(struct radeon_device *rdev)
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void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
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{
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+ u32 crtc_enabled, tmp, frame_count, blackout;
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+ int i, j;
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+
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save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
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save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
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- /* Stop all video */
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+ /* disable VGA render */
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WREG32(VGA_RENDER_CONTROL, 0);
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- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
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- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
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- if (rdev->num_crtc >= 4) {
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- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
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- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
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- }
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- if (rdev->num_crtc >= 6) {
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- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
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- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
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- }
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- WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
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- WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
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- if (rdev->num_crtc >= 4) {
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- WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
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- WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
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- }
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- if (rdev->num_crtc >= 6) {
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- WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
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- WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
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- }
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- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
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- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
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- if (rdev->num_crtc >= 4) {
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- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
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- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
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- }
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- if (rdev->num_crtc >= 6) {
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- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
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- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
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+ /* blank the display controllers */
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+ for (i = 0; i < rdev->num_crtc; i++) {
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+ crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
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+ if (crtc_enabled) {
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+ save->crtc_enabled[i] = true;
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+ if (ASIC_IS_DCE6(rdev)) {
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+ tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
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+ if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
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+ radeon_wait_for_vblank(rdev, i);
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+ tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
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+ WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
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+ }
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+ } else {
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+ tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
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+ if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
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+ radeon_wait_for_vblank(rdev, i);
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+ tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
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+ WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
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+ }
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+ }
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+ /* wait for the next frame */
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+ frame_count = radeon_get_vblank_counter(rdev, i);
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+ for (j = 0; j < rdev->usec_timeout; j++) {
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+ if (radeon_get_vblank_counter(rdev, i) != frame_count)
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+ break;
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+ udelay(1);
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+ }
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+ }
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}
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- WREG32(D1VGA_CONTROL, 0);
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- WREG32(D2VGA_CONTROL, 0);
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- if (rdev->num_crtc >= 4) {
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- WREG32(EVERGREEN_D3VGA_CONTROL, 0);
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- WREG32(EVERGREEN_D4VGA_CONTROL, 0);
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- }
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- if (rdev->num_crtc >= 6) {
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- WREG32(EVERGREEN_D5VGA_CONTROL, 0);
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- WREG32(EVERGREEN_D6VGA_CONTROL, 0);
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+ radeon_mc_wait_for_idle(rdev);
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+
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+ blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
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+ if ((blackout & BLACKOUT_MODE_MASK) != 1) {
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+ /* Block CPU access */
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+ WREG32(BIF_FB_EN, 0);
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+ /* blackout the MC */
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+ blackout &= ~BLACKOUT_MODE_MASK;
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+ WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
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}
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}
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void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
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{
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- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
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- upper_32_bits(rdev->mc.vram_start));
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- WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
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- upper_32_bits(rdev->mc.vram_start));
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- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
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- (u32)rdev->mc.vram_start);
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- WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
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- (u32)rdev->mc.vram_start);
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-
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- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
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- upper_32_bits(rdev->mc.vram_start));
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- WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
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- upper_32_bits(rdev->mc.vram_start));
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- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
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- (u32)rdev->mc.vram_start);
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- WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
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- (u32)rdev->mc.vram_start);
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-
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- if (rdev->num_crtc >= 4) {
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- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
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- upper_32_bits(rdev->mc.vram_start));
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- WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
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- upper_32_bits(rdev->mc.vram_start));
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- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
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- (u32)rdev->mc.vram_start);
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- WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
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- (u32)rdev->mc.vram_start);
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-
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- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
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- upper_32_bits(rdev->mc.vram_start));
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- WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
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- upper_32_bits(rdev->mc.vram_start));
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- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
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- (u32)rdev->mc.vram_start);
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- WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
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- (u32)rdev->mc.vram_start);
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- }
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- if (rdev->num_crtc >= 6) {
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- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
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- upper_32_bits(rdev->mc.vram_start));
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- WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
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- upper_32_bits(rdev->mc.vram_start));
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- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
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- (u32)rdev->mc.vram_start);
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- WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
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- (u32)rdev->mc.vram_start);
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+ u32 tmp, frame_count;
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+ int i, j;
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- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
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+ /* update crtc base addresses */
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+ for (i = 0; i < rdev->num_crtc; i++) {
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+ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
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upper_32_bits(rdev->mc.vram_start));
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- WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
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+ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
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upper_32_bits(rdev->mc.vram_start));
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- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
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+ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
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(u32)rdev->mc.vram_start);
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- WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
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+ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
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(u32)rdev->mc.vram_start);
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}
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-
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WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
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WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
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- /* Unlock host access */
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+
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+ /* unblackout the MC */
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+ tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
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+ tmp &= ~BLACKOUT_MODE_MASK;
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+ WREG32(MC_SHARED_BLACKOUT_CNTL, tmp);
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+ /* allow CPU access */
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+ WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
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+
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+ for (i = 0; i < rdev->num_crtc; i++) {
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+ if (save->crtc_enabled) {
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+ if (ASIC_IS_DCE6(rdev)) {
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+ tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
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+ tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
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+ WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
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+ } else {
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+ tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
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+ tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
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+ WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
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+ }
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+ /* wait for the next frame */
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+ frame_count = radeon_get_vblank_counter(rdev, i);
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+ for (j = 0; j < rdev->usec_timeout; j++) {
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+ if (radeon_get_vblank_counter(rdev, i) != frame_count)
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+ break;
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+ udelay(1);
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+ }
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+ }
|
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+ }
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+ /* Unlock vga access */
|
||||
WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
|
||||
mdelay(1);
|
||||
WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
|
||||
diff --git a/drivers/gpu/drm/radeon/evergreen_reg.h b/drivers/gpu/drm/radeon/evergreen_reg.h
|
||||
index 8beac10..034f4c2 100644
|
||||
--- a/drivers/gpu/drm/radeon/evergreen_reg.h
|
||||
+++ b/drivers/gpu/drm/radeon/evergreen_reg.h
|
||||
@@ -218,6 +218,8 @@
|
||||
#define EVERGREEN_CRTC_CONTROL 0x6e70
|
||||
# define EVERGREEN_CRTC_MASTER_EN (1 << 0)
|
||||
# define EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24)
|
||||
+#define EVERGREEN_CRTC_BLANK_CONTROL 0x6e74
|
||||
+# define EVERGREEN_CRTC_BLANK_DATA_EN (1 << 8)
|
||||
#define EVERGREEN_CRTC_STATUS 0x6e8c
|
||||
# define EVERGREEN_CRTC_V_BLANK (1 << 0)
|
||||
#define EVERGREEN_CRTC_STATUS_POSITION 0x6e90
|
||||
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
|
||||
index 302af4f..2bc0f6a 100644
|
||||
--- a/drivers/gpu/drm/radeon/evergreend.h
|
||||
+++ b/drivers/gpu/drm/radeon/evergreend.h
|
||||
@@ -87,6 +87,10 @@
|
||||
|
||||
#define CONFIG_MEMSIZE 0x5428
|
||||
|
||||
+#define BIF_FB_EN 0x5490
|
||||
+#define FB_READ_EN (1 << 0)
|
||||
+#define FB_WRITE_EN (1 << 1)
|
||||
+
|
||||
#define CP_STRMOUT_CNTL 0x84FC
|
||||
|
||||
#define CP_COHER_CNTL 0x85F0
|
||||
@@ -434,6 +438,9 @@
|
||||
#define NOOFCHAN_MASK 0x00003000
|
||||
#define MC_SHARED_CHREMAP 0x2008
|
||||
|
||||
+#define MC_SHARED_BLACKOUT_CNTL 0x20ac
|
||||
+#define BLACKOUT_MODE_MASK 0x00000007
|
||||
+
|
||||
#define MC_ARB_RAMCFG 0x2760
|
||||
#define NOOFBANK_SHIFT 0
|
||||
#define NOOFBANK_MASK 0x00000003
|
||||
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
|
||||
index 18c38d1..132429e 100644
|
||||
--- a/drivers/gpu/drm/radeon/radeon_asic.h
|
||||
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
|
||||
@@ -389,6 +389,7 @@ void r700_cp_fini(struct radeon_device *rdev);
|
||||
struct evergreen_mc_save {
|
||||
u32 vga_render_control;
|
||||
u32 vga_hdp_control;
|
||||
+ bool crtc_enabled[RADEON_MAX_CRTCS];
|
||||
};
|
||||
|
||||
void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
|
||||
--
|
||||
1.8.0
|
||||
|
||||
|
||||
From 5d46a79118cc6a8f5e30e39f19ad997bb2191b53 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Deucher <alexander.deucher@amd.com>
|
||||
Date: Mon, 3 Dec 2012 18:15:55 -0500
|
||||
Subject: [PATCH 3/3] drm/radeon: properly track the crtc not_enabled case
|
||||
evergreen_mc_stop()
|
||||
|
||||
Upstream commit 804cc4a0ad3a896ca295f771a28c6eb36ced7903
|
||||
|
||||
The save struct is not initialized previously so explicitly
|
||||
mark the crtcs as not used when they are not in use.
|
||||
|
||||
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
||||
Cc: stable@vger.kernel.org
|
||||
---
|
||||
drivers/gpu/drm/radeon/evergreen.c | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
|
||||
index 10b34b8..5528fea 100644
|
||||
--- a/drivers/gpu/drm/radeon/evergreen.c
|
||||
+++ b/drivers/gpu/drm/radeon/evergreen.c
|
||||
@@ -1276,6 +1276,8 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
|
||||
break;
|
||||
udelay(1);
|
||||
}
|
||||
+ } else {
|
||||
+ save->crtc_enabled[i] = false;
|
||||
}
|
||||
}
|
||||
|
||||
--
|
||||
1.8.0
|
||||
|
Loading…
Reference in New Issue
Block a user