Raspberry Pi DT updates, Update AllWinner A64 timer errata workaround
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Peter Robinson
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Sat, 12 Jan 2019 21:17:21 -0500 (EST)
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From: Samuel Holland <samuel@sholland.org>
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To: Catalin Marinas <catalin.marinas@arm.com>,
|
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Will Deacon <will.deacon@arm.com>,
|
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Maxime Ripard <maxime.ripard@bootlin.com>, Chen-Yu Tsai <wens@csie.org>,
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Rob Herring <robh+dt@kernel.org>, Mark Rutland <Mark.Rutland@arm.com>,
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Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <marc.zyngier@arm.com>
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Subject: [PATCH v3 1/2] arm64: arch_timer: Workaround for Allwinner A64 timer
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instability
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Date: Sat, 12 Jan 2019 20:17:18 -0600
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The Allwinner A64 SoC is known[1] to have an unstable architectural
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timer, which manifests itself most obviously in the time jumping forward
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a multiple of 95 years[2][3]. This coincides with 2^56 cycles at a
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timer frequency of 24 MHz, implying that the time went slightly backward
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(and this was interpreted by the kernel as it jumping forward and
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wrapping around past the epoch).
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Investigation revealed instability in the low bits of CNTVCT at the
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point a high bit rolls over. This leads to power-of-two cycle forward
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and backward jumps. (Testing shows that forward jumps are about twice as
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likely as backward jumps.) Since the counter value returns to normal
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after an indeterminate read, each "jump" really consists of both a
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forward and backward jump from the software perspective.
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Unless the kernel is trapping CNTVCT reads, a userspace program is able
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to read the register in a loop faster than it changes. A test program
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running on all 4 CPU cores that reported jumps larger than 100 ms was
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run for 13.6 hours and reported the following:
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Count | Event
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-------+---------------------------
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9940 | jumped backward 699ms
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268 | jumped backward 1398ms
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1 | jumped backward 2097ms
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16020 | jumped forward 175ms
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6443 | jumped forward 699ms
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2976 | jumped forward 1398ms
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9 | jumped forward 356516ms
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9 | jumped forward 357215ms
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4 | jumped forward 714430ms
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1 | jumped forward 3578440ms
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This works out to a jump larger than 100 ms about every 5.5 seconds on
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each CPU core.
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The largest jump (almost an hour!) was the following sequence of reads:
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0x0000007fffffffff → 0x00000093feffffff → 0x0000008000000000
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Note that the middle bits don't necessarily all read as all zeroes or
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all ones during the anomalous behavior; however the low 10 bits checked
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by the function in this patch have never been observed with any other
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value.
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Also note that smaller jumps are much more common, with backward jumps
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of 2048 (2^11) cycles observed over 400 times per second on each core.
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(Of course, this is partially explained by lower bits rolling over more
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frequently.) Any one of these could have caused the 95 year time skip.
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Similar anomalies were observed while reading CNTPCT (after patching the
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kernel to allow reads from userspace). However, the CNTPCT jumps are
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much less frequent, and only small jumps were observed. The same program
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as before (except now reading CNTPCT) observed after 72 hours:
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Count | Event
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-------+---------------------------
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17 | jumped backward 699ms
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52 | jumped forward 175ms
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2831 | jumped forward 699ms
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5 | jumped forward 1398ms
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Further investigation showed that the instability in CNTPCT/CNTVCT also
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affected the respective timer's TVAL register. The following values were
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observed immediately after writing CNVT_TVAL to 0x10000000:
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CNTVCT | CNTV_TVAL | CNTV_CVAL | CNTV_TVAL Error
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--------------------+------------+--------------------+-----------------
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0x000000d4a2d8bfff | 0x10003fff | 0x000000d4b2d8bfff | +0x00004000
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0x000000d4a2d94000 | 0x0fffffff | 0x000000d4b2d97fff | -0x00004000
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0x000000d4a2d97fff | 0x10003fff | 0x000000d4b2d97fff | +0x00004000
|
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0x000000d4a2d9c000 | 0x0fffffff | 0x000000d4b2d9ffff | -0x00004000
|
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|
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The pattern of errors in CNTV_TVAL seemed to depend on exactly which
|
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value was written to it. For example, after writing 0x10101010:
|
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|
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CNTVCT | CNTV_TVAL | CNTV_CVAL | CNTV_TVAL Error
|
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--------------------+------------+--------------------+-----------------
|
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0x000001ac3effffff | 0x1110100f | 0x000001ac4f10100f | +0x1000000
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0x000001ac40000000 | 0x1010100f | 0x000001ac5110100f | -0x1000000
|
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0x000001ac58ffffff | 0x1110100f | 0x000001ac6910100f | +0x1000000
|
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0x000001ac66000000 | 0x1010100f | 0x000001ac7710100f | -0x1000000
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0x000001ac6affffff | 0x1110100f | 0x000001ac7b10100f | +0x1000000
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0x000001ac6e000000 | 0x1010100f | 0x000001ac7f10100f | -0x1000000
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I was also twice able to reproduce the issue covered by Allwinner's
|
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workaround[4], that writing to TVAL sometimes fails, and both CVAL and
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TVAL are left with entirely bogus values. One was the following values:
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|
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CNTVCT | CNTV_TVAL | CNTV_CVAL
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--------------------+------------+--------------------------------------
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0x000000d4a2d6014c | 0x8fbd5721 | 0x000000d132935fff (615s in the past)
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========================================================================
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Because the CPU can read the CNTPCT/CNTVCT registers faster than they
|
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change, performing two reads of the register and comparing the high bits
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(like other workarounds) is not a workable solution. And because the
|
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timer can jump both forward and backward, no pair of reads can
|
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distinguish a good value from a bad one. The only way to guarantee a
|
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good value from consecutive reads would be to read _three_ times, and
|
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take the middle value only if the three values are 1) each unique and
|
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2) increasing. This takes at minimum 3 counter cycles (125 ns), or more
|
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if an anomaly is detected.
|
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|
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However, since there is a distinct pattern to the bad values, we can
|
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optimize the common case (1022/1024 of the time) to a single read by
|
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simply ignoring values that match the error pattern. This still takes no
|
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more than 3 cycles in the worst case, and requires much less code. As an
|
||||
additional safety check, we still limit the loop iteration to the number
|
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of max-frequency (1.2 GHz) CPU cycles in three 24 MHz counter periods.
|
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|
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For the TVAL registers, the simple solution is to not use them. Instead,
|
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read or write the CVAL and calculate the TVAL value in software.
|
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|
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Although the manufacturer is aware of at least part of the erratum[4],
|
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there is no official name for it. For now, use the kernel-internal name
|
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"UNKNOWN1".
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|
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[1]: https://github.com/armbian/build/commit/a08cd6fe7ae9
|
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[2]: https://forum.armbian.com/topic/3458-a64-datetime-clock-issue/
|
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[3]: https://irclog.whitequark.org/linux-sunxi/2018-01-26
|
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[4]: https://github.com/Allwinner-Homlet/H6-BSP4.9-linux/blob/master/drivers/clocksource/arm_arch_timer.c#L272
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|
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Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
|
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Tested-by: Andre Przywara <andre.przywara@arm.com>
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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Documentation/arm64/silicon-errata.txt | 2 +
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drivers/clocksource/Kconfig | 10 +++++
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drivers/clocksource/arm_arch_timer.c | 55 ++++++++++++++++++++++++++
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3 files changed, 67 insertions(+)
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diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
|
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index 8f9577621144..4a269732d2a0 100644
|
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--- a/Documentation/arm64/silicon-errata.txt
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+++ b/Documentation/arm64/silicon-errata.txt
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@@ -44,6 +44,8 @@ stable kernels.
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| Implementor | Component | Erratum ID | Kconfig |
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+----------------+-----------------+-----------------+-----------------------------+
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+| Allwinner | A64/R18 | UNKNOWN1 | SUN50I_ERRATUM_UNKNOWN1 |
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+| | | | |
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| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
|
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| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
|
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| ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
|
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diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
|
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index 55c77e44bb2d..d20ff4da07c3 100644
|
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--- a/drivers/clocksource/Kconfig
|
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+++ b/drivers/clocksource/Kconfig
|
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@@ -364,6 +364,16 @@ config ARM64_ERRATUM_858921
|
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The workaround will be dynamically enabled when an affected
|
||||
core is detected.
|
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|
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+config SUN50I_ERRATUM_UNKNOWN1
|
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+ bool "Workaround for Allwinner A64 erratum UNKNOWN1"
|
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+ default y
|
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+ depends on ARM_ARCH_TIMER && ARM64 && ARCH_SUNXI
|
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+ select ARM_ARCH_TIMER_OOL_WORKAROUND
|
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+ help
|
||||
+ This option enables a workaround for instability in the timer on
|
||||
+ the Allwinner A64 SoC. The workaround will only be active if the
|
||||
+ allwinner,erratum-unknown1 property is found in the timer node.
|
||||
+
|
||||
config ARM_GLOBAL_TIMER
|
||||
bool "Support for the ARM global timer" if COMPILE_TEST
|
||||
select TIMER_OF if OF
|
||||
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
|
||||
index 9a7d4dc00b6e..a8b20b65bd4b 100644
|
||||
--- a/drivers/clocksource/arm_arch_timer.c
|
||||
+++ b/drivers/clocksource/arm_arch_timer.c
|
||||
@@ -326,6 +326,48 @@ static u64 notrace arm64_1188873_read_cntvct_el0(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
+#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
|
||||
+/*
|
||||
+ * The low bits of the counter registers are indeterminate while bit 10 or
|
||||
+ * greater is rolling over. Since the counter value can jump both backward
|
||||
+ * (7ff -> 000 -> 800) and forward (7ff -> fff -> 800), ignore register values
|
||||
+ * with all ones or all zeros in the low bits. Bound the loop by the maximum
|
||||
+ * number of CPU cycles in 3 consecutive 24 MHz counter periods.
|
||||
+ */
|
||||
+#define __sun50i_a64_read_reg(reg) ({ \
|
||||
+ u64 _val; \
|
||||
+ int _retries = 150; \
|
||||
+ \
|
||||
+ do { \
|
||||
+ _val = read_sysreg(reg); \
|
||||
+ _retries--; \
|
||||
+ } while (((_val + 1) & GENMASK(9, 0)) <= 1 && _retries); \
|
||||
+ \
|
||||
+ WARN_ON_ONCE(!_retries); \
|
||||
+ _val; \
|
||||
+})
|
||||
+
|
||||
+static u64 notrace sun50i_a64_read_cntpct_el0(void)
|
||||
+{
|
||||
+ return __sun50i_a64_read_reg(cntpct_el0);
|
||||
+}
|
||||
+
|
||||
+static u64 notrace sun50i_a64_read_cntvct_el0(void)
|
||||
+{
|
||||
+ return __sun50i_a64_read_reg(cntvct_el0);
|
||||
+}
|
||||
+
|
||||
+static u32 notrace sun50i_a64_read_cntp_tval_el0(void)
|
||||
+{
|
||||
+ return read_sysreg(cntp_cval_el0) - sun50i_a64_read_cntpct_el0();
|
||||
+}
|
||||
+
|
||||
+static u32 notrace sun50i_a64_read_cntv_tval_el0(void)
|
||||
+{
|
||||
+ return read_sysreg(cntv_cval_el0) - sun50i_a64_read_cntvct_el0();
|
||||
+}
|
||||
+#endif
|
||||
+
|
||||
#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
|
||||
DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround);
|
||||
EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
|
||||
@@ -423,6 +465,19 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = {
|
||||
.read_cntvct_el0 = arm64_1188873_read_cntvct_el0,
|
||||
},
|
||||
#endif
|
||||
+#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
|
||||
+ {
|
||||
+ .match_type = ate_match_dt,
|
||||
+ .id = "allwinner,erratum-unknown1",
|
||||
+ .desc = "Allwinner erratum UNKNOWN1",
|
||||
+ .read_cntp_tval_el0 = sun50i_a64_read_cntp_tval_el0,
|
||||
+ .read_cntv_tval_el0 = sun50i_a64_read_cntv_tval_el0,
|
||||
+ .read_cntpct_el0 = sun50i_a64_read_cntpct_el0,
|
||||
+ .read_cntvct_el0 = sun50i_a64_read_cntvct_el0,
|
||||
+ .set_next_event_phys = erratum_set_next_event_tval_phys,
|
||||
+ .set_next_event_virt = erratum_set_next_event_tval_virt,
|
||||
+ },
|
||||
+#endif
|
||||
};
|
||||
|
||||
typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *,
|
||||
|
||||
From patchwork Sun Jan 13 02:17:19 2019
|
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X-Patchwork-Id: 10761195
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Sat, 12 Jan 2019 21:17:22 -0500 (EST)
|
||||
From: Samuel Holland <samuel@sholland.org>
|
||||
To: Catalin Marinas <catalin.marinas@arm.com>,
|
||||
Will Deacon <will.deacon@arm.com>,
|
||||
Maxime Ripard <maxime.ripard@bootlin.com>, Chen-Yu Tsai <wens@csie.org>,
|
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Rob Herring <robh+dt@kernel.org>, Mark Rutland <Mark.Rutland@arm.com>,
|
||||
Daniel Lezcano <daniel.lezcano@linaro.org>,
|
||||
Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <marc.zyngier@arm.com>
|
||||
Subject: [PATCH v3 2/2] arm64: dts: allwinner: a64: Enable A64 timer
|
||||
workaround
|
||||
Date: Sat, 12 Jan 2019 20:17:19 -0600
|
||||
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Cc: devicetree@vger.kernel.org, linux-sunxi@googlegroups.com,
|
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|
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|
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||||
|
||||
As instability in the architectural timer has been observed on multiple
|
||||
devices using this SoC, inluding the Pine64 and the Orange Pi Win,
|
||||
enable the workaround in the SoC's device tree.
|
||||
|
||||
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
|
||||
Signed-off-by: Samuel Holland <samuel@sholland.org>
|
||||
---
|
||||
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
||||
index f3a66f888205..13eac92a8c55 100644
|
||||
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
||||
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
||||
@@ -175,6 +175,7 @@
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
+ allwinner,erratum-unknown1;
|
||||
interrupts = <GIC_PPI 13
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||
<GIC_PPI 14
|
||||
|
|
@ -1,184 +0,0 @@
|
|||
From patchwork Fri May 11 02:27:50 2018
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 8bit
|
||||
Subject: [1/2] arm64: arch_timer: Workaround for Allwinner A64 timer
|
||||
instability
|
||||
From: Samuel Holland <samuel@sholland.org>
|
||||
X-Patchwork-Id: 10392891
|
||||
Message-Id: <20180511022751.9096-2-samuel@sholland.org>
|
||||
To: Maxime Ripard <maxime.ripard@bootlin.com>, Chen-Yu Tsai <wens@csie.org>,
|
||||
Catalin Marinas <catalin.marinas@arm.com>,
|
||||
Will Deacon <will.deacon@arm.com>,
|
||||
Daniel Lezcano <daniel.lezcano@linaro.org>,
|
||||
Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <marc.zyngier@arm.com>
|
||||
Cc: linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,
|
||||
linux-arm-kernel@lists.infradead.org, Samuel Holland <samuel@sholland.org>
|
||||
Date: Thu, 10 May 2018 21:27:50 -0500
|
||||
|
||||
The Allwinner A64 SoC is known [1] to have an unstable architectural
|
||||
timer, which manifests itself most obviously in the time jumping forward
|
||||
a multiple of 95 years [2][3]. This coincides with 2^56 cycles at a
|
||||
timer frequency of 24 MHz, implying that the time went slightly backward
|
||||
(and this was interpreted by the kernel as it jumping forward and
|
||||
wrapping around past the epoch).
|
||||
|
||||
Further investigation revealed instability in the low bits of CNTVCT at
|
||||
the point a high bit rolls over. This leads to power-of-two cycle
|
||||
forward and backward jumps. (Testing shows that forward jumps are about
|
||||
twice as likely as backward jumps.)
|
||||
|
||||
Without trapping reads to CNTVCT, a userspace program is able to read it
|
||||
in a loop faster than it changes. A test program running on all 4 CPU
|
||||
cores that reported jumps larger than 100 ms was run for 13.6 hours and
|
||||
reported the following:
|
||||
|
||||
Count | Event
|
||||
-------+---------------------------
|
||||
9940 | jumped backward 699ms
|
||||
268 | jumped backward 1398ms
|
||||
1 | jumped backward 2097ms
|
||||
16020 | jumped forward 175ms
|
||||
6443 | jumped forward 699ms
|
||||
2976 | jumped forward 1398ms
|
||||
9 | jumped forward 356516ms
|
||||
9 | jumped forward 357215ms
|
||||
4 | jumped forward 714430ms
|
||||
1 | jumped forward 3578440ms
|
||||
|
||||
This works out to a jump larger than 100 ms about every 5.5 seconds on
|
||||
each CPU core.
|
||||
|
||||
The largest jump (almost an hour!) was the following sequence of reads:
|
||||
0x0000007fffffffff → 0x00000093feffffff → 0x0000008000000000
|
||||
|
||||
Note that the middle bits don't necessarily all read as all zeroes or
|
||||
all ones during the anomalous behavior; however the low 11 bits checked
|
||||
by the function in this patch have never been observed with any other
|
||||
value.
|
||||
|
||||
Also note that smaller jumps are much more common, with the smallest
|
||||
backward jumps of 2048 cycles observed over 400 times per second on each
|
||||
core. (Of course, this is partially due to lower bits rolling over more
|
||||
frequently.) Any one of these could have caused the 95 year time skip.
|
||||
|
||||
Similar anomalies were observed while reading CNTPCT (after patching the
|
||||
kernel to allow reads from userspace). However, the jumps are much less
|
||||
frequent, and only small jumps were observed. The same program as before
|
||||
(except now reading CNTPCT) observed after 72 hours:
|
||||
|
||||
Count | Event
|
||||
-------+---------------------------
|
||||
17 | jumped backward 699ms
|
||||
52 | jumped forward 175ms
|
||||
2831 | jumped forward 699ms
|
||||
5 | jumped forward 1398ms
|
||||
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
|
||||
Tested-by: Andre Przywara <andre.przywara@arm.com>
|
||||
|
||||
========================================================================
|
||||
|
||||
Because the CPU can read the CNTPCT/CNTVCT registers faster than they
|
||||
change, performing two reads of the register and comparing the high bits
|
||||
(like other workarounds) is not a workable solution. And because the
|
||||
timer can jump both forward and backward, no pair of reads can
|
||||
distinguish a good value from a bad one. The only way to guarantee a
|
||||
good value from consecutive reads would be to read _three_ times, and
|
||||
take the middle value iff the three values are 1) individually unique
|
||||
and 2) increasing. This takes at minimum 3 cycles (125 ns), or more if
|
||||
an anomaly is detected.
|
||||
|
||||
However, since there is a distinct pattern to the bad values, we can
|
||||
optimize the common case (2046/2048 of the time) to a single read by
|
||||
simply ignoring values that match the pattern. This still takes no more
|
||||
than 3 cycles in the worst case, and requires much less code.
|
||||
|
||||
[1]: https://github.com/armbian/build/commit/a08cd6fe7ae9
|
||||
[2]: https://forum.armbian.com/topic/3458-a64-datetime-clock-issue/
|
||||
[3]: https://irclog.whitequark.org/linux-sunxi/2018-01-26
|
||||
|
||||
Signed-off-by: Samuel Holland <samuel@sholland.org>
|
||||
---
|
||||
drivers/clocksource/Kconfig | 11 ++++++++++
|
||||
drivers/clocksource/arm_arch_timer.c | 39 ++++++++++++++++++++++++++++++++++++
|
||||
2 files changed, 50 insertions(+)
|
||||
|
||||
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
|
||||
index 8e8a09755d10..7a5d434dd30b 100644
|
||||
--- a/drivers/clocksource/Kconfig
|
||||
+++ b/drivers/clocksource/Kconfig
|
||||
@@ -364,6 +364,17 @@ config ARM64_ERRATUM_858921
|
||||
The workaround will be dynamically enabled when an affected
|
||||
core is detected.
|
||||
|
||||
+config SUN50I_A64_UNSTABLE_TIMER
|
||||
+ bool "Workaround for Allwinner A64 timer instability"
|
||||
+ default y
|
||||
+ depends on ARM_ARCH_TIMER && ARM64 && ARCH_SUNXI
|
||||
+ select ARM_ARCH_TIMER_OOL_WORKAROUND
|
||||
+ help
|
||||
+ This option enables a workaround for instability in the timer on
|
||||
+ the Allwinner A64 SoC. The workaround will only be active if the
|
||||
+ allwinner,sun50i-a64-unstable-timer property is found in the
|
||||
+ timer node.
|
||||
+
|
||||
config ARM_GLOBAL_TIMER
|
||||
bool "Support for the ARM global timer" if COMPILE_TEST
|
||||
select TIMER_OF if OF
|
||||
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
|
||||
index 57cb2f00fc07..66ce13578c52 100644
|
||||
--- a/drivers/clocksource/arm_arch_timer.c
|
||||
+++ b/drivers/clocksource/arm_arch_timer.c
|
||||
@@ -319,6 +319,36 @@ static u64 notrace arm64_858921_read_cntvct_el0(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
+#ifdef CONFIG_SUN50I_A64_UNSTABLE_TIMER
|
||||
+/*
|
||||
+ * The low bits of each register can transiently read as all ones or all zeroes
|
||||
+ * when bit 11 or greater rolls over. Since the value can jump both backward
|
||||
+ * (7ff -> 000 -> 800) and forward (7ff -> fff -> 800), it is simplest to just
|
||||
+ * ignore register values with all ones or zeros in the low bits.
|
||||
+ */
|
||||
+static u64 notrace sun50i_a64_read_cntpct_el0(void)
|
||||
+{
|
||||
+ u64 val;
|
||||
+
|
||||
+ do {
|
||||
+ val = read_sysreg(cntpct_el0);
|
||||
+ } while (((val + 1) & GENMASK(10, 0)) <= 1);
|
||||
+
|
||||
+ return val;
|
||||
+}
|
||||
+
|
||||
+static u64 notrace sun50i_a64_read_cntvct_el0(void)
|
||||
+{
|
||||
+ u64 val;
|
||||
+
|
||||
+ do {
|
||||
+ val = read_sysreg(cntvct_el0);
|
||||
+ } while (((val + 1) & GENMASK(10, 0)) <= 1);
|
||||
+
|
||||
+ return val;
|
||||
+}
|
||||
+#endif
|
||||
+
|
||||
#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
|
||||
DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround);
|
||||
EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
|
||||
@@ -408,6 +438,15 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = {
|
||||
.read_cntvct_el0 = arm64_1188873_read_cntvct_el0,
|
||||
},
|
||||
#endif
|
||||
+#ifdef CONFIG_SUN50I_A64_UNSTABLE_TIMER
|
||||
+ {
|
||||
+ .match_type = ate_match_dt,
|
||||
+ .id = "allwinner,sun50i-a64-unstable-timer",
|
||||
+ .desc = "Allwinner A64 timer instability",
|
||||
+ .read_cntpct_el0 = sun50i_a64_read_cntpct_el0,
|
||||
+ .read_cntvct_el0 = sun50i_a64_read_cntvct_el0,
|
||||
+ },
|
||||
+#endif
|
||||
};
|
||||
|
||||
typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *,
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
From patchwork Fri May 11 02:27:51 2018
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [2/2] arm64: dts: allwinner: a64: Enable A64 timer workaround
|
||||
From: Samuel Holland <samuel@sholland.org>
|
||||
X-Patchwork-Id: 10392889
|
||||
Message-Id: <20180511022751.9096-3-samuel@sholland.org>
|
||||
To: Maxime Ripard <maxime.ripard@bootlin.com>, Chen-Yu Tsai <wens@csie.org>,
|
||||
Catalin Marinas <catalin.marinas@arm.com>,
|
||||
Will Deacon <will.deacon@arm.com>,
|
||||
Daniel Lezcano <daniel.lezcano@linaro.org>,
|
||||
Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <marc.zyngier@arm.com>
|
||||
Cc: linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,
|
||||
linux-arm-kernel@lists.infradead.org, Samuel Holland <samuel@sholland.org>
|
||||
Date: Thu, 10 May 2018 21:27:51 -0500
|
||||
|
||||
As instability in the architectural timer has been observed on multiple
|
||||
devices using this SoC, inluding the Pine64 and the Orange Pi Win,
|
||||
enable the workaround in the SoC's device tree.
|
||||
|
||||
Signed-off-by: Samuel Holland <samuel@sholland.org>
|
||||
---
|
||||
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
||||
index 1b2ef28c42bd..5202b76e9684 100644
|
||||
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
||||
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
||||
@@ -152,6 +152,7 @@
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
+ allwinner,sun50i-a64-unstable-timer;
|
||||
interrupts = <GIC_PPI 13
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||
<GIC_PPI 14
|
||||
|
|
@ -1,255 +0,0 @@
|
|||
From 99909530ec9b6e9b1b3b756a05a83fa1c7d6d4bc Mon Sep 17 00:00:00 2001
|
||||
From: Stefan Wahren <stefan.wahren@i2se.com>
|
||||
Date: Tue, 1 Jan 2019 18:29:08 +0100
|
||||
Subject: [PATCH] ARM: dts: bcm283x: Add missing GPIO line names
|
||||
|
||||
The GPIO sysfs is deprecated and disabled in the defconfig files.
|
||||
So in order to motivate the usage of the new GPIO character device API
|
||||
add the missing GPIO line names for Raspberry Pi 2 and 3.
|
||||
|
||||
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
|
||||
---
|
||||
arch/arm/boot/dts/bcm2836-rpi-2-b.dts | 66 ++++++++++++++++++++
|
||||
arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts | 70 ++++++++++++++++++++++
|
||||
arch/arm/boot/dts/bcm2837-rpi-3-b.dts | 70 ++++++++++++++++++++++
|
||||
3 files changed, 206 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
|
||||
index 871fc4a558cf..7b4e651bafdd 100644
|
||||
--- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
|
||||
+++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
|
||||
@@ -28,6 +28,72 @@
|
||||
};
|
||||
|
||||
&gpio {
|
||||
+ /*
|
||||
+ * Taken from rpi_SCH_2b_1p2_reduced.pdf and
|
||||
+ * the official GPU firmware DT blob.
|
||||
+ *
|
||||
+ * Legend:
|
||||
+ * "NC" = not connected (no rail from the SoC)
|
||||
+ * "FOO" = GPIO line named "FOO" on the schematic
|
||||
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
|
||||
+ */
|
||||
+ gpio-line-names = "ID_SDA",
|
||||
+ "ID_SCL",
|
||||
+ "SDA1",
|
||||
+ "SCL1",
|
||||
+ "GPIO_GCLK",
|
||||
+ "GPIO5",
|
||||
+ "GPIO6",
|
||||
+ "SPI_CE1_N",
|
||||
+ "SPI_CE0_N",
|
||||
+ "SPI_MISO",
|
||||
+ "SPI_MOSI",
|
||||
+ "SPI_SCLK",
|
||||
+ "GPIO12",
|
||||
+ "GPIO13",
|
||||
+ /* Serial port */
|
||||
+ "TXD0",
|
||||
+ "RXD0",
|
||||
+ "GPIO16",
|
||||
+ "GPIO17",
|
||||
+ "GPIO18",
|
||||
+ "GPIO19",
|
||||
+ "GPIO20",
|
||||
+ "GPIO21",
|
||||
+ "GPIO22",
|
||||
+ "GPIO23",
|
||||
+ "GPIO24",
|
||||
+ "GPIO25",
|
||||
+ "GPIO26",
|
||||
+ "GPIO27",
|
||||
+ "SDA0",
|
||||
+ "SCL0",
|
||||
+ "", /* GPIO30 */
|
||||
+ "LAN_RUN",
|
||||
+ "CAM_GPIO1",
|
||||
+ "", /* GPIO33 */
|
||||
+ "", /* GPIO34 */
|
||||
+ "PWR_LOW_N",
|
||||
+ "", /* GPIO36 */
|
||||
+ "", /* GPIO37 */
|
||||
+ "USB_LIMIT",
|
||||
+ "", /* GPIO39 */
|
||||
+ "PWM0_OUT",
|
||||
+ "CAM_GPIO0",
|
||||
+ "SMPS_SCL",
|
||||
+ "SMPS_SDA",
|
||||
+ "ETHCLK",
|
||||
+ "PWM1_OUT",
|
||||
+ "HDMI_HPD_N",
|
||||
+ "STATUS_LED",
|
||||
+ /* Used by SD Card */
|
||||
+ "SD_CLK_R",
|
||||
+ "SD_CMD_R",
|
||||
+ "SD_DATA0_R",
|
||||
+ "SD_DATA1_R",
|
||||
+ "SD_DATA2_R",
|
||||
+ "SD_DATA3_R";
|
||||
+
|
||||
pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
|
||||
|
||||
/* I2S interface */
|
||||
diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
|
||||
index 94886fcaf0b9..9358f8481f36 100644
|
||||
--- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
|
||||
+++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
|
||||
@@ -52,6 +52,76 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&gpio {
|
||||
+ /*
|
||||
+ * Taken from rpi_SCH_3bplus_1p0_reduced.pdf and
|
||||
+ * the official GPU firmware DT blob.
|
||||
+ *
|
||||
+ * Legend:
|
||||
+ * "NC" = not connected (no rail from the SoC)
|
||||
+ * "FOO" = GPIO line named "FOO" on the schematic
|
||||
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
|
||||
+ */
|
||||
+ gpio-line-names = "ID_SDA",
|
||||
+ "ID_SCL",
|
||||
+ "SDA1",
|
||||
+ "SCL1",
|
||||
+ "GPIO_GCLK",
|
||||
+ "GPIO5",
|
||||
+ "GPIO6",
|
||||
+ "SPI_CE1_N",
|
||||
+ "SPI_CE0_N",
|
||||
+ "SPI_MISO",
|
||||
+ "SPI_MOSI",
|
||||
+ "SPI_SCLK",
|
||||
+ "GPIO12",
|
||||
+ "GPIO13",
|
||||
+ /* Serial port */
|
||||
+ "TXD1",
|
||||
+ "RXD1",
|
||||
+ "GPIO16",
|
||||
+ "GPIO17",
|
||||
+ "GPIO18",
|
||||
+ "GPIO19",
|
||||
+ "GPIO20",
|
||||
+ "GPIO21",
|
||||
+ "GPIO22",
|
||||
+ "GPIO23",
|
||||
+ "GPIO24",
|
||||
+ "GPIO25",
|
||||
+ "GPIO26",
|
||||
+ "GPIO27",
|
||||
+ "HDMI_HPD_N",
|
||||
+ "STATUS_LED_G",
|
||||
+ /* Used by BT module */
|
||||
+ "CTS0",
|
||||
+ "RTS0",
|
||||
+ "TXD0",
|
||||
+ "RXD0",
|
||||
+ /* Used by Wifi */
|
||||
+ "SD1_CLK",
|
||||
+ "SD1_CMD",
|
||||
+ "SD1_DATA0",
|
||||
+ "SD1_DATA1",
|
||||
+ "SD1_DATA2",
|
||||
+ "SD1_DATA3",
|
||||
+ "PWM0_OUT",
|
||||
+ "PWM1_OUT",
|
||||
+ "ETHCLK",
|
||||
+ "WIFI_CLK",
|
||||
+ "SDA0",
|
||||
+ "SCL0",
|
||||
+ "SMPS_SCL",
|
||||
+ "SMPS_SDA",
|
||||
+ /* Used by SD Card */
|
||||
+ "SD_CLK_R",
|
||||
+ "SD_CMD_R",
|
||||
+ "SD_DATA0_R",
|
||||
+ "SD_DATA1_R",
|
||||
+ "SD_DATA2_R",
|
||||
+ "SD_DATA3_R";
|
||||
+};
|
||||
+
|
||||
&hdmi {
|
||||
hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
|
||||
index 31b1c03e0ff7..ce71f578c51a 100644
|
||||
--- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
|
||||
+++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
|
||||
@@ -47,6 +47,76 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&gpio {
|
||||
+ /*
|
||||
+ * Taken from rpi_SCH_3b_1p2_reduced.pdf and
|
||||
+ * the official GPU firmware DT blob.
|
||||
+ *
|
||||
+ * Legend:
|
||||
+ * "NC" = not connected (no rail from the SoC)
|
||||
+ * "FOO" = GPIO line named "FOO" on the schematic
|
||||
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
|
||||
+ */
|
||||
+ gpio-line-names = "ID_SDA",
|
||||
+ "ID_SCL",
|
||||
+ "SDA1",
|
||||
+ "SCL1",
|
||||
+ "GPIO_GCLK",
|
||||
+ "GPIO5",
|
||||
+ "GPIO6",
|
||||
+ "SPI_CE1_N",
|
||||
+ "SPI_CE0_N",
|
||||
+ "SPI_MISO",
|
||||
+ "SPI_MOSI",
|
||||
+ "SPI_SCLK",
|
||||
+ "GPIO12",
|
||||
+ "GPIO13",
|
||||
+ /* Serial port */
|
||||
+ "TXD1",
|
||||
+ "RXD1",
|
||||
+ "GPIO16",
|
||||
+ "GPIO17",
|
||||
+ "GPIO18",
|
||||
+ "GPIO19",
|
||||
+ "GPIO20",
|
||||
+ "GPIO21",
|
||||
+ "GPIO22",
|
||||
+ "GPIO23",
|
||||
+ "GPIO24",
|
||||
+ "GPIO25",
|
||||
+ "GPIO26",
|
||||
+ "GPIO27",
|
||||
+ "", /* GPIO 28 */
|
||||
+ "LAN_RUN_BOOT",
|
||||
+ /* Used by BT module */
|
||||
+ "CTS0",
|
||||
+ "RTS0",
|
||||
+ "TXD0",
|
||||
+ "RXD0",
|
||||
+ /* Used by Wifi */
|
||||
+ "SD1_CLK",
|
||||
+ "SD1_CMD",
|
||||
+ "SD1_DATA0",
|
||||
+ "SD1_DATA1",
|
||||
+ "SD1_DATA2",
|
||||
+ "SD1_DATA3",
|
||||
+ "PWM0_OUT",
|
||||
+ "PWM1_OUT",
|
||||
+ "ETHCLK",
|
||||
+ "WIFI_CLK",
|
||||
+ "SDA0",
|
||||
+ "SCL0",
|
||||
+ "SMPS_SCL",
|
||||
+ "SMPS_SDA",
|
||||
+ /* Used by SD Card */
|
||||
+ "SD_CLK_R",
|
||||
+ "SD_CMD_R",
|
||||
+ "SD_DATA0_R",
|
||||
+ "SD_DATA1_R",
|
||||
+ "SD_DATA2_R",
|
||||
+ "SD_DATA3_R";
|
||||
+};
|
||||
+
|
||||
&pwm {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>;
|
||||
|
|
@ -0,0 +1 @@
|
|||
CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
|
||||
|
|
@ -6034,6 +6034,7 @@ CONFIG_ST_UVIS25_SPI=m
|
|||
CONFIG_SUN50I_A64_CCU=y
|
||||
CONFIG_SUN50I_A64_UNSTABLE_TIMER=y
|
||||
CONFIG_SUN50I_DE2_BUS=y
|
||||
CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
|
||||
CONFIG_SUN50I_H6_CCU=y
|
||||
CONFIG_SUN50I_H6_R_CCU=y
|
||||
# CONFIG_SUN8I_A83T_CCU is not set
|
||||
|
|
|
|||
|
|
@ -6011,6 +6011,7 @@ CONFIG_ST_UVIS25_SPI=m
|
|||
CONFIG_SUN50I_A64_CCU=y
|
||||
CONFIG_SUN50I_A64_UNSTABLE_TIMER=y
|
||||
CONFIG_SUN50I_DE2_BUS=y
|
||||
CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
|
||||
CONFIG_SUN50I_H6_CCU=y
|
||||
CONFIG_SUN50I_H6_R_CCU=y
|
||||
# CONFIG_SUN8I_A83T_CCU is not set
|
||||
|
|
|
|||
12
kernel.spec
12
kernel.spec
|
|
@ -580,14 +580,14 @@ Patch330: bcm2837-dts-add-Raspberry-Pi-3-A.patch
|
|||
# https://patchwork.kernel.org/patch/10741809/
|
||||
Patch331: bcm2835-mmc-sdhci-iproc-handle-mmc_of_parse-errors-during-probe.patch
|
||||
|
||||
Patch332: bcm283x-Add-missing-GPIO-line-names.patch
|
||||
# https://www.spinics.net/lists/arm-kernel/msg699583.html
|
||||
Patch332: ARM-dts-bcm283x-Several-DTS-improvements.patch
|
||||
|
||||
Patch339: bcm2835-cpufreq-add-CPU-frequency-control-driver.patch
|
||||
|
||||
# Fix for AllWinner A64 Timer Errata, still not final
|
||||
# https://patchwork.kernel.org/patch/10392891/
|
||||
Patch350: arm64-arch_timer-Workaround-for-Allwinner-A64-timer-instability.patch
|
||||
Patch351: arm64-dts-allwinner-a64-Enable-A64-timer-workaround.patch
|
||||
# https://www.spinics.net/lists/arm-kernel/msg699622.html
|
||||
Patch350: Allwinner-A64-timer-workaround.patch
|
||||
|
||||
# 400 - IBM (ppc/s390x) patches
|
||||
|
||||
|
|
@ -1876,6 +1876,10 @@ fi
|
|||
#
|
||||
#
|
||||
%changelog
|
||||
* Sun Jan 13 2019 Peter Robinson <pbrobinson@fedoraproject.org>
|
||||
- Raspberry Pi updates
|
||||
- Update AllWinner A64 timer errata workaround
|
||||
|
||||
* Fri Jan 11 2019 Laura Abbott <labbott@redhat.com> - 5.0.0-0.rc1.git4.1
|
||||
- Linux v5.0-rc1-43-g1bdbe2274920
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue