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Update RISCV (riscv64) configs 

Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
This commit is contained in:
David Abdurachmanov 2019-09-18 22:11:26 +03:00
parent 98989ae15a
commit 576b1ae843
Signed by: davidlt
GPG Key ID: 8B7F1DA0E2C9FDBB
4 changed files with 6 additions and 4 deletions
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1
configs/fedora/generic/riscv/CONFIG_SPI Normal file
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@ -0,0 +1 @@
CONFIG_SPI=y

1
configs/fedora/generic/riscv/CONFIG_SPI_SIFIVE Normal file
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@ -0,0 +1 @@
CONFIG_SPI_SIFIVE=y

4
kernel-riscv64-debug.config
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@ -5046,7 +5046,6 @@ CONFIG_SPARSEMEM_MANUAL=y
CONFIG_SPI_FSL_LPSPI=m
# CONFIG_SPI_FSL_SPI is not set
# CONFIG_SPI_GPIO is not set
# CONFIG_SPI is not set
# CONFIG_SPI_LM70_LLP is not set
# CONFIG_SPI_LOOPBACK_TEST is not set
# CONFIG_SPI_MEM is not set
@ -5057,13 +5056,14 @@ CONFIG_SPI_FSL_LPSPI=m
# CONFIG_SPI_PXA2XX is not set
# CONFIG_SPI_ROCKCHIP is not set
# CONFIG_SPI_SC18IS602 is not set
# CONFIG_SPI_SIFIVE is not set
CONFIG_SPI_SIFIVE=y
# CONFIG_SPI_SLAVE is not set
# CONFIG_SPI_SPIDEV is not set
# CONFIG_SPI_TLE62X0 is not set
# CONFIG_SPI_TOPCLIFF_PCH is not set
# CONFIG_SPI_XCOMM is not set
# CONFIG_SPI_XILINX is not set
CONFIG_SPI=y
# CONFIG_SPI_ZYNQMP_GQSPI is not set
# CONFIG_SPMI is not set
# CONFIG_SPS30 is not set

4
kernel-riscv64.config
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@ -5023,7 +5023,6 @@ CONFIG_SPARSEMEM_MANUAL=y
CONFIG_SPI_FSL_LPSPI=m
# CONFIG_SPI_FSL_SPI is not set
# CONFIG_SPI_GPIO is not set
# CONFIG_SPI is not set
# CONFIG_SPI_LM70_LLP is not set
# CONFIG_SPI_LOOPBACK_TEST is not set
# CONFIG_SPI_MEM is not set
@ -5034,13 +5033,14 @@ CONFIG_SPI_FSL_LPSPI=m
# CONFIG_SPI_PXA2XX is not set
# CONFIG_SPI_ROCKCHIP is not set
# CONFIG_SPI_SC18IS602 is not set
# CONFIG_SPI_SIFIVE is not set
CONFIG_SPI_SIFIVE=y
# CONFIG_SPI_SLAVE is not set
# CONFIG_SPI_SPIDEV is not set
# CONFIG_SPI_TLE62X0 is not set
# CONFIG_SPI_TOPCLIFF_PCH is not set
# CONFIG_SPI_XCOMM is not set
# CONFIG_SPI_XILINX is not set
CONFIG_SPI=y
# CONFIG_SPI_ZYNQMP_GQSPI is not set
# CONFIG_SPMI is not set
# CONFIG_SPS30 is not set