Fix build for arm with gcc 8
This commit is contained in:
Justin M. Forbes
parent
a698721916
commit
4e95a71492
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@ -0,0 +1,164 @@
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From patchwork Fri Feb 2 15:07:34 2018
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [1/2] ARM: kvm: fix building with gcc-8
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From: Arnd Bergmann <arnd@arndb.de>
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X-Patchwork-Id: 10196985
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Message-Id: <20180202150756.420422-1-arnd@arndb.de>
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To: Christoffer Dall <christoffer.dall@linaro.org>,
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Marc Zyngier <marc.zyngier@arm.com>, Russell King <linux@armlinux.org.uk>
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Cc: Nicolas Pitre <nico@linaro.org>, Andi Kleen <ak@linux.intel.com>,
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Richard Earnshaw <rearnsha@gcc.gnu.org>,
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Tamar Christina <tnfchris@gcc.gnu.org>,
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Arnd Bergmann <arnd@arndb.de>, stable@vger.kernel.org,
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Julien Thierry <julien.thierry@arm.com>,
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linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu,
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linux-kernel@vger.kernel.org
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Date: Fri, 2 Feb 2018 16:07:34 +0100
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In banked-sr.c, we use a top-level '__asm__(".arch_extension virt")'
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statement to allow compilation of a multi-CPU kernel for ARMv6
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and older ARMv7-A that don't normally support access to the banked
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registers.
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This is considered to be a programming error by the gcc developers
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and will no longer work in gcc-8, where we now get a build error:
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/tmp/cc4Qy7GR.s:34: Error: Banked registers are not available with this architecture. -- `mrs r3,SP_usr'
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/tmp/cc4Qy7GR.s:41: Error: Banked registers are not available with this architecture. -- `mrs r3,ELR_hyp'
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/tmp/cc4Qy7GR.s:55: Error: Banked registers are not available with this architecture. -- `mrs r3,SP_svc'
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/tmp/cc4Qy7GR.s:62: Error: Banked registers are not available with this architecture. -- `mrs r3,LR_svc'
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/tmp/cc4Qy7GR.s:69: Error: Banked registers are not available with this architecture. -- `mrs r3,SPSR_svc'
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/tmp/cc4Qy7GR.s:76: Error: Banked registers are not available with this architecture. -- `mrs r3,SP_abt'
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Passign the '-march-armv7ve' flag to gcc works, and is ok here, because
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we know the functions won't ever be called on pre-ARMv7VE machines.
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Unfortunately, older compiler versions (4.8 and earlier) do not understand
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that flag, so we still need to keep the asm around.
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Backporting to stable kernels (4.6+) is needed to allow those to be built
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with future compilers as well.
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Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84129
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Fixes: 33280b4cd1dc ("ARM: KVM: Add banked registers save/restore")
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Cc: stable@vger.kernel.org
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Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
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---
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arch/arm/kvm/hyp/Makefile | 5 +++++
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arch/arm/kvm/hyp/banked-sr.c | 4 ++++
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2 files changed, 9 insertions(+)
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diff --git a/arch/arm/kvm/hyp/Makefile b/arch/arm/kvm/hyp/Makefile
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index 5638ce0c9524..63d6b404d88e 100644
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--- a/arch/arm/kvm/hyp/Makefile
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+++ b/arch/arm/kvm/hyp/Makefile
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@@ -7,6 +7,8 @@ ccflags-y += -fno-stack-protector -DDISABLE_BRANCH_PROFILING
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KVM=../../../../virt/kvm
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+CFLAGS_ARMV7VE :=$(call cc-option, -march=armv7ve)
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+
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obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/vgic-v2-sr.o
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obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/vgic-v3-sr.o
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obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/timer-sr.o
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@@ -15,7 +17,10 @@ obj-$(CONFIG_KVM_ARM_HOST) += tlb.o
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obj-$(CONFIG_KVM_ARM_HOST) += cp15-sr.o
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obj-$(CONFIG_KVM_ARM_HOST) += vfp.o
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obj-$(CONFIG_KVM_ARM_HOST) += banked-sr.o
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+CFLAGS_banked-sr.o += $(CFLAGS_ARMV7VE)
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+
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obj-$(CONFIG_KVM_ARM_HOST) += entry.o
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obj-$(CONFIG_KVM_ARM_HOST) += hyp-entry.o
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obj-$(CONFIG_KVM_ARM_HOST) += switch.o
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+CFLAGS_switch.o += $(CFLAGS_ARMV7VE)
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obj-$(CONFIG_KVM_ARM_HOST) += s2-setup.o
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diff --git a/arch/arm/kvm/hyp/banked-sr.c b/arch/arm/kvm/hyp/banked-sr.c
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index 111bda8cdebd..be4b8b0a40ad 100644
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--- a/arch/arm/kvm/hyp/banked-sr.c
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+++ b/arch/arm/kvm/hyp/banked-sr.c
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@@ -20,6 +20,10 @@
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#include <asm/kvm_hyp.h>
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+/*
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+ * gcc before 4.9 doesn't understand -march=armv7ve, so we have to
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+ * trick the assembler.
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+ */
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__asm__(".arch_extension virt");
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void __hyp_text __banked_save_state(struct kvm_cpu_context *ctxt)
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From patchwork Fri Feb 2 15:07:35 2018
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [2/2] ARM: xscale: fix gcc-8 build
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From: Arnd Bergmann <arnd@arndb.de>
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X-Patchwork-Id: 10196991
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Message-Id: <20180202150756.420422-2-arnd@arndb.de>
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To: Russell King <linux@armlinux.org.uk>
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Cc: Nicolas Pitre <nico@linaro.org>, Andi Kleen <ak@linux.intel.com>,
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Richard Earnshaw <rearnsha@gcc.gnu.org>,
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Tamar Christina <tnfchris@gcc.gnu.org>, Arnd Bergmann <arnd@arndb.de>,
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linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
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Date: Fri, 2 Feb 2018 16:07:35 +0100
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We use a hack in xscale-cp0.c to allow building it for ARMv4 while
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also using ARMv5TE and iWMMXt specific inline assembly, by
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adding a top-level asm statement.
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Unfortunately that hack no longer works with gcc-8, since it will
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revert back to the normal architecture. The recommended way of
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handling this is to use __attribute__((target("armv5te"))) on the
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functions that need it, or #pragma GCC target("arch=armv5te").
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Either of those work with gcc-8, but not earlier versions, and
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it seems worse to combine that with the old hack.
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Instead, this adds the .arch statement to each inline assembler
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statement that needs it individually. That is also slightly uglier
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than the previous hack, but it works with all compiler versions
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and documents better why we need the override in the first place.
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Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84129
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Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Acked-by: Nicolas Pitre <nico@linaro.org>
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---
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arch/arm/kernel/xscale-cp0.c | 7 ++++---
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1 file changed, 4 insertions(+), 3 deletions(-)
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diff --git a/arch/arm/kernel/xscale-cp0.c b/arch/arm/kernel/xscale-cp0.c
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index 77a2eef72115..e06a2f6dac4f 100644
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--- a/arch/arm/kernel/xscale-cp0.c
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+++ b/arch/arm/kernel/xscale-cp0.c
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@@ -17,11 +17,10 @@
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#include <asm/thread_notify.h>
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#include <asm/cputype.h>
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-asm(" .arch armv5te\n");
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-
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static inline void dsp_save_state(u32 *state)
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{
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__asm__ __volatile__ (
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+ ".arch armv5te\n\t"
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"mrrc p0, 0, %0, %1, c0\n"
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: "=r" (state[0]), "=r" (state[1]));
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}
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@@ -29,6 +28,7 @@ static inline void dsp_save_state(u32 *state)
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static inline void dsp_load_state(u32 *state)
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{
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__asm__ __volatile__ (
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+ ".arch armv5te\n\t"
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"mcrr p0, 0, %0, %1, c0\n"
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: : "r" (state[0]), "r" (state[1]));
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}
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@@ -134,7 +134,8 @@ static int __init cpu_has_iwmmxt(void)
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* tmrrc %0, %1, wR0
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*/
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__asm__ __volatile__ (
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- "mcrr p0, 0, %2, %3, c0\n"
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+ ".arch armv5te\n\t"
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+ "mcrr p0, 0, %2, %3, c0\n\t"
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"mrrc p0, 0, %0, %1, c0\n"
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: "=r" (lo), "=r" (hi)
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: "r" (0), "r" (0x100));
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@ -507,6 +507,8 @@ Patch001: 0001-tools-lib-subcmd-pager.c-do-not-alias-select-params.patch
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# ongoing complaint, full discussion delayed until ksummit/plumbers
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Patch002: 0001-iio-Use-event-header-from-kernel-tree.patch
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Patch003: arm-gcc-8-build-fixes.patch
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%if !%{nopatches}
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# Git trees.
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