arm: update brcmstm pcie patch to latest
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Peter Robinson
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418b602465
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@ -1,27 +1,27 @@
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Subject: [PATCH v4 1/8] dt-bindings: PCI: Add bindings for brcmstb's PCIe
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Subject: [PATCH v5 1/6] dt-bindings: PCI: Add bindings for brcmstb's PCIe
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device
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Subject: [PATCH v4 2/8] ARM: dts: bcm2711: Enable PCIe controller
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Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
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Subject: [PATCH v5 2/6] ARM: dts: bcm2711: Enable PCIe controller
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|
|||
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
|
||||
---
|
||||
|
||||
Changes since v4:
|
||||
- Rebase commit taking into account genet support series
|
||||
|
||||
Changes since v3:
|
||||
- Remove unwarranted comment
|
||||
|
||||
|
|
@ -353,22 +363,20 @@ Changes since v2:
|
|||
Changes since v1:
|
||||
- remove linux,pci-domain
|
||||
|
||||
arch/arm/boot/dts/bcm2711.dtsi | 37 ++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 37 insertions(+)
|
||||
[1] https://lkml.org/lkml/2019/11/21/235
|
||||
|
||||
arch/arm/boot/dts/bcm2711.dtsi | 31 ++++++++++++++++++++++++++++++-
|
||||
1 file changed, 30 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
|
||||
index 667658497898..5b61cd915f2b 100644
|
||||
index e2f6ffb00aa9..b56388ce1216 100644
|
||||
--- a/arch/arm/boot/dts/bcm2711.dtsi
|
||||
+++ b/arch/arm/boot/dts/bcm2711.dtsi
|
||||
@@ -288,6 +288,43 @@ IRQ_TYPE_LEVEL_LOW)>,
|
||||
arm,cpu-registers-not-fw-configured;
|
||||
};
|
||||
@@ -331,7 +331,36 @@ scb {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
+ scb {
|
||||
+ compatible = "simple-bus";
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
- ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>;
|
||||
+ ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>,
|
||||
+ <0x6 0x00000000 0x6 0x00000000 0x40000000>;
|
||||
+
|
||||
|
|
@ -399,36 +407,34 @@ index 667658497898..5b61cd915f2b 100644
|
|||
+ 0x0 0xc0000000>;
|
||||
+ brcm,enable-ssc;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
cpus: cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
genet: ethernet@7d580000 {
|
||||
compatible = "brcm,bcm2711-genet-v5";
|
||||
|
||||
From patchwork Tue Dec 3 11:47:36 2019
|
||||
From patchwork Mon Dec 16 11:01:09 2019
|
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Content-Type: text/plain; charset="utf-8"
|
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X-Patchwork-Submitter: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
|
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X-Patchwork-Id: 11271061
|
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X-Patchwork-Id: 11293817
|
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|
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To: andrew.murray@arm.com, maz@kernel.org, linux-kernel@vger.kernel.org,
|
||||
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
|
||||
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|
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bcm-kernel-feedback-list@broadcom.com, Eric Anholt <eric@anholt.net>,
|
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|
||||
Subject: [PATCH v4 3/8] PCI: brcmstb: Add Broadcom STB PCIe host controller
|
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bcm-kernel-feedback-list@broadcom.com,
|
||||
Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
|
||||
Subject: [PATCH v5 3/6] PCI: brcmstb: Add Broadcom STB PCIe host controller
|
||||
driver
|
||||
Date: Tue, 3 Dec 2019 12:47:36 +0100
|
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Message-Id: <20191203114743.1294-4-nsaenzjulienne@suse.de>
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Cc: mbrugger@suse.com, linux-pci@vger.kernel.org, phil@raspberrypi.org,
|
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jeremy.linton@arm.com, wahrenst@gmx.net, james.quinlan@broadcom.com,
|
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@ -514,6 +522,7 @@ Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
|
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Co-developed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
|
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Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
|
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Reviewed-by: Andrew Murray <andrew.murray@arm.com>
|
||||
Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
|
||||
---
|
||||
|
||||
Changes since v3:
|
||||
|
|
@ -1352,30 +1361,30 @@ index 000000000000..dd681164faa0
|
|||
+MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");
|
||||
+MODULE_AUTHOR("Broadcom");
|
||||
|
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From patchwork Tue Dec 3 11:47:37 2019
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|
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|
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@ -1860,4 +1871,125 @@ index dd681164faa0..7ba06a0e1a71 100644
|
|||
bridge->busnr = 0;
|
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bridge->ops = &brcm_pcie_ops;
|
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|
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|
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To: andrew.murray@arm.com,
|
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|
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|
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Subject: [PATCH v5 6/6] arm64: defconfig: Enable Broadcom's STB PCIe
|
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|
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pts rule name description
|
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---- ----------------------
|
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--------------------------------------------------
|
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0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3)
|
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[195.135.220.15 listed in wl.mailspike.net]
|
||||
-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/,
|
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medium trust [195.135.220.15 listed in list.dnswl.org]
|
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0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record
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|
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linux-pci@vger.kernel.org, phil@raspberrypi.org, jeremy.linton@arm.com,
|
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mbrugger@suse.com, wahrenst@gmx.net, james.quinlan@broadcom.com,
|
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Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>,
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|
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|
||||
For now mainly used in the Raspberry Pi 4.
|
||||
|
||||
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
|
||||
---
|
||||
arch/arm64/configs/defconfig | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
|
||||
index 2646fc76b8db..2b80980ef576 100644
|
||||
--- a/arch/arm64/configs/defconfig
|
||||
+++ b/arch/arm64/configs/defconfig
|
||||
@@ -192,6 +192,7 @@ CONFIG_PCIE_ALTERA_MSI=y
|
||||
CONFIG_PCI_HOST_THUNDER_PEM=y
|
||||
CONFIG_PCI_HOST_THUNDER_ECAM=y
|
||||
CONFIG_PCIE_ROCKCHIP_HOST=m
|
||||
+CONFIG_PCIE_BRCMSTB=m
|
||||
CONFIG_PCI_LAYERSCAPE=y
|
||||
CONFIG_PCI_HISI=y
|
||||
CONFIG_PCIE_QCOM=y
|
||||
|
|
|
|||
Loading…
Reference in New Issue