diff --git a/0001-ahci-Annotate-PCI-ids-for-mobile-Intel-chipsets-as-s.patch b/0001-ahci-Annotate-PCI-ids-for-mobile-Intel-chipsets-as-s.patch
new file mode 100644
index 000000000..d73ce05c6
--- /dev/null
+++ b/0001-ahci-Annotate-PCI-ids-for-mobile-Intel-chipsets-as-s.patch
@@ -0,0 +1,106 @@
+From cb1072f66e72eda65a8f7ac37d32c9f4217af6ba Mon Sep 17 00:00:00 2001
+From: Hans de Goede <hdegoede@redhat.com>
+Date: Tue, 21 Nov 2017 14:44:15 +0100
+Subject: [PATCH 1/3] ahci: Annotate PCI ids for mobile Intel chipsets as such
+
+Intel uses different SATA PCI ids for the Desktop and Mobile SKUs of their
+chipsets. For older models the comment describing which chipset the PCI id
+is for, aksi indicates when we're dealing with a mobile SKU. Extend the
+comments for recent chipsets to also indicate mobile SKUs.
+
+The information this commit adds comes from Intel's chipset datasheets.
+
+This commit is a preparation patch for allowing a different default
+sata link powermanagement policy for mobile chipsets.
+
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+---
+ drivers/ata/ahci.c | 32 ++++++++++++++++----------------
+ 1 file changed, 16 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
+index 5443cb71d7ba..9d842ff6ec51 100644
+--- a/drivers/ata/ahci.c
++++ b/drivers/ata/ahci.c
+@@ -268,9 +268,9 @@ static const struct pci_device_id ahci_pci_tbl[] = {
+ 	{ PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
+ 	{ PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
+-	{ PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
++	{ PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH M AHCI */
+ 	{ PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
+-	{ PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
++	{ PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH M RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
+ 	{ PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
+ 	{ PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
+@@ -293,9 +293,9 @@ static const struct pci_device_id ahci_pci_tbl[] = {
+ 	{ PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
+ 	{ PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
+ 	{ PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
+-	{ PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
++	{ PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT M AHCI */
+ 	{ PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
+-	{ PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
++	{ PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT M RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
+@@ -304,20 +304,20 @@ static const struct pci_device_id ahci_pci_tbl[] = {
+ 	{ PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
+ 	{ PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
+-	{ PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
++	{ PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point M AHCI */
+ 	{ PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
+-	{ PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
++	{ PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point M RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
+-	{ PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
++	{ PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point M AHCI */
+ 	{ PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
+-	{ PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
++	{ PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point M RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
+-	{ PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
++	{ PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point M RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
+-	{ PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
++	{ PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point M RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
+ 	{ PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
+ 	{ PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
+@@ -358,21 +358,21 @@ static const struct pci_device_id ahci_pci_tbl[] = {
+ 	{ PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
+-	{ PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
++	{ PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series M AHCI */
+ 	{ PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
+-	{ PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
++	{ PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series M RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
+-	{ PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
++	{ PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series M RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
+-	{ PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
++	{ PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series M RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
+ 	{ PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
+ 	{ PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
+-	{ PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
++	{ PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H M AHCI */
+ 	{ PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
+ 	{ PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
+-	{ PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
++	{ PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H M RAID */
+ 	{ PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
+ 	{ PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
+-- 
+2.14.3
+
diff --git a/0002-ahci-Add-PCI-ids-for-Intel-Bay-Trail-Cherry-Trail-an.patch b/0002-ahci-Add-PCI-ids-for-Intel-Bay-Trail-Cherry-Trail-an.patch
new file mode 100644
index 000000000..f27812b85
--- /dev/null
+++ b/0002-ahci-Add-PCI-ids-for-Intel-Bay-Trail-Cherry-Trail-an.patch
@@ -0,0 +1,33 @@
+From eab582db4b6c04a20a8bd792faa9ebf7adf1ec17 Mon Sep 17 00:00:00 2001
+From: Hans de Goede <hdegoede@redhat.com>
+Date: Mon, 27 Nov 2017 12:07:34 +0100
+Subject: [PATCH 2/3] ahci: Add PCI ids for Intel Bay Trail, Cherry Trail and
+ Apollo Lake AHCI
+
+Add PCI ids for Intel Bay Trail, Cherry Trail and Apollo Lake AHCI
+SATA controllers. This commit is a preparation patch for allowing a
+different default sata link powermanagement policy for mobile chipsets.
+
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+---
+ drivers/ata/ahci.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
+index 9d842ff6ec51..844f697bedbf 100644
+--- a/drivers/ata/ahci.c
++++ b/drivers/ata/ahci.c
+@@ -386,6 +386,10 @@ static const struct pci_device_id ahci_pci_tbl[] = {
+ 	{ PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
+ 	{ PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
+ 	{ PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
++	{ PCI_VDEVICE(INTEL, 0x0f22), board_ahci }, /* Bay Trail AHCI */
++	{ PCI_VDEVICE(INTEL, 0x0f23), board_ahci }, /* Bay Trail AHCI */
++	{ PCI_VDEVICE(INTEL, 0x22a3), board_ahci }, /* Cherry Trail AHCI */
++	{ PCI_VDEVICE(INTEL, 0x5ae3), board_ahci }, /* Apollo Lake AHCI */
+ 
+ 	/* JMicron 360/1/3/5/6, match class to avoid IDE function */
+ 	{ PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+-- 
+2.14.3
+
diff --git a/0003-ahci-Allow-setting-a-default-LPM-policy-for-mobile-c.patch b/0003-ahci-Allow-setting-a-default-LPM-policy-for-mobile-c.patch
new file mode 100644
index 000000000..fe7edde8f
--- /dev/null
+++ b/0003-ahci-Allow-setting-a-default-LPM-policy-for-mobile-c.patch
@@ -0,0 +1,274 @@
+From 262135cf058c28d248b997bd11b2c124e27d8d47 Mon Sep 17 00:00:00 2001
+From: Hans de Goede <hdegoede@redhat.com>
+Date: Mon, 27 Nov 2017 15:32:01 +0100
+Subject: [PATCH 3/3] ahci: Allow setting a default LPM policy for mobile
+ chipsets
+
+On many laptops setting a different LPM policy then unknown /
+max_performance can lead to power-savings of 1.0 - 1.5 Watts (when idle).
+
+Modern ultrabooks idle around 6W (at 50% screen brightness), 1.0 - 1.5W
+is a significant chunk of this.
+
+There are some performance / latency costs to enabling LPM by default,
+so it is desirable to make it possible to set a different LPM policy
+for mobile / laptop variants of chipsets / "South Bridges" vs their
+desktop / server counterparts. Also enabling LPM by default is not
+entirely without risk of regressions. At least min_power is known to
+cause issues with some disks, including some reports of data corruption.
+
+This commits adds a new ahci.mobile_lpm_policy kernel cmdline option,
+which defaults to a new SATA_MOBILE_LPM_POLICY Kconfig option so that
+Linux distributions can choose to set a LPM policy for mobile chipsets
+by default.
+
+The reason to have both a kernel cmdline option and a Kconfig default
+value for it, is to allow easy overriding of the default to allow
+trouble-shooting without needing to rebuild the kernel.
+
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+---
+Changes in v2:
+-Remove .config changes from the patch
+---
+ drivers/ata/Kconfig | 19 +++++++++++
+ drivers/ata/ahci.c  | 97 +++++++++++++++++++++++++++++++----------------------
+ drivers/ata/ahci.h  |  3 ++
+ 3 files changed, 78 insertions(+), 41 deletions(-)
+
+diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
+index cb5339166563..b3fad5663aeb 100644
+--- a/drivers/ata/Kconfig
++++ b/drivers/ata/Kconfig
+@@ -92,6 +92,25 @@ config SATA_AHCI
+ 
+ 	  If unsure, say N.
+ 
++config SATA_MOBILE_LPM_POLICY
++	int "Default SATA Link Power Management policy for mobile chipsets"
++	range 0 4
++	default 0
++	depends on SATA_AHCI
++	help
++	  Select the Default SATA Link Power Management (LPM) policy to use
++	  for mobile / laptop variants of chipsets / "South Bridges".
++
++	  The value set has the following meanings:
++		0 => Keep firmware settings
++		1 => Maximum performance
++		2 => Medium power
++		3 => Medium power with Device Initiated PM enabled
++		4 => Minimum power
++
++	  Note "Minimum power" is known to cause issues, including disk
++	  corruption, with some disks and should not be used.
++
+ config SATA_AHCI_PLATFORM
+ 	tristate "Platform AHCI SATA support"
+ 	help
+diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
+index 844f697bedbf..8e910fae8892 100644
+--- a/drivers/ata/ahci.c
++++ b/drivers/ata/ahci.c
+@@ -65,6 +65,7 @@ enum board_ids {
+ 	/* board IDs by feature in alphabetical order */
+ 	board_ahci,
+ 	board_ahci_ign_iferr,
++	board_ahci_mobile,
+ 	board_ahci_nomsi,
+ 	board_ahci_noncq,
+ 	board_ahci_nosntf,
+@@ -140,6 +141,13 @@ static const struct ata_port_info ahci_port_info[] = {
+ 		.udma_mask	= ATA_UDMA6,
+ 		.port_ops	= &ahci_ops,
+ 	},
++	[board_ahci_mobile] = {
++		AHCI_HFLAGS	(AHCI_HFLAG_IS_MOBILE),
++		.flags		= AHCI_FLAG_COMMON,
++		.pio_mask	= ATA_PIO4,
++		.udma_mask	= ATA_UDMA6,
++		.port_ops	= &ahci_ops,
++	},
+ 	[board_ahci_nomsi] = {
+ 		AHCI_HFLAGS	(AHCI_HFLAG_NO_MSI),
+ 		.flags		= AHCI_FLAG_COMMON,
+@@ -252,13 +260,13 @@ static const struct pci_device_id ahci_pci_tbl[] = {
+ 	{ PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
+ 	{ PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
+ 	{ PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
+-	{ PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
+-	{ PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
+-	{ PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
+-	{ PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
+-	{ PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
++	{ PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
++	{ PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
++	{ PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
++	{ PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
++	{ PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
+ 	{ PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
+-	{ PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
++	{ PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
+ 	{ PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
+ 	{ PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
+ 	{ PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
+@@ -268,9 +276,9 @@ static const struct pci_device_id ahci_pci_tbl[] = {
+ 	{ PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
+ 	{ PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
+-	{ PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH M AHCI */
++	{ PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
+ 	{ PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
+-	{ PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH M RAID */
++	{ PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
+ 	{ PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
+ 	{ PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
+@@ -293,9 +301,9 @@ static const struct pci_device_id ahci_pci_tbl[] = {
+ 	{ PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
+ 	{ PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
+ 	{ PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
+-	{ PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT M AHCI */
++	{ PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
+ 	{ PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
+-	{ PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT M RAID */
++	{ PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
+@@ -304,28 +312,28 @@ static const struct pci_device_id ahci_pci_tbl[] = {
+ 	{ PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
+ 	{ PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
+-	{ PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point M AHCI */
++	{ PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
+ 	{ PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
+-	{ PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point M RAID */
++	{ PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
+-	{ PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point M AHCI */
++	{ PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
+ 	{ PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
+-	{ PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point M RAID */
++	{ PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
+-	{ PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point M RAID */
++	{ PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
+-	{ PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point M RAID */
+-	{ PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
+-	{ PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
+-	{ PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
+-	{ PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
+-	{ PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
+-	{ PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
+-	{ PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
+-	{ PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
++	{ PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
++	{ PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
++	{ PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
++	{ PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
++	{ PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
++	{ PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
++	{ PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
++	{ PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
++	{ PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
+ 	{ PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
+ 	{ PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
+@@ -353,26 +361,26 @@ static const struct pci_device_id ahci_pci_tbl[] = {
+ 	{ PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
+-	{ PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
+-	{ PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
+-	{ PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
+-	{ PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
++	{ PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
++	{ PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
++	{ PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
++	{ PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
+-	{ PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series M AHCI */
++	{ PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
+ 	{ PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
+-	{ PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series M RAID */
++	{ PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
+-	{ PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series M RAID */
++	{ PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
+-	{ PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series M RAID */
+-	{ PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
+-	{ PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
+-	{ PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
++	{ PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
++	{ PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
++	{ PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
++	{ PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
+ 	{ PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
+-	{ PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H M AHCI */
++	{ PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
+ 	{ PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
+ 	{ PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
+-	{ PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H M RAID */
++	{ PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
+ 	{ PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
+ 	{ PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
+@@ -386,10 +394,10 @@ static const struct pci_device_id ahci_pci_tbl[] = {
+ 	{ PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
+ 	{ PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
+ 	{ PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
+-	{ PCI_VDEVICE(INTEL, 0x0f22), board_ahci }, /* Bay Trail AHCI */
+-	{ PCI_VDEVICE(INTEL, 0x0f23), board_ahci }, /* Bay Trail AHCI */
+-	{ PCI_VDEVICE(INTEL, 0x22a3), board_ahci }, /* Cherry Trail AHCI */
+-	{ PCI_VDEVICE(INTEL, 0x5ae3), board_ahci }, /* Apollo Lake AHCI */
++	{ PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
++	{ PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
++	{ PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
++	{ PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
+ 
+ 	/* JMicron 360/1/3/5/6, match class to avoid IDE function */
+ 	{ PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+@@ -597,6 +605,9 @@ static int marvell_enable = 1;
+ module_param(marvell_enable, int, 0644);
+ MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
+ 
++static int mobile_lpm_policy = CONFIG_SATA_MOBILE_LPM_POLICY;
++module_param(mobile_lpm_policy, int, 0644);
++MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
+ 
+ static void ahci_pci_save_initial_config(struct pci_dev *pdev,
+ 					 struct ahci_host_priv *hpriv)
+@@ -1732,6 +1743,10 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
+ 		if (ap->flags & ATA_FLAG_EM)
+ 			ap->em_message_type = hpriv->em_msg_type;
+ 
++		if ((hpriv->flags & AHCI_HFLAG_IS_MOBILE) &&
++		    mobile_lpm_policy >= ATA_LPM_UNKNOWN &&
++		    mobile_lpm_policy <= ATA_LPM_MIN_POWER)
++			ap->target_lpm_policy = mobile_lpm_policy;
+ 
+ 		/* disabled/not-implemented port */
+ 		if (!(hpriv->port_map & (1 << i)))
+diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
+index 749fd94441b0..a9d996e17d75 100644
+--- a/drivers/ata/ahci.h
++++ b/drivers/ata/ahci.h
+@@ -251,6 +251,9 @@ enum {
+ 	AHCI_HFLAG_YES_ALPM		= (1 << 23), /* force ALPM cap on */
+ 	AHCI_HFLAG_NO_WRITE_TO_RO	= (1 << 24), /* don't write to read
+ 							only registers */
++	AHCI_HFLAG_IS_MOBILE		= (1 << 25), /* mobile chipset, use
++							SATA_MOBILE_LPM_POLICY
++							as default lpm_policy */
+ 
+ 	/* ap->flags bits */
+ 
+-- 
+2.14.3
+
diff --git a/configs/base-generic/CONFIG_SATA_MOBILE_LPM_POLICY b/configs/base-generic/CONFIG_SATA_MOBILE_LPM_POLICY
new file mode 100644
index 000000000..17ae48a01
--- /dev/null
+++ b/configs/base-generic/CONFIG_SATA_MOBILE_LPM_POLICY
@@ -0,0 +1 @@
+CONFIG_SATA_MOBILE_LPM_POLICY=3
diff --git a/kernel-aarch64-debug.config b/kernel-aarch64-debug.config
index 44f165806..6b15480e1 100644
--- a/kernel-aarch64-debug.config
+++ b/kernel-aarch64-debug.config
@@ -4667,6 +4667,7 @@ CONFIG_SATA_AHCI=y
 # CONFIG_SATA_DWC is not set
 # CONFIG_SATA_HIGHBANK is not set
 # CONFIG_SATA_INIC162X is not set
+CONFIG_SATA_MOBILE_LPM_POLICY=3
 CONFIG_SATA_MV=m
 # CONFIG_SATA_NV is not set
 CONFIG_SATA_PMP=y
diff --git a/kernel-aarch64.config b/kernel-aarch64.config
index 52144db1c..c3900be9d 100644
--- a/kernel-aarch64.config
+++ b/kernel-aarch64.config
@@ -4645,6 +4645,7 @@ CONFIG_SATA_AHCI=y
 # CONFIG_SATA_DWC is not set
 # CONFIG_SATA_HIGHBANK is not set
 # CONFIG_SATA_INIC162X is not set
+CONFIG_SATA_MOBILE_LPM_POLICY=3
 CONFIG_SATA_MV=m
 # CONFIG_SATA_NV is not set
 CONFIG_SATA_PMP=y
diff --git a/kernel-armv7hl-debug.config b/kernel-armv7hl-debug.config
index 9a013793e..e05481570 100644
--- a/kernel-armv7hl-debug.config
+++ b/kernel-armv7hl-debug.config
@@ -5021,6 +5021,7 @@ CONFIG_SATA_AHCI=y
 # CONFIG_SATA_DWC is not set
 CONFIG_SATA_HIGHBANK=m
 # CONFIG_SATA_INIC162X is not set
+CONFIG_SATA_MOBILE_LPM_POLICY=3
 CONFIG_SATA_MV=m
 # CONFIG_SATA_NV is not set
 CONFIG_SATA_PMP=y
diff --git a/kernel-armv7hl-lpae-debug.config b/kernel-armv7hl-lpae-debug.config
index dc0960df5..d7640bb34 100644
--- a/kernel-armv7hl-lpae-debug.config
+++ b/kernel-armv7hl-lpae-debug.config
@@ -4715,6 +4715,7 @@ CONFIG_SATA_AHCI=y
 # CONFIG_SATA_DWC is not set
 CONFIG_SATA_HIGHBANK=m
 # CONFIG_SATA_INIC162X is not set
+CONFIG_SATA_MOBILE_LPM_POLICY=3
 CONFIG_SATA_MV=m
 # CONFIG_SATA_NV is not set
 CONFIG_SATA_PMP=y
diff --git a/kernel-armv7hl-lpae.config b/kernel-armv7hl-lpae.config
index ce1c2057c..18e8cdfd9 100644
--- a/kernel-armv7hl-lpae.config
+++ b/kernel-armv7hl-lpae.config
@@ -4693,6 +4693,7 @@ CONFIG_SATA_AHCI=y
 # CONFIG_SATA_DWC is not set
 CONFIG_SATA_HIGHBANK=m
 # CONFIG_SATA_INIC162X is not set
+CONFIG_SATA_MOBILE_LPM_POLICY=3
 CONFIG_SATA_MV=m
 # CONFIG_SATA_NV is not set
 CONFIG_SATA_PMP=y
diff --git a/kernel-armv7hl.config b/kernel-armv7hl.config
index 5db29a722..9530243dc 100644
--- a/kernel-armv7hl.config
+++ b/kernel-armv7hl.config
@@ -4999,6 +4999,7 @@ CONFIG_SATA_AHCI=y
 # CONFIG_SATA_DWC is not set
 CONFIG_SATA_HIGHBANK=m
 # CONFIG_SATA_INIC162X is not set
+CONFIG_SATA_MOBILE_LPM_POLICY=3
 CONFIG_SATA_MV=m
 # CONFIG_SATA_NV is not set
 CONFIG_SATA_PMP=y
diff --git a/kernel-i686-PAE.config b/kernel-i686-PAE.config
index 8c2aaece9..638b83c95 100644
--- a/kernel-i686-PAE.config
+++ b/kernel-i686-PAE.config
@@ -4368,6 +4368,7 @@ CONFIG_SATA_AHCI=y
 # CONFIG_SATA_DWC is not set
 # CONFIG_SATA_HIGHBANK is not set
 CONFIG_SATA_INIC162X=m
+CONFIG_SATA_MOBILE_LPM_POLICY=3
 CONFIG_SATA_MV=m
 CONFIG_SATA_NV=m
 CONFIG_SATA_PMP=y
diff --git a/kernel-i686-PAEdebug.config b/kernel-i686-PAEdebug.config
index 2cf7da05d..724b391fd 100644
--- a/kernel-i686-PAEdebug.config
+++ b/kernel-i686-PAEdebug.config
@@ -4389,6 +4389,7 @@ CONFIG_SATA_AHCI=y
 # CONFIG_SATA_DWC is not set
 # CONFIG_SATA_HIGHBANK is not set
 CONFIG_SATA_INIC162X=m
+CONFIG_SATA_MOBILE_LPM_POLICY=3
 CONFIG_SATA_MV=m
 CONFIG_SATA_NV=m
 CONFIG_SATA_PMP=y
diff --git a/kernel-i686-debug.config b/kernel-i686-debug.config
index d0ebe24e2..995c28093 100644
--- a/kernel-i686-debug.config
+++ b/kernel-i686-debug.config
@@ -4389,6 +4389,7 @@ CONFIG_SATA_AHCI=y
 # CONFIG_SATA_DWC is not set
 # CONFIG_SATA_HIGHBANK is not set
 CONFIG_SATA_INIC162X=m
+CONFIG_SATA_MOBILE_LPM_POLICY=3
 CONFIG_SATA_MV=m
 CONFIG_SATA_NV=m
 CONFIG_SATA_PMP=y
diff --git a/kernel-i686.config b/kernel-i686.config
index 2d277a3d1..d7ae93a75 100644
--- a/kernel-i686.config
+++ b/kernel-i686.config
@@ -4368,6 +4368,7 @@ CONFIG_SATA_AHCI=y
 # CONFIG_SATA_DWC is not set
 # CONFIG_SATA_HIGHBANK is not set
 CONFIG_SATA_INIC162X=m
+CONFIG_SATA_MOBILE_LPM_POLICY=3
 CONFIG_SATA_MV=m
 CONFIG_SATA_NV=m
 CONFIG_SATA_PMP=y
diff --git a/kernel-ppc64-debug.config b/kernel-ppc64-debug.config
index c2f943803..8046de3ff 100644
--- a/kernel-ppc64-debug.config
+++ b/kernel-ppc64-debug.config
@@ -4199,6 +4199,7 @@ CONFIG_SATA_AHCI=y
 # CONFIG_SATA_DWC is not set
 # CONFIG_SATA_HIGHBANK is not set
 CONFIG_SATA_INIC162X=m
+CONFIG_SATA_MOBILE_LPM_POLICY=3
 CONFIG_SATA_MV=m
 CONFIG_SATA_NV=m
 CONFIG_SATA_PMP=y
diff --git a/kernel-ppc64.config b/kernel-ppc64.config
index db9741c64..05f6532ed 100644
--- a/kernel-ppc64.config
+++ b/kernel-ppc64.config
@@ -4176,6 +4176,7 @@ CONFIG_SATA_AHCI=y
 # CONFIG_SATA_DWC is not set
 # CONFIG_SATA_HIGHBANK is not set
 CONFIG_SATA_INIC162X=m
+CONFIG_SATA_MOBILE_LPM_POLICY=3
 CONFIG_SATA_MV=m
 CONFIG_SATA_NV=m
 CONFIG_SATA_PMP=y
diff --git a/kernel-ppc64le-debug.config b/kernel-ppc64le-debug.config
index 6ad305601..0d2f38e3a 100644
--- a/kernel-ppc64le-debug.config
+++ b/kernel-ppc64le-debug.config
@@ -4138,6 +4138,7 @@ CONFIG_SATA_AHCI=y
 # CONFIG_SATA_DWC is not set
 # CONFIG_SATA_HIGHBANK is not set
 CONFIG_SATA_INIC162X=m
+CONFIG_SATA_MOBILE_LPM_POLICY=3
 CONFIG_SATA_MV=m
 CONFIG_SATA_NV=m
 CONFIG_SATA_PMP=y
diff --git a/kernel-ppc64le.config b/kernel-ppc64le.config
index 4c343ecc9..49d8b7c00 100644
--- a/kernel-ppc64le.config
+++ b/kernel-ppc64le.config
@@ -4115,6 +4115,7 @@ CONFIG_SATA_AHCI=y
 # CONFIG_SATA_DWC is not set
 # CONFIG_SATA_HIGHBANK is not set
 CONFIG_SATA_INIC162X=m
+CONFIG_SATA_MOBILE_LPM_POLICY=3
 CONFIG_SATA_MV=m
 CONFIG_SATA_NV=m
 CONFIG_SATA_PMP=y
diff --git a/kernel-s390x-debug.config b/kernel-s390x-debug.config
index 4e949a02d..ce9029aae 100644
--- a/kernel-s390x-debug.config
+++ b/kernel-s390x-debug.config
@@ -4037,6 +4037,7 @@ CONFIG_SATA_AHCI=y
 # CONFIG_SATA_DWC is not set
 # CONFIG_SATA_HIGHBANK is not set
 CONFIG_SATA_INIC162X=m
+CONFIG_SATA_MOBILE_LPM_POLICY=3
 CONFIG_SATA_MV=m
 CONFIG_SATA_NV=m
 CONFIG_SATA_PMP=y
diff --git a/kernel-s390x.config b/kernel-s390x.config
index eca0d1125..6585ae530 100644
--- a/kernel-s390x.config
+++ b/kernel-s390x.config
@@ -4014,6 +4014,7 @@ CONFIG_SATA_AHCI=y
 # CONFIG_SATA_DWC is not set
 # CONFIG_SATA_HIGHBANK is not set
 CONFIG_SATA_INIC162X=m
+CONFIG_SATA_MOBILE_LPM_POLICY=3
 CONFIG_SATA_MV=m
 CONFIG_SATA_NV=m
 CONFIG_SATA_PMP=y
diff --git a/kernel-x86_64-debug.config b/kernel-x86_64-debug.config
index c060c15d9..d57f24884 100644
--- a/kernel-x86_64-debug.config
+++ b/kernel-x86_64-debug.config
@@ -4466,6 +4466,7 @@ CONFIG_SATA_AHCI=y
 # CONFIG_SATA_DWC is not set
 # CONFIG_SATA_HIGHBANK is not set
 CONFIG_SATA_INIC162X=m
+CONFIG_SATA_MOBILE_LPM_POLICY=3
 CONFIG_SATA_MV=m
 CONFIG_SATA_NV=m
 CONFIG_SATA_PMP=y
diff --git a/kernel-x86_64.config b/kernel-x86_64.config
index 90a988c4b..026ed3344 100644
--- a/kernel-x86_64.config
+++ b/kernel-x86_64.config
@@ -4445,6 +4445,7 @@ CONFIG_SATA_AHCI=y
 # CONFIG_SATA_DWC is not set
 # CONFIG_SATA_HIGHBANK is not set
 CONFIG_SATA_INIC162X=m
+CONFIG_SATA_MOBILE_LPM_POLICY=3
 CONFIG_SATA_MV=m
 CONFIG_SATA_NV=m
 CONFIG_SATA_PMP=y
diff --git a/kernel.spec b/kernel.spec
index e6fae51ae..0112063bf 100644
--- a/kernel.spec
+++ b/kernel.spec
@@ -640,6 +640,13 @@ Patch632: 0003-HID-multitouch-Combine-all-left-button-events-in-a-f.patch
 # Reported upstream
 Patch635: 0003-x86-PCI-limit-the-size-of-the-64bit-BAR-to-256GB.patch
 
+# Make SATA link powermanagement policy configurable for:
+# https://fedoraproject.org/wiki/Changes/ImprovedLaptopBatteryLife
+# Queued upstream for merging into 4.16
+Patch636: 0001-ahci-Annotate-PCI-ids-for-mobile-Intel-chipsets-as-s.patch
+Patch637: 0002-ahci-Add-PCI-ids-for-Intel-Bay-Trail-Cherry-Trail-an.patch
+Patch638: 0003-ahci-Allow-setting-a-default-LPM-policy-for-mobile-c.patch
+
 # END OF PATCH DEFINITIONS
 
 %endif
@@ -2191,6 +2198,10 @@ fi
 #
 #
 %changelog
+* Fri Dec 22 2017 Hans de Goede <jwrdegoede@fedoraproject.org>
+- Add patches which allow specifying a default SATA linkpower management policy
+  for mobile chipsets and set the default LPM policy to "med_power_with_dipm"
+
 * Fri Dec 22 2017 Laura Abbott <labbott@redhat.com> - 4.15.0-0.rc4.git4.1
 - Linux v4.15-rc4-202-gead68f216110